2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
10 #include <linux/vmalloc.h>
11 #include <asm/uaccess.h>
13 static uint16_t qla2x00_nvram_request(scsi_qla_host_t
*, uint32_t);
14 static void qla2x00_nv_deselect(scsi_qla_host_t
*);
15 static void qla2x00_nv_write(scsi_qla_host_t
*, uint16_t);
18 * NVRAM support routines
22 * qla2x00_lock_nvram_access() -
26 qla2x00_lock_nvram_access(scsi_qla_host_t
*ha
)
29 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
31 if (!IS_QLA2100(ha
) && !IS_QLA2200(ha
) && !IS_QLA2300(ha
)) {
32 data
= RD_REG_WORD(®
->nvram
);
33 while (data
& NVR_BUSY
) {
35 data
= RD_REG_WORD(®
->nvram
);
39 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0x1);
40 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
42 data
= RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
43 while ((data
& BIT_0
) == 0) {
46 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0x1);
47 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
49 data
= RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
55 * qla2x00_unlock_nvram_access() -
59 qla2x00_unlock_nvram_access(scsi_qla_host_t
*ha
)
61 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
63 if (!IS_QLA2100(ha
) && !IS_QLA2200(ha
) && !IS_QLA2300(ha
)) {
64 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0);
65 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
70 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
71 * request routine to get the word from NVRAM.
73 * @addr: Address in NVRAM to read
75 * Returns the word read from nvram @addr.
78 qla2x00_get_nvram_word(scsi_qla_host_t
*ha
, uint32_t addr
)
85 data
= qla2x00_nvram_request(ha
, nv_cmd
);
91 * qla2x00_write_nvram_word() - Write NVRAM data.
93 * @addr: Address in NVRAM to write
94 * @data: word to program
97 qla2x00_write_nvram_word(scsi_qla_host_t
*ha
, uint32_t addr
, uint16_t data
)
101 uint32_t nv_cmd
, wait_cnt
;
102 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
104 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
105 qla2x00_nv_write(ha
, 0);
106 qla2x00_nv_write(ha
, 0);
108 for (word
= 0; word
< 8; word
++)
109 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
111 qla2x00_nv_deselect(ha
);
114 nv_cmd
= (addr
<< 16) | NV_WRITE_OP
;
117 for (count
= 0; count
< 27; count
++) {
119 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
121 qla2x00_nv_write(ha
, 0);
126 qla2x00_nv_deselect(ha
);
128 /* Wait for NVRAM to become ready */
129 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
130 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
131 wait_cnt
= NVR_WAIT_CNT
;
134 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
135 __func__
, ha
->host_no
));
139 word
= RD_REG_WORD(®
->nvram
);
140 } while ((word
& NVR_DATA_IN
) == 0);
142 qla2x00_nv_deselect(ha
);
145 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
146 for (count
= 0; count
< 10; count
++)
147 qla2x00_nv_write(ha
, 0);
149 qla2x00_nv_deselect(ha
);
153 qla2x00_write_nvram_word_tmo(scsi_qla_host_t
*ha
, uint32_t addr
, uint16_t data
,
159 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
163 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
164 qla2x00_nv_write(ha
, 0);
165 qla2x00_nv_write(ha
, 0);
167 for (word
= 0; word
< 8; word
++)
168 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
170 qla2x00_nv_deselect(ha
);
173 nv_cmd
= (addr
<< 16) | NV_WRITE_OP
;
176 for (count
= 0; count
< 27; count
++) {
178 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
180 qla2x00_nv_write(ha
, 0);
185 qla2x00_nv_deselect(ha
);
187 /* Wait for NVRAM to become ready */
188 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
189 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
192 word
= RD_REG_WORD(®
->nvram
);
194 ret
= QLA_FUNCTION_FAILED
;
197 } while ((word
& NVR_DATA_IN
) == 0);
199 qla2x00_nv_deselect(ha
);
202 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
203 for (count
= 0; count
< 10; count
++)
204 qla2x00_nv_write(ha
, 0);
206 qla2x00_nv_deselect(ha
);
212 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
215 * @nv_cmd: NVRAM command
217 * Bit definitions for NVRAM command:
220 * Bit 25, 24 = opcode
221 * Bit 23-16 = address
222 * Bit 15-0 = write data
224 * Returns the word read from nvram @addr.
227 qla2x00_nvram_request(scsi_qla_host_t
*ha
, uint32_t nv_cmd
)
230 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
234 /* Send command to NVRAM. */
236 for (cnt
= 0; cnt
< 11; cnt
++) {
238 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
240 qla2x00_nv_write(ha
, 0);
244 /* Read data from NVRAM. */
245 for (cnt
= 0; cnt
< 16; cnt
++) {
246 WRT_REG_WORD(®
->nvram
, NVR_SELECT
| NVR_CLOCK
);
247 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
250 reg_data
= RD_REG_WORD(®
->nvram
);
251 if (reg_data
& NVR_DATA_IN
)
253 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
254 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
259 WRT_REG_WORD(®
->nvram
, NVR_DESELECT
);
260 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
267 * qla2x00_nv_write() - Clean NVRAM operations.
271 qla2x00_nv_deselect(scsi_qla_host_t
*ha
)
273 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
275 WRT_REG_WORD(®
->nvram
, NVR_DESELECT
);
276 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
281 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
283 * @data: Serial interface selector
286 qla2x00_nv_write(scsi_qla_host_t
*ha
, uint16_t data
)
288 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
290 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_WRT_ENABLE
);
291 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
293 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_CLOCK
|
295 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
297 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_WRT_ENABLE
);
298 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
303 * qla2x00_clear_nvram_protection() -
307 qla2x00_clear_nvram_protection(scsi_qla_host_t
*ha
)
310 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
311 uint32_t word
, wait_cnt
;
312 uint16_t wprot
, wprot_old
;
314 /* Clear NVRAM write protection. */
315 ret
= QLA_FUNCTION_FAILED
;
317 wprot_old
= cpu_to_le16(qla2x00_get_nvram_word(ha
, ha
->nvram_base
));
318 stat
= qla2x00_write_nvram_word_tmo(ha
, ha
->nvram_base
,
319 __constant_cpu_to_le16(0x1234), 100000);
320 wprot
= cpu_to_le16(qla2x00_get_nvram_word(ha
, ha
->nvram_base
));
321 if (stat
!= QLA_SUCCESS
|| wprot
!= 0x1234) {
323 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
324 qla2x00_nv_write(ha
, 0);
325 qla2x00_nv_write(ha
, 0);
326 for (word
= 0; word
< 8; word
++)
327 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
329 qla2x00_nv_deselect(ha
);
331 /* Enable protection register. */
332 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
333 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
334 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
335 for (word
= 0; word
< 8; word
++)
336 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
338 qla2x00_nv_deselect(ha
);
340 /* Clear protection register (ffff is cleared). */
341 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
342 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
343 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
344 for (word
= 0; word
< 8; word
++)
345 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
347 qla2x00_nv_deselect(ha
);
349 /* Wait for NVRAM to become ready. */
350 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
351 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
352 wait_cnt
= NVR_WAIT_CNT
;
355 DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
356 "ready...\n", __func__
,
361 word
= RD_REG_WORD(®
->nvram
);
362 } while ((word
& NVR_DATA_IN
) == 0);
367 qla2x00_write_nvram_word(ha
, ha
->nvram_base
, wprot_old
);
373 qla2x00_set_nvram_protection(scsi_qla_host_t
*ha
, int stat
)
375 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
376 uint32_t word
, wait_cnt
;
378 if (stat
!= QLA_SUCCESS
)
381 /* Set NVRAM write protection. */
383 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
384 qla2x00_nv_write(ha
, 0);
385 qla2x00_nv_write(ha
, 0);
386 for (word
= 0; word
< 8; word
++)
387 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
389 qla2x00_nv_deselect(ha
);
391 /* Enable protection register. */
392 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
393 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
394 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
395 for (word
= 0; word
< 8; word
++)
396 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
398 qla2x00_nv_deselect(ha
);
400 /* Enable protection register. */
401 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
402 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
403 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
404 for (word
= 0; word
< 8; word
++)
405 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
407 qla2x00_nv_deselect(ha
);
409 /* Wait for NVRAM to become ready. */
410 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
411 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
412 wait_cnt
= NVR_WAIT_CNT
;
415 DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
416 __func__
, ha
->host_no
));
420 word
= RD_REG_WORD(®
->nvram
);
421 } while ((word
& NVR_DATA_IN
) == 0);
425 /*****************************************************************************/
426 /* Flash Manipulation Routines */
427 /*****************************************************************************/
429 #define OPTROM_BURST_SIZE 0x1000
430 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
432 static inline uint32_t
433 flash_conf_to_access_addr(uint32_t faddr
)
435 return FARX_ACCESS_FLASH_CONF
| faddr
;
438 static inline uint32_t
439 flash_data_to_access_addr(uint32_t faddr
)
441 return FARX_ACCESS_FLASH_DATA
| faddr
;
444 static inline uint32_t
445 nvram_conf_to_access_addr(uint32_t naddr
)
447 return FARX_ACCESS_NVRAM_CONF
| naddr
;
450 static inline uint32_t
451 nvram_data_to_access_addr(uint32_t naddr
)
453 return FARX_ACCESS_NVRAM_DATA
| naddr
;
457 qla24xx_read_flash_dword(scsi_qla_host_t
*ha
, uint32_t addr
)
461 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
463 WRT_REG_DWORD(®
->flash_addr
, addr
& ~FARX_DATA_FLAG
);
464 /* Wait for READ cycle to complete. */
467 (RD_REG_DWORD(®
->flash_addr
) & FARX_DATA_FLAG
) == 0 &&
468 rval
== QLA_SUCCESS
; cnt
--) {
472 rval
= QLA_FUNCTION_TIMEOUT
;
476 /* TODO: What happens if we time out? */
478 if (rval
== QLA_SUCCESS
)
479 data
= RD_REG_DWORD(®
->flash_data
);
485 qla24xx_read_flash_data(scsi_qla_host_t
*ha
, uint32_t *dwptr
, uint32_t faddr
,
490 /* Dword reads to flash. */
491 for (i
= 0; i
< dwords
; i
++, faddr
++)
492 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
493 flash_data_to_access_addr(faddr
)));
499 qla24xx_write_flash_dword(scsi_qla_host_t
*ha
, uint32_t addr
, uint32_t data
)
503 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
505 WRT_REG_DWORD(®
->flash_data
, data
);
506 RD_REG_DWORD(®
->flash_data
); /* PCI Posting. */
507 WRT_REG_DWORD(®
->flash_addr
, addr
| FARX_DATA_FLAG
);
508 /* Wait for Write cycle to complete. */
510 for (cnt
= 500000; (RD_REG_DWORD(®
->flash_addr
) & FARX_DATA_FLAG
) &&
511 rval
== QLA_SUCCESS
; cnt
--) {
515 rval
= QLA_FUNCTION_TIMEOUT
;
522 qla24xx_get_flash_manufacturer(scsi_qla_host_t
*ha
, uint8_t *man_id
,
527 ids
= qla24xx_read_flash_dword(ha
, flash_data_to_access_addr(0xd03ab));
529 *flash_id
= MSB(ids
);
531 /* Check if man_id and flash_id are valid. */
532 if (ids
!= 0xDEADDEAD && (*man_id
== 0 || *flash_id
== 0)) {
533 /* Read information using 0x9f opcode
534 * Device ID, Mfg ID would be read in the format:
535 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
536 * Example: ATMEL 0x00 01 45 1F
537 * Extract MFG and Dev ID from last two bytes.
539 ids
= qla24xx_read_flash_dword(ha
,
540 flash_data_to_access_addr(0xd009f));
542 *flash_id
= MSB(ids
);
547 qla2xxx_find_flt_start(scsi_qla_host_t
*ha
, uint32_t *start
)
549 const char *loc
, *locations
[] = { "DEF", "PCI" };
550 uint32_t pcihdr
, pcids
;
552 uint8_t *buf
, *bcode
, last_image
;
553 uint16_t cnt
, chksum
, *wptr
;
554 struct qla_flt_location
*fltl
;
557 * FLT-location structure resides after the last PCI region.
560 /* Begin with sane defaults. */
562 *start
= IS_QLA24XX_TYPE(ha
) ? FA_FLASH_LAYOUT_ADDR_24
:
563 FA_FLASH_LAYOUT_ADDR
;
565 /* Begin with first PCI expansion ROM header. */
566 buf
= (uint8_t *)ha
->request_ring
;
567 dcode
= (uint32_t *)ha
->request_ring
;
571 /* Verify PCI expansion ROM header. */
572 qla24xx_read_flash_data(ha
, dcode
, pcihdr
>> 2, 0x20);
573 bcode
= buf
+ (pcihdr
% 4);
574 if (bcode
[0x0] != 0x55 || bcode
[0x1] != 0xaa)
577 /* Locate PCI data structure. */
578 pcids
= pcihdr
+ ((bcode
[0x19] << 8) | bcode
[0x18]);
579 qla24xx_read_flash_data(ha
, dcode
, pcids
>> 2, 0x20);
580 bcode
= buf
+ (pcihdr
% 4);
582 /* Validate signature of PCI data structure. */
583 if (bcode
[0x0] != 'P' || bcode
[0x1] != 'C' ||
584 bcode
[0x2] != 'I' || bcode
[0x3] != 'R')
587 last_image
= bcode
[0x15] & BIT_7
;
589 /* Locate next PCI expansion ROM. */
590 pcihdr
+= ((bcode
[0x11] << 8) | bcode
[0x10]) * 512;
591 } while (!last_image
);
593 /* Now verify FLT-location structure. */
594 fltl
= (struct qla_flt_location
*)ha
->request_ring
;
595 qla24xx_read_flash_data(ha
, dcode
, pcihdr
>> 2,
596 sizeof(struct qla_flt_location
) >> 2);
597 if (fltl
->sig
[0] != 'Q' || fltl
->sig
[1] != 'F' ||
598 fltl
->sig
[2] != 'L' || fltl
->sig
[3] != 'T')
601 wptr
= (uint16_t *)ha
->request_ring
;
602 cnt
= sizeof(struct qla_flt_location
) >> 1;
603 for (chksum
= 0; cnt
; cnt
--)
604 chksum
+= le16_to_cpu(*wptr
++);
606 qla_printk(KERN_ERR
, ha
,
607 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum
);
608 qla2x00_dump_buffer(buf
, sizeof(struct qla_flt_location
));
609 return QLA_FUNCTION_FAILED
;
612 /* Good data. Use specified location. */
614 *start
= le16_to_cpu(fltl
->start_hi
) << 16 |
615 le16_to_cpu(fltl
->start_lo
);
617 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "FLTL[%s] = 0x%x.\n", loc
, *start
));
622 qla2xxx_get_flt_info(scsi_qla_host_t
*ha
, uint32_t flt_addr
)
624 const char *loc
, *locations
[] = { "DEF", "FLT" };
626 uint16_t cnt
, chksum
;
628 struct qla_flt_header
*flt
;
629 struct qla_flt_region
*region
;
631 ha
->flt_region_flt
= flt_addr
;
632 wptr
= (uint16_t *)ha
->request_ring
;
633 flt
= (struct qla_flt_header
*)ha
->request_ring
;
634 region
= (struct qla_flt_region
*)&flt
[1];
635 ha
->isp_ops
->read_optrom(ha
, (uint8_t *)ha
->request_ring
,
636 flt_addr
<< 2, OPTROM_BURST_SIZE
);
637 if (*wptr
== __constant_cpu_to_le16(0xffff))
639 if (flt
->version
!= __constant_cpu_to_le16(1)) {
640 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unsupported FLT detected: "
641 "version=0x%x length=0x%x checksum=0x%x.\n",
642 le16_to_cpu(flt
->version
), le16_to_cpu(flt
->length
),
643 le16_to_cpu(flt
->checksum
)));
647 cnt
= (sizeof(struct qla_flt_header
) + le16_to_cpu(flt
->length
)) >> 1;
648 for (chksum
= 0; cnt
; cnt
--)
649 chksum
+= le16_to_cpu(*wptr
++);
651 DEBUG2(qla_printk(KERN_INFO
, ha
, "Inconsistent FLT detected: "
652 "version=0x%x length=0x%x checksum=0x%x.\n",
653 le16_to_cpu(flt
->version
), le16_to_cpu(flt
->length
),
659 cnt
= le16_to_cpu(flt
->length
) / sizeof(struct qla_flt_region
);
660 for ( ; cnt
; cnt
--, region
++) {
661 /* Store addresses as DWORD offsets. */
662 start
= le32_to_cpu(region
->start
) >> 2;
664 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "FLT[%02x]: start=0x%x "
665 "end=0x%x size=0x%x.\n", le32_to_cpu(region
->code
), start
,
666 le32_to_cpu(region
->end
) >> 2, le32_to_cpu(region
->size
)));
668 switch (le32_to_cpu(region
->code
)) {
670 ha
->flt_region_fw
= start
;
672 case FLT_REG_BOOT_CODE
:
673 ha
->flt_region_boot
= start
;
676 ha
->flt_region_vpd_nvram
= start
;
679 ha
->flt_region_fdt
= start
;
681 case FLT_REG_HW_EVENT_0
:
682 if (!PCI_FUNC(ha
->pdev
->devfn
))
683 ha
->flt_region_hw_event
= start
;
685 case FLT_REG_HW_EVENT_1
:
686 if (PCI_FUNC(ha
->pdev
->devfn
))
687 ha
->flt_region_hw_event
= start
;
689 case FLT_REG_NPIV_CONF_0
:
690 if (!PCI_FUNC(ha
->pdev
->devfn
))
691 ha
->flt_region_npiv_conf
= start
;
693 case FLT_REG_NPIV_CONF_1
:
694 if (PCI_FUNC(ha
->pdev
->devfn
))
695 ha
->flt_region_npiv_conf
= start
;
702 /* Use hardcoded defaults. */
704 ha
->flt_region_fw
= FA_RISC_CODE_ADDR
;
705 ha
->flt_region_boot
= FA_BOOT_CODE_ADDR
;
706 ha
->flt_region_vpd_nvram
= FA_VPD_NVRAM_ADDR
;
707 ha
->flt_region_fdt
= IS_QLA24XX_TYPE(ha
) ? FA_FLASH_DESCR_ADDR_24
:
709 ha
->flt_region_hw_event
= !PCI_FUNC(ha
->pdev
->devfn
) ?
710 FA_HW_EVENT0_ADDR
: FA_HW_EVENT1_ADDR
;
711 ha
->flt_region_npiv_conf
= !PCI_FUNC(ha
->pdev
->devfn
) ?
712 (IS_QLA24XX_TYPE(ha
) ? FA_NPIV_CONF0_ADDR_24
: FA_NPIV_CONF0_ADDR
):
713 (IS_QLA24XX_TYPE(ha
) ? FA_NPIV_CONF1_ADDR_24
: FA_NPIV_CONF1_ADDR
);
715 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "FLT[%s]: boot=0x%x fw=0x%x "
716 "vpd_nvram=0x%x fdt=0x%x flt=0x%x hwe=0x%x npiv=0x%x.\n", loc
,
717 ha
->flt_region_boot
, ha
->flt_region_fw
, ha
->flt_region_vpd_nvram
,
718 ha
->flt_region_fdt
, ha
->flt_region_flt
, ha
->flt_region_hw_event
,
719 ha
->flt_region_npiv_conf
));
723 qla2xxx_get_fdt_info(scsi_qla_host_t
*ha
)
725 #define FLASH_BLK_SIZE_4K 0x1000
726 #define FLASH_BLK_SIZE_32K 0x8000
727 #define FLASH_BLK_SIZE_64K 0x10000
728 const char *loc
, *locations
[] = { "MID", "FDT" };
729 uint16_t cnt
, chksum
;
731 struct qla_fdt_layout
*fdt
;
732 uint8_t man_id
, flash_id
;
735 wptr
= (uint16_t *)ha
->request_ring
;
736 fdt
= (struct qla_fdt_layout
*)ha
->request_ring
;
737 ha
->isp_ops
->read_optrom(ha
, (uint8_t *)ha
->request_ring
,
738 ha
->flt_region_fdt
<< 2, OPTROM_BURST_SIZE
);
739 if (*wptr
== __constant_cpu_to_le16(0xffff))
741 if (fdt
->sig
[0] != 'Q' || fdt
->sig
[1] != 'L' || fdt
->sig
[2] != 'I' ||
745 for (cnt
= 0, chksum
= 0; cnt
< sizeof(struct qla_fdt_layout
) >> 1;
747 chksum
+= le16_to_cpu(*wptr
++);
749 DEBUG2(qla_printk(KERN_INFO
, ha
, "Inconsistent FDT detected: "
750 "checksum=0x%x id=%c version=0x%x.\n", chksum
, fdt
->sig
[0],
751 le16_to_cpu(fdt
->version
)));
752 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt
, sizeof(*fdt
)));
757 mid
= le16_to_cpu(fdt
->man_id
);
758 fid
= le16_to_cpu(fdt
->id
);
759 ha
->fdt_wrt_disable
= fdt
->wrt_disable_bits
;
760 ha
->fdt_erase_cmd
= flash_conf_to_access_addr(0x0300 | fdt
->erase_cmd
);
761 ha
->fdt_block_size
= le32_to_cpu(fdt
->block_size
);
762 if (fdt
->unprotect_sec_cmd
) {
763 ha
->fdt_unprotect_sec_cmd
= flash_conf_to_access_addr(0x0300 |
764 fdt
->unprotect_sec_cmd
);
765 ha
->fdt_protect_sec_cmd
= fdt
->protect_sec_cmd
?
766 flash_conf_to_access_addr(0x0300 | fdt
->protect_sec_cmd
):
767 flash_conf_to_access_addr(0x0336);
772 qla24xx_get_flash_manufacturer(ha
, &man_id
, &flash_id
);
775 ha
->fdt_wrt_disable
= 0x9c;
776 ha
->fdt_erase_cmd
= flash_conf_to_access_addr(0x03d8);
778 case 0xbf: /* STT flash. */
779 if (flash_id
== 0x8e)
780 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
782 ha
->fdt_block_size
= FLASH_BLK_SIZE_32K
;
784 if (flash_id
== 0x80)
785 ha
->fdt_erase_cmd
= flash_conf_to_access_addr(0x0352);
787 case 0x13: /* ST M25P80. */
788 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
790 case 0x1f: /* Atmel 26DF081A. */
791 ha
->fdt_block_size
= FLASH_BLK_SIZE_4K
;
792 ha
->fdt_erase_cmd
= flash_conf_to_access_addr(0x0320);
793 ha
->fdt_unprotect_sec_cmd
= flash_conf_to_access_addr(0x0339);
794 ha
->fdt_protect_sec_cmd
= flash_conf_to_access_addr(0x0336);
797 /* Default to 64 kb sector size. */
798 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
802 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
803 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc
, mid
, fid
,
804 ha
->fdt_erase_cmd
, ha
->fdt_protect_sec_cmd
,
805 ha
->fdt_unprotect_sec_cmd
, ha
->fdt_wrt_disable
,
806 ha
->fdt_block_size
));
810 qla2xxx_get_flash_info(scsi_qla_host_t
*ha
)
815 if (!IS_QLA24XX_TYPE(ha
) && !IS_QLA25XX(ha
))
818 ret
= qla2xxx_find_flt_start(ha
, &flt_addr
);
819 if (ret
!= QLA_SUCCESS
)
822 qla2xxx_get_flt_info(ha
, flt_addr
);
823 qla2xxx_get_fdt_info(ha
);
829 qla2xxx_flash_npiv_conf(scsi_qla_host_t
*ha
)
831 #define NPIV_CONFIG_SIZE (16*1024)
834 uint16_t cnt
, chksum
;
835 struct qla_npiv_header hdr
;
836 struct qla_npiv_entry
*entry
;
838 if (!IS_QLA24XX_TYPE(ha
) && !IS_QLA25XX(ha
))
841 ha
->isp_ops
->read_optrom(ha
, (uint8_t *)&hdr
,
842 ha
->flt_region_npiv_conf
<< 2, sizeof(struct qla_npiv_header
));
843 if (hdr
.version
== __constant_cpu_to_le16(0xffff))
845 if (hdr
.version
!= __constant_cpu_to_le16(1)) {
846 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unsupported NPIV-Config "
847 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
848 le16_to_cpu(hdr
.version
), le16_to_cpu(hdr
.entries
),
849 le16_to_cpu(hdr
.checksum
)));
853 data
= kmalloc(NPIV_CONFIG_SIZE
, GFP_KERNEL
);
855 DEBUG2(qla_printk(KERN_INFO
, ha
, "NPIV-Config: Unable to "
856 "allocate memory.\n"));
860 ha
->isp_ops
->read_optrom(ha
, (uint8_t *)data
,
861 ha
->flt_region_npiv_conf
<< 2, NPIV_CONFIG_SIZE
);
863 cnt
= (sizeof(struct qla_npiv_header
) + le16_to_cpu(hdr
.entries
) *
864 sizeof(struct qla_npiv_entry
)) >> 1;
865 for (wptr
= data
, chksum
= 0; cnt
; cnt
--)
866 chksum
+= le16_to_cpu(*wptr
++);
868 DEBUG2(qla_printk(KERN_INFO
, ha
, "Inconsistent NPIV-Config "
869 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
870 le16_to_cpu(hdr
.version
), le16_to_cpu(hdr
.entries
),
875 entry
= data
+ sizeof(struct qla_npiv_header
);
876 cnt
= le16_to_cpu(hdr
.entries
);
877 for ( ; cnt
; cnt
--, entry
++) {
879 struct fc_vport_identifiers vid
;
880 struct fc_vport
*vport
;
882 flags
= le16_to_cpu(entry
->flags
);
885 if ((flags
& BIT_0
) == 0)
888 memset(&vid
, 0, sizeof(vid
));
889 vid
.roles
= FC_PORT_ROLE_FCP_INITIATOR
;
890 vid
.vport_type
= FC_PORTTYPE_NPIV
;
892 vid
.port_name
= wwn_to_u64(entry
->port_name
);
893 vid
.node_name
= wwn_to_u64(entry
->node_name
);
895 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "NPIV[%02x]: wwpn=%llx "
896 "wwnn=%llx vf_id=0x%x qos=0x%x.\n", cnt
,
897 (unsigned long long)vid
.port_name
,
898 (unsigned long long)vid
.node_name
,
899 le16_to_cpu(entry
->vf_id
), le16_to_cpu(entry
->qos
)));
901 vport
= fc_vport_create(ha
->host
, 0, &vid
);
903 qla_printk(KERN_INFO
, ha
, "NPIV-Config: Failed to "
904 "create vport [%02x]: wwpn=%llx wwnn=%llx.\n", cnt
,
905 (unsigned long long)vid
.port_name
,
906 (unsigned long long)vid
.node_name
);
913 qla24xx_unprotect_flash(scsi_qla_host_t
*ha
)
915 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
917 /* Enable flash write. */
918 WRT_REG_DWORD(®
->ctrl_status
,
919 RD_REG_DWORD(®
->ctrl_status
) | CSRX_FLASH_ENABLE
);
920 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
922 if (!ha
->fdt_wrt_disable
)
925 /* Disable flash write-protection. */
926 qla24xx_write_flash_dword(ha
, flash_conf_to_access_addr(0x101), 0);
927 /* Some flash parts need an additional zero-write to clear bits.*/
928 qla24xx_write_flash_dword(ha
, flash_conf_to_access_addr(0x101), 0);
932 qla24xx_protect_flash(scsi_qla_host_t
*ha
)
935 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
937 if (!ha
->fdt_wrt_disable
)
938 goto skip_wrt_protect
;
940 /* Enable flash write-protection and wait for completion. */
941 qla24xx_write_flash_dword(ha
, flash_conf_to_access_addr(0x101),
942 ha
->fdt_wrt_disable
);
943 for (cnt
= 300; cnt
&&
944 qla24xx_read_flash_dword(ha
,
945 flash_conf_to_access_addr(0x005)) & BIT_0
;
951 /* Disable flash write. */
952 WRT_REG_DWORD(®
->ctrl_status
,
953 RD_REG_DWORD(®
->ctrl_status
) & ~CSRX_FLASH_ENABLE
);
954 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
958 qla24xx_write_flash_data(scsi_qla_host_t
*ha
, uint32_t *dwptr
, uint32_t faddr
,
962 uint32_t liter
, miter
;
963 uint32_t sec_mask
, rest_addr
;
964 uint32_t fdata
, findex
;
965 dma_addr_t optrom_dma
;
971 /* Prepare burst-capable write on supported ISPs. */
972 if (IS_QLA25XX(ha
) && !(faddr
& 0xfff) &&
973 dwords
> OPTROM_BURST_DWORDS
) {
974 optrom
= dma_alloc_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
975 &optrom_dma
, GFP_KERNEL
);
977 qla_printk(KERN_DEBUG
, ha
,
978 "Unable to allocate memory for optrom burst write "
979 "(%x KB).\n", OPTROM_BURST_SIZE
/ 1024);
983 rest_addr
= (ha
->fdt_block_size
>> 2) - 1;
984 sec_mask
= 0x80000 - (ha
->fdt_block_size
>> 2);
986 qla24xx_unprotect_flash(ha
);
988 for (liter
= 0; liter
< dwords
; liter
++, faddr
++, dwptr
++) {
991 fdata
= (findex
& sec_mask
) << 2;
993 /* Are we at the beginning of a sector? */
994 if ((findex
& rest_addr
) == 0) {
995 /* Do sector unprotect. */
996 if (ha
->fdt_unprotect_sec_cmd
)
997 qla24xx_write_flash_dword(ha
,
998 ha
->fdt_unprotect_sec_cmd
,
999 (fdata
& 0xff00) | ((fdata
<< 16) &
1000 0xff0000) | ((fdata
>> 16) & 0xff));
1001 ret
= qla24xx_write_flash_dword(ha
, ha
->fdt_erase_cmd
,
1002 (fdata
& 0xff00) |((fdata
<< 16) &
1003 0xff0000) | ((fdata
>> 16) & 0xff));
1004 if (ret
!= QLA_SUCCESS
) {
1005 DEBUG9(printk("%s(%ld) Unable to flash "
1006 "sector: address=%x.\n", __func__
,
1007 ha
->host_no
, faddr
));
1012 /* Go with burst-write. */
1013 if (optrom
&& (liter
+ OPTROM_BURST_DWORDS
) <= dwords
) {
1014 /* Copy data to DMA'ble buffer. */
1015 for (miter
= 0, s
= optrom
, d
= dwptr
;
1016 miter
< OPTROM_BURST_DWORDS
; miter
++, s
++, d
++)
1017 *s
= cpu_to_le32(*d
);
1019 ret
= qla2x00_load_ram(ha
, optrom_dma
,
1020 flash_data_to_access_addr(faddr
),
1021 OPTROM_BURST_DWORDS
);
1022 if (ret
!= QLA_SUCCESS
) {
1023 qla_printk(KERN_WARNING
, ha
,
1024 "Unable to burst-write optrom segment "
1025 "(%x/%x/%llx).\n", ret
,
1026 flash_data_to_access_addr(faddr
),
1027 (unsigned long long)optrom_dma
);
1028 qla_printk(KERN_WARNING
, ha
,
1029 "Reverting to slow-write.\n");
1031 dma_free_coherent(&ha
->pdev
->dev
,
1032 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
1035 liter
+= OPTROM_BURST_DWORDS
- 1;
1036 faddr
+= OPTROM_BURST_DWORDS
- 1;
1037 dwptr
+= OPTROM_BURST_DWORDS
- 1;
1042 ret
= qla24xx_write_flash_dword(ha
,
1043 flash_data_to_access_addr(faddr
), cpu_to_le32(*dwptr
));
1044 if (ret
!= QLA_SUCCESS
) {
1045 DEBUG9(printk("%s(%ld) Unable to program flash "
1046 "address=%x data=%x.\n", __func__
,
1047 ha
->host_no
, faddr
, *dwptr
));
1051 /* Do sector protect. */
1052 if (ha
->fdt_unprotect_sec_cmd
&&
1053 ((faddr
& rest_addr
) == rest_addr
))
1054 qla24xx_write_flash_dword(ha
,
1055 ha
->fdt_protect_sec_cmd
,
1056 (fdata
& 0xff00) | ((fdata
<< 16) &
1057 0xff0000) | ((fdata
>> 16) & 0xff));
1060 qla24xx_protect_flash(ha
);
1063 dma_free_coherent(&ha
->pdev
->dev
,
1064 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
1070 qla2x00_read_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
1076 /* Word reads to NVRAM via registers. */
1077 wptr
= (uint16_t *)buf
;
1078 qla2x00_lock_nvram_access(ha
);
1079 for (i
= 0; i
< bytes
>> 1; i
++, naddr
++)
1080 wptr
[i
] = cpu_to_le16(qla2x00_get_nvram_word(ha
,
1082 qla2x00_unlock_nvram_access(ha
);
1088 qla24xx_read_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
1094 /* Dword reads to flash. */
1095 dwptr
= (uint32_t *)buf
;
1096 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++)
1097 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
1098 nvram_data_to_access_addr(naddr
)));
1104 qla2x00_write_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
1110 unsigned long flags
;
1114 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1115 qla2x00_lock_nvram_access(ha
);
1117 /* Disable NVRAM write-protection. */
1118 stat
= qla2x00_clear_nvram_protection(ha
);
1120 wptr
= (uint16_t *)buf
;
1121 for (i
= 0; i
< bytes
>> 1; i
++, naddr
++) {
1122 qla2x00_write_nvram_word(ha
, naddr
,
1123 cpu_to_le16(*wptr
));
1127 /* Enable NVRAM write-protection. */
1128 qla2x00_set_nvram_protection(ha
, stat
);
1130 qla2x00_unlock_nvram_access(ha
);
1131 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1137 qla24xx_write_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
1143 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1147 /* Enable flash write. */
1148 WRT_REG_DWORD(®
->ctrl_status
,
1149 RD_REG_DWORD(®
->ctrl_status
) | CSRX_FLASH_ENABLE
);
1150 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
1152 /* Disable NVRAM write-protection. */
1153 qla24xx_write_flash_dword(ha
, nvram_conf_to_access_addr(0x101),
1155 qla24xx_write_flash_dword(ha
, nvram_conf_to_access_addr(0x101),
1158 /* Dword writes to flash. */
1159 dwptr
= (uint32_t *)buf
;
1160 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++, dwptr
++) {
1161 ret
= qla24xx_write_flash_dword(ha
,
1162 nvram_data_to_access_addr(naddr
),
1163 cpu_to_le32(*dwptr
));
1164 if (ret
!= QLA_SUCCESS
) {
1165 DEBUG9(printk("%s(%ld) Unable to program "
1166 "nvram address=%x data=%x.\n", __func__
,
1167 ha
->host_no
, naddr
, *dwptr
));
1172 /* Enable NVRAM write-protection. */
1173 qla24xx_write_flash_dword(ha
, nvram_conf_to_access_addr(0x101),
1176 /* Disable flash write. */
1177 WRT_REG_DWORD(®
->ctrl_status
,
1178 RD_REG_DWORD(®
->ctrl_status
) & ~CSRX_FLASH_ENABLE
);
1179 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
1185 qla25xx_read_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
1191 /* Dword reads to flash. */
1192 dwptr
= (uint32_t *)buf
;
1193 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++)
1194 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
1195 flash_data_to_access_addr(ha
->flt_region_vpd_nvram
|
1202 qla25xx_write_nvram_data(scsi_qla_host_t
*ha
, uint8_t *buf
, uint32_t naddr
,
1205 #define RMW_BUFFER_SIZE (64 * 1024)
1208 dbuf
= vmalloc(RMW_BUFFER_SIZE
);
1210 return QLA_MEMORY_ALLOC_FAILED
;
1211 ha
->isp_ops
->read_optrom(ha
, dbuf
, ha
->flt_region_vpd_nvram
<< 2,
1213 memcpy(dbuf
+ (naddr
<< 2), buf
, bytes
);
1214 ha
->isp_ops
->write_optrom(ha
, dbuf
, ha
->flt_region_vpd_nvram
<< 2,
1222 qla2x00_flip_colors(scsi_qla_host_t
*ha
, uint16_t *pflags
)
1224 if (IS_QLA2322(ha
)) {
1225 /* Flip all colors. */
1226 if (ha
->beacon_color_state
== QLA_LED_ALL_ON
) {
1228 ha
->beacon_color_state
= 0;
1229 *pflags
= GPIO_LED_ALL_OFF
;
1232 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1233 *pflags
= GPIO_LED_RGA_ON
;
1236 /* Flip green led only. */
1237 if (ha
->beacon_color_state
== QLA_LED_GRN_ON
) {
1239 ha
->beacon_color_state
= 0;
1240 *pflags
= GPIO_LED_GREEN_OFF_AMBER_OFF
;
1243 ha
->beacon_color_state
= QLA_LED_GRN_ON
;
1244 *pflags
= GPIO_LED_GREEN_ON_AMBER_OFF
;
1249 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1252 qla2x00_beacon_blink(struct scsi_qla_host
*ha
)
1254 uint16_t gpio_enable
;
1256 uint16_t led_color
= 0;
1257 unsigned long flags
;
1258 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1260 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1262 /* Save the Original GPIOE. */
1263 if (ha
->pio_address
) {
1264 gpio_enable
= RD_REG_WORD_PIO(PIO_REG(ha
, gpioe
));
1265 gpio_data
= RD_REG_WORD_PIO(PIO_REG(ha
, gpiod
));
1267 gpio_enable
= RD_REG_WORD(®
->gpioe
);
1268 gpio_data
= RD_REG_WORD(®
->gpiod
);
1271 /* Set the modified gpio_enable values */
1272 gpio_enable
|= GPIO_LED_MASK
;
1274 if (ha
->pio_address
) {
1275 WRT_REG_WORD_PIO(PIO_REG(ha
, gpioe
), gpio_enable
);
1277 WRT_REG_WORD(®
->gpioe
, gpio_enable
);
1278 RD_REG_WORD(®
->gpioe
);
1281 qla2x00_flip_colors(ha
, &led_color
);
1283 /* Clear out any previously set LED color. */
1284 gpio_data
&= ~GPIO_LED_MASK
;
1286 /* Set the new input LED color to GPIOD. */
1287 gpio_data
|= led_color
;
1289 /* Set the modified gpio_data values */
1290 if (ha
->pio_address
) {
1291 WRT_REG_WORD_PIO(PIO_REG(ha
, gpiod
), gpio_data
);
1293 WRT_REG_WORD(®
->gpiod
, gpio_data
);
1294 RD_REG_WORD(®
->gpiod
);
1297 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1301 qla2x00_beacon_on(struct scsi_qla_host
*ha
)
1303 uint16_t gpio_enable
;
1305 unsigned long flags
;
1306 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1308 ha
->fw_options
[1] &= ~FO1_SET_EMPHASIS_SWING
;
1309 ha
->fw_options
[1] |= FO1_DISABLE_GPIO6_7
;
1311 if (qla2x00_set_fw_options(ha
, ha
->fw_options
) != QLA_SUCCESS
) {
1312 qla_printk(KERN_WARNING
, ha
,
1313 "Unable to update fw options (beacon on).\n");
1314 return QLA_FUNCTION_FAILED
;
1317 /* Turn off LEDs. */
1318 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1319 if (ha
->pio_address
) {
1320 gpio_enable
= RD_REG_WORD_PIO(PIO_REG(ha
, gpioe
));
1321 gpio_data
= RD_REG_WORD_PIO(PIO_REG(ha
, gpiod
));
1323 gpio_enable
= RD_REG_WORD(®
->gpioe
);
1324 gpio_data
= RD_REG_WORD(®
->gpiod
);
1326 gpio_enable
|= GPIO_LED_MASK
;
1328 /* Set the modified gpio_enable values. */
1329 if (ha
->pio_address
) {
1330 WRT_REG_WORD_PIO(PIO_REG(ha
, gpioe
), gpio_enable
);
1332 WRT_REG_WORD(®
->gpioe
, gpio_enable
);
1333 RD_REG_WORD(®
->gpioe
);
1336 /* Clear out previously set LED colour. */
1337 gpio_data
&= ~GPIO_LED_MASK
;
1338 if (ha
->pio_address
) {
1339 WRT_REG_WORD_PIO(PIO_REG(ha
, gpiod
), gpio_data
);
1341 WRT_REG_WORD(®
->gpiod
, gpio_data
);
1342 RD_REG_WORD(®
->gpiod
);
1344 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1347 * Let the per HBA timer kick off the blinking process based on
1348 * the following flags. No need to do anything else now.
1350 ha
->beacon_blink_led
= 1;
1351 ha
->beacon_color_state
= 0;
1357 qla2x00_beacon_off(struct scsi_qla_host
*ha
)
1359 int rval
= QLA_SUCCESS
;
1361 ha
->beacon_blink_led
= 0;
1363 /* Set the on flag so when it gets flipped it will be off. */
1365 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1367 ha
->beacon_color_state
= QLA_LED_GRN_ON
;
1369 ha
->isp_ops
->beacon_blink(ha
); /* This turns green LED off */
1371 ha
->fw_options
[1] &= ~FO1_SET_EMPHASIS_SWING
;
1372 ha
->fw_options
[1] &= ~FO1_DISABLE_GPIO6_7
;
1374 rval
= qla2x00_set_fw_options(ha
, ha
->fw_options
);
1375 if (rval
!= QLA_SUCCESS
)
1376 qla_printk(KERN_WARNING
, ha
,
1377 "Unable to update fw options (beacon off).\n");
1383 qla24xx_flip_colors(scsi_qla_host_t
*ha
, uint16_t *pflags
)
1385 /* Flip all colors. */
1386 if (ha
->beacon_color_state
== QLA_LED_ALL_ON
) {
1388 ha
->beacon_color_state
= 0;
1392 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1393 *pflags
= GPDX_LED_YELLOW_ON
| GPDX_LED_AMBER_ON
;
1398 qla24xx_beacon_blink(struct scsi_qla_host
*ha
)
1400 uint16_t led_color
= 0;
1402 unsigned long flags
;
1403 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1405 /* Save the Original GPIOD. */
1406 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1407 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1409 /* Enable the gpio_data reg for update. */
1410 gpio_data
|= GPDX_LED_UPDATE_MASK
;
1412 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1413 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1415 /* Set the color bits. */
1416 qla24xx_flip_colors(ha
, &led_color
);
1418 /* Clear out any previously set LED color. */
1419 gpio_data
&= ~GPDX_LED_COLOR_MASK
;
1421 /* Set the new input LED color to GPIOD. */
1422 gpio_data
|= led_color
;
1424 /* Set the modified gpio_data values. */
1425 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1426 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1427 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1431 qla24xx_beacon_on(struct scsi_qla_host
*ha
)
1434 unsigned long flags
;
1435 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1437 if (ha
->beacon_blink_led
== 0) {
1438 /* Enable firmware for update */
1439 ha
->fw_options
[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL
;
1441 if (qla2x00_set_fw_options(ha
, ha
->fw_options
) != QLA_SUCCESS
)
1442 return QLA_FUNCTION_FAILED
;
1444 if (qla2x00_get_fw_options(ha
, ha
->fw_options
) !=
1446 qla_printk(KERN_WARNING
, ha
,
1447 "Unable to update fw options (beacon on).\n");
1448 return QLA_FUNCTION_FAILED
;
1451 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1452 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1454 /* Enable the gpio_data reg for update. */
1455 gpio_data
|= GPDX_LED_UPDATE_MASK
;
1456 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1457 RD_REG_DWORD(®
->gpiod
);
1459 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1462 /* So all colors blink together. */
1463 ha
->beacon_color_state
= 0;
1465 /* Let the per HBA timer kick off the blinking process. */
1466 ha
->beacon_blink_led
= 1;
1472 qla24xx_beacon_off(struct scsi_qla_host
*ha
)
1475 unsigned long flags
;
1476 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1478 ha
->beacon_blink_led
= 0;
1479 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1481 ha
->isp_ops
->beacon_blink(ha
); /* Will flip to all off. */
1483 /* Give control back to firmware. */
1484 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1485 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1487 /* Disable the gpio_data reg for update. */
1488 gpio_data
&= ~GPDX_LED_UPDATE_MASK
;
1489 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1490 RD_REG_DWORD(®
->gpiod
);
1491 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1493 ha
->fw_options
[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL
;
1495 if (qla2x00_set_fw_options(ha
, ha
->fw_options
) != QLA_SUCCESS
) {
1496 qla_printk(KERN_WARNING
, ha
,
1497 "Unable to update fw options (beacon off).\n");
1498 return QLA_FUNCTION_FAILED
;
1501 if (qla2x00_get_fw_options(ha
, ha
->fw_options
) != QLA_SUCCESS
) {
1502 qla_printk(KERN_WARNING
, ha
,
1503 "Unable to get fw options (beacon off).\n");
1504 return QLA_FUNCTION_FAILED
;
1512 * Flash support routines
1516 * qla2x00_flash_enable() - Setup flash for reading and writing.
1520 qla2x00_flash_enable(scsi_qla_host_t
*ha
)
1523 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1525 data
= RD_REG_WORD(®
->ctrl_status
);
1526 data
|= CSR_FLASH_ENABLE
;
1527 WRT_REG_WORD(®
->ctrl_status
, data
);
1528 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1532 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1536 qla2x00_flash_disable(scsi_qla_host_t
*ha
)
1539 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1541 data
= RD_REG_WORD(®
->ctrl_status
);
1542 data
&= ~(CSR_FLASH_ENABLE
);
1543 WRT_REG_WORD(®
->ctrl_status
, data
);
1544 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1548 * qla2x00_read_flash_byte() - Reads a byte from flash
1550 * @addr: Address in flash to read
1552 * A word is read from the chip, but, only the lower byte is valid.
1554 * Returns the byte read from flash @addr.
1557 qla2x00_read_flash_byte(scsi_qla_host_t
*ha
, uint32_t addr
)
1560 uint16_t bank_select
;
1561 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1563 bank_select
= RD_REG_WORD(®
->ctrl_status
);
1565 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
1566 /* Specify 64K address range: */
1567 /* clear out Module Select and Flash Address bits [19:16]. */
1568 bank_select
&= ~0xf8;
1569 bank_select
|= addr
>> 12 & 0xf0;
1570 bank_select
|= CSR_FLASH_64K_BANK
;
1571 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1572 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1574 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1575 data
= RD_REG_WORD(®
->flash_data
);
1577 return (uint8_t)data
;
1580 /* Setup bit 16 of flash address. */
1581 if ((addr
& BIT_16
) && ((bank_select
& CSR_FLASH_64K_BANK
) == 0)) {
1582 bank_select
|= CSR_FLASH_64K_BANK
;
1583 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1584 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1585 } else if (((addr
& BIT_16
) == 0) &&
1586 (bank_select
& CSR_FLASH_64K_BANK
)) {
1587 bank_select
&= ~(CSR_FLASH_64K_BANK
);
1588 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1589 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1592 /* Always perform IO mapped accesses to the FLASH registers. */
1593 if (ha
->pio_address
) {
1596 WRT_REG_WORD_PIO(PIO_REG(ha
, flash_address
), (uint16_t)addr
);
1598 data
= RD_REG_WORD_PIO(PIO_REG(ha
, flash_data
));
1601 data2
= RD_REG_WORD_PIO(PIO_REG(ha
, flash_data
));
1602 } while (data
!= data2
);
1604 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1605 data
= qla2x00_debounce_register(®
->flash_data
);
1608 return (uint8_t)data
;
1612 * qla2x00_write_flash_byte() - Write a byte to flash
1614 * @addr: Address in flash to write
1615 * @data: Data to write
1618 qla2x00_write_flash_byte(scsi_qla_host_t
*ha
, uint32_t addr
, uint8_t data
)
1620 uint16_t bank_select
;
1621 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1623 bank_select
= RD_REG_WORD(®
->ctrl_status
);
1624 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
1625 /* Specify 64K address range: */
1626 /* clear out Module Select and Flash Address bits [19:16]. */
1627 bank_select
&= ~0xf8;
1628 bank_select
|= addr
>> 12 & 0xf0;
1629 bank_select
|= CSR_FLASH_64K_BANK
;
1630 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1631 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1633 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1634 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1635 WRT_REG_WORD(®
->flash_data
, (uint16_t)data
);
1636 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1641 /* Setup bit 16 of flash address. */
1642 if ((addr
& BIT_16
) && ((bank_select
& CSR_FLASH_64K_BANK
) == 0)) {
1643 bank_select
|= CSR_FLASH_64K_BANK
;
1644 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1645 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1646 } else if (((addr
& BIT_16
) == 0) &&
1647 (bank_select
& CSR_FLASH_64K_BANK
)) {
1648 bank_select
&= ~(CSR_FLASH_64K_BANK
);
1649 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1650 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1653 /* Always perform IO mapped accesses to the FLASH registers. */
1654 if (ha
->pio_address
) {
1655 WRT_REG_WORD_PIO(PIO_REG(ha
, flash_address
), (uint16_t)addr
);
1656 WRT_REG_WORD_PIO(PIO_REG(ha
, flash_data
), (uint16_t)data
);
1658 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1659 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1660 WRT_REG_WORD(®
->flash_data
, (uint16_t)data
);
1661 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1666 * qla2x00_poll_flash() - Polls flash for completion.
1668 * @addr: Address in flash to poll
1669 * @poll_data: Data to be polled
1670 * @man_id: Flash manufacturer ID
1671 * @flash_id: Flash ID
1673 * This function polls the device until bit 7 of what is read matches data
1674 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1675 * out (a fatal error). The flash book recommeds reading bit 7 again after
1676 * reading bit 5 as a 1.
1678 * Returns 0 on success, else non-zero.
1681 qla2x00_poll_flash(scsi_qla_host_t
*ha
, uint32_t addr
, uint8_t poll_data
,
1682 uint8_t man_id
, uint8_t flash_id
)
1690 /* Wait for 30 seconds for command to finish. */
1692 for (cnt
= 3000000; cnt
; cnt
--) {
1693 flash_data
= qla2x00_read_flash_byte(ha
, addr
);
1694 if ((flash_data
& BIT_7
) == poll_data
) {
1699 if (man_id
!= 0x40 && man_id
!= 0xda) {
1700 if ((flash_data
& BIT_5
) && cnt
> 2)
1711 * qla2x00_program_flash_address() - Programs a flash address
1713 * @addr: Address in flash to program
1714 * @data: Data to be written in flash
1715 * @man_id: Flash manufacturer ID
1716 * @flash_id: Flash ID
1718 * Returns 0 on success, else non-zero.
1721 qla2x00_program_flash_address(scsi_qla_host_t
*ha
, uint32_t addr
, uint8_t data
,
1722 uint8_t man_id
, uint8_t flash_id
)
1724 /* Write Program Command Sequence. */
1725 if (IS_OEM_001(ha
)) {
1726 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1727 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1728 qla2x00_write_flash_byte(ha
, 0xaaa, 0xa0);
1729 qla2x00_write_flash_byte(ha
, addr
, data
);
1731 if (man_id
== 0xda && flash_id
== 0xc1) {
1732 qla2x00_write_flash_byte(ha
, addr
, data
);
1736 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1737 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1738 qla2x00_write_flash_byte(ha
, 0x5555, 0xa0);
1739 qla2x00_write_flash_byte(ha
, addr
, data
);
1745 /* Wait for write to complete. */
1746 return qla2x00_poll_flash(ha
, addr
, data
, man_id
, flash_id
);
1750 * qla2x00_erase_flash() - Erase the flash.
1752 * @man_id: Flash manufacturer ID
1753 * @flash_id: Flash ID
1755 * Returns 0 on success, else non-zero.
1758 qla2x00_erase_flash(scsi_qla_host_t
*ha
, uint8_t man_id
, uint8_t flash_id
)
1760 /* Individual Sector Erase Command Sequence */
1761 if (IS_OEM_001(ha
)) {
1762 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1763 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1764 qla2x00_write_flash_byte(ha
, 0xaaa, 0x80);
1765 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1766 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1767 qla2x00_write_flash_byte(ha
, 0xaaa, 0x10);
1769 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1770 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1771 qla2x00_write_flash_byte(ha
, 0x5555, 0x80);
1772 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1773 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1774 qla2x00_write_flash_byte(ha
, 0x5555, 0x10);
1779 /* Wait for erase to complete. */
1780 return qla2x00_poll_flash(ha
, 0x00, 0x80, man_id
, flash_id
);
1784 * qla2x00_erase_flash_sector() - Erase a flash sector.
1786 * @addr: Flash sector to erase
1787 * @sec_mask: Sector address mask
1788 * @man_id: Flash manufacturer ID
1789 * @flash_id: Flash ID
1791 * Returns 0 on success, else non-zero.
1794 qla2x00_erase_flash_sector(scsi_qla_host_t
*ha
, uint32_t addr
,
1795 uint32_t sec_mask
, uint8_t man_id
, uint8_t flash_id
)
1797 /* Individual Sector Erase Command Sequence */
1798 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1799 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1800 qla2x00_write_flash_byte(ha
, 0x5555, 0x80);
1801 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1802 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1803 if (man_id
== 0x1f && flash_id
== 0x13)
1804 qla2x00_write_flash_byte(ha
, addr
& sec_mask
, 0x10);
1806 qla2x00_write_flash_byte(ha
, addr
& sec_mask
, 0x30);
1810 /* Wait for erase to complete. */
1811 return qla2x00_poll_flash(ha
, addr
, 0x80, man_id
, flash_id
);
1815 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1816 * @man_id: Flash manufacturer ID
1817 * @flash_id: Flash ID
1820 qla2x00_get_flash_manufacturer(scsi_qla_host_t
*ha
, uint8_t *man_id
,
1823 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1824 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1825 qla2x00_write_flash_byte(ha
, 0x5555, 0x90);
1826 *man_id
= qla2x00_read_flash_byte(ha
, 0x0000);
1827 *flash_id
= qla2x00_read_flash_byte(ha
, 0x0001);
1828 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1829 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1830 qla2x00_write_flash_byte(ha
, 0x5555, 0xf0);
1834 qla2x00_read_flash_data(scsi_qla_host_t
*ha
, uint8_t *tmp_buf
, uint32_t saddr
,
1837 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1838 uint32_t midpoint
, ilength
;
1841 midpoint
= length
/ 2;
1843 WRT_REG_WORD(®
->nvram
, 0);
1844 RD_REG_WORD(®
->nvram
);
1845 for (ilength
= 0; ilength
< length
; saddr
++, ilength
++, tmp_buf
++) {
1846 if (ilength
== midpoint
) {
1847 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
1848 RD_REG_WORD(®
->nvram
);
1850 data
= qla2x00_read_flash_byte(ha
, saddr
);
1859 qla2x00_suspend_hba(struct scsi_qla_host
*ha
)
1862 unsigned long flags
;
1863 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1866 scsi_block_requests(ha
->host
);
1867 ha
->isp_ops
->disable_intrs(ha
);
1868 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
1871 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1872 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
1873 RD_REG_WORD(®
->hccr
);
1874 if (IS_QLA2100(ha
) || IS_QLA2200(ha
) || IS_QLA2300(ha
)) {
1875 for (cnt
= 0; cnt
< 30000; cnt
++) {
1876 if ((RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) != 0)
1883 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1887 qla2x00_resume_hba(struct scsi_qla_host
*ha
)
1890 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
1891 set_bit(ISP_ABORT_NEEDED
, &ha
->dpc_flags
);
1892 qla2xxx_wake_dpc(ha
);
1893 qla2x00_wait_for_hba_online(ha
);
1894 scsi_unblock_requests(ha
->host
);
1898 qla2x00_read_optrom_data(struct scsi_qla_host
*ha
, uint8_t *buf
,
1899 uint32_t offset
, uint32_t length
)
1901 uint32_t addr
, midpoint
;
1903 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1906 qla2x00_suspend_hba(ha
);
1909 midpoint
= ha
->optrom_size
/ 2;
1911 qla2x00_flash_enable(ha
);
1912 WRT_REG_WORD(®
->nvram
, 0);
1913 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
1914 for (addr
= offset
, data
= buf
; addr
< length
; addr
++, data
++) {
1915 if (addr
== midpoint
) {
1916 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
1917 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
1920 *data
= qla2x00_read_flash_byte(ha
, addr
);
1922 qla2x00_flash_disable(ha
);
1925 qla2x00_resume_hba(ha
);
1931 qla2x00_write_optrom_data(struct scsi_qla_host
*ha
, uint8_t *buf
,
1932 uint32_t offset
, uint32_t length
)
1936 uint8_t man_id
, flash_id
, sec_number
, data
;
1938 uint32_t addr
, liter
, sec_mask
, rest_addr
;
1939 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1942 qla2x00_suspend_hba(ha
);
1947 /* Reset ISP chip. */
1948 WRT_REG_WORD(®
->ctrl_status
, CSR_ISP_SOFT_RESET
);
1949 pci_read_config_word(ha
->pdev
, PCI_COMMAND
, &wd
);
1951 /* Go with write. */
1952 qla2x00_flash_enable(ha
);
1953 do { /* Loop once to provide quick error exit */
1954 /* Structure of flash memory based on manufacturer */
1955 if (IS_OEM_001(ha
)) {
1956 /* OEM variant with special flash part. */
1957 man_id
= flash_id
= 0;
1962 qla2x00_get_flash_manufacturer(ha
, &man_id
, &flash_id
);
1964 case 0x20: /* ST flash. */
1965 if (flash_id
== 0xd2 || flash_id
== 0xe3) {
1967 * ST m29w008at part - 64kb sector size with
1968 * 32kb,8kb,8kb,16kb sectors at memory address
1976 * ST m29w010b part - 16kb sector size
1977 * Default to 16kb sectors
1982 case 0x40: /* Mostel flash. */
1983 /* Mostel v29c51001 part - 512 byte sector size. */
1987 case 0xbf: /* SST flash. */
1988 /* SST39sf10 part - 4kb sector size. */
1992 case 0xda: /* Winbond flash. */
1993 /* Winbond W29EE011 part - 256 byte sector size. */
1997 case 0xc2: /* Macronix flash. */
1998 /* 64k sector size. */
1999 if (flash_id
== 0x38 || flash_id
== 0x4f) {
2004 /* Fall through... */
2006 case 0x1f: /* Atmel flash. */
2007 /* 512k sector size. */
2008 if (flash_id
== 0x13) {
2009 rest_addr
= 0x7fffffff;
2010 sec_mask
= 0x80000000;
2013 /* Fall through... */
2015 case 0x01: /* AMD flash. */
2016 if (flash_id
== 0x38 || flash_id
== 0x40 ||
2018 /* Am29LV081 part - 64kb sector size. */
2019 /* Am29LV002BT part - 64kb sector size. */
2023 } else if (flash_id
== 0x3e) {
2025 * Am29LV008b part - 64kb sector size with
2026 * 32kb,8kb,8kb,16kb sector at memory address
2032 } else if (flash_id
== 0x20 || flash_id
== 0x6e) {
2034 * Am29LV010 part or AM29f010 - 16kb sector
2040 } else if (flash_id
== 0x6d) {
2041 /* Am29LV001 part - 8kb sector size. */
2047 /* Default to 16 kb sector size. */
2054 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
2055 if (qla2x00_erase_flash(ha
, man_id
, flash_id
)) {
2056 rval
= QLA_FUNCTION_FAILED
;
2061 for (addr
= offset
, liter
= 0; liter
< length
; liter
++,
2064 /* Are we at the beginning of a sector? */
2065 if ((addr
& rest_addr
) == 0) {
2066 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
2067 if (addr
>= 0x10000UL
) {
2068 if (((addr
>> 12) & 0xf0) &&
2070 flash_id
== 0x3e) ||
2072 flash_id
== 0xd2))) {
2074 if (sec_number
== 1) {
2095 } else if (addr
== ha
->optrom_size
/ 2) {
2096 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
2097 RD_REG_WORD(®
->nvram
);
2100 if (flash_id
== 0xda && man_id
== 0xc1) {
2101 qla2x00_write_flash_byte(ha
, 0x5555,
2103 qla2x00_write_flash_byte(ha
, 0x2aaa,
2105 qla2x00_write_flash_byte(ha
, 0x5555,
2107 } else if (!IS_QLA2322(ha
) && !IS_QLA6322(ha
)) {
2109 if (qla2x00_erase_flash_sector(ha
,
2110 addr
, sec_mask
, man_id
,
2112 rval
= QLA_FUNCTION_FAILED
;
2115 if (man_id
== 0x01 && flash_id
== 0x6d)
2120 if (man_id
== 0x01 && flash_id
== 0x6d) {
2121 if (sec_number
== 1 &&
2122 addr
== (rest_addr
- 1)) {
2125 } else if (sec_number
== 3 && (addr
& 0x7ffe)) {
2131 if (qla2x00_program_flash_address(ha
, addr
, data
,
2132 man_id
, flash_id
)) {
2133 rval
= QLA_FUNCTION_FAILED
;
2139 qla2x00_flash_disable(ha
);
2142 qla2x00_resume_hba(ha
);
2148 qla24xx_read_optrom_data(struct scsi_qla_host
*ha
, uint8_t *buf
,
2149 uint32_t offset
, uint32_t length
)
2152 scsi_block_requests(ha
->host
);
2153 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2156 qla24xx_read_flash_data(ha
, (uint32_t *)buf
, offset
>> 2, length
>> 2);
2159 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2160 scsi_unblock_requests(ha
->host
);
2166 qla24xx_write_optrom_data(struct scsi_qla_host
*ha
, uint8_t *buf
,
2167 uint32_t offset
, uint32_t length
)
2172 scsi_block_requests(ha
->host
);
2173 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2175 /* Go with write. */
2176 rval
= qla24xx_write_flash_data(ha
, (uint32_t *)buf
, offset
>> 2,
2179 /* Resume HBA -- RISC reset needed. */
2180 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2181 set_bit(ISP_ABORT_NEEDED
, &ha
->dpc_flags
);
2182 qla2xxx_wake_dpc(ha
);
2183 qla2x00_wait_for_hba_online(ha
);
2184 scsi_unblock_requests(ha
->host
);
2190 qla25xx_read_optrom_data(struct scsi_qla_host
*ha
, uint8_t *buf
,
2191 uint32_t offset
, uint32_t length
)
2194 dma_addr_t optrom_dma
;
2197 uint32_t faddr
, left
, burst
;
2201 if (length
< OPTROM_BURST_SIZE
)
2204 optrom
= dma_alloc_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
2205 &optrom_dma
, GFP_KERNEL
);
2207 qla_printk(KERN_DEBUG
, ha
,
2208 "Unable to allocate memory for optrom burst read "
2209 "(%x KB).\n", OPTROM_BURST_SIZE
/ 1024);
2215 faddr
= offset
>> 2;
2217 burst
= OPTROM_BURST_DWORDS
;
2222 rval
= qla2x00_dump_ram(ha
, optrom_dma
,
2223 flash_data_to_access_addr(faddr
), burst
);
2225 qla_printk(KERN_WARNING
, ha
,
2226 "Unable to burst-read optrom segment "
2227 "(%x/%x/%llx).\n", rval
,
2228 flash_data_to_access_addr(faddr
),
2229 (unsigned long long)optrom_dma
);
2230 qla_printk(KERN_WARNING
, ha
,
2231 "Reverting to slow-read.\n");
2233 dma_free_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
2234 optrom
, optrom_dma
);
2238 memcpy(pbuf
, optrom
, burst
* 4);
2245 dma_free_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
, optrom
,
2251 return qla24xx_read_optrom_data(ha
, buf
, offset
, length
);
2255 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2257 * @pcids: Pointer to the FCODE PCI data structure
2259 * The process of retrieving the FCODE version information is at best
2260 * described as interesting.
2262 * Within the first 100h bytes of the image an ASCII string is present
2263 * which contains several pieces of information including the FCODE
2264 * version. Unfortunately it seems the only reliable way to retrieve
2265 * the version is by scanning for another sentinel within the string,
2266 * the FCODE build date:
2268 * ... 2.00.02 10/17/02 ...
2270 * Returns QLA_SUCCESS on successful retrieval of version.
2273 qla2x00_get_fcode_version(scsi_qla_host_t
*ha
, uint32_t pcids
)
2275 int ret
= QLA_FUNCTION_FAILED
;
2276 uint32_t istart
, iend
, iter
, vend
;
2277 uint8_t do_next
, rbyte
, *vbyte
;
2279 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2281 /* Skip the PCI data structure. */
2283 ((qla2x00_read_flash_byte(ha
, pcids
+ 0x0B) << 8) |
2284 qla2x00_read_flash_byte(ha
, pcids
+ 0x0A));
2285 iend
= istart
+ 0x100;
2287 /* Scan for the sentinel date string...eeewww. */
2290 while ((iter
< iend
) && !do_next
) {
2292 if (qla2x00_read_flash_byte(ha
, iter
) == '/') {
2293 if (qla2x00_read_flash_byte(ha
, iter
+ 2) ==
2296 else if (qla2x00_read_flash_byte(ha
,
2304 /* Backtrack to previous ' ' (space). */
2306 while ((iter
> istart
) && !do_next
) {
2308 if (qla2x00_read_flash_byte(ha
, iter
) == ' ')
2315 * Mark end of version tag, and find previous ' ' (space) or
2316 * string length (recent FCODE images -- major hack ahead!!!).
2320 while ((iter
> istart
) && !do_next
) {
2322 rbyte
= qla2x00_read_flash_byte(ha
, iter
);
2323 if (rbyte
== ' ' || rbyte
== 0xd || rbyte
== 0x10)
2329 /* Mark beginning of version tag, and copy data. */
2331 if ((vend
- iter
) &&
2332 ((vend
- iter
) < sizeof(ha
->fcode_revision
))) {
2333 vbyte
= ha
->fcode_revision
;
2334 while (iter
<= vend
) {
2335 *vbyte
++ = qla2x00_read_flash_byte(ha
, iter
);
2342 if (ret
!= QLA_SUCCESS
)
2343 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2347 qla2x00_get_flash_version(scsi_qla_host_t
*ha
, void *mbuf
)
2349 int ret
= QLA_SUCCESS
;
2350 uint8_t code_type
, last_image
;
2351 uint32_t pcihdr
, pcids
;
2355 if (!ha
->pio_address
|| !mbuf
)
2356 return QLA_FUNCTION_FAILED
;
2358 memset(ha
->bios_revision
, 0, sizeof(ha
->bios_revision
));
2359 memset(ha
->efi_revision
, 0, sizeof(ha
->efi_revision
));
2360 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2361 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2363 qla2x00_flash_enable(ha
);
2365 /* Begin with first PCI expansion ROM header. */
2369 /* Verify PCI expansion ROM header. */
2370 if (qla2x00_read_flash_byte(ha
, pcihdr
) != 0x55 ||
2371 qla2x00_read_flash_byte(ha
, pcihdr
+ 0x01) != 0xaa) {
2373 DEBUG2(printk("scsi(%ld): No matching ROM "
2374 "signature.\n", ha
->host_no
));
2375 ret
= QLA_FUNCTION_FAILED
;
2379 /* Locate PCI data structure. */
2381 ((qla2x00_read_flash_byte(ha
, pcihdr
+ 0x19) << 8) |
2382 qla2x00_read_flash_byte(ha
, pcihdr
+ 0x18));
2384 /* Validate signature of PCI data structure. */
2385 if (qla2x00_read_flash_byte(ha
, pcids
) != 'P' ||
2386 qla2x00_read_flash_byte(ha
, pcids
+ 0x1) != 'C' ||
2387 qla2x00_read_flash_byte(ha
, pcids
+ 0x2) != 'I' ||
2388 qla2x00_read_flash_byte(ha
, pcids
+ 0x3) != 'R') {
2389 /* Incorrect header. */
2390 DEBUG2(printk("%s(): PCI data struct not found "
2391 "pcir_adr=%x.\n", __func__
, pcids
));
2392 ret
= QLA_FUNCTION_FAILED
;
2397 code_type
= qla2x00_read_flash_byte(ha
, pcids
+ 0x14);
2398 switch (code_type
) {
2399 case ROM_CODE_TYPE_BIOS
:
2400 /* Intel x86, PC-AT compatible. */
2401 ha
->bios_revision
[0] =
2402 qla2x00_read_flash_byte(ha
, pcids
+ 0x12);
2403 ha
->bios_revision
[1] =
2404 qla2x00_read_flash_byte(ha
, pcids
+ 0x13);
2405 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__
,
2406 ha
->bios_revision
[1], ha
->bios_revision
[0]));
2408 case ROM_CODE_TYPE_FCODE
:
2409 /* Open Firmware standard for PCI (FCode). */
2411 qla2x00_get_fcode_version(ha
, pcids
);
2413 case ROM_CODE_TYPE_EFI
:
2414 /* Extensible Firmware Interface (EFI). */
2415 ha
->efi_revision
[0] =
2416 qla2x00_read_flash_byte(ha
, pcids
+ 0x12);
2417 ha
->efi_revision
[1] =
2418 qla2x00_read_flash_byte(ha
, pcids
+ 0x13);
2419 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__
,
2420 ha
->efi_revision
[1], ha
->efi_revision
[0]));
2423 DEBUG2(printk("%s(): Unrecognized code type %x at "
2424 "pcids %x.\n", __func__
, code_type
, pcids
));
2428 last_image
= qla2x00_read_flash_byte(ha
, pcids
+ 0x15) & BIT_7
;
2430 /* Locate next PCI expansion ROM. */
2431 pcihdr
+= ((qla2x00_read_flash_byte(ha
, pcids
+ 0x11) << 8) |
2432 qla2x00_read_flash_byte(ha
, pcids
+ 0x10)) * 512;
2433 } while (!last_image
);
2435 if (IS_QLA2322(ha
)) {
2436 /* Read firmware image information. */
2437 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2439 memset(dbyte
, 0, 8);
2440 dcode
= (uint16_t *)dbyte
;
2442 qla2x00_read_flash_data(ha
, dbyte
, ha
->flt_region_fw
* 4 + 10,
2444 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n",
2445 __func__
, ha
->host_no
));
2446 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte
, 8));
2448 if ((dcode
[0] == 0xffff && dcode
[1] == 0xffff &&
2449 dcode
[2] == 0xffff && dcode
[3] == 0xffff) ||
2450 (dcode
[0] == 0 && dcode
[1] == 0 && dcode
[2] == 0 &&
2452 DEBUG2(printk("%s(): Unrecognized fw revision at "
2453 "%x.\n", __func__
, ha
->flt_region_fw
* 4));
2455 /* values are in big endian */
2456 ha
->fw_revision
[0] = dbyte
[0] << 16 | dbyte
[1];
2457 ha
->fw_revision
[1] = dbyte
[2] << 16 | dbyte
[3];
2458 ha
->fw_revision
[2] = dbyte
[4] << 16 | dbyte
[5];
2462 qla2x00_flash_disable(ha
);
2468 qla24xx_get_flash_version(scsi_qla_host_t
*ha
, void *mbuf
)
2470 int ret
= QLA_SUCCESS
;
2471 uint32_t pcihdr
, pcids
;
2474 uint8_t code_type
, last_image
;
2478 return QLA_FUNCTION_FAILED
;
2480 memset(ha
->bios_revision
, 0, sizeof(ha
->bios_revision
));
2481 memset(ha
->efi_revision
, 0, sizeof(ha
->efi_revision
));
2482 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2483 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2487 /* Begin with first PCI expansion ROM header. */
2488 pcihdr
= ha
->flt_region_boot
;
2491 /* Verify PCI expansion ROM header. */
2492 qla24xx_read_flash_data(ha
, dcode
, pcihdr
>> 2, 0x20);
2493 bcode
= mbuf
+ (pcihdr
% 4);
2494 if (bcode
[0x0] != 0x55 || bcode
[0x1] != 0xaa) {
2496 DEBUG2(printk("scsi(%ld): No matching ROM "
2497 "signature.\n", ha
->host_no
));
2498 ret
= QLA_FUNCTION_FAILED
;
2502 /* Locate PCI data structure. */
2503 pcids
= pcihdr
+ ((bcode
[0x19] << 8) | bcode
[0x18]);
2505 qla24xx_read_flash_data(ha
, dcode
, pcids
>> 2, 0x20);
2506 bcode
= mbuf
+ (pcihdr
% 4);
2508 /* Validate signature of PCI data structure. */
2509 if (bcode
[0x0] != 'P' || bcode
[0x1] != 'C' ||
2510 bcode
[0x2] != 'I' || bcode
[0x3] != 'R') {
2511 /* Incorrect header. */
2512 DEBUG2(printk("%s(): PCI data struct not found "
2513 "pcir_adr=%x.\n", __func__
, pcids
));
2514 ret
= QLA_FUNCTION_FAILED
;
2519 code_type
= bcode
[0x14];
2520 switch (code_type
) {
2521 case ROM_CODE_TYPE_BIOS
:
2522 /* Intel x86, PC-AT compatible. */
2523 ha
->bios_revision
[0] = bcode
[0x12];
2524 ha
->bios_revision
[1] = bcode
[0x13];
2525 DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__
,
2526 ha
->bios_revision
[1], ha
->bios_revision
[0]));
2528 case ROM_CODE_TYPE_FCODE
:
2529 /* Open Firmware standard for PCI (FCode). */
2530 ha
->fcode_revision
[0] = bcode
[0x12];
2531 ha
->fcode_revision
[1] = bcode
[0x13];
2532 DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__
,
2533 ha
->fcode_revision
[1], ha
->fcode_revision
[0]));
2535 case ROM_CODE_TYPE_EFI
:
2536 /* Extensible Firmware Interface (EFI). */
2537 ha
->efi_revision
[0] = bcode
[0x12];
2538 ha
->efi_revision
[1] = bcode
[0x13];
2539 DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__
,
2540 ha
->efi_revision
[1], ha
->efi_revision
[0]));
2543 DEBUG2(printk("%s(): Unrecognized code type %x at "
2544 "pcids %x.\n", __func__
, code_type
, pcids
));
2548 last_image
= bcode
[0x15] & BIT_7
;
2550 /* Locate next PCI expansion ROM. */
2551 pcihdr
+= ((bcode
[0x11] << 8) | bcode
[0x10]) * 512;
2552 } while (!last_image
);
2554 /* Read firmware image information. */
2555 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2558 qla24xx_read_flash_data(ha
, dcode
, ha
->flt_region_fw
+ 4, 4);
2559 for (i
= 0; i
< 4; i
++)
2560 dcode
[i
] = be32_to_cpu(dcode
[i
]);
2562 if ((dcode
[0] == 0xffffffff && dcode
[1] == 0xffffffff &&
2563 dcode
[2] == 0xffffffff && dcode
[3] == 0xffffffff) ||
2564 (dcode
[0] == 0 && dcode
[1] == 0 && dcode
[2] == 0 &&
2566 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n",
2567 __func__
, ha
->flt_region_fw
));
2569 ha
->fw_revision
[0] = dcode
[0];
2570 ha
->fw_revision
[1] = dcode
[1];
2571 ha
->fw_revision
[2] = dcode
[2];
2572 ha
->fw_revision
[3] = dcode
[3];
2579 qla2xxx_is_vpd_valid(uint8_t *pos
, uint8_t *end
)
2581 if (pos
>= end
|| *pos
!= 0x82)
2585 if (pos
>= end
|| *pos
!= 0x90)
2589 if (pos
>= end
|| *pos
!= 0x78)
2596 qla2xxx_get_vpd_field(scsi_qla_host_t
*ha
, char *key
, char *str
, size_t size
)
2598 uint8_t *pos
= ha
->vpd
;
2599 uint8_t *end
= pos
+ ha
->vpd_size
;
2602 if (!IS_FWI2_CAPABLE(ha
) || !qla2xxx_is_vpd_valid(pos
, end
))
2605 while (pos
< end
&& *pos
!= 0x78) {
2606 len
= (*pos
== 0x82) ? pos
[1] : pos
[2];
2608 if (!strncmp(pos
, key
, strlen(key
)))
2611 if (*pos
!= 0x90 && *pos
!= 0x91)
2617 if (pos
< end
- len
&& *pos
!= 0x78)
2618 return snprintf(str
, size
, "%.*s", len
, pos
+ 3);
2624 qla2xxx_hw_event_store(scsi_qla_host_t
*ha
, uint32_t *fdata
)
2626 uint32_t d
[2], faddr
;
2628 /* Locate first empty entry. */
2630 if (ha
->hw_event_ptr
>=
2631 ha
->flt_region_hw_event
+ FA_HW_EVENT_SIZE
) {
2632 DEBUG2(qla_printk(KERN_WARNING
, ha
,
2633 "HW event -- Log Full!\n"));
2634 return QLA_MEMORY_ALLOC_FAILED
;
2637 qla24xx_read_flash_data(ha
, d
, ha
->hw_event_ptr
, 2);
2638 faddr
= flash_data_to_access_addr(ha
->hw_event_ptr
);
2639 ha
->hw_event_ptr
+= FA_HW_EVENT_ENTRY_SIZE
;
2640 if (d
[0] == __constant_cpu_to_le32(0xffffffff) &&
2641 d
[1] == __constant_cpu_to_le32(0xffffffff)) {
2642 qla24xx_unprotect_flash(ha
);
2644 qla24xx_write_flash_dword(ha
, faddr
++,
2645 cpu_to_le32(jiffies
));
2646 qla24xx_write_flash_dword(ha
, faddr
++, 0);
2647 qla24xx_write_flash_dword(ha
, faddr
++, *fdata
++);
2648 qla24xx_write_flash_dword(ha
, faddr
++, *fdata
);
2650 qla24xx_protect_flash(ha
);
2658 qla2xxx_hw_event_log(scsi_qla_host_t
*ha
, uint16_t code
, uint16_t d1
,
2659 uint16_t d2
, uint16_t d3
)
2661 #define QMARK(a, b, c, d) \
2662 cpu_to_le32(LSB(a) << 24 | LSB(b) << 16 | LSB(c) << 8 | LSB(d))
2665 uint32_t marker
[2], fdata
[4];
2667 if (ha
->flt_region_hw_event
== 0)
2668 return QLA_FUNCTION_FAILED
;
2670 DEBUG2(qla_printk(KERN_WARNING
, ha
,
2671 "HW event -- code=%x, d1=%x, d2=%x, d3=%x.\n", code
, d1
, d2
, d3
));
2673 /* If marker not already found, locate or write. */
2674 if (!ha
->flags
.hw_event_marker_found
) {
2675 /* Create marker. */
2676 marker
[0] = QMARK('L', ha
->fw_major_version
,
2677 ha
->fw_minor_version
, ha
->fw_subminor_version
);
2678 marker
[1] = QMARK(QLA_DRIVER_MAJOR_VER
, QLA_DRIVER_MINOR_VER
,
2679 QLA_DRIVER_PATCH_VER
, QLA_DRIVER_BETA_VER
);
2681 /* Locate marker. */
2682 ha
->hw_event_ptr
= ha
->flt_region_hw_event
;
2684 qla24xx_read_flash_data(ha
, fdata
, ha
->hw_event_ptr
,
2686 if (fdata
[0] == __constant_cpu_to_le32(0xffffffff) &&
2687 fdata
[1] == __constant_cpu_to_le32(0xffffffff))
2689 ha
->hw_event_ptr
+= FA_HW_EVENT_ENTRY_SIZE
;
2690 if (ha
->hw_event_ptr
>=
2691 ha
->flt_region_hw_event
+ FA_HW_EVENT_SIZE
) {
2692 DEBUG2(qla_printk(KERN_WARNING
, ha
,
2693 "HW event -- Log Full!\n"));
2694 return QLA_MEMORY_ALLOC_FAILED
;
2696 if (fdata
[2] == marker
[0] && fdata
[3] == marker
[1]) {
2697 ha
->flags
.hw_event_marker_found
= 1;
2701 /* No marker, write it. */
2702 if (!ha
->flags
.hw_event_marker_found
) {
2703 rval
= qla2xxx_hw_event_store(ha
, marker
);
2704 if (rval
!= QLA_SUCCESS
) {
2705 DEBUG2(qla_printk(KERN_WARNING
, ha
,
2706 "HW event -- Failed marker write=%x.!\n",
2710 ha
->flags
.hw_event_marker_found
= 1;
2715 fdata
[0] = cpu_to_le32(code
<< 16 | d1
);
2716 fdata
[1] = cpu_to_le32(d2
<< 16 | d3
);
2717 rval
= qla2xxx_hw_event_store(ha
, fdata
);
2718 if (rval
!= QLA_SUCCESS
) {
2719 DEBUG2(qla_printk(KERN_WARNING
, ha
,
2720 "HW event -- Failed error write=%x.!\n",