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Merge branches 'slab/documentation', 'slab/fixes', 'slob/cleanups' and 'slub/fixes...
[deliverable/linux.git] / drivers / scsi / qla2xxx / qla_sup.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/delay.h>
10 #include <linux/vmalloc.h>
11 #include <asm/uaccess.h>
12
13 /*
14 * NVRAM support routines
15 */
16
17 /**
18 * qla2x00_lock_nvram_access() -
19 * @ha: HA context
20 */
21 static void
22 qla2x00_lock_nvram_access(struct qla_hw_data *ha)
23 {
24 uint16_t data;
25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
26
27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
28 data = RD_REG_WORD(&reg->nvram);
29 while (data & NVR_BUSY) {
30 udelay(100);
31 data = RD_REG_WORD(&reg->nvram);
32 }
33
34 /* Lock resource */
35 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
36 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
37 udelay(5);
38 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
39 while ((data & BIT_0) == 0) {
40 /* Lock failed */
41 udelay(100);
42 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
43 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
44 udelay(5);
45 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
46 }
47 }
48 }
49
50 /**
51 * qla2x00_unlock_nvram_access() -
52 * @ha: HA context
53 */
54 static void
55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
56 {
57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
58
59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
60 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
61 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
62 }
63 }
64
65 /**
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
67 * @ha: HA context
68 * @data: Serial interface selector
69 */
70 static void
71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
72 {
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
74
75 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
76 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
77 NVRAM_DELAY();
78 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_CLOCK |
79 NVR_WRT_ENABLE);
80 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
81 NVRAM_DELAY();
82 WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
83 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
84 NVRAM_DELAY();
85 }
86
87 /**
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
89 * NVRAM.
90 * @ha: HA context
91 * @nv_cmd: NVRAM command
92 *
93 * Bit definitions for NVRAM command:
94 *
95 * Bit 26 = start bit
96 * Bit 25, 24 = opcode
97 * Bit 23-16 = address
98 * Bit 15-0 = write data
99 *
100 * Returns the word read from nvram @addr.
101 */
102 static uint16_t
103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
104 {
105 uint8_t cnt;
106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
107 uint16_t data = 0;
108 uint16_t reg_data;
109
110 /* Send command to NVRAM. */
111 nv_cmd <<= 5;
112 for (cnt = 0; cnt < 11; cnt++) {
113 if (nv_cmd & BIT_31)
114 qla2x00_nv_write(ha, NVR_DATA_OUT);
115 else
116 qla2x00_nv_write(ha, 0);
117 nv_cmd <<= 1;
118 }
119
120 /* Read data from NVRAM. */
121 for (cnt = 0; cnt < 16; cnt++) {
122 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
123 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
124 NVRAM_DELAY();
125 data <<= 1;
126 reg_data = RD_REG_WORD(&reg->nvram);
127 if (reg_data & NVR_DATA_IN)
128 data |= BIT_0;
129 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
130 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
131 NVRAM_DELAY();
132 }
133
134 /* Deselect chip. */
135 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
136 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
137 NVRAM_DELAY();
138
139 return data;
140 }
141
142
143 /**
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
146 * @ha: HA context
147 * @addr: Address in NVRAM to read
148 *
149 * Returns the word read from nvram @addr.
150 */
151 static uint16_t
152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
153 {
154 uint16_t data;
155 uint32_t nv_cmd;
156
157 nv_cmd = addr << 16;
158 nv_cmd |= NV_READ_OP;
159 data = qla2x00_nvram_request(ha, nv_cmd);
160
161 return (data);
162 }
163
164 /**
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
166 * @ha: HA context
167 */
168 static void
169 qla2x00_nv_deselect(struct qla_hw_data *ha)
170 {
171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
172
173 WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
174 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
175 NVRAM_DELAY();
176 }
177
178 /**
179 * qla2x00_write_nvram_word() - Write NVRAM data.
180 * @ha: HA context
181 * @addr: Address in NVRAM to write
182 * @data: word to program
183 */
184 static void
185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
186 {
187 int count;
188 uint16_t word;
189 uint32_t nv_cmd, wait_cnt;
190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
191
192 qla2x00_nv_write(ha, NVR_DATA_OUT);
193 qla2x00_nv_write(ha, 0);
194 qla2x00_nv_write(ha, 0);
195
196 for (word = 0; word < 8; word++)
197 qla2x00_nv_write(ha, NVR_DATA_OUT);
198
199 qla2x00_nv_deselect(ha);
200
201 /* Write data */
202 nv_cmd = (addr << 16) | NV_WRITE_OP;
203 nv_cmd |= data;
204 nv_cmd <<= 5;
205 for (count = 0; count < 27; count++) {
206 if (nv_cmd & BIT_31)
207 qla2x00_nv_write(ha, NVR_DATA_OUT);
208 else
209 qla2x00_nv_write(ha, 0);
210
211 nv_cmd <<= 1;
212 }
213
214 qla2x00_nv_deselect(ha);
215
216 /* Wait for NVRAM to become ready */
217 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
218 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
219 wait_cnt = NVR_WAIT_CNT;
220 do {
221 if (!--wait_cnt) {
222 DEBUG9_10(qla_printk(KERN_WARNING, ha,
223 "NVRAM didn't go ready...\n"));
224 break;
225 }
226 NVRAM_DELAY();
227 word = RD_REG_WORD(&reg->nvram);
228 } while ((word & NVR_DATA_IN) == 0);
229
230 qla2x00_nv_deselect(ha);
231
232 /* Disable writes */
233 qla2x00_nv_write(ha, NVR_DATA_OUT);
234 for (count = 0; count < 10; count++)
235 qla2x00_nv_write(ha, 0);
236
237 qla2x00_nv_deselect(ha);
238 }
239
240 static int
241 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
242 uint16_t data, uint32_t tmo)
243 {
244 int ret, count;
245 uint16_t word;
246 uint32_t nv_cmd;
247 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
248
249 ret = QLA_SUCCESS;
250
251 qla2x00_nv_write(ha, NVR_DATA_OUT);
252 qla2x00_nv_write(ha, 0);
253 qla2x00_nv_write(ha, 0);
254
255 for (word = 0; word < 8; word++)
256 qla2x00_nv_write(ha, NVR_DATA_OUT);
257
258 qla2x00_nv_deselect(ha);
259
260 /* Write data */
261 nv_cmd = (addr << 16) | NV_WRITE_OP;
262 nv_cmd |= data;
263 nv_cmd <<= 5;
264 for (count = 0; count < 27; count++) {
265 if (nv_cmd & BIT_31)
266 qla2x00_nv_write(ha, NVR_DATA_OUT);
267 else
268 qla2x00_nv_write(ha, 0);
269
270 nv_cmd <<= 1;
271 }
272
273 qla2x00_nv_deselect(ha);
274
275 /* Wait for NVRAM to become ready */
276 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
277 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
278 do {
279 NVRAM_DELAY();
280 word = RD_REG_WORD(&reg->nvram);
281 if (!--tmo) {
282 ret = QLA_FUNCTION_FAILED;
283 break;
284 }
285 } while ((word & NVR_DATA_IN) == 0);
286
287 qla2x00_nv_deselect(ha);
288
289 /* Disable writes */
290 qla2x00_nv_write(ha, NVR_DATA_OUT);
291 for (count = 0; count < 10; count++)
292 qla2x00_nv_write(ha, 0);
293
294 qla2x00_nv_deselect(ha);
295
296 return ret;
297 }
298
299 /**
300 * qla2x00_clear_nvram_protection() -
301 * @ha: HA context
302 */
303 static int
304 qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
305 {
306 int ret, stat;
307 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
308 uint32_t word, wait_cnt;
309 uint16_t wprot, wprot_old;
310
311 /* Clear NVRAM write protection. */
312 ret = QLA_FUNCTION_FAILED;
313
314 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
315 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
316 __constant_cpu_to_le16(0x1234), 100000);
317 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 if (stat != QLA_SUCCESS || wprot != 0x1234) {
319 /* Write enable. */
320 qla2x00_nv_write(ha, NVR_DATA_OUT);
321 qla2x00_nv_write(ha, 0);
322 qla2x00_nv_write(ha, 0);
323 for (word = 0; word < 8; word++)
324 qla2x00_nv_write(ha, NVR_DATA_OUT);
325
326 qla2x00_nv_deselect(ha);
327
328 /* Enable protection register. */
329 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
330 qla2x00_nv_write(ha, NVR_PR_ENABLE);
331 qla2x00_nv_write(ha, NVR_PR_ENABLE);
332 for (word = 0; word < 8; word++)
333 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
334
335 qla2x00_nv_deselect(ha);
336
337 /* Clear protection register (ffff is cleared). */
338 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
339 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
341 for (word = 0; word < 8; word++)
342 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
343
344 qla2x00_nv_deselect(ha);
345
346 /* Wait for NVRAM to become ready. */
347 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
348 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
349 wait_cnt = NVR_WAIT_CNT;
350 do {
351 if (!--wait_cnt) {
352 DEBUG9_10(qla_printk(KERN_WARNING, ha,
353 "NVRAM didn't go ready...\n"));
354 break;
355 }
356 NVRAM_DELAY();
357 word = RD_REG_WORD(&reg->nvram);
358 } while ((word & NVR_DATA_IN) == 0);
359
360 if (wait_cnt)
361 ret = QLA_SUCCESS;
362 } else
363 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
364
365 return ret;
366 }
367
368 static void
369 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
370 {
371 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
372 uint32_t word, wait_cnt;
373
374 if (stat != QLA_SUCCESS)
375 return;
376
377 /* Set NVRAM write protection. */
378 /* Write enable. */
379 qla2x00_nv_write(ha, NVR_DATA_OUT);
380 qla2x00_nv_write(ha, 0);
381 qla2x00_nv_write(ha, 0);
382 for (word = 0; word < 8; word++)
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384
385 qla2x00_nv_deselect(ha);
386
387 /* Enable protection register. */
388 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
389 qla2x00_nv_write(ha, NVR_PR_ENABLE);
390 qla2x00_nv_write(ha, NVR_PR_ENABLE);
391 for (word = 0; word < 8; word++)
392 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
393
394 qla2x00_nv_deselect(ha);
395
396 /* Enable protection register. */
397 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
398 qla2x00_nv_write(ha, NVR_PR_ENABLE);
399 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
400 for (word = 0; word < 8; word++)
401 qla2x00_nv_write(ha, NVR_PR_ENABLE);
402
403 qla2x00_nv_deselect(ha);
404
405 /* Wait for NVRAM to become ready. */
406 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
407 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
408 wait_cnt = NVR_WAIT_CNT;
409 do {
410 if (!--wait_cnt) {
411 DEBUG9_10(qla_printk(KERN_WARNING, ha,
412 "NVRAM didn't go ready...\n"));
413 break;
414 }
415 NVRAM_DELAY();
416 word = RD_REG_WORD(&reg->nvram);
417 } while ((word & NVR_DATA_IN) == 0);
418 }
419
420
421 /*****************************************************************************/
422 /* Flash Manipulation Routines */
423 /*****************************************************************************/
424
425 #define OPTROM_BURST_SIZE 0x1000
426 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
427
428 static inline uint32_t
429 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
430 {
431 return ha->flash_conf_off | faddr;
432 }
433
434 static inline uint32_t
435 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
436 {
437 return ha->flash_data_off | faddr;
438 }
439
440 static inline uint32_t
441 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
442 {
443 return ha->nvram_conf_off | naddr;
444 }
445
446 static inline uint32_t
447 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
448 {
449 return ha->nvram_data_off | naddr;
450 }
451
452 static uint32_t
453 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
454 {
455 int rval;
456 uint32_t cnt, data;
457 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
458
459 WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
460 /* Wait for READ cycle to complete. */
461 rval = QLA_SUCCESS;
462 for (cnt = 3000;
463 (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
464 rval == QLA_SUCCESS; cnt--) {
465 if (cnt)
466 udelay(10);
467 else
468 rval = QLA_FUNCTION_TIMEOUT;
469 cond_resched();
470 }
471
472 /* TODO: What happens if we time out? */
473 data = 0xDEADDEAD;
474 if (rval == QLA_SUCCESS)
475 data = RD_REG_DWORD(&reg->flash_data);
476
477 return data;
478 }
479
480 uint32_t *
481 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
482 uint32_t dwords)
483 {
484 uint32_t i;
485 struct qla_hw_data *ha = vha->hw;
486
487 /* Dword reads to flash. */
488 for (i = 0; i < dwords; i++, faddr++)
489 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
490 flash_data_addr(ha, faddr)));
491
492 return dwptr;
493 }
494
495 static int
496 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
497 {
498 int rval;
499 uint32_t cnt;
500 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
501
502 WRT_REG_DWORD(&reg->flash_data, data);
503 RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
504 WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
505 /* Wait for Write cycle to complete. */
506 rval = QLA_SUCCESS;
507 for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
508 rval == QLA_SUCCESS; cnt--) {
509 if (cnt)
510 udelay(10);
511 else
512 rval = QLA_FUNCTION_TIMEOUT;
513 cond_resched();
514 }
515 return rval;
516 }
517
518 static void
519 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
520 uint8_t *flash_id)
521 {
522 uint32_t ids;
523
524 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
525 *man_id = LSB(ids);
526 *flash_id = MSB(ids);
527
528 /* Check if man_id and flash_id are valid. */
529 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
530 /* Read information using 0x9f opcode
531 * Device ID, Mfg ID would be read in the format:
532 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
533 * Example: ATMEL 0x00 01 45 1F
534 * Extract MFG and Dev ID from last two bytes.
535 */
536 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
537 *man_id = LSB(ids);
538 *flash_id = MSB(ids);
539 }
540 }
541
542 static int
543 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
544 {
545 const char *loc, *locations[] = { "DEF", "PCI" };
546 uint32_t pcihdr, pcids;
547 uint32_t *dcode;
548 uint8_t *buf, *bcode, last_image;
549 uint16_t cnt, chksum, *wptr;
550 struct qla_flt_location *fltl;
551 struct qla_hw_data *ha = vha->hw;
552 struct req_que *req = ha->req_q_map[0];
553
554 /*
555 * FLT-location structure resides after the last PCI region.
556 */
557
558 /* Begin with sane defaults. */
559 loc = locations[0];
560 *start = 0;
561 if (IS_QLA24XX_TYPE(ha))
562 *start = FA_FLASH_LAYOUT_ADDR_24;
563 else if (IS_QLA25XX(ha))
564 *start = FA_FLASH_LAYOUT_ADDR;
565 else if (IS_QLA81XX(ha))
566 *start = FA_FLASH_LAYOUT_ADDR_81;
567 /* Begin with first PCI expansion ROM header. */
568 buf = (uint8_t *)req->ring;
569 dcode = (uint32_t *)req->ring;
570 pcihdr = 0;
571 last_image = 1;
572 do {
573 /* Verify PCI expansion ROM header. */
574 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
575 bcode = buf + (pcihdr % 4);
576 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
577 goto end;
578
579 /* Locate PCI data structure. */
580 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
581 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
582 bcode = buf + (pcihdr % 4);
583
584 /* Validate signature of PCI data structure. */
585 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
586 bcode[0x2] != 'I' || bcode[0x3] != 'R')
587 goto end;
588
589 last_image = bcode[0x15] & BIT_7;
590
591 /* Locate next PCI expansion ROM. */
592 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
593 } while (!last_image);
594
595 /* Now verify FLT-location structure. */
596 fltl = (struct qla_flt_location *)req->ring;
597 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
598 sizeof(struct qla_flt_location) >> 2);
599 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
600 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
601 goto end;
602
603 wptr = (uint16_t *)req->ring;
604 cnt = sizeof(struct qla_flt_location) >> 1;
605 for (chksum = 0; cnt; cnt--)
606 chksum += le16_to_cpu(*wptr++);
607 if (chksum) {
608 qla_printk(KERN_ERR, ha,
609 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
610 qla2x00_dump_buffer(buf, sizeof(struct qla_flt_location));
611 return QLA_FUNCTION_FAILED;
612 }
613
614 /* Good data. Use specified location. */
615 loc = locations[1];
616 *start = (le16_to_cpu(fltl->start_hi) << 16 |
617 le16_to_cpu(fltl->start_lo)) >> 2;
618 end:
619 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLTL[%s] = 0x%x.\n", loc, *start));
620 return QLA_SUCCESS;
621 }
622
623 static void
624 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
625 {
626 const char *loc, *locations[] = { "DEF", "FLT" };
627 const uint32_t def_fw[] =
628 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
629 const uint32_t def_boot[] =
630 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
631 const uint32_t def_vpd_nvram[] =
632 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
633 const uint32_t def_vpd0[] =
634 { 0, 0, FA_VPD0_ADDR_81 };
635 const uint32_t def_vpd1[] =
636 { 0, 0, FA_VPD1_ADDR_81 };
637 const uint32_t def_nvram0[] =
638 { 0, 0, FA_NVRAM0_ADDR_81 };
639 const uint32_t def_nvram1[] =
640 { 0, 0, FA_NVRAM1_ADDR_81 };
641 const uint32_t def_fdt[] =
642 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
643 FA_FLASH_DESCR_ADDR_81 };
644 const uint32_t def_npiv_conf0[] =
645 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
646 FA_NPIV_CONF0_ADDR_81 };
647 const uint32_t def_npiv_conf1[] =
648 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
649 FA_NPIV_CONF1_ADDR_81 };
650 uint32_t def;
651 uint16_t *wptr;
652 uint16_t cnt, chksum;
653 uint32_t start;
654 struct qla_flt_header *flt;
655 struct qla_flt_region *region;
656 struct qla_hw_data *ha = vha->hw;
657 struct req_que *req = ha->req_q_map[0];
658
659 ha->flt_region_flt = flt_addr;
660 wptr = (uint16_t *)req->ring;
661 flt = (struct qla_flt_header *)req->ring;
662 region = (struct qla_flt_region *)&flt[1];
663 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
664 flt_addr << 2, OPTROM_BURST_SIZE);
665 if (*wptr == __constant_cpu_to_le16(0xffff))
666 goto no_flash_data;
667 if (flt->version != __constant_cpu_to_le16(1)) {
668 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported FLT detected: "
669 "version=0x%x length=0x%x checksum=0x%x.\n",
670 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
671 le16_to_cpu(flt->checksum)));
672 goto no_flash_data;
673 }
674
675 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
676 for (chksum = 0; cnt; cnt--)
677 chksum += le16_to_cpu(*wptr++);
678 if (chksum) {
679 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FLT detected: "
680 "version=0x%x length=0x%x checksum=0x%x.\n",
681 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
682 chksum));
683 goto no_flash_data;
684 }
685
686 loc = locations[1];
687 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
688 for ( ; cnt; cnt--, region++) {
689 /* Store addresses as DWORD offsets. */
690 start = le32_to_cpu(region->start) >> 2;
691
692 DEBUG3(qla_printk(KERN_DEBUG, ha, "FLT[%02x]: start=0x%x "
693 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code), start,
694 le32_to_cpu(region->end) >> 2, le32_to_cpu(region->size)));
695
696 switch (le32_to_cpu(region->code) & 0xff) {
697 case FLT_REG_FW:
698 ha->flt_region_fw = start;
699 break;
700 case FLT_REG_BOOT_CODE:
701 ha->flt_region_boot = start;
702 break;
703 case FLT_REG_VPD_0:
704 ha->flt_region_vpd_nvram = start;
705 if (ha->flags.port0)
706 ha->flt_region_vpd = start;
707 break;
708 case FLT_REG_VPD_1:
709 if (!ha->flags.port0)
710 ha->flt_region_vpd = start;
711 break;
712 case FLT_REG_NVRAM_0:
713 if (ha->flags.port0)
714 ha->flt_region_nvram = start;
715 break;
716 case FLT_REG_NVRAM_1:
717 if (!ha->flags.port0)
718 ha->flt_region_nvram = start;
719 break;
720 case FLT_REG_FDT:
721 ha->flt_region_fdt = start;
722 break;
723 case FLT_REG_NPIV_CONF_0:
724 if (ha->flags.port0)
725 ha->flt_region_npiv_conf = start;
726 break;
727 case FLT_REG_NPIV_CONF_1:
728 if (!ha->flags.port0)
729 ha->flt_region_npiv_conf = start;
730 break;
731 case FLT_REG_GOLD_FW:
732 ha->flt_region_gold_fw = start;
733 break;
734 }
735 }
736 goto done;
737
738 no_flash_data:
739 /* Use hardcoded defaults. */
740 loc = locations[0];
741 def = 0;
742 if (IS_QLA24XX_TYPE(ha))
743 def = 0;
744 else if (IS_QLA25XX(ha))
745 def = 1;
746 else if (IS_QLA81XX(ha))
747 def = 2;
748 ha->flt_region_fw = def_fw[def];
749 ha->flt_region_boot = def_boot[def];
750 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
751 ha->flt_region_vpd = ha->flags.port0 ?
752 def_vpd0[def]: def_vpd1[def];
753 ha->flt_region_nvram = ha->flags.port0 ?
754 def_nvram0[def]: def_nvram1[def];
755 ha->flt_region_fdt = def_fdt[def];
756 ha->flt_region_npiv_conf = ha->flags.port0 ?
757 def_npiv_conf0[def]: def_npiv_conf1[def];
758 done:
759 DEBUG2(qla_printk(KERN_DEBUG, ha, "FLT[%s]: boot=0x%x fw=0x%x "
760 "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x "
761 "npiv=0x%x.\n", loc, ha->flt_region_boot, ha->flt_region_fw,
762 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
763 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf));
764 }
765
766 static void
767 qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
768 {
769 #define FLASH_BLK_SIZE_4K 0x1000
770 #define FLASH_BLK_SIZE_32K 0x8000
771 #define FLASH_BLK_SIZE_64K 0x10000
772 const char *loc, *locations[] = { "MID", "FDT" };
773 uint16_t cnt, chksum;
774 uint16_t *wptr;
775 struct qla_fdt_layout *fdt;
776 uint8_t man_id, flash_id;
777 uint16_t mid, fid;
778 struct qla_hw_data *ha = vha->hw;
779 struct req_que *req = ha->req_q_map[0];
780
781 wptr = (uint16_t *)req->ring;
782 fdt = (struct qla_fdt_layout *)req->ring;
783 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
784 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
785 if (*wptr == __constant_cpu_to_le16(0xffff))
786 goto no_flash_data;
787 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
788 fdt->sig[3] != 'D')
789 goto no_flash_data;
790
791 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
792 cnt++)
793 chksum += le16_to_cpu(*wptr++);
794 if (chksum) {
795 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent FDT detected: "
796 "checksum=0x%x id=%c version=0x%x.\n", chksum, fdt->sig[0],
797 le16_to_cpu(fdt->version)));
798 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt, sizeof(*fdt)));
799 goto no_flash_data;
800 }
801
802 loc = locations[1];
803 mid = le16_to_cpu(fdt->man_id);
804 fid = le16_to_cpu(fdt->id);
805 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
806 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
807 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
808 if (fdt->unprotect_sec_cmd) {
809 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
810 fdt->unprotect_sec_cmd);
811 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
812 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
813 flash_conf_addr(ha, 0x0336);
814 }
815 goto done;
816 no_flash_data:
817 loc = locations[0];
818 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
819 mid = man_id;
820 fid = flash_id;
821 ha->fdt_wrt_disable = 0x9c;
822 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
823 switch (man_id) {
824 case 0xbf: /* STT flash. */
825 if (flash_id == 0x8e)
826 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
827 else
828 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
829
830 if (flash_id == 0x80)
831 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
832 break;
833 case 0x13: /* ST M25P80. */
834 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
835 break;
836 case 0x1f: /* Atmel 26DF081A. */
837 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
838 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
839 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
840 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
841 break;
842 default:
843 /* Default to 64 kb sector size. */
844 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
845 break;
846 }
847 done:
848 DEBUG2(qla_printk(KERN_DEBUG, ha, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
849 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc, mid, fid,
850 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
851 ha->fdt_unprotect_sec_cmd, ha->fdt_wrt_disable,
852 ha->fdt_block_size));
853 }
854
855 int
856 qla2xxx_get_flash_info(scsi_qla_host_t *vha)
857 {
858 int ret;
859 uint32_t flt_addr;
860 struct qla_hw_data *ha = vha->hw;
861
862 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
863 return QLA_SUCCESS;
864
865 ret = qla2xxx_find_flt_start(vha, &flt_addr);
866 if (ret != QLA_SUCCESS)
867 return ret;
868
869 qla2xxx_get_flt_info(vha, flt_addr);
870 qla2xxx_get_fdt_info(vha);
871
872 return QLA_SUCCESS;
873 }
874
875 void
876 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
877 {
878 #define NPIV_CONFIG_SIZE (16*1024)
879 void *data;
880 uint16_t *wptr;
881 uint16_t cnt, chksum;
882 int i;
883 struct qla_npiv_header hdr;
884 struct qla_npiv_entry *entry;
885 struct qla_hw_data *ha = vha->hw;
886
887 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha))
888 return;
889
890 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
891 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
892 if (hdr.version == __constant_cpu_to_le16(0xffff))
893 return;
894 if (hdr.version != __constant_cpu_to_le16(1)) {
895 DEBUG2(qla_printk(KERN_INFO, ha, "Unsupported NPIV-Config "
896 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
897 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
898 le16_to_cpu(hdr.checksum)));
899 return;
900 }
901
902 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
903 if (!data) {
904 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV-Config: Unable to "
905 "allocate memory.\n"));
906 return;
907 }
908
909 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
910 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
911
912 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
913 sizeof(struct qla_npiv_entry)) >> 1;
914 for (wptr = data, chksum = 0; cnt; cnt--)
915 chksum += le16_to_cpu(*wptr++);
916 if (chksum) {
917 DEBUG2(qla_printk(KERN_INFO, ha, "Inconsistent NPIV-Config "
918 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
919 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
920 chksum));
921 goto done;
922 }
923
924 entry = data + sizeof(struct qla_npiv_header);
925 cnt = le16_to_cpu(hdr.entries);
926 for (i = 0; cnt; cnt--, entry++, i++) {
927 uint16_t flags;
928 struct fc_vport_identifiers vid;
929 struct fc_vport *vport;
930
931 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
932
933 flags = le16_to_cpu(entry->flags);
934 if (flags == 0xffff)
935 continue;
936 if ((flags & BIT_0) == 0)
937 continue;
938
939 memset(&vid, 0, sizeof(vid));
940 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
941 vid.vport_type = FC_PORTTYPE_NPIV;
942 vid.disable = false;
943 vid.port_name = wwn_to_u64(entry->port_name);
944 vid.node_name = wwn_to_u64(entry->node_name);
945
946 DEBUG2(qla_printk(KERN_INFO, ha, "NPIV[%02x]: wwpn=%llx "
947 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
948 vid.port_name, vid.node_name, le16_to_cpu(entry->vf_id),
949 entry->q_qos, entry->f_qos));
950
951 if (i < QLA_PRECONFIG_VPORTS) {
952 vport = fc_vport_create(vha->host, 0, &vid);
953 if (!vport)
954 qla_printk(KERN_INFO, ha,
955 "NPIV-Config: Failed to create vport [%02x]: "
956 "wwpn=%llx wwnn=%llx.\n", cnt,
957 vid.port_name, vid.node_name);
958 }
959 }
960 done:
961 kfree(data);
962 }
963
964 static int
965 qla24xx_unprotect_flash(scsi_qla_host_t *vha)
966 {
967 struct qla_hw_data *ha = vha->hw;
968 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
969
970 if (ha->flags.fac_supported)
971 return qla81xx_fac_do_write_enable(vha, 1);
972
973 /* Enable flash write. */
974 WRT_REG_DWORD(&reg->ctrl_status,
975 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
976 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
977
978 if (!ha->fdt_wrt_disable)
979 goto done;
980
981 /* Disable flash write-protection, first clear SR protection bit */
982 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
983 /* Then write zero again to clear remaining SR bits.*/
984 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
985 done:
986 return QLA_SUCCESS;
987 }
988
989 static int
990 qla24xx_protect_flash(scsi_qla_host_t *vha)
991 {
992 uint32_t cnt;
993 struct qla_hw_data *ha = vha->hw;
994 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
995
996 if (ha->flags.fac_supported)
997 return qla81xx_fac_do_write_enable(vha, 0);
998
999 if (!ha->fdt_wrt_disable)
1000 goto skip_wrt_protect;
1001
1002 /* Enable flash write-protection and wait for completion. */
1003 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1004 ha->fdt_wrt_disable);
1005 for (cnt = 300; cnt &&
1006 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1007 cnt--) {
1008 udelay(10);
1009 }
1010
1011 skip_wrt_protect:
1012 /* Disable flash write. */
1013 WRT_REG_DWORD(&reg->ctrl_status,
1014 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1015 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1016
1017 return QLA_SUCCESS;
1018 }
1019
1020 static int
1021 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1022 {
1023 struct qla_hw_data *ha = vha->hw;
1024 uint32_t start, finish;
1025
1026 if (ha->flags.fac_supported) {
1027 start = fdata >> 2;
1028 finish = start + (ha->fdt_block_size >> 2) - 1;
1029 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1030 start), flash_data_addr(ha, finish));
1031 }
1032
1033 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1034 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1035 ((fdata >> 16) & 0xff));
1036 }
1037
1038 static int
1039 qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1040 uint32_t dwords)
1041 {
1042 int ret;
1043 uint32_t liter;
1044 uint32_t sec_mask, rest_addr;
1045 uint32_t fdata;
1046 dma_addr_t optrom_dma;
1047 void *optrom = NULL;
1048 struct qla_hw_data *ha = vha->hw;
1049
1050 /* Prepare burst-capable write on supported ISPs. */
1051 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && !(faddr & 0xfff) &&
1052 dwords > OPTROM_BURST_DWORDS) {
1053 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1054 &optrom_dma, GFP_KERNEL);
1055 if (!optrom) {
1056 qla_printk(KERN_DEBUG, ha,
1057 "Unable to allocate memory for optrom burst write "
1058 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1059 }
1060 }
1061
1062 rest_addr = (ha->fdt_block_size >> 2) - 1;
1063 sec_mask = ~rest_addr;
1064
1065 ret = qla24xx_unprotect_flash(vha);
1066 if (ret != QLA_SUCCESS) {
1067 qla_printk(KERN_WARNING, ha,
1068 "Unable to unprotect flash for update.\n");
1069 goto done;
1070 }
1071
1072 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1073 fdata = (faddr & sec_mask) << 2;
1074
1075 /* Are we at the beginning of a sector? */
1076 if ((faddr & rest_addr) == 0) {
1077 /* Do sector unprotect. */
1078 if (ha->fdt_unprotect_sec_cmd)
1079 qla24xx_write_flash_dword(ha,
1080 ha->fdt_unprotect_sec_cmd,
1081 (fdata & 0xff00) | ((fdata << 16) &
1082 0xff0000) | ((fdata >> 16) & 0xff));
1083 ret = qla24xx_erase_sector(vha, fdata);
1084 if (ret != QLA_SUCCESS) {
1085 DEBUG9(qla_printk(KERN_WARNING, ha,
1086 "Unable to erase sector: address=%x.\n",
1087 faddr));
1088 break;
1089 }
1090 }
1091
1092 /* Go with burst-write. */
1093 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1094 /* Copy data to DMA'ble buffer. */
1095 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1096
1097 ret = qla2x00_load_ram(vha, optrom_dma,
1098 flash_data_addr(ha, faddr),
1099 OPTROM_BURST_DWORDS);
1100 if (ret != QLA_SUCCESS) {
1101 qla_printk(KERN_WARNING, ha,
1102 "Unable to burst-write optrom segment "
1103 "(%x/%x/%llx).\n", ret,
1104 flash_data_addr(ha, faddr),
1105 (unsigned long long)optrom_dma);
1106 qla_printk(KERN_WARNING, ha,
1107 "Reverting to slow-write.\n");
1108
1109 dma_free_coherent(&ha->pdev->dev,
1110 OPTROM_BURST_SIZE, optrom, optrom_dma);
1111 optrom = NULL;
1112 } else {
1113 liter += OPTROM_BURST_DWORDS - 1;
1114 faddr += OPTROM_BURST_DWORDS - 1;
1115 dwptr += OPTROM_BURST_DWORDS - 1;
1116 continue;
1117 }
1118 }
1119
1120 ret = qla24xx_write_flash_dword(ha,
1121 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1122 if (ret != QLA_SUCCESS) {
1123 DEBUG9(printk("%s(%ld) Unable to program flash "
1124 "address=%x data=%x.\n", __func__,
1125 vha->host_no, faddr, *dwptr));
1126 break;
1127 }
1128
1129 /* Do sector protect. */
1130 if (ha->fdt_unprotect_sec_cmd &&
1131 ((faddr & rest_addr) == rest_addr))
1132 qla24xx_write_flash_dword(ha,
1133 ha->fdt_protect_sec_cmd,
1134 (fdata & 0xff00) | ((fdata << 16) &
1135 0xff0000) | ((fdata >> 16) & 0xff));
1136 }
1137
1138 ret = qla24xx_protect_flash(vha);
1139 if (ret != QLA_SUCCESS)
1140 qla_printk(KERN_WARNING, ha,
1141 "Unable to protect flash after update.\n");
1142 done:
1143 if (optrom)
1144 dma_free_coherent(&ha->pdev->dev,
1145 OPTROM_BURST_SIZE, optrom, optrom_dma);
1146
1147 return ret;
1148 }
1149
1150 uint8_t *
1151 qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1152 uint32_t bytes)
1153 {
1154 uint32_t i;
1155 uint16_t *wptr;
1156 struct qla_hw_data *ha = vha->hw;
1157
1158 /* Word reads to NVRAM via registers. */
1159 wptr = (uint16_t *)buf;
1160 qla2x00_lock_nvram_access(ha);
1161 for (i = 0; i < bytes >> 1; i++, naddr++)
1162 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1163 naddr));
1164 qla2x00_unlock_nvram_access(ha);
1165
1166 return buf;
1167 }
1168
1169 uint8_t *
1170 qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1171 uint32_t bytes)
1172 {
1173 uint32_t i;
1174 uint32_t *dwptr;
1175 struct qla_hw_data *ha = vha->hw;
1176
1177 /* Dword reads to flash. */
1178 dwptr = (uint32_t *)buf;
1179 for (i = 0; i < bytes >> 2; i++, naddr++)
1180 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1181 nvram_data_addr(ha, naddr)));
1182
1183 return buf;
1184 }
1185
1186 int
1187 qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1188 uint32_t bytes)
1189 {
1190 int ret, stat;
1191 uint32_t i;
1192 uint16_t *wptr;
1193 unsigned long flags;
1194 struct qla_hw_data *ha = vha->hw;
1195
1196 ret = QLA_SUCCESS;
1197
1198 spin_lock_irqsave(&ha->hardware_lock, flags);
1199 qla2x00_lock_nvram_access(ha);
1200
1201 /* Disable NVRAM write-protection. */
1202 stat = qla2x00_clear_nvram_protection(ha);
1203
1204 wptr = (uint16_t *)buf;
1205 for (i = 0; i < bytes >> 1; i++, naddr++) {
1206 qla2x00_write_nvram_word(ha, naddr,
1207 cpu_to_le16(*wptr));
1208 wptr++;
1209 }
1210
1211 /* Enable NVRAM write-protection. */
1212 qla2x00_set_nvram_protection(ha, stat);
1213
1214 qla2x00_unlock_nvram_access(ha);
1215 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1216
1217 return ret;
1218 }
1219
1220 int
1221 qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1222 uint32_t bytes)
1223 {
1224 int ret;
1225 uint32_t i;
1226 uint32_t *dwptr;
1227 struct qla_hw_data *ha = vha->hw;
1228 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1229
1230 ret = QLA_SUCCESS;
1231
1232 /* Enable flash write. */
1233 WRT_REG_DWORD(&reg->ctrl_status,
1234 RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
1235 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1236
1237 /* Disable NVRAM write-protection. */
1238 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1239 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1240
1241 /* Dword writes to flash. */
1242 dwptr = (uint32_t *)buf;
1243 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1244 ret = qla24xx_write_flash_dword(ha,
1245 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1246 if (ret != QLA_SUCCESS) {
1247 DEBUG9(qla_printk(KERN_WARNING, ha,
1248 "Unable to program nvram address=%x data=%x.\n",
1249 naddr, *dwptr));
1250 break;
1251 }
1252 }
1253
1254 /* Enable NVRAM write-protection. */
1255 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1256
1257 /* Disable flash write. */
1258 WRT_REG_DWORD(&reg->ctrl_status,
1259 RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
1260 RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
1261
1262 return ret;
1263 }
1264
1265 uint8_t *
1266 qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1267 uint32_t bytes)
1268 {
1269 uint32_t i;
1270 uint32_t *dwptr;
1271 struct qla_hw_data *ha = vha->hw;
1272
1273 /* Dword reads to flash. */
1274 dwptr = (uint32_t *)buf;
1275 for (i = 0; i < bytes >> 2; i++, naddr++)
1276 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1277 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1278
1279 return buf;
1280 }
1281
1282 int
1283 qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1284 uint32_t bytes)
1285 {
1286 struct qla_hw_data *ha = vha->hw;
1287 #define RMW_BUFFER_SIZE (64 * 1024)
1288 uint8_t *dbuf;
1289
1290 dbuf = vmalloc(RMW_BUFFER_SIZE);
1291 if (!dbuf)
1292 return QLA_MEMORY_ALLOC_FAILED;
1293 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1294 RMW_BUFFER_SIZE);
1295 memcpy(dbuf + (naddr << 2), buf, bytes);
1296 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1297 RMW_BUFFER_SIZE);
1298 vfree(dbuf);
1299
1300 return QLA_SUCCESS;
1301 }
1302
1303 static inline void
1304 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1305 {
1306 if (IS_QLA2322(ha)) {
1307 /* Flip all colors. */
1308 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1309 /* Turn off. */
1310 ha->beacon_color_state = 0;
1311 *pflags = GPIO_LED_ALL_OFF;
1312 } else {
1313 /* Turn on. */
1314 ha->beacon_color_state = QLA_LED_ALL_ON;
1315 *pflags = GPIO_LED_RGA_ON;
1316 }
1317 } else {
1318 /* Flip green led only. */
1319 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1320 /* Turn off. */
1321 ha->beacon_color_state = 0;
1322 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1323 } else {
1324 /* Turn on. */
1325 ha->beacon_color_state = QLA_LED_GRN_ON;
1326 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1327 }
1328 }
1329 }
1330
1331 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1332
1333 void
1334 qla2x00_beacon_blink(struct scsi_qla_host *vha)
1335 {
1336 uint16_t gpio_enable;
1337 uint16_t gpio_data;
1338 uint16_t led_color = 0;
1339 unsigned long flags;
1340 struct qla_hw_data *ha = vha->hw;
1341 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1342
1343 spin_lock_irqsave(&ha->hardware_lock, flags);
1344
1345 /* Save the Original GPIOE. */
1346 if (ha->pio_address) {
1347 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1348 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1349 } else {
1350 gpio_enable = RD_REG_WORD(&reg->gpioe);
1351 gpio_data = RD_REG_WORD(&reg->gpiod);
1352 }
1353
1354 /* Set the modified gpio_enable values */
1355 gpio_enable |= GPIO_LED_MASK;
1356
1357 if (ha->pio_address) {
1358 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1359 } else {
1360 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1361 RD_REG_WORD(&reg->gpioe);
1362 }
1363
1364 qla2x00_flip_colors(ha, &led_color);
1365
1366 /* Clear out any previously set LED color. */
1367 gpio_data &= ~GPIO_LED_MASK;
1368
1369 /* Set the new input LED color to GPIOD. */
1370 gpio_data |= led_color;
1371
1372 /* Set the modified gpio_data values */
1373 if (ha->pio_address) {
1374 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1375 } else {
1376 WRT_REG_WORD(&reg->gpiod, gpio_data);
1377 RD_REG_WORD(&reg->gpiod);
1378 }
1379
1380 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1381 }
1382
1383 int
1384 qla2x00_beacon_on(struct scsi_qla_host *vha)
1385 {
1386 uint16_t gpio_enable;
1387 uint16_t gpio_data;
1388 unsigned long flags;
1389 struct qla_hw_data *ha = vha->hw;
1390 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1391
1392 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1393 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1394
1395 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1396 qla_printk(KERN_WARNING, ha,
1397 "Unable to update fw options (beacon on).\n");
1398 return QLA_FUNCTION_FAILED;
1399 }
1400
1401 /* Turn off LEDs. */
1402 spin_lock_irqsave(&ha->hardware_lock, flags);
1403 if (ha->pio_address) {
1404 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1405 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1406 } else {
1407 gpio_enable = RD_REG_WORD(&reg->gpioe);
1408 gpio_data = RD_REG_WORD(&reg->gpiod);
1409 }
1410 gpio_enable |= GPIO_LED_MASK;
1411
1412 /* Set the modified gpio_enable values. */
1413 if (ha->pio_address) {
1414 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1415 } else {
1416 WRT_REG_WORD(&reg->gpioe, gpio_enable);
1417 RD_REG_WORD(&reg->gpioe);
1418 }
1419
1420 /* Clear out previously set LED colour. */
1421 gpio_data &= ~GPIO_LED_MASK;
1422 if (ha->pio_address) {
1423 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1424 } else {
1425 WRT_REG_WORD(&reg->gpiod, gpio_data);
1426 RD_REG_WORD(&reg->gpiod);
1427 }
1428 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1429
1430 /*
1431 * Let the per HBA timer kick off the blinking process based on
1432 * the following flags. No need to do anything else now.
1433 */
1434 ha->beacon_blink_led = 1;
1435 ha->beacon_color_state = 0;
1436
1437 return QLA_SUCCESS;
1438 }
1439
1440 int
1441 qla2x00_beacon_off(struct scsi_qla_host *vha)
1442 {
1443 int rval = QLA_SUCCESS;
1444 struct qla_hw_data *ha = vha->hw;
1445
1446 ha->beacon_blink_led = 0;
1447
1448 /* Set the on flag so when it gets flipped it will be off. */
1449 if (IS_QLA2322(ha))
1450 ha->beacon_color_state = QLA_LED_ALL_ON;
1451 else
1452 ha->beacon_color_state = QLA_LED_GRN_ON;
1453
1454 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */
1455
1456 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1457 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1458
1459 rval = qla2x00_set_fw_options(vha, ha->fw_options);
1460 if (rval != QLA_SUCCESS)
1461 qla_printk(KERN_WARNING, ha,
1462 "Unable to update fw options (beacon off).\n");
1463 return rval;
1464 }
1465
1466
1467 static inline void
1468 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1469 {
1470 /* Flip all colors. */
1471 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1472 /* Turn off. */
1473 ha->beacon_color_state = 0;
1474 *pflags = 0;
1475 } else {
1476 /* Turn on. */
1477 ha->beacon_color_state = QLA_LED_ALL_ON;
1478 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1479 }
1480 }
1481
1482 void
1483 qla24xx_beacon_blink(struct scsi_qla_host *vha)
1484 {
1485 uint16_t led_color = 0;
1486 uint32_t gpio_data;
1487 unsigned long flags;
1488 struct qla_hw_data *ha = vha->hw;
1489 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1490
1491 /* Save the Original GPIOD. */
1492 spin_lock_irqsave(&ha->hardware_lock, flags);
1493 gpio_data = RD_REG_DWORD(&reg->gpiod);
1494
1495 /* Enable the gpio_data reg for update. */
1496 gpio_data |= GPDX_LED_UPDATE_MASK;
1497
1498 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1499 gpio_data = RD_REG_DWORD(&reg->gpiod);
1500
1501 /* Set the color bits. */
1502 qla24xx_flip_colors(ha, &led_color);
1503
1504 /* Clear out any previously set LED color. */
1505 gpio_data &= ~GPDX_LED_COLOR_MASK;
1506
1507 /* Set the new input LED color to GPIOD. */
1508 gpio_data |= led_color;
1509
1510 /* Set the modified gpio_data values. */
1511 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1512 gpio_data = RD_REG_DWORD(&reg->gpiod);
1513 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1514 }
1515
1516 int
1517 qla24xx_beacon_on(struct scsi_qla_host *vha)
1518 {
1519 uint32_t gpio_data;
1520 unsigned long flags;
1521 struct qla_hw_data *ha = vha->hw;
1522 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1523
1524 if (ha->beacon_blink_led == 0) {
1525 /* Enable firmware for update */
1526 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1527
1528 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1529 return QLA_FUNCTION_FAILED;
1530
1531 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1532 QLA_SUCCESS) {
1533 qla_printk(KERN_WARNING, ha,
1534 "Unable to update fw options (beacon on).\n");
1535 return QLA_FUNCTION_FAILED;
1536 }
1537
1538 spin_lock_irqsave(&ha->hardware_lock, flags);
1539 gpio_data = RD_REG_DWORD(&reg->gpiod);
1540
1541 /* Enable the gpio_data reg for update. */
1542 gpio_data |= GPDX_LED_UPDATE_MASK;
1543 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1544 RD_REG_DWORD(&reg->gpiod);
1545
1546 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1547 }
1548
1549 /* So all colors blink together. */
1550 ha->beacon_color_state = 0;
1551
1552 /* Let the per HBA timer kick off the blinking process. */
1553 ha->beacon_blink_led = 1;
1554
1555 return QLA_SUCCESS;
1556 }
1557
1558 int
1559 qla24xx_beacon_off(struct scsi_qla_host *vha)
1560 {
1561 uint32_t gpio_data;
1562 unsigned long flags;
1563 struct qla_hw_data *ha = vha->hw;
1564 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1565
1566 ha->beacon_blink_led = 0;
1567 ha->beacon_color_state = QLA_LED_ALL_ON;
1568
1569 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */
1570
1571 /* Give control back to firmware. */
1572 spin_lock_irqsave(&ha->hardware_lock, flags);
1573 gpio_data = RD_REG_DWORD(&reg->gpiod);
1574
1575 /* Disable the gpio_data reg for update. */
1576 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1577 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1578 RD_REG_DWORD(&reg->gpiod);
1579 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1580
1581 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1582
1583 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1584 qla_printk(KERN_WARNING, ha,
1585 "Unable to update fw options (beacon off).\n");
1586 return QLA_FUNCTION_FAILED;
1587 }
1588
1589 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1590 qla_printk(KERN_WARNING, ha,
1591 "Unable to get fw options (beacon off).\n");
1592 return QLA_FUNCTION_FAILED;
1593 }
1594
1595 return QLA_SUCCESS;
1596 }
1597
1598
1599 /*
1600 * Flash support routines
1601 */
1602
1603 /**
1604 * qla2x00_flash_enable() - Setup flash for reading and writing.
1605 * @ha: HA context
1606 */
1607 static void
1608 qla2x00_flash_enable(struct qla_hw_data *ha)
1609 {
1610 uint16_t data;
1611 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1612
1613 data = RD_REG_WORD(&reg->ctrl_status);
1614 data |= CSR_FLASH_ENABLE;
1615 WRT_REG_WORD(&reg->ctrl_status, data);
1616 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1617 }
1618
1619 /**
1620 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1621 * @ha: HA context
1622 */
1623 static void
1624 qla2x00_flash_disable(struct qla_hw_data *ha)
1625 {
1626 uint16_t data;
1627 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1628
1629 data = RD_REG_WORD(&reg->ctrl_status);
1630 data &= ~(CSR_FLASH_ENABLE);
1631 WRT_REG_WORD(&reg->ctrl_status, data);
1632 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1633 }
1634
1635 /**
1636 * qla2x00_read_flash_byte() - Reads a byte from flash
1637 * @ha: HA context
1638 * @addr: Address in flash to read
1639 *
1640 * A word is read from the chip, but, only the lower byte is valid.
1641 *
1642 * Returns the byte read from flash @addr.
1643 */
1644 static uint8_t
1645 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1646 {
1647 uint16_t data;
1648 uint16_t bank_select;
1649 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1650
1651 bank_select = RD_REG_WORD(&reg->ctrl_status);
1652
1653 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1654 /* Specify 64K address range: */
1655 /* clear out Module Select and Flash Address bits [19:16]. */
1656 bank_select &= ~0xf8;
1657 bank_select |= addr >> 12 & 0xf0;
1658 bank_select |= CSR_FLASH_64K_BANK;
1659 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1660 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1661
1662 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1663 data = RD_REG_WORD(&reg->flash_data);
1664
1665 return (uint8_t)data;
1666 }
1667
1668 /* Setup bit 16 of flash address. */
1669 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1670 bank_select |= CSR_FLASH_64K_BANK;
1671 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1672 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1673 } else if (((addr & BIT_16) == 0) &&
1674 (bank_select & CSR_FLASH_64K_BANK)) {
1675 bank_select &= ~(CSR_FLASH_64K_BANK);
1676 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1677 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1678 }
1679
1680 /* Always perform IO mapped accesses to the FLASH registers. */
1681 if (ha->pio_address) {
1682 uint16_t data2;
1683
1684 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1685 do {
1686 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1687 barrier();
1688 cpu_relax();
1689 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1690 } while (data != data2);
1691 } else {
1692 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1693 data = qla2x00_debounce_register(&reg->flash_data);
1694 }
1695
1696 return (uint8_t)data;
1697 }
1698
1699 /**
1700 * qla2x00_write_flash_byte() - Write a byte to flash
1701 * @ha: HA context
1702 * @addr: Address in flash to write
1703 * @data: Data to write
1704 */
1705 static void
1706 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1707 {
1708 uint16_t bank_select;
1709 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1710
1711 bank_select = RD_REG_WORD(&reg->ctrl_status);
1712 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1713 /* Specify 64K address range: */
1714 /* clear out Module Select and Flash Address bits [19:16]. */
1715 bank_select &= ~0xf8;
1716 bank_select |= addr >> 12 & 0xf0;
1717 bank_select |= CSR_FLASH_64K_BANK;
1718 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1719 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1720
1721 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1722 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1723 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1724 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1725
1726 return;
1727 }
1728
1729 /* Setup bit 16 of flash address. */
1730 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1731 bank_select |= CSR_FLASH_64K_BANK;
1732 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1733 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1734 } else if (((addr & BIT_16) == 0) &&
1735 (bank_select & CSR_FLASH_64K_BANK)) {
1736 bank_select &= ~(CSR_FLASH_64K_BANK);
1737 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1738 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1739 }
1740
1741 /* Always perform IO mapped accesses to the FLASH registers. */
1742 if (ha->pio_address) {
1743 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1744 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1745 } else {
1746 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1747 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1748 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1749 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1750 }
1751 }
1752
1753 /**
1754 * qla2x00_poll_flash() - Polls flash for completion.
1755 * @ha: HA context
1756 * @addr: Address in flash to poll
1757 * @poll_data: Data to be polled
1758 * @man_id: Flash manufacturer ID
1759 * @flash_id: Flash ID
1760 *
1761 * This function polls the device until bit 7 of what is read matches data
1762 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1763 * out (a fatal error). The flash book recommeds reading bit 7 again after
1764 * reading bit 5 as a 1.
1765 *
1766 * Returns 0 on success, else non-zero.
1767 */
1768 static int
1769 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
1770 uint8_t man_id, uint8_t flash_id)
1771 {
1772 int status;
1773 uint8_t flash_data;
1774 uint32_t cnt;
1775
1776 status = 1;
1777
1778 /* Wait for 30 seconds for command to finish. */
1779 poll_data &= BIT_7;
1780 for (cnt = 3000000; cnt; cnt--) {
1781 flash_data = qla2x00_read_flash_byte(ha, addr);
1782 if ((flash_data & BIT_7) == poll_data) {
1783 status = 0;
1784 break;
1785 }
1786
1787 if (man_id != 0x40 && man_id != 0xda) {
1788 if ((flash_data & BIT_5) && cnt > 2)
1789 cnt = 2;
1790 }
1791 udelay(10);
1792 barrier();
1793 cond_resched();
1794 }
1795 return status;
1796 }
1797
1798 /**
1799 * qla2x00_program_flash_address() - Programs a flash address
1800 * @ha: HA context
1801 * @addr: Address in flash to program
1802 * @data: Data to be written in flash
1803 * @man_id: Flash manufacturer ID
1804 * @flash_id: Flash ID
1805 *
1806 * Returns 0 on success, else non-zero.
1807 */
1808 static int
1809 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
1810 uint8_t data, uint8_t man_id, uint8_t flash_id)
1811 {
1812 /* Write Program Command Sequence. */
1813 if (IS_OEM_001(ha)) {
1814 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1815 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1816 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1817 qla2x00_write_flash_byte(ha, addr, data);
1818 } else {
1819 if (man_id == 0xda && flash_id == 0xc1) {
1820 qla2x00_write_flash_byte(ha, addr, data);
1821 if (addr & 0x7e)
1822 return 0;
1823 } else {
1824 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1825 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1826 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1827 qla2x00_write_flash_byte(ha, addr, data);
1828 }
1829 }
1830
1831 udelay(150);
1832
1833 /* Wait for write to complete. */
1834 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1835 }
1836
1837 /**
1838 * qla2x00_erase_flash() - Erase the flash.
1839 * @ha: HA context
1840 * @man_id: Flash manufacturer ID
1841 * @flash_id: Flash ID
1842 *
1843 * Returns 0 on success, else non-zero.
1844 */
1845 static int
1846 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
1847 {
1848 /* Individual Sector Erase Command Sequence */
1849 if (IS_OEM_001(ha)) {
1850 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1851 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1852 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1853 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1854 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1855 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1856 } else {
1857 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1858 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1859 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1860 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1861 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1862 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1863 }
1864
1865 udelay(150);
1866
1867 /* Wait for erase to complete. */
1868 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1869 }
1870
1871 /**
1872 * qla2x00_erase_flash_sector() - Erase a flash sector.
1873 * @ha: HA context
1874 * @addr: Flash sector to erase
1875 * @sec_mask: Sector address mask
1876 * @man_id: Flash manufacturer ID
1877 * @flash_id: Flash ID
1878 *
1879 * Returns 0 on success, else non-zero.
1880 */
1881 static int
1882 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
1883 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1884 {
1885 /* Individual Sector Erase Command Sequence */
1886 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1887 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1888 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1889 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1890 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1891 if (man_id == 0x1f && flash_id == 0x13)
1892 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1893 else
1894 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1895
1896 udelay(150);
1897
1898 /* Wait for erase to complete. */
1899 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1900 }
1901
1902 /**
1903 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1904 * @man_id: Flash manufacturer ID
1905 * @flash_id: Flash ID
1906 */
1907 static void
1908 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
1909 uint8_t *flash_id)
1910 {
1911 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1912 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1913 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1914 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1915 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1916 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1917 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1918 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1919 }
1920
1921 static void
1922 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
1923 uint32_t saddr, uint32_t length)
1924 {
1925 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1926 uint32_t midpoint, ilength;
1927 uint8_t data;
1928
1929 midpoint = length / 2;
1930
1931 WRT_REG_WORD(&reg->nvram, 0);
1932 RD_REG_WORD(&reg->nvram);
1933 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1934 if (ilength == midpoint) {
1935 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1936 RD_REG_WORD(&reg->nvram);
1937 }
1938 data = qla2x00_read_flash_byte(ha, saddr);
1939 if (saddr % 100)
1940 udelay(10);
1941 *tmp_buf = data;
1942 cond_resched();
1943 }
1944 }
1945
1946 static inline void
1947 qla2x00_suspend_hba(struct scsi_qla_host *vha)
1948 {
1949 int cnt;
1950 unsigned long flags;
1951 struct qla_hw_data *ha = vha->hw;
1952 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1953
1954 /* Suspend HBA. */
1955 scsi_block_requests(vha->host);
1956 ha->isp_ops->disable_intrs(ha);
1957 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1958
1959 /* Pause RISC. */
1960 spin_lock_irqsave(&ha->hardware_lock, flags);
1961 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1962 RD_REG_WORD(&reg->hccr);
1963 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1964 for (cnt = 0; cnt < 30000; cnt++) {
1965 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1966 break;
1967 udelay(100);
1968 }
1969 } else {
1970 udelay(10);
1971 }
1972 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1973 }
1974
1975 static inline void
1976 qla2x00_resume_hba(struct scsi_qla_host *vha)
1977 {
1978 struct qla_hw_data *ha = vha->hw;
1979
1980 /* Resume HBA. */
1981 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1982 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
1983 qla2xxx_wake_dpc(vha);
1984 qla2x00_wait_for_chip_reset(vha);
1985 scsi_unblock_requests(vha->host);
1986 }
1987
1988 uint8_t *
1989 qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
1990 uint32_t offset, uint32_t length)
1991 {
1992 uint32_t addr, midpoint;
1993 uint8_t *data;
1994 struct qla_hw_data *ha = vha->hw;
1995 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1996
1997 /* Suspend HBA. */
1998 qla2x00_suspend_hba(vha);
1999
2000 /* Go with read. */
2001 midpoint = ha->optrom_size / 2;
2002
2003 qla2x00_flash_enable(ha);
2004 WRT_REG_WORD(&reg->nvram, 0);
2005 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2006 for (addr = offset, data = buf; addr < length; addr++, data++) {
2007 if (addr == midpoint) {
2008 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2009 RD_REG_WORD(&reg->nvram); /* PCI Posting. */
2010 }
2011
2012 *data = qla2x00_read_flash_byte(ha, addr);
2013 }
2014 qla2x00_flash_disable(ha);
2015
2016 /* Resume HBA. */
2017 qla2x00_resume_hba(vha);
2018
2019 return buf;
2020 }
2021
2022 int
2023 qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2024 uint32_t offset, uint32_t length)
2025 {
2026
2027 int rval;
2028 uint8_t man_id, flash_id, sec_number, data;
2029 uint16_t wd;
2030 uint32_t addr, liter, sec_mask, rest_addr;
2031 struct qla_hw_data *ha = vha->hw;
2032 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2033
2034 /* Suspend HBA. */
2035 qla2x00_suspend_hba(vha);
2036
2037 rval = QLA_SUCCESS;
2038 sec_number = 0;
2039
2040 /* Reset ISP chip. */
2041 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2042 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2043
2044 /* Go with write. */
2045 qla2x00_flash_enable(ha);
2046 do { /* Loop once to provide quick error exit */
2047 /* Structure of flash memory based on manufacturer */
2048 if (IS_OEM_001(ha)) {
2049 /* OEM variant with special flash part. */
2050 man_id = flash_id = 0;
2051 rest_addr = 0xffff;
2052 sec_mask = 0x10000;
2053 goto update_flash;
2054 }
2055 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2056 switch (man_id) {
2057 case 0x20: /* ST flash. */
2058 if (flash_id == 0xd2 || flash_id == 0xe3) {
2059 /*
2060 * ST m29w008at part - 64kb sector size with
2061 * 32kb,8kb,8kb,16kb sectors at memory address
2062 * 0xf0000.
2063 */
2064 rest_addr = 0xffff;
2065 sec_mask = 0x10000;
2066 break;
2067 }
2068 /*
2069 * ST m29w010b part - 16kb sector size
2070 * Default to 16kb sectors
2071 */
2072 rest_addr = 0x3fff;
2073 sec_mask = 0x1c000;
2074 break;
2075 case 0x40: /* Mostel flash. */
2076 /* Mostel v29c51001 part - 512 byte sector size. */
2077 rest_addr = 0x1ff;
2078 sec_mask = 0x1fe00;
2079 break;
2080 case 0xbf: /* SST flash. */
2081 /* SST39sf10 part - 4kb sector size. */
2082 rest_addr = 0xfff;
2083 sec_mask = 0x1f000;
2084 break;
2085 case 0xda: /* Winbond flash. */
2086 /* Winbond W29EE011 part - 256 byte sector size. */
2087 rest_addr = 0x7f;
2088 sec_mask = 0x1ff80;
2089 break;
2090 case 0xc2: /* Macronix flash. */
2091 /* 64k sector size. */
2092 if (flash_id == 0x38 || flash_id == 0x4f) {
2093 rest_addr = 0xffff;
2094 sec_mask = 0x10000;
2095 break;
2096 }
2097 /* Fall through... */
2098
2099 case 0x1f: /* Atmel flash. */
2100 /* 512k sector size. */
2101 if (flash_id == 0x13) {
2102 rest_addr = 0x7fffffff;
2103 sec_mask = 0x80000000;
2104 break;
2105 }
2106 /* Fall through... */
2107
2108 case 0x01: /* AMD flash. */
2109 if (flash_id == 0x38 || flash_id == 0x40 ||
2110 flash_id == 0x4f) {
2111 /* Am29LV081 part - 64kb sector size. */
2112 /* Am29LV002BT part - 64kb sector size. */
2113 rest_addr = 0xffff;
2114 sec_mask = 0x10000;
2115 break;
2116 } else if (flash_id == 0x3e) {
2117 /*
2118 * Am29LV008b part - 64kb sector size with
2119 * 32kb,8kb,8kb,16kb sector at memory address
2120 * h0xf0000.
2121 */
2122 rest_addr = 0xffff;
2123 sec_mask = 0x10000;
2124 break;
2125 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2126 /*
2127 * Am29LV010 part or AM29f010 - 16kb sector
2128 * size.
2129 */
2130 rest_addr = 0x3fff;
2131 sec_mask = 0x1c000;
2132 break;
2133 } else if (flash_id == 0x6d) {
2134 /* Am29LV001 part - 8kb sector size. */
2135 rest_addr = 0x1fff;
2136 sec_mask = 0x1e000;
2137 break;
2138 }
2139 default:
2140 /* Default to 16 kb sector size. */
2141 rest_addr = 0x3fff;
2142 sec_mask = 0x1c000;
2143 break;
2144 }
2145
2146 update_flash:
2147 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2148 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2149 rval = QLA_FUNCTION_FAILED;
2150 break;
2151 }
2152 }
2153
2154 for (addr = offset, liter = 0; liter < length; liter++,
2155 addr++) {
2156 data = buf[liter];
2157 /* Are we at the beginning of a sector? */
2158 if ((addr & rest_addr) == 0) {
2159 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2160 if (addr >= 0x10000UL) {
2161 if (((addr >> 12) & 0xf0) &&
2162 ((man_id == 0x01 &&
2163 flash_id == 0x3e) ||
2164 (man_id == 0x20 &&
2165 flash_id == 0xd2))) {
2166 sec_number++;
2167 if (sec_number == 1) {
2168 rest_addr =
2169 0x7fff;
2170 sec_mask =
2171 0x18000;
2172 } else if (
2173 sec_number == 2 ||
2174 sec_number == 3) {
2175 rest_addr =
2176 0x1fff;
2177 sec_mask =
2178 0x1e000;
2179 } else if (
2180 sec_number == 4) {
2181 rest_addr =
2182 0x3fff;
2183 sec_mask =
2184 0x1c000;
2185 }
2186 }
2187 }
2188 } else if (addr == ha->optrom_size / 2) {
2189 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
2190 RD_REG_WORD(&reg->nvram);
2191 }
2192
2193 if (flash_id == 0xda && man_id == 0xc1) {
2194 qla2x00_write_flash_byte(ha, 0x5555,
2195 0xaa);
2196 qla2x00_write_flash_byte(ha, 0x2aaa,
2197 0x55);
2198 qla2x00_write_flash_byte(ha, 0x5555,
2199 0xa0);
2200 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2201 /* Then erase it */
2202 if (qla2x00_erase_flash_sector(ha,
2203 addr, sec_mask, man_id,
2204 flash_id)) {
2205 rval = QLA_FUNCTION_FAILED;
2206 break;
2207 }
2208 if (man_id == 0x01 && flash_id == 0x6d)
2209 sec_number++;
2210 }
2211 }
2212
2213 if (man_id == 0x01 && flash_id == 0x6d) {
2214 if (sec_number == 1 &&
2215 addr == (rest_addr - 1)) {
2216 rest_addr = 0x0fff;
2217 sec_mask = 0x1f000;
2218 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2219 rest_addr = 0x3fff;
2220 sec_mask = 0x1c000;
2221 }
2222 }
2223
2224 if (qla2x00_program_flash_address(ha, addr, data,
2225 man_id, flash_id)) {
2226 rval = QLA_FUNCTION_FAILED;
2227 break;
2228 }
2229 cond_resched();
2230 }
2231 } while (0);
2232 qla2x00_flash_disable(ha);
2233
2234 /* Resume HBA. */
2235 qla2x00_resume_hba(vha);
2236
2237 return rval;
2238 }
2239
2240 uint8_t *
2241 qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2242 uint32_t offset, uint32_t length)
2243 {
2244 struct qla_hw_data *ha = vha->hw;
2245
2246 /* Suspend HBA. */
2247 scsi_block_requests(vha->host);
2248 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2249
2250 /* Go with read. */
2251 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2252
2253 /* Resume HBA. */
2254 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2255 scsi_unblock_requests(vha->host);
2256
2257 return buf;
2258 }
2259
2260 int
2261 qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2262 uint32_t offset, uint32_t length)
2263 {
2264 int rval;
2265 struct qla_hw_data *ha = vha->hw;
2266
2267 /* Suspend HBA. */
2268 scsi_block_requests(vha->host);
2269 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2270
2271 /* Go with write. */
2272 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2273 length >> 2);
2274
2275 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2276 scsi_unblock_requests(vha->host);
2277
2278 return rval;
2279 }
2280
2281 uint8_t *
2282 qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2283 uint32_t offset, uint32_t length)
2284 {
2285 int rval;
2286 dma_addr_t optrom_dma;
2287 void *optrom;
2288 uint8_t *pbuf;
2289 uint32_t faddr, left, burst;
2290 struct qla_hw_data *ha = vha->hw;
2291
2292 if (offset & 0xfff)
2293 goto slow_read;
2294 if (length < OPTROM_BURST_SIZE)
2295 goto slow_read;
2296
2297 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2298 &optrom_dma, GFP_KERNEL);
2299 if (!optrom) {
2300 qla_printk(KERN_DEBUG, ha,
2301 "Unable to allocate memory for optrom burst read "
2302 "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
2303
2304 goto slow_read;
2305 }
2306
2307 pbuf = buf;
2308 faddr = offset >> 2;
2309 left = length >> 2;
2310 burst = OPTROM_BURST_DWORDS;
2311 while (left != 0) {
2312 if (burst > left)
2313 burst = left;
2314
2315 rval = qla2x00_dump_ram(vha, optrom_dma,
2316 flash_data_addr(ha, faddr), burst);
2317 if (rval) {
2318 qla_printk(KERN_WARNING, ha,
2319 "Unable to burst-read optrom segment "
2320 "(%x/%x/%llx).\n", rval,
2321 flash_data_addr(ha, faddr),
2322 (unsigned long long)optrom_dma);
2323 qla_printk(KERN_WARNING, ha,
2324 "Reverting to slow-read.\n");
2325
2326 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2327 optrom, optrom_dma);
2328 goto slow_read;
2329 }
2330
2331 memcpy(pbuf, optrom, burst * 4);
2332
2333 left -= burst;
2334 faddr += burst;
2335 pbuf += burst * 4;
2336 }
2337
2338 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2339 optrom_dma);
2340
2341 return buf;
2342
2343 slow_read:
2344 return qla24xx_read_optrom_data(vha, buf, offset, length);
2345 }
2346
2347 /**
2348 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2349 * @ha: HA context
2350 * @pcids: Pointer to the FCODE PCI data structure
2351 *
2352 * The process of retrieving the FCODE version information is at best
2353 * described as interesting.
2354 *
2355 * Within the first 100h bytes of the image an ASCII string is present
2356 * which contains several pieces of information including the FCODE
2357 * version. Unfortunately it seems the only reliable way to retrieve
2358 * the version is by scanning for another sentinel within the string,
2359 * the FCODE build date:
2360 *
2361 * ... 2.00.02 10/17/02 ...
2362 *
2363 * Returns QLA_SUCCESS on successful retrieval of version.
2364 */
2365 static void
2366 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2367 {
2368 int ret = QLA_FUNCTION_FAILED;
2369 uint32_t istart, iend, iter, vend;
2370 uint8_t do_next, rbyte, *vbyte;
2371
2372 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2373
2374 /* Skip the PCI data structure. */
2375 istart = pcids +
2376 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2377 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2378 iend = istart + 0x100;
2379 do {
2380 /* Scan for the sentinel date string...eeewww. */
2381 do_next = 0;
2382 iter = istart;
2383 while ((iter < iend) && !do_next) {
2384 iter++;
2385 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2386 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2387 '/')
2388 do_next++;
2389 else if (qla2x00_read_flash_byte(ha,
2390 iter + 3) == '/')
2391 do_next++;
2392 }
2393 }
2394 if (!do_next)
2395 break;
2396
2397 /* Backtrack to previous ' ' (space). */
2398 do_next = 0;
2399 while ((iter > istart) && !do_next) {
2400 iter--;
2401 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2402 do_next++;
2403 }
2404 if (!do_next)
2405 break;
2406
2407 /*
2408 * Mark end of version tag, and find previous ' ' (space) or
2409 * string length (recent FCODE images -- major hack ahead!!!).
2410 */
2411 vend = iter - 1;
2412 do_next = 0;
2413 while ((iter > istart) && !do_next) {
2414 iter--;
2415 rbyte = qla2x00_read_flash_byte(ha, iter);
2416 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2417 do_next++;
2418 }
2419 if (!do_next)
2420 break;
2421
2422 /* Mark beginning of version tag, and copy data. */
2423 iter++;
2424 if ((vend - iter) &&
2425 ((vend - iter) < sizeof(ha->fcode_revision))) {
2426 vbyte = ha->fcode_revision;
2427 while (iter <= vend) {
2428 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2429 iter++;
2430 }
2431 ret = QLA_SUCCESS;
2432 }
2433 } while (0);
2434
2435 if (ret != QLA_SUCCESS)
2436 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2437 }
2438
2439 int
2440 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2441 {
2442 int ret = QLA_SUCCESS;
2443 uint8_t code_type, last_image;
2444 uint32_t pcihdr, pcids;
2445 uint8_t *dbyte;
2446 uint16_t *dcode;
2447 struct qla_hw_data *ha = vha->hw;
2448
2449 if (!ha->pio_address || !mbuf)
2450 return QLA_FUNCTION_FAILED;
2451
2452 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2453 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2454 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2455 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2456
2457 qla2x00_flash_enable(ha);
2458
2459 /* Begin with first PCI expansion ROM header. */
2460 pcihdr = 0;
2461 last_image = 1;
2462 do {
2463 /* Verify PCI expansion ROM header. */
2464 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2465 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2466 /* No signature */
2467 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2468 "signature.\n"));
2469 ret = QLA_FUNCTION_FAILED;
2470 break;
2471 }
2472
2473 /* Locate PCI data structure. */
2474 pcids = pcihdr +
2475 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2476 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2477
2478 /* Validate signature of PCI data structure. */
2479 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2480 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2481 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2482 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2483 /* Incorrect header. */
2484 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2485 "found pcir_adr=%x.\n", pcids));
2486 ret = QLA_FUNCTION_FAILED;
2487 break;
2488 }
2489
2490 /* Read version */
2491 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2492 switch (code_type) {
2493 case ROM_CODE_TYPE_BIOS:
2494 /* Intel x86, PC-AT compatible. */
2495 ha->bios_revision[0] =
2496 qla2x00_read_flash_byte(ha, pcids + 0x12);
2497 ha->bios_revision[1] =
2498 qla2x00_read_flash_byte(ha, pcids + 0x13);
2499 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2500 ha->bios_revision[1], ha->bios_revision[0]));
2501 break;
2502 case ROM_CODE_TYPE_FCODE:
2503 /* Open Firmware standard for PCI (FCode). */
2504 /* Eeeewww... */
2505 qla2x00_get_fcode_version(ha, pcids);
2506 break;
2507 case ROM_CODE_TYPE_EFI:
2508 /* Extensible Firmware Interface (EFI). */
2509 ha->efi_revision[0] =
2510 qla2x00_read_flash_byte(ha, pcids + 0x12);
2511 ha->efi_revision[1] =
2512 qla2x00_read_flash_byte(ha, pcids + 0x13);
2513 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2514 ha->efi_revision[1], ha->efi_revision[0]));
2515 break;
2516 default:
2517 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2518 "type %x at pcids %x.\n", code_type, pcids));
2519 break;
2520 }
2521
2522 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2523
2524 /* Locate next PCI expansion ROM. */
2525 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2526 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2527 } while (!last_image);
2528
2529 if (IS_QLA2322(ha)) {
2530 /* Read firmware image information. */
2531 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2532 dbyte = mbuf;
2533 memset(dbyte, 0, 8);
2534 dcode = (uint16_t *)dbyte;
2535
2536 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2537 8);
2538 DEBUG3(qla_printk(KERN_DEBUG, ha, "dumping fw ver from "
2539 "flash:\n"));
2540 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2541
2542 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2543 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2544 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2545 dcode[3] == 0)) {
2546 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2547 "revision at %x.\n", ha->flt_region_fw * 4));
2548 } else {
2549 /* values are in big endian */
2550 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2551 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2552 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2553 }
2554 }
2555
2556 qla2x00_flash_disable(ha);
2557
2558 return ret;
2559 }
2560
2561 int
2562 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2563 {
2564 int ret = QLA_SUCCESS;
2565 uint32_t pcihdr, pcids;
2566 uint32_t *dcode;
2567 uint8_t *bcode;
2568 uint8_t code_type, last_image;
2569 int i;
2570 struct qla_hw_data *ha = vha->hw;
2571
2572 if (!mbuf)
2573 return QLA_FUNCTION_FAILED;
2574
2575 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2576 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2577 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2578 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2579
2580 dcode = mbuf;
2581
2582 /* Begin with first PCI expansion ROM header. */
2583 pcihdr = ha->flt_region_boot << 2;
2584 last_image = 1;
2585 do {
2586 /* Verify PCI expansion ROM header. */
2587 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2588 bcode = mbuf + (pcihdr % 4);
2589 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2590 /* No signature */
2591 DEBUG2(qla_printk(KERN_DEBUG, ha, "No matching ROM "
2592 "signature.\n"));
2593 ret = QLA_FUNCTION_FAILED;
2594 break;
2595 }
2596
2597 /* Locate PCI data structure. */
2598 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2599
2600 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2601 bcode = mbuf + (pcihdr % 4);
2602
2603 /* Validate signature of PCI data structure. */
2604 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2605 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2606 /* Incorrect header. */
2607 DEBUG2(qla_printk(KERN_INFO, ha, "PCI data struct not "
2608 "found pcir_adr=%x.\n", pcids));
2609 ret = QLA_FUNCTION_FAILED;
2610 break;
2611 }
2612
2613 /* Read version */
2614 code_type = bcode[0x14];
2615 switch (code_type) {
2616 case ROM_CODE_TYPE_BIOS:
2617 /* Intel x86, PC-AT compatible. */
2618 ha->bios_revision[0] = bcode[0x12];
2619 ha->bios_revision[1] = bcode[0x13];
2620 DEBUG3(qla_printk(KERN_DEBUG, ha, "read BIOS %d.%d.\n",
2621 ha->bios_revision[1], ha->bios_revision[0]));
2622 break;
2623 case ROM_CODE_TYPE_FCODE:
2624 /* Open Firmware standard for PCI (FCode). */
2625 ha->fcode_revision[0] = bcode[0x12];
2626 ha->fcode_revision[1] = bcode[0x13];
2627 DEBUG3(qla_printk(KERN_DEBUG, ha, "read FCODE %d.%d.\n",
2628 ha->fcode_revision[1], ha->fcode_revision[0]));
2629 break;
2630 case ROM_CODE_TYPE_EFI:
2631 /* Extensible Firmware Interface (EFI). */
2632 ha->efi_revision[0] = bcode[0x12];
2633 ha->efi_revision[1] = bcode[0x13];
2634 DEBUG3(qla_printk(KERN_DEBUG, ha, "read EFI %d.%d.\n",
2635 ha->efi_revision[1], ha->efi_revision[0]));
2636 break;
2637 default:
2638 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized code "
2639 "type %x at pcids %x.\n", code_type, pcids));
2640 break;
2641 }
2642
2643 last_image = bcode[0x15] & BIT_7;
2644
2645 /* Locate next PCI expansion ROM. */
2646 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2647 } while (!last_image);
2648
2649 /* Read firmware image information. */
2650 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2651 dcode = mbuf;
2652
2653 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2654 for (i = 0; i < 4; i++)
2655 dcode[i] = be32_to_cpu(dcode[i]);
2656
2657 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2658 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2659 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2660 dcode[3] == 0)) {
2661 DEBUG2(qla_printk(KERN_INFO, ha, "Unrecognized fw "
2662 "revision at %x.\n", ha->flt_region_fw * 4));
2663 } else {
2664 ha->fw_revision[0] = dcode[0];
2665 ha->fw_revision[1] = dcode[1];
2666 ha->fw_revision[2] = dcode[2];
2667 ha->fw_revision[3] = dcode[3];
2668 }
2669
2670 return ret;
2671 }
2672
2673 static int
2674 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2675 {
2676 if (pos >= end || *pos != 0x82)
2677 return 0;
2678
2679 pos += 3 + pos[1];
2680 if (pos >= end || *pos != 0x90)
2681 return 0;
2682
2683 pos += 3 + pos[1];
2684 if (pos >= end || *pos != 0x78)
2685 return 0;
2686
2687 return 1;
2688 }
2689
2690 int
2691 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2692 {
2693 struct qla_hw_data *ha = vha->hw;
2694 uint8_t *pos = ha->vpd;
2695 uint8_t *end = pos + ha->vpd_size;
2696 int len = 0;
2697
2698 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2699 return 0;
2700
2701 while (pos < end && *pos != 0x78) {
2702 len = (*pos == 0x82) ? pos[1] : pos[2];
2703
2704 if (!strncmp(pos, key, strlen(key)))
2705 break;
2706
2707 if (*pos != 0x90 && *pos != 0x91)
2708 pos += len;
2709
2710 pos += 3;
2711 }
2712
2713 if (pos < end - len && *pos != 0x78)
2714 return snprintf(str, size, "%.*s", len, pos + 3);
2715
2716 return 0;
2717 }
Linux kernel - Deliverables
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