2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
10 #include <linux/vmalloc.h>
11 #include <asm/uaccess.h>
14 * NVRAM support routines
18 * qla2x00_lock_nvram_access() -
22 qla2x00_lock_nvram_access(struct qla_hw_data
*ha
)
25 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
27 if (!IS_QLA2100(ha
) && !IS_QLA2200(ha
) && !IS_QLA2300(ha
)) {
28 data
= RD_REG_WORD(®
->nvram
);
29 while (data
& NVR_BUSY
) {
31 data
= RD_REG_WORD(®
->nvram
);
35 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0x1);
36 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
38 data
= RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
39 while ((data
& BIT_0
) == 0) {
42 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0x1);
43 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
45 data
= RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
51 * qla2x00_unlock_nvram_access() -
55 qla2x00_unlock_nvram_access(struct qla_hw_data
*ha
)
57 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
59 if (!IS_QLA2100(ha
) && !IS_QLA2200(ha
) && !IS_QLA2300(ha
)) {
60 WRT_REG_WORD(®
->u
.isp2300
.host_semaphore
, 0);
61 RD_REG_WORD(®
->u
.isp2300
.host_semaphore
);
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
68 * @data: Serial interface selector
71 qla2x00_nv_write(struct qla_hw_data
*ha
, uint16_t data
)
73 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
75 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_WRT_ENABLE
);
76 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
78 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_CLOCK
|
80 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
82 WRT_REG_WORD(®
->nvram
, data
| NVR_SELECT
| NVR_WRT_ENABLE
);
83 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
91 * @nv_cmd: NVRAM command
93 * Bit definitions for NVRAM command:
98 * Bit 15-0 = write data
100 * Returns the word read from nvram @addr.
103 qla2x00_nvram_request(struct qla_hw_data
*ha
, uint32_t nv_cmd
)
106 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
110 /* Send command to NVRAM. */
112 for (cnt
= 0; cnt
< 11; cnt
++) {
114 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
116 qla2x00_nv_write(ha
, 0);
120 /* Read data from NVRAM. */
121 for (cnt
= 0; cnt
< 16; cnt
++) {
122 WRT_REG_WORD(®
->nvram
, NVR_SELECT
| NVR_CLOCK
);
123 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
126 reg_data
= RD_REG_WORD(®
->nvram
);
127 if (reg_data
& NVR_DATA_IN
)
129 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
130 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
135 WRT_REG_WORD(®
->nvram
, NVR_DESELECT
);
136 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
145 * request routine to get the word from NVRAM.
147 * @addr: Address in NVRAM to read
149 * Returns the word read from nvram @addr.
152 qla2x00_get_nvram_word(struct qla_hw_data
*ha
, uint32_t addr
)
158 nv_cmd
|= NV_READ_OP
;
159 data
= qla2x00_nvram_request(ha
, nv_cmd
);
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
169 qla2x00_nv_deselect(struct qla_hw_data
*ha
)
171 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
173 WRT_REG_WORD(®
->nvram
, NVR_DESELECT
);
174 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
179 * qla2x00_write_nvram_word() - Write NVRAM data.
181 * @addr: Address in NVRAM to write
182 * @data: word to program
185 qla2x00_write_nvram_word(struct qla_hw_data
*ha
, uint32_t addr
, uint16_t data
)
189 uint32_t nv_cmd
, wait_cnt
;
190 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
192 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
193 qla2x00_nv_write(ha
, 0);
194 qla2x00_nv_write(ha
, 0);
196 for (word
= 0; word
< 8; word
++)
197 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
199 qla2x00_nv_deselect(ha
);
202 nv_cmd
= (addr
<< 16) | NV_WRITE_OP
;
205 for (count
= 0; count
< 27; count
++) {
207 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
209 qla2x00_nv_write(ha
, 0);
214 qla2x00_nv_deselect(ha
);
216 /* Wait for NVRAM to become ready */
217 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
218 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
219 wait_cnt
= NVR_WAIT_CNT
;
222 DEBUG9_10(qla_printk(KERN_WARNING
, ha
,
223 "NVRAM didn't go ready...\n"));
227 word
= RD_REG_WORD(®
->nvram
);
228 } while ((word
& NVR_DATA_IN
) == 0);
230 qla2x00_nv_deselect(ha
);
233 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
234 for (count
= 0; count
< 10; count
++)
235 qla2x00_nv_write(ha
, 0);
237 qla2x00_nv_deselect(ha
);
241 qla2x00_write_nvram_word_tmo(struct qla_hw_data
*ha
, uint32_t addr
,
242 uint16_t data
, uint32_t tmo
)
247 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
251 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
252 qla2x00_nv_write(ha
, 0);
253 qla2x00_nv_write(ha
, 0);
255 for (word
= 0; word
< 8; word
++)
256 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
258 qla2x00_nv_deselect(ha
);
261 nv_cmd
= (addr
<< 16) | NV_WRITE_OP
;
264 for (count
= 0; count
< 27; count
++) {
266 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
268 qla2x00_nv_write(ha
, 0);
273 qla2x00_nv_deselect(ha
);
275 /* Wait for NVRAM to become ready */
276 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
277 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
280 word
= RD_REG_WORD(®
->nvram
);
282 ret
= QLA_FUNCTION_FAILED
;
285 } while ((word
& NVR_DATA_IN
) == 0);
287 qla2x00_nv_deselect(ha
);
290 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
291 for (count
= 0; count
< 10; count
++)
292 qla2x00_nv_write(ha
, 0);
294 qla2x00_nv_deselect(ha
);
300 * qla2x00_clear_nvram_protection() -
304 qla2x00_clear_nvram_protection(struct qla_hw_data
*ha
)
307 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
308 uint32_t word
, wait_cnt
;
309 uint16_t wprot
, wprot_old
;
311 /* Clear NVRAM write protection. */
312 ret
= QLA_FUNCTION_FAILED
;
314 wprot_old
= cpu_to_le16(qla2x00_get_nvram_word(ha
, ha
->nvram_base
));
315 stat
= qla2x00_write_nvram_word_tmo(ha
, ha
->nvram_base
,
316 __constant_cpu_to_le16(0x1234), 100000);
317 wprot
= cpu_to_le16(qla2x00_get_nvram_word(ha
, ha
->nvram_base
));
318 if (stat
!= QLA_SUCCESS
|| wprot
!= 0x1234) {
320 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
321 qla2x00_nv_write(ha
, 0);
322 qla2x00_nv_write(ha
, 0);
323 for (word
= 0; word
< 8; word
++)
324 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
326 qla2x00_nv_deselect(ha
);
328 /* Enable protection register. */
329 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
330 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
331 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
332 for (word
= 0; word
< 8; word
++)
333 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
335 qla2x00_nv_deselect(ha
);
337 /* Clear protection register (ffff is cleared). */
338 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
339 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
340 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
341 for (word
= 0; word
< 8; word
++)
342 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
344 qla2x00_nv_deselect(ha
);
346 /* Wait for NVRAM to become ready. */
347 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
348 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
349 wait_cnt
= NVR_WAIT_CNT
;
352 DEBUG9_10(qla_printk(KERN_WARNING
, ha
,
353 "NVRAM didn't go ready...\n"));
357 word
= RD_REG_WORD(®
->nvram
);
358 } while ((word
& NVR_DATA_IN
) == 0);
363 qla2x00_write_nvram_word(ha
, ha
->nvram_base
, wprot_old
);
369 qla2x00_set_nvram_protection(struct qla_hw_data
*ha
, int stat
)
371 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
372 uint32_t word
, wait_cnt
;
374 if (stat
!= QLA_SUCCESS
)
377 /* Set NVRAM write protection. */
379 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
380 qla2x00_nv_write(ha
, 0);
381 qla2x00_nv_write(ha
, 0);
382 for (word
= 0; word
< 8; word
++)
383 qla2x00_nv_write(ha
, NVR_DATA_OUT
);
385 qla2x00_nv_deselect(ha
);
387 /* Enable protection register. */
388 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
389 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
390 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
391 for (word
= 0; word
< 8; word
++)
392 qla2x00_nv_write(ha
, NVR_DATA_OUT
| NVR_PR_ENABLE
);
394 qla2x00_nv_deselect(ha
);
396 /* Enable protection register. */
397 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
398 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
399 qla2x00_nv_write(ha
, NVR_PR_ENABLE
| NVR_DATA_OUT
);
400 for (word
= 0; word
< 8; word
++)
401 qla2x00_nv_write(ha
, NVR_PR_ENABLE
);
403 qla2x00_nv_deselect(ha
);
405 /* Wait for NVRAM to become ready. */
406 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
407 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
408 wait_cnt
= NVR_WAIT_CNT
;
411 DEBUG9_10(qla_printk(KERN_WARNING
, ha
,
412 "NVRAM didn't go ready...\n"));
416 word
= RD_REG_WORD(®
->nvram
);
417 } while ((word
& NVR_DATA_IN
) == 0);
421 /*****************************************************************************/
422 /* Flash Manipulation Routines */
423 /*****************************************************************************/
425 #define OPTROM_BURST_SIZE 0x1000
426 #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4)
428 static inline uint32_t
429 flash_conf_addr(struct qla_hw_data
*ha
, uint32_t faddr
)
431 return ha
->flash_conf_off
| faddr
;
434 static inline uint32_t
435 flash_data_addr(struct qla_hw_data
*ha
, uint32_t faddr
)
437 return ha
->flash_data_off
| faddr
;
440 static inline uint32_t
441 nvram_conf_addr(struct qla_hw_data
*ha
, uint32_t naddr
)
443 return ha
->nvram_conf_off
| naddr
;
446 static inline uint32_t
447 nvram_data_addr(struct qla_hw_data
*ha
, uint32_t naddr
)
449 return ha
->nvram_data_off
| naddr
;
453 qla24xx_read_flash_dword(struct qla_hw_data
*ha
, uint32_t addr
)
457 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
459 WRT_REG_DWORD(®
->flash_addr
, addr
& ~FARX_DATA_FLAG
);
460 /* Wait for READ cycle to complete. */
463 (RD_REG_DWORD(®
->flash_addr
) & FARX_DATA_FLAG
) == 0 &&
464 rval
== QLA_SUCCESS
; cnt
--) {
468 rval
= QLA_FUNCTION_TIMEOUT
;
472 /* TODO: What happens if we time out? */
474 if (rval
== QLA_SUCCESS
)
475 data
= RD_REG_DWORD(®
->flash_data
);
481 qla24xx_read_flash_data(scsi_qla_host_t
*vha
, uint32_t *dwptr
, uint32_t faddr
,
485 struct qla_hw_data
*ha
= vha
->hw
;
487 /* Dword reads to flash. */
488 for (i
= 0; i
< dwords
; i
++, faddr
++)
489 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
490 flash_data_addr(ha
, faddr
)));
496 qla24xx_write_flash_dword(struct qla_hw_data
*ha
, uint32_t addr
, uint32_t data
)
500 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
502 WRT_REG_DWORD(®
->flash_data
, data
);
503 RD_REG_DWORD(®
->flash_data
); /* PCI Posting. */
504 WRT_REG_DWORD(®
->flash_addr
, addr
| FARX_DATA_FLAG
);
505 /* Wait for Write cycle to complete. */
507 for (cnt
= 500000; (RD_REG_DWORD(®
->flash_addr
) & FARX_DATA_FLAG
) &&
508 rval
== QLA_SUCCESS
; cnt
--) {
512 rval
= QLA_FUNCTION_TIMEOUT
;
519 qla24xx_get_flash_manufacturer(struct qla_hw_data
*ha
, uint8_t *man_id
,
524 ids
= qla24xx_read_flash_dword(ha
, flash_conf_addr(ha
, 0x03ab));
526 *flash_id
= MSB(ids
);
528 /* Check if man_id and flash_id are valid. */
529 if (ids
!= 0xDEADDEAD && (*man_id
== 0 || *flash_id
== 0)) {
530 /* Read information using 0x9f opcode
531 * Device ID, Mfg ID would be read in the format:
532 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
533 * Example: ATMEL 0x00 01 45 1F
534 * Extract MFG and Dev ID from last two bytes.
536 ids
= qla24xx_read_flash_dword(ha
, flash_conf_addr(ha
, 0x009f));
538 *flash_id
= MSB(ids
);
543 qla2xxx_find_flt_start(scsi_qla_host_t
*vha
, uint32_t *start
)
545 const char *loc
, *locations
[] = { "DEF", "PCI" };
546 uint32_t pcihdr
, pcids
;
548 uint8_t *buf
, *bcode
, last_image
;
549 uint16_t cnt
, chksum
, *wptr
;
550 struct qla_flt_location
*fltl
;
551 struct qla_hw_data
*ha
= vha
->hw
;
552 struct req_que
*req
= ha
->req_q_map
[0];
555 * FLT-location structure resides after the last PCI region.
558 /* Begin with sane defaults. */
561 if (IS_QLA24XX_TYPE(ha
))
562 *start
= FA_FLASH_LAYOUT_ADDR_24
;
563 else if (IS_QLA25XX(ha
))
564 *start
= FA_FLASH_LAYOUT_ADDR
;
565 else if (IS_QLA81XX(ha
))
566 *start
= FA_FLASH_LAYOUT_ADDR_81
;
567 /* Begin with first PCI expansion ROM header. */
568 buf
= (uint8_t *)req
->ring
;
569 dcode
= (uint32_t *)req
->ring
;
573 /* Verify PCI expansion ROM header. */
574 qla24xx_read_flash_data(vha
, dcode
, pcihdr
>> 2, 0x20);
575 bcode
= buf
+ (pcihdr
% 4);
576 if (bcode
[0x0] != 0x55 || bcode
[0x1] != 0xaa)
579 /* Locate PCI data structure. */
580 pcids
= pcihdr
+ ((bcode
[0x19] << 8) | bcode
[0x18]);
581 qla24xx_read_flash_data(vha
, dcode
, pcids
>> 2, 0x20);
582 bcode
= buf
+ (pcihdr
% 4);
584 /* Validate signature of PCI data structure. */
585 if (bcode
[0x0] != 'P' || bcode
[0x1] != 'C' ||
586 bcode
[0x2] != 'I' || bcode
[0x3] != 'R')
589 last_image
= bcode
[0x15] & BIT_7
;
591 /* Locate next PCI expansion ROM. */
592 pcihdr
+= ((bcode
[0x11] << 8) | bcode
[0x10]) * 512;
593 } while (!last_image
);
595 /* Now verify FLT-location structure. */
596 fltl
= (struct qla_flt_location
*)req
->ring
;
597 qla24xx_read_flash_data(vha
, dcode
, pcihdr
>> 2,
598 sizeof(struct qla_flt_location
) >> 2);
599 if (fltl
->sig
[0] != 'Q' || fltl
->sig
[1] != 'F' ||
600 fltl
->sig
[2] != 'L' || fltl
->sig
[3] != 'T')
603 wptr
= (uint16_t *)req
->ring
;
604 cnt
= sizeof(struct qla_flt_location
) >> 1;
605 for (chksum
= 0; cnt
; cnt
--)
606 chksum
+= le16_to_cpu(*wptr
++);
608 qla_printk(KERN_ERR
, ha
,
609 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum
);
610 qla2x00_dump_buffer(buf
, sizeof(struct qla_flt_location
));
611 return QLA_FUNCTION_FAILED
;
614 /* Good data. Use specified location. */
616 *start
= (le16_to_cpu(fltl
->start_hi
) << 16 |
617 le16_to_cpu(fltl
->start_lo
)) >> 2;
619 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "FLTL[%s] = 0x%x.\n", loc
, *start
));
624 qla2xxx_get_flt_info(scsi_qla_host_t
*vha
, uint32_t flt_addr
)
626 const char *loc
, *locations
[] = { "DEF", "FLT" };
627 const uint32_t def_fw
[] =
628 { FA_RISC_CODE_ADDR
, FA_RISC_CODE_ADDR
, FA_RISC_CODE_ADDR_81
};
629 const uint32_t def_boot
[] =
630 { FA_BOOT_CODE_ADDR
, FA_BOOT_CODE_ADDR
, FA_BOOT_CODE_ADDR_81
};
631 const uint32_t def_vpd_nvram
[] =
632 { FA_VPD_NVRAM_ADDR
, FA_VPD_NVRAM_ADDR
, FA_VPD_NVRAM_ADDR_81
};
633 const uint32_t def_vpd0
[] =
634 { 0, 0, FA_VPD0_ADDR_81
};
635 const uint32_t def_vpd1
[] =
636 { 0, 0, FA_VPD1_ADDR_81
};
637 const uint32_t def_nvram0
[] =
638 { 0, 0, FA_NVRAM0_ADDR_81
};
639 const uint32_t def_nvram1
[] =
640 { 0, 0, FA_NVRAM1_ADDR_81
};
641 const uint32_t def_fdt
[] =
642 { FA_FLASH_DESCR_ADDR_24
, FA_FLASH_DESCR_ADDR
,
643 FA_FLASH_DESCR_ADDR_81
};
644 const uint32_t def_npiv_conf0
[] =
645 { FA_NPIV_CONF0_ADDR_24
, FA_NPIV_CONF0_ADDR
,
646 FA_NPIV_CONF0_ADDR_81
};
647 const uint32_t def_npiv_conf1
[] =
648 { FA_NPIV_CONF1_ADDR_24
, FA_NPIV_CONF1_ADDR
,
649 FA_NPIV_CONF1_ADDR_81
};
652 uint16_t cnt
, chksum
;
654 struct qla_flt_header
*flt
;
655 struct qla_flt_region
*region
;
656 struct qla_hw_data
*ha
= vha
->hw
;
657 struct req_que
*req
= ha
->req_q_map
[0];
659 ha
->flt_region_flt
= flt_addr
;
660 wptr
= (uint16_t *)req
->ring
;
661 flt
= (struct qla_flt_header
*)req
->ring
;
662 region
= (struct qla_flt_region
*)&flt
[1];
663 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)req
->ring
,
664 flt_addr
<< 2, OPTROM_BURST_SIZE
);
665 if (*wptr
== __constant_cpu_to_le16(0xffff))
667 if (flt
->version
!= __constant_cpu_to_le16(1)) {
668 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unsupported FLT detected: "
669 "version=0x%x length=0x%x checksum=0x%x.\n",
670 le16_to_cpu(flt
->version
), le16_to_cpu(flt
->length
),
671 le16_to_cpu(flt
->checksum
)));
675 cnt
= (sizeof(struct qla_flt_header
) + le16_to_cpu(flt
->length
)) >> 1;
676 for (chksum
= 0; cnt
; cnt
--)
677 chksum
+= le16_to_cpu(*wptr
++);
679 DEBUG2(qla_printk(KERN_INFO
, ha
, "Inconsistent FLT detected: "
680 "version=0x%x length=0x%x checksum=0x%x.\n",
681 le16_to_cpu(flt
->version
), le16_to_cpu(flt
->length
),
687 cnt
= le16_to_cpu(flt
->length
) / sizeof(struct qla_flt_region
);
688 for ( ; cnt
; cnt
--, region
++) {
689 /* Store addresses as DWORD offsets. */
690 start
= le32_to_cpu(region
->start
) >> 2;
692 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "FLT[%02x]: start=0x%x "
693 "end=0x%x size=0x%x.\n", le32_to_cpu(region
->code
), start
,
694 le32_to_cpu(region
->end
) >> 2, le32_to_cpu(region
->size
)));
696 switch (le32_to_cpu(region
->code
) & 0xff) {
698 ha
->flt_region_fw
= start
;
700 case FLT_REG_BOOT_CODE
:
701 ha
->flt_region_boot
= start
;
704 ha
->flt_region_vpd_nvram
= start
;
706 ha
->flt_region_vpd
= start
;
709 if (!ha
->flags
.port0
)
710 ha
->flt_region_vpd
= start
;
712 case FLT_REG_NVRAM_0
:
714 ha
->flt_region_nvram
= start
;
716 case FLT_REG_NVRAM_1
:
717 if (!ha
->flags
.port0
)
718 ha
->flt_region_nvram
= start
;
721 ha
->flt_region_fdt
= start
;
723 case FLT_REG_NPIV_CONF_0
:
725 ha
->flt_region_npiv_conf
= start
;
727 case FLT_REG_NPIV_CONF_1
:
728 if (!ha
->flags
.port0
)
729 ha
->flt_region_npiv_conf
= start
;
736 /* Use hardcoded defaults. */
739 if (IS_QLA24XX_TYPE(ha
))
741 else if (IS_QLA25XX(ha
))
743 else if (IS_QLA81XX(ha
))
745 ha
->flt_region_fw
= def_fw
[def
];
746 ha
->flt_region_boot
= def_boot
[def
];
747 ha
->flt_region_vpd_nvram
= def_vpd_nvram
[def
];
748 ha
->flt_region_vpd
= ha
->flags
.port0
?
749 def_vpd0
[def
]: def_vpd1
[def
];
750 ha
->flt_region_nvram
= ha
->flags
.port0
?
751 def_nvram0
[def
]: def_nvram1
[def
];
752 ha
->flt_region_fdt
= def_fdt
[def
];
753 ha
->flt_region_npiv_conf
= ha
->flags
.port0
?
754 def_npiv_conf0
[def
]: def_npiv_conf1
[def
];
756 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "FLT[%s]: boot=0x%x fw=0x%x "
757 "vpd_nvram=0x%x vpd=0x%x nvram=0x%x fdt=0x%x flt=0x%x "
758 "npiv=0x%x.\n", loc
, ha
->flt_region_boot
, ha
->flt_region_fw
,
759 ha
->flt_region_vpd_nvram
, ha
->flt_region_vpd
, ha
->flt_region_nvram
,
760 ha
->flt_region_fdt
, ha
->flt_region_flt
, ha
->flt_region_npiv_conf
));
764 qla2xxx_get_fdt_info(scsi_qla_host_t
*vha
)
766 #define FLASH_BLK_SIZE_4K 0x1000
767 #define FLASH_BLK_SIZE_32K 0x8000
768 #define FLASH_BLK_SIZE_64K 0x10000
769 const char *loc
, *locations
[] = { "MID", "FDT" };
770 uint16_t cnt
, chksum
;
772 struct qla_fdt_layout
*fdt
;
773 uint8_t man_id
, flash_id
;
775 struct qla_hw_data
*ha
= vha
->hw
;
776 struct req_que
*req
= ha
->req_q_map
[0];
778 wptr
= (uint16_t *)req
->ring
;
779 fdt
= (struct qla_fdt_layout
*)req
->ring
;
780 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)req
->ring
,
781 ha
->flt_region_fdt
<< 2, OPTROM_BURST_SIZE
);
782 if (*wptr
== __constant_cpu_to_le16(0xffff))
784 if (fdt
->sig
[0] != 'Q' || fdt
->sig
[1] != 'L' || fdt
->sig
[2] != 'I' ||
788 for (cnt
= 0, chksum
= 0; cnt
< sizeof(struct qla_fdt_layout
) >> 1;
790 chksum
+= le16_to_cpu(*wptr
++);
792 DEBUG2(qla_printk(KERN_INFO
, ha
, "Inconsistent FDT detected: "
793 "checksum=0x%x id=%c version=0x%x.\n", chksum
, fdt
->sig
[0],
794 le16_to_cpu(fdt
->version
)));
795 DEBUG9(qla2x00_dump_buffer((uint8_t *)fdt
, sizeof(*fdt
)));
800 mid
= le16_to_cpu(fdt
->man_id
);
801 fid
= le16_to_cpu(fdt
->id
);
802 ha
->fdt_wrt_disable
= fdt
->wrt_disable_bits
;
803 ha
->fdt_erase_cmd
= flash_conf_addr(ha
, 0x0300 | fdt
->erase_cmd
);
804 ha
->fdt_block_size
= le32_to_cpu(fdt
->block_size
);
805 if (fdt
->unprotect_sec_cmd
) {
806 ha
->fdt_unprotect_sec_cmd
= flash_conf_addr(ha
, 0x0300 |
807 fdt
->unprotect_sec_cmd
);
808 ha
->fdt_protect_sec_cmd
= fdt
->protect_sec_cmd
?
809 flash_conf_addr(ha
, 0x0300 | fdt
->protect_sec_cmd
):
810 flash_conf_addr(ha
, 0x0336);
815 qla24xx_get_flash_manufacturer(ha
, &man_id
, &flash_id
);
818 ha
->fdt_wrt_disable
= 0x9c;
819 ha
->fdt_erase_cmd
= flash_conf_addr(ha
, 0x03d8);
821 case 0xbf: /* STT flash. */
822 if (flash_id
== 0x8e)
823 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
825 ha
->fdt_block_size
= FLASH_BLK_SIZE_32K
;
827 if (flash_id
== 0x80)
828 ha
->fdt_erase_cmd
= flash_conf_addr(ha
, 0x0352);
830 case 0x13: /* ST M25P80. */
831 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
833 case 0x1f: /* Atmel 26DF081A. */
834 ha
->fdt_block_size
= FLASH_BLK_SIZE_4K
;
835 ha
->fdt_erase_cmd
= flash_conf_addr(ha
, 0x0320);
836 ha
->fdt_unprotect_sec_cmd
= flash_conf_addr(ha
, 0x0339);
837 ha
->fdt_protect_sec_cmd
= flash_conf_addr(ha
, 0x0336);
840 /* Default to 64 kb sector size. */
841 ha
->fdt_block_size
= FLASH_BLK_SIZE_64K
;
845 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "FDT[%s]: (0x%x/0x%x) erase=0x%x "
846 "pro=%x upro=%x wrtd=0x%x blk=0x%x.\n", loc
, mid
, fid
,
847 ha
->fdt_erase_cmd
, ha
->fdt_protect_sec_cmd
,
848 ha
->fdt_unprotect_sec_cmd
, ha
->fdt_wrt_disable
,
849 ha
->fdt_block_size
));
853 qla2xxx_get_flash_info(scsi_qla_host_t
*vha
)
857 struct qla_hw_data
*ha
= vha
->hw
;
859 if (!IS_QLA24XX_TYPE(ha
) && !IS_QLA25XX(ha
) && !IS_QLA81XX(ha
))
862 ret
= qla2xxx_find_flt_start(vha
, &flt_addr
);
863 if (ret
!= QLA_SUCCESS
)
866 qla2xxx_get_flt_info(vha
, flt_addr
);
867 qla2xxx_get_fdt_info(vha
);
873 qla2xxx_flash_npiv_conf(scsi_qla_host_t
*vha
)
875 #define NPIV_CONFIG_SIZE (16*1024)
878 uint16_t cnt
, chksum
;
880 struct qla_npiv_header hdr
;
881 struct qla_npiv_entry
*entry
;
882 struct qla_hw_data
*ha
= vha
->hw
;
884 if (!IS_QLA24XX_TYPE(ha
) && !IS_QLA25XX(ha
) && !IS_QLA81XX(ha
))
887 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)&hdr
,
888 ha
->flt_region_npiv_conf
<< 2, sizeof(struct qla_npiv_header
));
889 if (hdr
.version
== __constant_cpu_to_le16(0xffff))
891 if (hdr
.version
!= __constant_cpu_to_le16(1)) {
892 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unsupported NPIV-Config "
893 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
894 le16_to_cpu(hdr
.version
), le16_to_cpu(hdr
.entries
),
895 le16_to_cpu(hdr
.checksum
)));
899 data
= kmalloc(NPIV_CONFIG_SIZE
, GFP_KERNEL
);
901 DEBUG2(qla_printk(KERN_INFO
, ha
, "NPIV-Config: Unable to "
902 "allocate memory.\n"));
906 ha
->isp_ops
->read_optrom(vha
, (uint8_t *)data
,
907 ha
->flt_region_npiv_conf
<< 2, NPIV_CONFIG_SIZE
);
909 cnt
= (sizeof(struct qla_npiv_header
) + le16_to_cpu(hdr
.entries
) *
910 sizeof(struct qla_npiv_entry
)) >> 1;
911 for (wptr
= data
, chksum
= 0; cnt
; cnt
--)
912 chksum
+= le16_to_cpu(*wptr
++);
914 DEBUG2(qla_printk(KERN_INFO
, ha
, "Inconsistent NPIV-Config "
915 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
916 le16_to_cpu(hdr
.version
), le16_to_cpu(hdr
.entries
),
921 entry
= data
+ sizeof(struct qla_npiv_header
);
922 cnt
= le16_to_cpu(hdr
.entries
);
923 ha
->flex_port_count
= cnt
;
924 for (i
= 0; cnt
; cnt
--, entry
++, i
++) {
926 struct fc_vport_identifiers vid
;
927 struct fc_vport
*vport
;
929 flags
= le16_to_cpu(entry
->flags
);
932 if ((flags
& BIT_0
) == 0)
935 memset(&vid
, 0, sizeof(vid
));
936 vid
.roles
= FC_PORT_ROLE_FCP_INITIATOR
;
937 vid
.vport_type
= FC_PORTTYPE_NPIV
;
939 vid
.port_name
= wwn_to_u64(entry
->port_name
);
940 vid
.node_name
= wwn_to_u64(entry
->node_name
);
942 memcpy(&ha
->npiv_info
[i
], entry
, sizeof(struct qla_npiv_entry
));
944 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "NPIV[%02x]: wwpn=%llx "
945 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt
,
946 vid
.port_name
, vid
.node_name
, le16_to_cpu(entry
->vf_id
),
947 entry
->q_qos
, entry
->f_qos
));
949 if (i
< QLA_PRECONFIG_VPORTS
) {
950 vport
= fc_vport_create(vha
->host
, 0, &vid
);
952 qla_printk(KERN_INFO
, ha
,
953 "NPIV-Config: Failed to create vport [%02x]: "
954 "wwpn=%llx wwnn=%llx.\n", cnt
,
955 vid
.port_name
, vid
.node_name
);
960 ha
->npiv_info
= NULL
;
964 qla24xx_unprotect_flash(scsi_qla_host_t
*vha
)
966 struct qla_hw_data
*ha
= vha
->hw
;
967 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
969 if (ha
->flags
.fac_supported
)
970 return qla81xx_fac_do_write_enable(vha
, 1);
972 /* Enable flash write. */
973 WRT_REG_DWORD(®
->ctrl_status
,
974 RD_REG_DWORD(®
->ctrl_status
) | CSRX_FLASH_ENABLE
);
975 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
977 if (!ha
->fdt_wrt_disable
)
980 /* Disable flash write-protection, first clear SR protection bit */
981 qla24xx_write_flash_dword(ha
, flash_conf_addr(ha
, 0x101), 0);
982 /* Then write zero again to clear remaining SR bits.*/
983 qla24xx_write_flash_dword(ha
, flash_conf_addr(ha
, 0x101), 0);
989 qla24xx_protect_flash(scsi_qla_host_t
*vha
)
992 struct qla_hw_data
*ha
= vha
->hw
;
993 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
995 if (ha
->flags
.fac_supported
)
996 return qla81xx_fac_do_write_enable(vha
, 0);
998 if (!ha
->fdt_wrt_disable
)
999 goto skip_wrt_protect
;
1001 /* Enable flash write-protection and wait for completion. */
1002 qla24xx_write_flash_dword(ha
, flash_conf_addr(ha
, 0x101),
1003 ha
->fdt_wrt_disable
);
1004 for (cnt
= 300; cnt
&&
1005 qla24xx_read_flash_dword(ha
, flash_conf_addr(ha
, 0x005)) & BIT_0
;
1011 /* Disable flash write. */
1012 WRT_REG_DWORD(®
->ctrl_status
,
1013 RD_REG_DWORD(®
->ctrl_status
) & ~CSRX_FLASH_ENABLE
);
1014 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
1020 qla24xx_erase_sector(scsi_qla_host_t
*vha
, uint32_t fdata
)
1022 struct qla_hw_data
*ha
= vha
->hw
;
1023 uint32_t start
, finish
;
1025 if (ha
->flags
.fac_supported
) {
1027 finish
= start
+ (ha
->fdt_block_size
>> 2) - 1;
1028 return qla81xx_fac_erase_sector(vha
, flash_data_addr(ha
,
1029 start
), flash_data_addr(ha
, finish
));
1032 return qla24xx_write_flash_dword(ha
, ha
->fdt_erase_cmd
,
1033 (fdata
& 0xff00) | ((fdata
<< 16) & 0xff0000) |
1034 ((fdata
>> 16) & 0xff));
1038 qla24xx_write_flash_data(scsi_qla_host_t
*vha
, uint32_t *dwptr
, uint32_t faddr
,
1043 uint32_t sec_mask
, rest_addr
;
1045 dma_addr_t optrom_dma
;
1046 void *optrom
= NULL
;
1047 struct qla_hw_data
*ha
= vha
->hw
;
1049 /* Prepare burst-capable write on supported ISPs. */
1050 if ((IS_QLA25XX(ha
) || IS_QLA81XX(ha
)) && !(faddr
& 0xfff) &&
1051 dwords
> OPTROM_BURST_DWORDS
) {
1052 optrom
= dma_alloc_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
1053 &optrom_dma
, GFP_KERNEL
);
1055 qla_printk(KERN_DEBUG
, ha
,
1056 "Unable to allocate memory for optrom burst write "
1057 "(%x KB).\n", OPTROM_BURST_SIZE
/ 1024);
1061 rest_addr
= (ha
->fdt_block_size
>> 2) - 1;
1062 sec_mask
= ~rest_addr
;
1064 ret
= qla24xx_unprotect_flash(vha
);
1065 if (ret
!= QLA_SUCCESS
) {
1066 qla_printk(KERN_WARNING
, ha
,
1067 "Unable to unprotect flash for update.\n");
1071 for (liter
= 0; liter
< dwords
; liter
++, faddr
++, dwptr
++) {
1072 fdata
= (faddr
& sec_mask
) << 2;
1074 /* Are we at the beginning of a sector? */
1075 if ((faddr
& rest_addr
) == 0) {
1076 /* Do sector unprotect. */
1077 if (ha
->fdt_unprotect_sec_cmd
)
1078 qla24xx_write_flash_dword(ha
,
1079 ha
->fdt_unprotect_sec_cmd
,
1080 (fdata
& 0xff00) | ((fdata
<< 16) &
1081 0xff0000) | ((fdata
>> 16) & 0xff));
1082 ret
= qla24xx_erase_sector(vha
, fdata
);
1083 if (ret
!= QLA_SUCCESS
) {
1084 DEBUG9(qla_printk(KERN_WARNING
, ha
,
1085 "Unable to erase sector: address=%x.\n",
1091 /* Go with burst-write. */
1092 if (optrom
&& (liter
+ OPTROM_BURST_DWORDS
) <= dwords
) {
1093 /* Copy data to DMA'ble buffer. */
1094 memcpy(optrom
, dwptr
, OPTROM_BURST_SIZE
);
1096 ret
= qla2x00_load_ram(vha
, optrom_dma
,
1097 flash_data_addr(ha
, faddr
),
1098 OPTROM_BURST_DWORDS
);
1099 if (ret
!= QLA_SUCCESS
) {
1100 qla_printk(KERN_WARNING
, ha
,
1101 "Unable to burst-write optrom segment "
1102 "(%x/%x/%llx).\n", ret
,
1103 flash_data_addr(ha
, faddr
),
1104 (unsigned long long)optrom_dma
);
1105 qla_printk(KERN_WARNING
, ha
,
1106 "Reverting to slow-write.\n");
1108 dma_free_coherent(&ha
->pdev
->dev
,
1109 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
1112 liter
+= OPTROM_BURST_DWORDS
- 1;
1113 faddr
+= OPTROM_BURST_DWORDS
- 1;
1114 dwptr
+= OPTROM_BURST_DWORDS
- 1;
1119 ret
= qla24xx_write_flash_dword(ha
,
1120 flash_data_addr(ha
, faddr
), cpu_to_le32(*dwptr
));
1121 if (ret
!= QLA_SUCCESS
) {
1122 DEBUG9(printk("%s(%ld) Unable to program flash "
1123 "address=%x data=%x.\n", __func__
,
1124 vha
->host_no
, faddr
, *dwptr
));
1128 /* Do sector protect. */
1129 if (ha
->fdt_unprotect_sec_cmd
&&
1130 ((faddr
& rest_addr
) == rest_addr
))
1131 qla24xx_write_flash_dword(ha
,
1132 ha
->fdt_protect_sec_cmd
,
1133 (fdata
& 0xff00) | ((fdata
<< 16) &
1134 0xff0000) | ((fdata
>> 16) & 0xff));
1137 ret
= qla24xx_protect_flash(vha
);
1138 if (ret
!= QLA_SUCCESS
)
1139 qla_printk(KERN_WARNING
, ha
,
1140 "Unable to protect flash after update.\n");
1143 dma_free_coherent(&ha
->pdev
->dev
,
1144 OPTROM_BURST_SIZE
, optrom
, optrom_dma
);
1150 qla2x00_read_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1155 struct qla_hw_data
*ha
= vha
->hw
;
1157 /* Word reads to NVRAM via registers. */
1158 wptr
= (uint16_t *)buf
;
1159 qla2x00_lock_nvram_access(ha
);
1160 for (i
= 0; i
< bytes
>> 1; i
++, naddr
++)
1161 wptr
[i
] = cpu_to_le16(qla2x00_get_nvram_word(ha
,
1163 qla2x00_unlock_nvram_access(ha
);
1169 qla24xx_read_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1174 struct qla_hw_data
*ha
= vha
->hw
;
1176 /* Dword reads to flash. */
1177 dwptr
= (uint32_t *)buf
;
1178 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++)
1179 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
1180 nvram_data_addr(ha
, naddr
)));
1186 qla2x00_write_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1192 unsigned long flags
;
1193 struct qla_hw_data
*ha
= vha
->hw
;
1197 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1198 qla2x00_lock_nvram_access(ha
);
1200 /* Disable NVRAM write-protection. */
1201 stat
= qla2x00_clear_nvram_protection(ha
);
1203 wptr
= (uint16_t *)buf
;
1204 for (i
= 0; i
< bytes
>> 1; i
++, naddr
++) {
1205 qla2x00_write_nvram_word(ha
, naddr
,
1206 cpu_to_le16(*wptr
));
1210 /* Enable NVRAM write-protection. */
1211 qla2x00_set_nvram_protection(ha
, stat
);
1213 qla2x00_unlock_nvram_access(ha
);
1214 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1220 qla24xx_write_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1226 struct qla_hw_data
*ha
= vha
->hw
;
1227 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1231 /* Enable flash write. */
1232 WRT_REG_DWORD(®
->ctrl_status
,
1233 RD_REG_DWORD(®
->ctrl_status
) | CSRX_FLASH_ENABLE
);
1234 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
1236 /* Disable NVRAM write-protection. */
1237 qla24xx_write_flash_dword(ha
, nvram_conf_addr(ha
, 0x101), 0);
1238 qla24xx_write_flash_dword(ha
, nvram_conf_addr(ha
, 0x101), 0);
1240 /* Dword writes to flash. */
1241 dwptr
= (uint32_t *)buf
;
1242 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++, dwptr
++) {
1243 ret
= qla24xx_write_flash_dword(ha
,
1244 nvram_data_addr(ha
, naddr
), cpu_to_le32(*dwptr
));
1245 if (ret
!= QLA_SUCCESS
) {
1246 DEBUG9(qla_printk(KERN_WARNING
, ha
,
1247 "Unable to program nvram address=%x data=%x.\n",
1253 /* Enable NVRAM write-protection. */
1254 qla24xx_write_flash_dword(ha
, nvram_conf_addr(ha
, 0x101), 0x8c);
1256 /* Disable flash write. */
1257 WRT_REG_DWORD(®
->ctrl_status
,
1258 RD_REG_DWORD(®
->ctrl_status
) & ~CSRX_FLASH_ENABLE
);
1259 RD_REG_DWORD(®
->ctrl_status
); /* PCI Posting. */
1265 qla25xx_read_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1270 struct qla_hw_data
*ha
= vha
->hw
;
1272 /* Dword reads to flash. */
1273 dwptr
= (uint32_t *)buf
;
1274 for (i
= 0; i
< bytes
>> 2; i
++, naddr
++)
1275 dwptr
[i
] = cpu_to_le32(qla24xx_read_flash_dword(ha
,
1276 flash_data_addr(ha
, ha
->flt_region_vpd_nvram
| naddr
)));
1282 qla25xx_write_nvram_data(scsi_qla_host_t
*vha
, uint8_t *buf
, uint32_t naddr
,
1285 struct qla_hw_data
*ha
= vha
->hw
;
1286 #define RMW_BUFFER_SIZE (64 * 1024)
1289 dbuf
= vmalloc(RMW_BUFFER_SIZE
);
1291 return QLA_MEMORY_ALLOC_FAILED
;
1292 ha
->isp_ops
->read_optrom(vha
, dbuf
, ha
->flt_region_vpd_nvram
<< 2,
1294 memcpy(dbuf
+ (naddr
<< 2), buf
, bytes
);
1295 ha
->isp_ops
->write_optrom(vha
, dbuf
, ha
->flt_region_vpd_nvram
<< 2,
1303 qla2x00_flip_colors(struct qla_hw_data
*ha
, uint16_t *pflags
)
1305 if (IS_QLA2322(ha
)) {
1306 /* Flip all colors. */
1307 if (ha
->beacon_color_state
== QLA_LED_ALL_ON
) {
1309 ha
->beacon_color_state
= 0;
1310 *pflags
= GPIO_LED_ALL_OFF
;
1313 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1314 *pflags
= GPIO_LED_RGA_ON
;
1317 /* Flip green led only. */
1318 if (ha
->beacon_color_state
== QLA_LED_GRN_ON
) {
1320 ha
->beacon_color_state
= 0;
1321 *pflags
= GPIO_LED_GREEN_OFF_AMBER_OFF
;
1324 ha
->beacon_color_state
= QLA_LED_GRN_ON
;
1325 *pflags
= GPIO_LED_GREEN_ON_AMBER_OFF
;
1330 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1333 qla2x00_beacon_blink(struct scsi_qla_host
*vha
)
1335 uint16_t gpio_enable
;
1337 uint16_t led_color
= 0;
1338 unsigned long flags
;
1339 struct qla_hw_data
*ha
= vha
->hw
;
1340 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1342 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1344 /* Save the Original GPIOE. */
1345 if (ha
->pio_address
) {
1346 gpio_enable
= RD_REG_WORD_PIO(PIO_REG(ha
, gpioe
));
1347 gpio_data
= RD_REG_WORD_PIO(PIO_REG(ha
, gpiod
));
1349 gpio_enable
= RD_REG_WORD(®
->gpioe
);
1350 gpio_data
= RD_REG_WORD(®
->gpiod
);
1353 /* Set the modified gpio_enable values */
1354 gpio_enable
|= GPIO_LED_MASK
;
1356 if (ha
->pio_address
) {
1357 WRT_REG_WORD_PIO(PIO_REG(ha
, gpioe
), gpio_enable
);
1359 WRT_REG_WORD(®
->gpioe
, gpio_enable
);
1360 RD_REG_WORD(®
->gpioe
);
1363 qla2x00_flip_colors(ha
, &led_color
);
1365 /* Clear out any previously set LED color. */
1366 gpio_data
&= ~GPIO_LED_MASK
;
1368 /* Set the new input LED color to GPIOD. */
1369 gpio_data
|= led_color
;
1371 /* Set the modified gpio_data values */
1372 if (ha
->pio_address
) {
1373 WRT_REG_WORD_PIO(PIO_REG(ha
, gpiod
), gpio_data
);
1375 WRT_REG_WORD(®
->gpiod
, gpio_data
);
1376 RD_REG_WORD(®
->gpiod
);
1379 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1383 qla2x00_beacon_on(struct scsi_qla_host
*vha
)
1385 uint16_t gpio_enable
;
1387 unsigned long flags
;
1388 struct qla_hw_data
*ha
= vha
->hw
;
1389 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1391 ha
->fw_options
[1] &= ~FO1_SET_EMPHASIS_SWING
;
1392 ha
->fw_options
[1] |= FO1_DISABLE_GPIO6_7
;
1394 if (qla2x00_set_fw_options(vha
, ha
->fw_options
) != QLA_SUCCESS
) {
1395 qla_printk(KERN_WARNING
, ha
,
1396 "Unable to update fw options (beacon on).\n");
1397 return QLA_FUNCTION_FAILED
;
1400 /* Turn off LEDs. */
1401 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1402 if (ha
->pio_address
) {
1403 gpio_enable
= RD_REG_WORD_PIO(PIO_REG(ha
, gpioe
));
1404 gpio_data
= RD_REG_WORD_PIO(PIO_REG(ha
, gpiod
));
1406 gpio_enable
= RD_REG_WORD(®
->gpioe
);
1407 gpio_data
= RD_REG_WORD(®
->gpiod
);
1409 gpio_enable
|= GPIO_LED_MASK
;
1411 /* Set the modified gpio_enable values. */
1412 if (ha
->pio_address
) {
1413 WRT_REG_WORD_PIO(PIO_REG(ha
, gpioe
), gpio_enable
);
1415 WRT_REG_WORD(®
->gpioe
, gpio_enable
);
1416 RD_REG_WORD(®
->gpioe
);
1419 /* Clear out previously set LED colour. */
1420 gpio_data
&= ~GPIO_LED_MASK
;
1421 if (ha
->pio_address
) {
1422 WRT_REG_WORD_PIO(PIO_REG(ha
, gpiod
), gpio_data
);
1424 WRT_REG_WORD(®
->gpiod
, gpio_data
);
1425 RD_REG_WORD(®
->gpiod
);
1427 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1430 * Let the per HBA timer kick off the blinking process based on
1431 * the following flags. No need to do anything else now.
1433 ha
->beacon_blink_led
= 1;
1434 ha
->beacon_color_state
= 0;
1440 qla2x00_beacon_off(struct scsi_qla_host
*vha
)
1442 int rval
= QLA_SUCCESS
;
1443 struct qla_hw_data
*ha
= vha
->hw
;
1445 ha
->beacon_blink_led
= 0;
1447 /* Set the on flag so when it gets flipped it will be off. */
1449 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1451 ha
->beacon_color_state
= QLA_LED_GRN_ON
;
1453 ha
->isp_ops
->beacon_blink(vha
); /* This turns green LED off */
1455 ha
->fw_options
[1] &= ~FO1_SET_EMPHASIS_SWING
;
1456 ha
->fw_options
[1] &= ~FO1_DISABLE_GPIO6_7
;
1458 rval
= qla2x00_set_fw_options(vha
, ha
->fw_options
);
1459 if (rval
!= QLA_SUCCESS
)
1460 qla_printk(KERN_WARNING
, ha
,
1461 "Unable to update fw options (beacon off).\n");
1467 qla24xx_flip_colors(struct qla_hw_data
*ha
, uint16_t *pflags
)
1469 /* Flip all colors. */
1470 if (ha
->beacon_color_state
== QLA_LED_ALL_ON
) {
1472 ha
->beacon_color_state
= 0;
1476 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1477 *pflags
= GPDX_LED_YELLOW_ON
| GPDX_LED_AMBER_ON
;
1482 qla24xx_beacon_blink(struct scsi_qla_host
*vha
)
1484 uint16_t led_color
= 0;
1486 unsigned long flags
;
1487 struct qla_hw_data
*ha
= vha
->hw
;
1488 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1490 /* Save the Original GPIOD. */
1491 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1492 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1494 /* Enable the gpio_data reg for update. */
1495 gpio_data
|= GPDX_LED_UPDATE_MASK
;
1497 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1498 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1500 /* Set the color bits. */
1501 qla24xx_flip_colors(ha
, &led_color
);
1503 /* Clear out any previously set LED color. */
1504 gpio_data
&= ~GPDX_LED_COLOR_MASK
;
1506 /* Set the new input LED color to GPIOD. */
1507 gpio_data
|= led_color
;
1509 /* Set the modified gpio_data values. */
1510 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1511 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1512 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1516 qla24xx_beacon_on(struct scsi_qla_host
*vha
)
1519 unsigned long flags
;
1520 struct qla_hw_data
*ha
= vha
->hw
;
1521 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1523 if (ha
->beacon_blink_led
== 0) {
1524 /* Enable firmware for update */
1525 ha
->fw_options
[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL
;
1527 if (qla2x00_set_fw_options(vha
, ha
->fw_options
) != QLA_SUCCESS
)
1528 return QLA_FUNCTION_FAILED
;
1530 if (qla2x00_get_fw_options(vha
, ha
->fw_options
) !=
1532 qla_printk(KERN_WARNING
, ha
,
1533 "Unable to update fw options (beacon on).\n");
1534 return QLA_FUNCTION_FAILED
;
1537 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1538 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1540 /* Enable the gpio_data reg for update. */
1541 gpio_data
|= GPDX_LED_UPDATE_MASK
;
1542 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1543 RD_REG_DWORD(®
->gpiod
);
1545 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1548 /* So all colors blink together. */
1549 ha
->beacon_color_state
= 0;
1551 /* Let the per HBA timer kick off the blinking process. */
1552 ha
->beacon_blink_led
= 1;
1558 qla24xx_beacon_off(struct scsi_qla_host
*vha
)
1561 unsigned long flags
;
1562 struct qla_hw_data
*ha
= vha
->hw
;
1563 struct device_reg_24xx __iomem
*reg
= &ha
->iobase
->isp24
;
1565 ha
->beacon_blink_led
= 0;
1566 ha
->beacon_color_state
= QLA_LED_ALL_ON
;
1568 ha
->isp_ops
->beacon_blink(vha
); /* Will flip to all off. */
1570 /* Give control back to firmware. */
1571 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1572 gpio_data
= RD_REG_DWORD(®
->gpiod
);
1574 /* Disable the gpio_data reg for update. */
1575 gpio_data
&= ~GPDX_LED_UPDATE_MASK
;
1576 WRT_REG_DWORD(®
->gpiod
, gpio_data
);
1577 RD_REG_DWORD(®
->gpiod
);
1578 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1580 ha
->fw_options
[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL
;
1582 if (qla2x00_set_fw_options(vha
, ha
->fw_options
) != QLA_SUCCESS
) {
1583 qla_printk(KERN_WARNING
, ha
,
1584 "Unable to update fw options (beacon off).\n");
1585 return QLA_FUNCTION_FAILED
;
1588 if (qla2x00_get_fw_options(vha
, ha
->fw_options
) != QLA_SUCCESS
) {
1589 qla_printk(KERN_WARNING
, ha
,
1590 "Unable to get fw options (beacon off).\n");
1591 return QLA_FUNCTION_FAILED
;
1599 * Flash support routines
1603 * qla2x00_flash_enable() - Setup flash for reading and writing.
1607 qla2x00_flash_enable(struct qla_hw_data
*ha
)
1610 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1612 data
= RD_REG_WORD(®
->ctrl_status
);
1613 data
|= CSR_FLASH_ENABLE
;
1614 WRT_REG_WORD(®
->ctrl_status
, data
);
1615 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1619 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1623 qla2x00_flash_disable(struct qla_hw_data
*ha
)
1626 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1628 data
= RD_REG_WORD(®
->ctrl_status
);
1629 data
&= ~(CSR_FLASH_ENABLE
);
1630 WRT_REG_WORD(®
->ctrl_status
, data
);
1631 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1635 * qla2x00_read_flash_byte() - Reads a byte from flash
1637 * @addr: Address in flash to read
1639 * A word is read from the chip, but, only the lower byte is valid.
1641 * Returns the byte read from flash @addr.
1644 qla2x00_read_flash_byte(struct qla_hw_data
*ha
, uint32_t addr
)
1647 uint16_t bank_select
;
1648 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1650 bank_select
= RD_REG_WORD(®
->ctrl_status
);
1652 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
1653 /* Specify 64K address range: */
1654 /* clear out Module Select and Flash Address bits [19:16]. */
1655 bank_select
&= ~0xf8;
1656 bank_select
|= addr
>> 12 & 0xf0;
1657 bank_select
|= CSR_FLASH_64K_BANK
;
1658 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1659 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1661 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1662 data
= RD_REG_WORD(®
->flash_data
);
1664 return (uint8_t)data
;
1667 /* Setup bit 16 of flash address. */
1668 if ((addr
& BIT_16
) && ((bank_select
& CSR_FLASH_64K_BANK
) == 0)) {
1669 bank_select
|= CSR_FLASH_64K_BANK
;
1670 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1671 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1672 } else if (((addr
& BIT_16
) == 0) &&
1673 (bank_select
& CSR_FLASH_64K_BANK
)) {
1674 bank_select
&= ~(CSR_FLASH_64K_BANK
);
1675 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1676 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1679 /* Always perform IO mapped accesses to the FLASH registers. */
1680 if (ha
->pio_address
) {
1683 WRT_REG_WORD_PIO(PIO_REG(ha
, flash_address
), (uint16_t)addr
);
1685 data
= RD_REG_WORD_PIO(PIO_REG(ha
, flash_data
));
1688 data2
= RD_REG_WORD_PIO(PIO_REG(ha
, flash_data
));
1689 } while (data
!= data2
);
1691 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1692 data
= qla2x00_debounce_register(®
->flash_data
);
1695 return (uint8_t)data
;
1699 * qla2x00_write_flash_byte() - Write a byte to flash
1701 * @addr: Address in flash to write
1702 * @data: Data to write
1705 qla2x00_write_flash_byte(struct qla_hw_data
*ha
, uint32_t addr
, uint8_t data
)
1707 uint16_t bank_select
;
1708 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1710 bank_select
= RD_REG_WORD(®
->ctrl_status
);
1711 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
1712 /* Specify 64K address range: */
1713 /* clear out Module Select and Flash Address bits [19:16]. */
1714 bank_select
&= ~0xf8;
1715 bank_select
|= addr
>> 12 & 0xf0;
1716 bank_select
|= CSR_FLASH_64K_BANK
;
1717 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1718 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1720 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1721 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1722 WRT_REG_WORD(®
->flash_data
, (uint16_t)data
);
1723 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1728 /* Setup bit 16 of flash address. */
1729 if ((addr
& BIT_16
) && ((bank_select
& CSR_FLASH_64K_BANK
) == 0)) {
1730 bank_select
|= CSR_FLASH_64K_BANK
;
1731 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1732 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1733 } else if (((addr
& BIT_16
) == 0) &&
1734 (bank_select
& CSR_FLASH_64K_BANK
)) {
1735 bank_select
&= ~(CSR_FLASH_64K_BANK
);
1736 WRT_REG_WORD(®
->ctrl_status
, bank_select
);
1737 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1740 /* Always perform IO mapped accesses to the FLASH registers. */
1741 if (ha
->pio_address
) {
1742 WRT_REG_WORD_PIO(PIO_REG(ha
, flash_address
), (uint16_t)addr
);
1743 WRT_REG_WORD_PIO(PIO_REG(ha
, flash_data
), (uint16_t)data
);
1745 WRT_REG_WORD(®
->flash_address
, (uint16_t)addr
);
1746 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1747 WRT_REG_WORD(®
->flash_data
, (uint16_t)data
);
1748 RD_REG_WORD(®
->ctrl_status
); /* PCI Posting. */
1753 * qla2x00_poll_flash() - Polls flash for completion.
1755 * @addr: Address in flash to poll
1756 * @poll_data: Data to be polled
1757 * @man_id: Flash manufacturer ID
1758 * @flash_id: Flash ID
1760 * This function polls the device until bit 7 of what is read matches data
1761 * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
1762 * out (a fatal error). The flash book recommeds reading bit 7 again after
1763 * reading bit 5 as a 1.
1765 * Returns 0 on success, else non-zero.
1768 qla2x00_poll_flash(struct qla_hw_data
*ha
, uint32_t addr
, uint8_t poll_data
,
1769 uint8_t man_id
, uint8_t flash_id
)
1777 /* Wait for 30 seconds for command to finish. */
1779 for (cnt
= 3000000; cnt
; cnt
--) {
1780 flash_data
= qla2x00_read_flash_byte(ha
, addr
);
1781 if ((flash_data
& BIT_7
) == poll_data
) {
1786 if (man_id
!= 0x40 && man_id
!= 0xda) {
1787 if ((flash_data
& BIT_5
) && cnt
> 2)
1798 * qla2x00_program_flash_address() - Programs a flash address
1800 * @addr: Address in flash to program
1801 * @data: Data to be written in flash
1802 * @man_id: Flash manufacturer ID
1803 * @flash_id: Flash ID
1805 * Returns 0 on success, else non-zero.
1808 qla2x00_program_flash_address(struct qla_hw_data
*ha
, uint32_t addr
,
1809 uint8_t data
, uint8_t man_id
, uint8_t flash_id
)
1811 /* Write Program Command Sequence. */
1812 if (IS_OEM_001(ha
)) {
1813 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1814 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1815 qla2x00_write_flash_byte(ha
, 0xaaa, 0xa0);
1816 qla2x00_write_flash_byte(ha
, addr
, data
);
1818 if (man_id
== 0xda && flash_id
== 0xc1) {
1819 qla2x00_write_flash_byte(ha
, addr
, data
);
1823 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1824 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1825 qla2x00_write_flash_byte(ha
, 0x5555, 0xa0);
1826 qla2x00_write_flash_byte(ha
, addr
, data
);
1832 /* Wait for write to complete. */
1833 return qla2x00_poll_flash(ha
, addr
, data
, man_id
, flash_id
);
1837 * qla2x00_erase_flash() - Erase the flash.
1839 * @man_id: Flash manufacturer ID
1840 * @flash_id: Flash ID
1842 * Returns 0 on success, else non-zero.
1845 qla2x00_erase_flash(struct qla_hw_data
*ha
, uint8_t man_id
, uint8_t flash_id
)
1847 /* Individual Sector Erase Command Sequence */
1848 if (IS_OEM_001(ha
)) {
1849 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1850 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1851 qla2x00_write_flash_byte(ha
, 0xaaa, 0x80);
1852 qla2x00_write_flash_byte(ha
, 0xaaa, 0xaa);
1853 qla2x00_write_flash_byte(ha
, 0x555, 0x55);
1854 qla2x00_write_flash_byte(ha
, 0xaaa, 0x10);
1856 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1857 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1858 qla2x00_write_flash_byte(ha
, 0x5555, 0x80);
1859 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1860 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1861 qla2x00_write_flash_byte(ha
, 0x5555, 0x10);
1866 /* Wait for erase to complete. */
1867 return qla2x00_poll_flash(ha
, 0x00, 0x80, man_id
, flash_id
);
1871 * qla2x00_erase_flash_sector() - Erase a flash sector.
1873 * @addr: Flash sector to erase
1874 * @sec_mask: Sector address mask
1875 * @man_id: Flash manufacturer ID
1876 * @flash_id: Flash ID
1878 * Returns 0 on success, else non-zero.
1881 qla2x00_erase_flash_sector(struct qla_hw_data
*ha
, uint32_t addr
,
1882 uint32_t sec_mask
, uint8_t man_id
, uint8_t flash_id
)
1884 /* Individual Sector Erase Command Sequence */
1885 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1886 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1887 qla2x00_write_flash_byte(ha
, 0x5555, 0x80);
1888 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1889 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1890 if (man_id
== 0x1f && flash_id
== 0x13)
1891 qla2x00_write_flash_byte(ha
, addr
& sec_mask
, 0x10);
1893 qla2x00_write_flash_byte(ha
, addr
& sec_mask
, 0x30);
1897 /* Wait for erase to complete. */
1898 return qla2x00_poll_flash(ha
, addr
, 0x80, man_id
, flash_id
);
1902 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1903 * @man_id: Flash manufacturer ID
1904 * @flash_id: Flash ID
1907 qla2x00_get_flash_manufacturer(struct qla_hw_data
*ha
, uint8_t *man_id
,
1910 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1911 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1912 qla2x00_write_flash_byte(ha
, 0x5555, 0x90);
1913 *man_id
= qla2x00_read_flash_byte(ha
, 0x0000);
1914 *flash_id
= qla2x00_read_flash_byte(ha
, 0x0001);
1915 qla2x00_write_flash_byte(ha
, 0x5555, 0xaa);
1916 qla2x00_write_flash_byte(ha
, 0x2aaa, 0x55);
1917 qla2x00_write_flash_byte(ha
, 0x5555, 0xf0);
1921 qla2x00_read_flash_data(struct qla_hw_data
*ha
, uint8_t *tmp_buf
,
1922 uint32_t saddr
, uint32_t length
)
1924 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1925 uint32_t midpoint
, ilength
;
1928 midpoint
= length
/ 2;
1930 WRT_REG_WORD(®
->nvram
, 0);
1931 RD_REG_WORD(®
->nvram
);
1932 for (ilength
= 0; ilength
< length
; saddr
++, ilength
++, tmp_buf
++) {
1933 if (ilength
== midpoint
) {
1934 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
1935 RD_REG_WORD(®
->nvram
);
1937 data
= qla2x00_read_flash_byte(ha
, saddr
);
1946 qla2x00_suspend_hba(struct scsi_qla_host
*vha
)
1949 unsigned long flags
;
1950 struct qla_hw_data
*ha
= vha
->hw
;
1951 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1954 scsi_block_requests(vha
->host
);
1955 ha
->isp_ops
->disable_intrs(ha
);
1956 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
1959 spin_lock_irqsave(&ha
->hardware_lock
, flags
);
1960 WRT_REG_WORD(®
->hccr
, HCCR_PAUSE_RISC
);
1961 RD_REG_WORD(®
->hccr
);
1962 if (IS_QLA2100(ha
) || IS_QLA2200(ha
) || IS_QLA2300(ha
)) {
1963 for (cnt
= 0; cnt
< 30000; cnt
++) {
1964 if ((RD_REG_WORD(®
->hccr
) & HCCR_RISC_PAUSE
) != 0)
1971 spin_unlock_irqrestore(&ha
->hardware_lock
, flags
);
1975 qla2x00_resume_hba(struct scsi_qla_host
*vha
)
1977 struct qla_hw_data
*ha
= vha
->hw
;
1980 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
1981 set_bit(ISP_ABORT_NEEDED
, &vha
->dpc_flags
);
1982 qla2xxx_wake_dpc(vha
);
1983 qla2x00_wait_for_chip_reset(vha
);
1984 scsi_unblock_requests(vha
->host
);
1988 qla2x00_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
1989 uint32_t offset
, uint32_t length
)
1991 uint32_t addr
, midpoint
;
1993 struct qla_hw_data
*ha
= vha
->hw
;
1994 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
1997 qla2x00_suspend_hba(vha
);
2000 midpoint
= ha
->optrom_size
/ 2;
2002 qla2x00_flash_enable(ha
);
2003 WRT_REG_WORD(®
->nvram
, 0);
2004 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
2005 for (addr
= offset
, data
= buf
; addr
< length
; addr
++, data
++) {
2006 if (addr
== midpoint
) {
2007 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
2008 RD_REG_WORD(®
->nvram
); /* PCI Posting. */
2011 *data
= qla2x00_read_flash_byte(ha
, addr
);
2013 qla2x00_flash_disable(ha
);
2016 qla2x00_resume_hba(vha
);
2022 qla2x00_write_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2023 uint32_t offset
, uint32_t length
)
2027 uint8_t man_id
, flash_id
, sec_number
, data
;
2029 uint32_t addr
, liter
, sec_mask
, rest_addr
;
2030 struct qla_hw_data
*ha
= vha
->hw
;
2031 struct device_reg_2xxx __iomem
*reg
= &ha
->iobase
->isp
;
2034 qla2x00_suspend_hba(vha
);
2039 /* Reset ISP chip. */
2040 WRT_REG_WORD(®
->ctrl_status
, CSR_ISP_SOFT_RESET
);
2041 pci_read_config_word(ha
->pdev
, PCI_COMMAND
, &wd
);
2043 /* Go with write. */
2044 qla2x00_flash_enable(ha
);
2045 do { /* Loop once to provide quick error exit */
2046 /* Structure of flash memory based on manufacturer */
2047 if (IS_OEM_001(ha
)) {
2048 /* OEM variant with special flash part. */
2049 man_id
= flash_id
= 0;
2054 qla2x00_get_flash_manufacturer(ha
, &man_id
, &flash_id
);
2056 case 0x20: /* ST flash. */
2057 if (flash_id
== 0xd2 || flash_id
== 0xe3) {
2059 * ST m29w008at part - 64kb sector size with
2060 * 32kb,8kb,8kb,16kb sectors at memory address
2068 * ST m29w010b part - 16kb sector size
2069 * Default to 16kb sectors
2074 case 0x40: /* Mostel flash. */
2075 /* Mostel v29c51001 part - 512 byte sector size. */
2079 case 0xbf: /* SST flash. */
2080 /* SST39sf10 part - 4kb sector size. */
2084 case 0xda: /* Winbond flash. */
2085 /* Winbond W29EE011 part - 256 byte sector size. */
2089 case 0xc2: /* Macronix flash. */
2090 /* 64k sector size. */
2091 if (flash_id
== 0x38 || flash_id
== 0x4f) {
2096 /* Fall through... */
2098 case 0x1f: /* Atmel flash. */
2099 /* 512k sector size. */
2100 if (flash_id
== 0x13) {
2101 rest_addr
= 0x7fffffff;
2102 sec_mask
= 0x80000000;
2105 /* Fall through... */
2107 case 0x01: /* AMD flash. */
2108 if (flash_id
== 0x38 || flash_id
== 0x40 ||
2110 /* Am29LV081 part - 64kb sector size. */
2111 /* Am29LV002BT part - 64kb sector size. */
2115 } else if (flash_id
== 0x3e) {
2117 * Am29LV008b part - 64kb sector size with
2118 * 32kb,8kb,8kb,16kb sector at memory address
2124 } else if (flash_id
== 0x20 || flash_id
== 0x6e) {
2126 * Am29LV010 part or AM29f010 - 16kb sector
2132 } else if (flash_id
== 0x6d) {
2133 /* Am29LV001 part - 8kb sector size. */
2139 /* Default to 16 kb sector size. */
2146 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
2147 if (qla2x00_erase_flash(ha
, man_id
, flash_id
)) {
2148 rval
= QLA_FUNCTION_FAILED
;
2153 for (addr
= offset
, liter
= 0; liter
< length
; liter
++,
2156 /* Are we at the beginning of a sector? */
2157 if ((addr
& rest_addr
) == 0) {
2158 if (IS_QLA2322(ha
) || IS_QLA6322(ha
)) {
2159 if (addr
>= 0x10000UL
) {
2160 if (((addr
>> 12) & 0xf0) &&
2162 flash_id
== 0x3e) ||
2164 flash_id
== 0xd2))) {
2166 if (sec_number
== 1) {
2187 } else if (addr
== ha
->optrom_size
/ 2) {
2188 WRT_REG_WORD(®
->nvram
, NVR_SELECT
);
2189 RD_REG_WORD(®
->nvram
);
2192 if (flash_id
== 0xda && man_id
== 0xc1) {
2193 qla2x00_write_flash_byte(ha
, 0x5555,
2195 qla2x00_write_flash_byte(ha
, 0x2aaa,
2197 qla2x00_write_flash_byte(ha
, 0x5555,
2199 } else if (!IS_QLA2322(ha
) && !IS_QLA6322(ha
)) {
2201 if (qla2x00_erase_flash_sector(ha
,
2202 addr
, sec_mask
, man_id
,
2204 rval
= QLA_FUNCTION_FAILED
;
2207 if (man_id
== 0x01 && flash_id
== 0x6d)
2212 if (man_id
== 0x01 && flash_id
== 0x6d) {
2213 if (sec_number
== 1 &&
2214 addr
== (rest_addr
- 1)) {
2217 } else if (sec_number
== 3 && (addr
& 0x7ffe)) {
2223 if (qla2x00_program_flash_address(ha
, addr
, data
,
2224 man_id
, flash_id
)) {
2225 rval
= QLA_FUNCTION_FAILED
;
2231 qla2x00_flash_disable(ha
);
2234 qla2x00_resume_hba(vha
);
2240 qla24xx_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2241 uint32_t offset
, uint32_t length
)
2243 struct qla_hw_data
*ha
= vha
->hw
;
2246 scsi_block_requests(vha
->host
);
2247 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2250 qla24xx_read_flash_data(vha
, (uint32_t *)buf
, offset
>> 2, length
>> 2);
2253 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2254 scsi_unblock_requests(vha
->host
);
2260 qla24xx_write_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2261 uint32_t offset
, uint32_t length
)
2264 struct qla_hw_data
*ha
= vha
->hw
;
2267 scsi_block_requests(vha
->host
);
2268 set_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2270 /* Go with write. */
2271 rval
= qla24xx_write_flash_data(vha
, (uint32_t *)buf
, offset
>> 2,
2274 clear_bit(MBX_UPDATE_FLASH_ACTIVE
, &ha
->mbx_cmd_flags
);
2275 scsi_unblock_requests(vha
->host
);
2281 qla25xx_read_optrom_data(struct scsi_qla_host
*vha
, uint8_t *buf
,
2282 uint32_t offset
, uint32_t length
)
2285 dma_addr_t optrom_dma
;
2288 uint32_t faddr
, left
, burst
;
2289 struct qla_hw_data
*ha
= vha
->hw
;
2293 if (length
< OPTROM_BURST_SIZE
)
2296 optrom
= dma_alloc_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
2297 &optrom_dma
, GFP_KERNEL
);
2299 qla_printk(KERN_DEBUG
, ha
,
2300 "Unable to allocate memory for optrom burst read "
2301 "(%x KB).\n", OPTROM_BURST_SIZE
/ 1024);
2307 faddr
= offset
>> 2;
2309 burst
= OPTROM_BURST_DWORDS
;
2314 rval
= qla2x00_dump_ram(vha
, optrom_dma
,
2315 flash_data_addr(ha
, faddr
), burst
);
2317 qla_printk(KERN_WARNING
, ha
,
2318 "Unable to burst-read optrom segment "
2319 "(%x/%x/%llx).\n", rval
,
2320 flash_data_addr(ha
, faddr
),
2321 (unsigned long long)optrom_dma
);
2322 qla_printk(KERN_WARNING
, ha
,
2323 "Reverting to slow-read.\n");
2325 dma_free_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
,
2326 optrom
, optrom_dma
);
2330 memcpy(pbuf
, optrom
, burst
* 4);
2337 dma_free_coherent(&ha
->pdev
->dev
, OPTROM_BURST_SIZE
, optrom
,
2343 return qla24xx_read_optrom_data(vha
, buf
, offset
, length
);
2347 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
2349 * @pcids: Pointer to the FCODE PCI data structure
2351 * The process of retrieving the FCODE version information is at best
2352 * described as interesting.
2354 * Within the first 100h bytes of the image an ASCII string is present
2355 * which contains several pieces of information including the FCODE
2356 * version. Unfortunately it seems the only reliable way to retrieve
2357 * the version is by scanning for another sentinel within the string,
2358 * the FCODE build date:
2360 * ... 2.00.02 10/17/02 ...
2362 * Returns QLA_SUCCESS on successful retrieval of version.
2365 qla2x00_get_fcode_version(struct qla_hw_data
*ha
, uint32_t pcids
)
2367 int ret
= QLA_FUNCTION_FAILED
;
2368 uint32_t istart
, iend
, iter
, vend
;
2369 uint8_t do_next
, rbyte
, *vbyte
;
2371 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2373 /* Skip the PCI data structure. */
2375 ((qla2x00_read_flash_byte(ha
, pcids
+ 0x0B) << 8) |
2376 qla2x00_read_flash_byte(ha
, pcids
+ 0x0A));
2377 iend
= istart
+ 0x100;
2379 /* Scan for the sentinel date string...eeewww. */
2382 while ((iter
< iend
) && !do_next
) {
2384 if (qla2x00_read_flash_byte(ha
, iter
) == '/') {
2385 if (qla2x00_read_flash_byte(ha
, iter
+ 2) ==
2388 else if (qla2x00_read_flash_byte(ha
,
2396 /* Backtrack to previous ' ' (space). */
2398 while ((iter
> istart
) && !do_next
) {
2400 if (qla2x00_read_flash_byte(ha
, iter
) == ' ')
2407 * Mark end of version tag, and find previous ' ' (space) or
2408 * string length (recent FCODE images -- major hack ahead!!!).
2412 while ((iter
> istart
) && !do_next
) {
2414 rbyte
= qla2x00_read_flash_byte(ha
, iter
);
2415 if (rbyte
== ' ' || rbyte
== 0xd || rbyte
== 0x10)
2421 /* Mark beginning of version tag, and copy data. */
2423 if ((vend
- iter
) &&
2424 ((vend
- iter
) < sizeof(ha
->fcode_revision
))) {
2425 vbyte
= ha
->fcode_revision
;
2426 while (iter
<= vend
) {
2427 *vbyte
++ = qla2x00_read_flash_byte(ha
, iter
);
2434 if (ret
!= QLA_SUCCESS
)
2435 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2439 qla2x00_get_flash_version(scsi_qla_host_t
*vha
, void *mbuf
)
2441 int ret
= QLA_SUCCESS
;
2442 uint8_t code_type
, last_image
;
2443 uint32_t pcihdr
, pcids
;
2446 struct qla_hw_data
*ha
= vha
->hw
;
2448 if (!ha
->pio_address
|| !mbuf
)
2449 return QLA_FUNCTION_FAILED
;
2451 memset(ha
->bios_revision
, 0, sizeof(ha
->bios_revision
));
2452 memset(ha
->efi_revision
, 0, sizeof(ha
->efi_revision
));
2453 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2454 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2456 qla2x00_flash_enable(ha
);
2458 /* Begin with first PCI expansion ROM header. */
2462 /* Verify PCI expansion ROM header. */
2463 if (qla2x00_read_flash_byte(ha
, pcihdr
) != 0x55 ||
2464 qla2x00_read_flash_byte(ha
, pcihdr
+ 0x01) != 0xaa) {
2466 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "No matching ROM "
2468 ret
= QLA_FUNCTION_FAILED
;
2472 /* Locate PCI data structure. */
2474 ((qla2x00_read_flash_byte(ha
, pcihdr
+ 0x19) << 8) |
2475 qla2x00_read_flash_byte(ha
, pcihdr
+ 0x18));
2477 /* Validate signature of PCI data structure. */
2478 if (qla2x00_read_flash_byte(ha
, pcids
) != 'P' ||
2479 qla2x00_read_flash_byte(ha
, pcids
+ 0x1) != 'C' ||
2480 qla2x00_read_flash_byte(ha
, pcids
+ 0x2) != 'I' ||
2481 qla2x00_read_flash_byte(ha
, pcids
+ 0x3) != 'R') {
2482 /* Incorrect header. */
2483 DEBUG2(qla_printk(KERN_INFO
, ha
, "PCI data struct not "
2484 "found pcir_adr=%x.\n", pcids
));
2485 ret
= QLA_FUNCTION_FAILED
;
2490 code_type
= qla2x00_read_flash_byte(ha
, pcids
+ 0x14);
2491 switch (code_type
) {
2492 case ROM_CODE_TYPE_BIOS
:
2493 /* Intel x86, PC-AT compatible. */
2494 ha
->bios_revision
[0] =
2495 qla2x00_read_flash_byte(ha
, pcids
+ 0x12);
2496 ha
->bios_revision
[1] =
2497 qla2x00_read_flash_byte(ha
, pcids
+ 0x13);
2498 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "read BIOS %d.%d.\n",
2499 ha
->bios_revision
[1], ha
->bios_revision
[0]));
2501 case ROM_CODE_TYPE_FCODE
:
2502 /* Open Firmware standard for PCI (FCode). */
2504 qla2x00_get_fcode_version(ha
, pcids
);
2506 case ROM_CODE_TYPE_EFI
:
2507 /* Extensible Firmware Interface (EFI). */
2508 ha
->efi_revision
[0] =
2509 qla2x00_read_flash_byte(ha
, pcids
+ 0x12);
2510 ha
->efi_revision
[1] =
2511 qla2x00_read_flash_byte(ha
, pcids
+ 0x13);
2512 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "read EFI %d.%d.\n",
2513 ha
->efi_revision
[1], ha
->efi_revision
[0]));
2516 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unrecognized code "
2517 "type %x at pcids %x.\n", code_type
, pcids
));
2521 last_image
= qla2x00_read_flash_byte(ha
, pcids
+ 0x15) & BIT_7
;
2523 /* Locate next PCI expansion ROM. */
2524 pcihdr
+= ((qla2x00_read_flash_byte(ha
, pcids
+ 0x11) << 8) |
2525 qla2x00_read_flash_byte(ha
, pcids
+ 0x10)) * 512;
2526 } while (!last_image
);
2528 if (IS_QLA2322(ha
)) {
2529 /* Read firmware image information. */
2530 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2532 memset(dbyte
, 0, 8);
2533 dcode
= (uint16_t *)dbyte
;
2535 qla2x00_read_flash_data(ha
, dbyte
, ha
->flt_region_fw
* 4 + 10,
2537 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "dumping fw ver from "
2539 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte
, 8));
2541 if ((dcode
[0] == 0xffff && dcode
[1] == 0xffff &&
2542 dcode
[2] == 0xffff && dcode
[3] == 0xffff) ||
2543 (dcode
[0] == 0 && dcode
[1] == 0 && dcode
[2] == 0 &&
2545 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unrecognized fw "
2546 "revision at %x.\n", ha
->flt_region_fw
* 4));
2548 /* values are in big endian */
2549 ha
->fw_revision
[0] = dbyte
[0] << 16 | dbyte
[1];
2550 ha
->fw_revision
[1] = dbyte
[2] << 16 | dbyte
[3];
2551 ha
->fw_revision
[2] = dbyte
[4] << 16 | dbyte
[5];
2555 qla2x00_flash_disable(ha
);
2561 qla24xx_get_flash_version(scsi_qla_host_t
*vha
, void *mbuf
)
2563 int ret
= QLA_SUCCESS
;
2564 uint32_t pcihdr
, pcids
;
2567 uint8_t code_type
, last_image
;
2569 struct qla_hw_data
*ha
= vha
->hw
;
2572 return QLA_FUNCTION_FAILED
;
2574 memset(ha
->bios_revision
, 0, sizeof(ha
->bios_revision
));
2575 memset(ha
->efi_revision
, 0, sizeof(ha
->efi_revision
));
2576 memset(ha
->fcode_revision
, 0, sizeof(ha
->fcode_revision
));
2577 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2581 /* Begin with first PCI expansion ROM header. */
2582 pcihdr
= ha
->flt_region_boot
<< 2;
2585 /* Verify PCI expansion ROM header. */
2586 qla24xx_read_flash_data(vha
, dcode
, pcihdr
>> 2, 0x20);
2587 bcode
= mbuf
+ (pcihdr
% 4);
2588 if (bcode
[0x0] != 0x55 || bcode
[0x1] != 0xaa) {
2590 DEBUG2(qla_printk(KERN_DEBUG
, ha
, "No matching ROM "
2592 ret
= QLA_FUNCTION_FAILED
;
2596 /* Locate PCI data structure. */
2597 pcids
= pcihdr
+ ((bcode
[0x19] << 8) | bcode
[0x18]);
2599 qla24xx_read_flash_data(vha
, dcode
, pcids
>> 2, 0x20);
2600 bcode
= mbuf
+ (pcihdr
% 4);
2602 /* Validate signature of PCI data structure. */
2603 if (bcode
[0x0] != 'P' || bcode
[0x1] != 'C' ||
2604 bcode
[0x2] != 'I' || bcode
[0x3] != 'R') {
2605 /* Incorrect header. */
2606 DEBUG2(qla_printk(KERN_INFO
, ha
, "PCI data struct not "
2607 "found pcir_adr=%x.\n", pcids
));
2608 ret
= QLA_FUNCTION_FAILED
;
2613 code_type
= bcode
[0x14];
2614 switch (code_type
) {
2615 case ROM_CODE_TYPE_BIOS
:
2616 /* Intel x86, PC-AT compatible. */
2617 ha
->bios_revision
[0] = bcode
[0x12];
2618 ha
->bios_revision
[1] = bcode
[0x13];
2619 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "read BIOS %d.%d.\n",
2620 ha
->bios_revision
[1], ha
->bios_revision
[0]));
2622 case ROM_CODE_TYPE_FCODE
:
2623 /* Open Firmware standard for PCI (FCode). */
2624 ha
->fcode_revision
[0] = bcode
[0x12];
2625 ha
->fcode_revision
[1] = bcode
[0x13];
2626 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "read FCODE %d.%d.\n",
2627 ha
->fcode_revision
[1], ha
->fcode_revision
[0]));
2629 case ROM_CODE_TYPE_EFI
:
2630 /* Extensible Firmware Interface (EFI). */
2631 ha
->efi_revision
[0] = bcode
[0x12];
2632 ha
->efi_revision
[1] = bcode
[0x13];
2633 DEBUG3(qla_printk(KERN_DEBUG
, ha
, "read EFI %d.%d.\n",
2634 ha
->efi_revision
[1], ha
->efi_revision
[0]));
2637 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unrecognized code "
2638 "type %x at pcids %x.\n", code_type
, pcids
));
2642 last_image
= bcode
[0x15] & BIT_7
;
2644 /* Locate next PCI expansion ROM. */
2645 pcihdr
+= ((bcode
[0x11] << 8) | bcode
[0x10]) * 512;
2646 } while (!last_image
);
2648 /* Read firmware image information. */
2649 memset(ha
->fw_revision
, 0, sizeof(ha
->fw_revision
));
2652 qla24xx_read_flash_data(vha
, dcode
, ha
->flt_region_fw
+ 4, 4);
2653 for (i
= 0; i
< 4; i
++)
2654 dcode
[i
] = be32_to_cpu(dcode
[i
]);
2656 if ((dcode
[0] == 0xffffffff && dcode
[1] == 0xffffffff &&
2657 dcode
[2] == 0xffffffff && dcode
[3] == 0xffffffff) ||
2658 (dcode
[0] == 0 && dcode
[1] == 0 && dcode
[2] == 0 &&
2660 DEBUG2(qla_printk(KERN_INFO
, ha
, "Unrecognized fw "
2661 "revision at %x.\n", ha
->flt_region_fw
* 4));
2663 ha
->fw_revision
[0] = dcode
[0];
2664 ha
->fw_revision
[1] = dcode
[1];
2665 ha
->fw_revision
[2] = dcode
[2];
2666 ha
->fw_revision
[3] = dcode
[3];
2673 qla2xxx_is_vpd_valid(uint8_t *pos
, uint8_t *end
)
2675 if (pos
>= end
|| *pos
!= 0x82)
2679 if (pos
>= end
|| *pos
!= 0x90)
2683 if (pos
>= end
|| *pos
!= 0x78)
2690 qla2xxx_get_vpd_field(scsi_qla_host_t
*vha
, char *key
, char *str
, size_t size
)
2692 struct qla_hw_data
*ha
= vha
->hw
;
2693 uint8_t *pos
= ha
->vpd
;
2694 uint8_t *end
= pos
+ ha
->vpd_size
;
2697 if (!IS_FWI2_CAPABLE(ha
) || !qla2xxx_is_vpd_valid(pos
, end
))
2700 while (pos
< end
&& *pos
!= 0x78) {
2701 len
= (*pos
== 0x82) ? pos
[1] : pos
[2];
2703 if (!strncmp(pos
, key
, strlen(key
)))
2706 if (*pos
!= 0x90 && *pos
!= 0x91)
2712 if (pos
< end
- len
&& *pos
!= 0x78)
2713 return snprintf(str
, size
, "%.*s", len
, pos
+ 3);