drivers/scsi/qla4xxx/ql4_def.h

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2010 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7
   8 #ifndef __QL4_DEF_H
   9 #define __QL4_DEF_H
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/module.h>
  15 #include <linux/list.h>
  16 #include <linux/pci.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/sched.h>
  19 #include <linux/slab.h>
  20 #include <linux/dmapool.h>
  21 #include <linux/mempool.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/mutex.h>
  27 #include <linux/aer.h>
  28 #include <linux/bsg-lib.h>
  29
  30 #include <net/tcp.h>
  31 #include <scsi/scsi.h>
  32 #include <scsi/scsi_host.h>
  33 #include <scsi/scsi_device.h>
  34 #include <scsi/scsi_cmnd.h>
  35 #include <scsi/scsi_transport.h>
  36 #include <scsi/scsi_transport_iscsi.h>
  37 #include <scsi/scsi_bsg_iscsi.h>
  38 #include <scsi/scsi_netlink.h>
  39 #include <scsi/libiscsi.h>
  40
  41 #include "ql4_dbg.h"
  42 #include "ql4_nx.h"
  43 #include "ql4_fw.h"
  44 #include "ql4_nvram.h"
  45
  46 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
  47 #define PCI_DEVICE_ID_QLOGIC_ISP4010    0x4010
  48 #endif
  49
  50 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
  51 #define PCI_DEVICE_ID_QLOGIC_ISP4022    0x4022
  52 #endif
  53
  54 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
  55 #define PCI_DEVICE_ID_QLOGIC_ISP4032    0x4032
  56 #endif
  57
  58 #ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
  59 #define PCI_DEVICE_ID_QLOGIC_ISP8022    0x8022
  60 #endif
  61
  62 #define ISP4XXX_PCI_FN_1        0x1
  63 #define ISP4XXX_PCI_FN_2        0x3
  64
  65 #define QLA_SUCCESS                     0
  66 #define QLA_ERROR                       1
  67
  68 /*
  69  * Data bit definitions
  70  */
  71 #define BIT_0   0x1
  72 #define BIT_1   0x2
  73 #define BIT_2   0x4
  74 #define BIT_3   0x8
  75 #define BIT_4   0x10
  76 #define BIT_5   0x20
  77 #define BIT_6   0x40
  78 #define BIT_7   0x80
  79 #define BIT_8   0x100
  80 #define BIT_9   0x200
  81 #define BIT_10  0x400
  82 #define BIT_11  0x800
  83 #define BIT_12  0x1000
  84 #define BIT_13  0x2000
  85 #define BIT_14  0x4000
  86 #define BIT_15  0x8000
  87 #define BIT_16  0x10000
  88 #define BIT_17  0x20000
  89 #define BIT_18  0x40000
  90 #define BIT_19  0x80000
  91 #define BIT_20  0x100000
  92 #define BIT_21  0x200000
  93 #define BIT_22  0x400000
  94 #define BIT_23  0x800000
  95 #define BIT_24  0x1000000
  96 #define BIT_25  0x2000000
  97 #define BIT_26  0x4000000
  98 #define BIT_27  0x8000000
  99 #define BIT_28  0x10000000
 100 #define BIT_29  0x20000000
 101 #define BIT_30  0x40000000
 102 #define BIT_31  0x80000000
 103
 104 /**
 105  * Macros to help code, maintain, etc.
 106  **/
 107 #define ql4_printk(level, ha, format, arg...) \
 108         dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
 109
 110
 111 /*
 112  * Host adapter default definitions
 113  ***********************************/
 114 #define MAX_HBAS                16
 115 #define MAX_BUSES               1
 116 #define MAX_TARGETS             MAX_DEV_DB_ENTRIES
 117 #define MAX_LUNS                0xffff
 118 #define MAX_AEN_ENTRIES         MAX_DEV_DB_ENTRIES
 119 #define MAX_DDB_ENTRIES         MAX_DEV_DB_ENTRIES
 120 #define MAX_PDU_ENTRIES         32
 121 #define INVALID_ENTRY           0xFFFF
 122 #define MAX_CMDS_TO_RISC        1024
 123 #define MAX_SRBS                MAX_CMDS_TO_RISC
 124 #define MBOX_AEN_REG_COUNT      8
 125 #define MAX_INIT_RETRIES        5
 126
 127 /*
 128  * Buffer sizes
 129  */
 130 #define REQUEST_QUEUE_DEPTH             MAX_CMDS_TO_RISC
 131 #define RESPONSE_QUEUE_DEPTH            64
 132 #define QUEUE_SIZE                      64
 133 #define DMA_BUFFER_SIZE                 512
 134
 135 /*
 136  * Misc
 137  */
 138 #define MAC_ADDR_LEN                    6       /* in bytes */
 139 #define IP_ADDR_LEN                     4       /* in bytes */
 140 #define IPv6_ADDR_LEN                   16      /* IPv6 address size */
 141 #define DRIVER_NAME                     "qla4xxx"
 142
 143 #define MAX_LINKED_CMDS_PER_LUN         3
 144 #define MAX_REQS_SERVICED_PER_INTR      1
 145
 146 #define ISCSI_IPADDR_SIZE               4       /* IP address size */
 147 #define ISCSI_ALIAS_SIZE                32      /* ISCSI Alias name size */
 148 #define ISCSI_NAME_SIZE                 0xE0    /* ISCSI Name size */
 149
 150 #define QL4_SESS_RECOVERY_TMO           120     /* iSCSI session */
 151                                                 /* recovery timeout */
 152
 153 #define LSDW(x) ((u32)((u64)(x)))
 154 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
 155
 156 /*
 157  * Retry & Timeout Values
 158  */
 159 #define MBOX_TOV                        60
 160 #define SOFT_RESET_TOV                  30
 161 #define RESET_INTR_TOV                  3
 162 #define SEMAPHORE_TOV                   10
 163 #define ADAPTER_INIT_TOV                30
 164 #define ADAPTER_RESET_TOV               180
 165 #define EXTEND_CMD_TOV                  60
 166 #define WAIT_CMD_TOV                    30
 167 #define EH_WAIT_CMD_TOV                 120
 168 #define FIRMWARE_UP_TOV                 60
 169 #define RESET_FIRMWARE_TOV              30
 170 #define LOGOUT_TOV                      10
 171 #define IOCB_TOV_MARGIN                 10
 172 #define RELOGIN_TOV                     18
 173 #define ISNS_DEREG_TOV                  5
 174 #define HBA_ONLINE_TOV                  30
 175 #define DISABLE_ACB_TOV                 30
 176 #define IP_CONFIG_TOV                   30
 177 #define LOGIN_TOV                       12
 178
 179 #define MAX_RESET_HA_RETRIES            2
 180 #define FW_ALIVE_WAIT_TOV               3
 181
 182 #define CMD_SP(Cmnd)                    ((Cmnd)->SCp.ptr)
 183
 184 /*
 185  * SCSI Request Block structure  (srb)  that is placed
 186  * on cmd->SCp location of every I/O     [We have 22 bytes available]
 187  */
 188 struct srb {
 189         struct list_head list;  /* (8)   */
 190         struct scsi_qla_host *ha;       /* HA the SP is queued on */
 191         struct ddb_entry *ddb;
 192         uint16_t flags;         /* (1) Status flags. */
 193
 194 #define SRB_DMA_VALID           BIT_3   /* DMA Buffer mapped. */
 195 #define SRB_GOT_SENSE           BIT_4   /* sense data received. */
 196         uint8_t state;          /* (1) Status flags. */
 197
 198 #define SRB_NO_QUEUE_STATE       0      /* Request is in between states */
 199 #define SRB_FREE_STATE           1
 200 #define SRB_ACTIVE_STATE         3
 201 #define SRB_ACTIVE_TIMEOUT_STATE 4
 202 #define SRB_SUSPENDED_STATE      7      /* Request in suspended state */
 203
 204         struct scsi_cmnd *cmd;  /* (4) SCSI command block */
 205         dma_addr_t dma_handle;  /* (4) for unmap of single transfers */
 206         struct kref srb_ref;    /* reference count for this srb */
 207         uint8_t err_id;         /* error id */
 208 #define SRB_ERR_PORT       1    /* Request failed because "port down" */
 209 #define SRB_ERR_LOOP       2    /* Request failed because "loop down" */
 210 #define SRB_ERR_DEVICE     3    /* Request failed because "device error" */
 211 #define SRB_ERR_OTHER      4
 212
 213         uint16_t reserved;
 214         uint16_t iocb_tov;
 215         uint16_t iocb_cnt;      /* Number of used iocbs */
 216         uint16_t cc_stat;
 217
 218         /* Used for extended sense / status continuation */
 219         uint8_t *req_sense_ptr;
 220         uint16_t req_sense_len;
 221         uint16_t reserved2;
 222 };
 223
 224 /* Mailbox request block structure */
 225 struct mrb {
 226         struct scsi_qla_host *ha;
 227         struct mbox_cmd_iocb *mbox;
 228         uint32_t mbox_cmd;
 229         uint16_t iocb_cnt;              /* Number of used iocbs */
 230         uint32_t pid;
 231 };
 232
 233 /*
 234  * Asynchronous Event Queue structure
 235  */
 236 struct aen {
 237         uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
 238 };
 239
 240 struct ql4_aen_log {
 241         int count;
 242         struct aen entry[MAX_AEN_ENTRIES];
 243 };
 244
 245 /*
 246  * Device Database (DDB) structure
 247  */
 248 struct ddb_entry {
 249         struct scsi_qla_host *ha;
 250         struct iscsi_cls_session *sess;
 251         struct iscsi_cls_conn *conn;
 252
 253         uint16_t fw_ddb_index;  /* DDB firmware index */
 254         uint32_t fw_ddb_device_state; /* F/W Device State  -- see ql4_fw.h */
 255         uint16_t ddb_type;
 256 #define FLASH_DDB 0x01
 257
 258         struct dev_db_entry fw_ddb_entry;
 259         int (*unblock_sess)(struct iscsi_cls_session *cls_session);
 260         int (*ddb_change)(struct scsi_qla_host *ha, uint32_t fw_ddb_index,
 261                           struct ddb_entry *ddb_entry, uint32_t state);
 262
 263         /* Driver Re-login  */
 264         unsigned long flags;              /* DDB Flags */
 265         uint16_t default_relogin_timeout; /*  Max time to wait for
 266                                            *  relogin to complete */
 267         atomic_t retry_relogin_timer;     /* Min Time between relogins
 268                                            * (4000 only) */
 269         atomic_t relogin_timer;           /* Max Time to wait for
 270                                            * relogin to complete */
 271         atomic_t relogin_retry_count;     /* Num of times relogin has been
 272                                            * retried */
 273         uint32_t default_time2wait;       /* Default Min time between
 274                                            * relogins (+aens) */
 275         uint16_t chap_tbl_idx;
 276 };
 277
 278 struct qla_ddb_index {
 279         struct list_head list;
 280         uint16_t fw_ddb_idx;
 281         struct dev_db_entry fw_ddb;
 282         uint8_t flash_isid[6];
 283 };
 284
 285 #define DDB_IPADDR_LEN 64
 286
 287 struct ql4_tuple_ddb {
 288         int port;
 289         int tpgt;
 290         char ip_addr[DDB_IPADDR_LEN];
 291         char iscsi_name[ISCSI_NAME_SIZE];
 292         uint16_t options;
 293 #define DDB_OPT_IPV6 0x0e0e
 294 #define DDB_OPT_IPV4 0x0f0f
 295         uint8_t isid[6];
 296 };
 297
 298 /*
 299  * DDB states.
 300  */
 301 #define DDB_STATE_DEAD          0       /* We can no longer talk to
 302                                          * this device */
 303 #define DDB_STATE_ONLINE        1       /* Device ready to accept
 304                                          * commands */
 305 #define DDB_STATE_MISSING       2       /* Device logged off, trying
 306                                          * to re-login */
 307
 308 /*
 309  * DDB flags.
 310  */
 311 #define DF_RELOGIN              0       /* Relogin to device */
 312 #define DF_ISNS_DISCOVERED      2       /* Device was discovered via iSNS */
 313 #define DF_FO_MASKED            3
 314
 315 enum qla4_work_type {
 316         QLA4_EVENT_AEN,
 317         QLA4_EVENT_PING_STATUS,
 318 };
 319
 320 struct qla4_work_evt {
 321         struct list_head list;
 322         enum qla4_work_type type;
 323         union {
 324                 struct {
 325                         enum iscsi_host_event_code code;
 326                         uint32_t data_size;
 327                         uint8_t data[0];
 328                 } aen;
 329                 struct {
 330                         uint32_t status;
 331                         uint32_t pid;
 332                         uint32_t data_size;
 333                         uint8_t data[0];
 334                 } ping;
 335         } u;
 336 };
 337
 338 struct ql82xx_hw_data {
 339         /* Offsets for flash/nvram access (set to ~0 if not used). */
 340         uint32_t flash_conf_off;
 341         uint32_t flash_data_off;
 342
 343         uint32_t fdt_wrt_disable;
 344         uint32_t fdt_erase_cmd;
 345         uint32_t fdt_block_size;
 346         uint32_t fdt_unprotect_sec_cmd;
 347         uint32_t fdt_protect_sec_cmd;
 348
 349         uint32_t flt_region_flt;
 350         uint32_t flt_region_fdt;
 351         uint32_t flt_region_boot;
 352         uint32_t flt_region_bootload;
 353         uint32_t flt_region_fw;
 354
 355         uint32_t flt_iscsi_param;
 356         uint32_t flt_region_chap;
 357         uint32_t flt_chap_size;
 358 };
 359
 360 struct qla4_8xxx_legacy_intr_set {
 361         uint32_t int_vec_bit;
 362         uint32_t tgt_status_reg;
 363         uint32_t tgt_mask_reg;
 364         uint32_t pci_int_reg;
 365 };
 366
 367 /* MSI-X Support */
 368
 369 #define QLA_MSIX_DEFAULT        0x00
 370 #define QLA_MSIX_RSP_Q          0x01
 371
 372 #define QLA_MSIX_ENTRIES        2
 373 #define QLA_MIDX_DEFAULT        0
 374 #define QLA_MIDX_RSP_Q          1
 375
 376 struct ql4_msix_entry {
 377         int have_irq;
 378         uint16_t msix_vector;
 379         uint16_t msix_entry;
 380 };
 381
 382 /*
 383  * ISP Operations
 384  */
 385 struct isp_operations {
 386         int (*iospace_config) (struct scsi_qla_host *ha);
 387         void (*pci_config) (struct scsi_qla_host *);
 388         void (*disable_intrs) (struct scsi_qla_host *);
 389         void (*enable_intrs) (struct scsi_qla_host *);
 390         int (*start_firmware) (struct scsi_qla_host *);
 391         irqreturn_t (*intr_handler) (int , void *);
 392         void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
 393         int (*reset_chip) (struct scsi_qla_host *);
 394         int (*reset_firmware) (struct scsi_qla_host *);
 395         void (*queue_iocb) (struct scsi_qla_host *);
 396         void (*complete_iocb) (struct scsi_qla_host *);
 397         uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
 398         uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
 399         int (*get_sys_info) (struct scsi_qla_host *);
 400 };
 401
 402 struct ql4_mdump_size_table {
 403         uint32_t size;
 404         uint32_t size_cmask_02;
 405         uint32_t size_cmask_04;
 406         uint32_t size_cmask_08;
 407         uint32_t size_cmask_10;
 408         uint32_t size_cmask_FF;
 409         uint32_t version;
 410 };
 411
 412 /*qla4xxx ipaddress configuration details */
 413 struct ipaddress_config {
 414         uint16_t ipv4_options;
 415         uint16_t tcp_options;
 416         uint16_t ipv4_vlan_tag;
 417         uint8_t ipv4_addr_state;
 418         uint8_t ip_address[IP_ADDR_LEN];
 419         uint8_t subnet_mask[IP_ADDR_LEN];
 420         uint8_t gateway[IP_ADDR_LEN];
 421         uint32_t ipv6_options;
 422         uint32_t ipv6_addl_options;
 423         uint8_t ipv6_link_local_state;
 424         uint8_t ipv6_addr0_state;
 425         uint8_t ipv6_addr1_state;
 426         uint8_t ipv6_default_router_state;
 427         uint16_t ipv6_vlan_tag;
 428         struct in6_addr ipv6_link_local_addr;
 429         struct in6_addr ipv6_addr0;
 430         struct in6_addr ipv6_addr1;
 431         struct in6_addr ipv6_default_router_addr;
 432         uint16_t eth_mtu_size;
 433         uint16_t ipv4_port;
 434         uint16_t ipv6_port;
 435 };
 436
 437 #define QL4_CHAP_MAX_NAME_LEN 256
 438 #define QL4_CHAP_MAX_SECRET_LEN 100
 439 #define LOCAL_CHAP      0
 440 #define BIDI_CHAP       1
 441
 442 struct ql4_chap_format {
 443         u8  intr_chap_name[QL4_CHAP_MAX_NAME_LEN];
 444         u8  intr_secret[QL4_CHAP_MAX_SECRET_LEN];
 445         u8  target_chap_name[QL4_CHAP_MAX_NAME_LEN];
 446         u8  target_secret[QL4_CHAP_MAX_SECRET_LEN];
 447         u16 intr_chap_name_length;
 448         u16 intr_secret_length;
 449         u16 target_chap_name_length;
 450         u16 target_secret_length;
 451 };
 452
 453 struct ip_address_format {
 454         u8 ip_type;
 455         u8 ip_address[16];
 456 };
 457
 458 struct  ql4_conn_info {
 459         u16     dest_port;
 460         struct  ip_address_format dest_ipaddr;
 461         struct  ql4_chap_format chap;
 462 };
 463
 464 struct ql4_boot_session_info {
 465         u8      target_name[224];
 466         struct  ql4_conn_info conn_list[1];
 467 };
 468
 469 struct ql4_boot_tgt_info {
 470         struct ql4_boot_session_info boot_pri_sess;
 471         struct ql4_boot_session_info boot_sec_sess;
 472 };
 473
 474 /*
 475  * Linux Host Adapter structure
 476  */
 477 struct scsi_qla_host {
 478         /* Linux adapter configuration data */
 479         unsigned long flags;
 480
 481 #define AF_ONLINE                       0 /* 0x00000001 */
 482 #define AF_INIT_DONE                    1 /* 0x00000002 */
 483 #define AF_MBOX_COMMAND                 2 /* 0x00000004 */
 484 #define AF_MBOX_COMMAND_DONE            3 /* 0x00000008 */
 485 #define AF_INTERRUPTS_ON                6 /* 0x00000040 */
 486 #define AF_GET_CRASH_RECORD             7 /* 0x00000080 */
 487 #define AF_LINK_UP                      8 /* 0x00000100 */
 488 #define AF_IRQ_ATTACHED                 10 /* 0x00000400 */
 489 #define AF_DISABLE_ACB_COMPLETE         11 /* 0x00000800 */
 490 #define AF_HA_REMOVAL                   12 /* 0x00001000 */
 491 #define AF_INTx_ENABLED                 15 /* 0x00008000 */
 492 #define AF_MSI_ENABLED                  16 /* 0x00010000 */
 493 #define AF_MSIX_ENABLED                 17 /* 0x00020000 */
 494 #define AF_MBOX_COMMAND_NOPOLL          18 /* 0x00040000 */
 495 #define AF_FW_RECOVERY                  19 /* 0x00080000 */
 496 #define AF_EEH_BUSY                     20 /* 0x00100000 */
 497 #define AF_PCI_CHANNEL_IO_PERM_FAILURE  21 /* 0x00200000 */
 498 #define AF_BUILD_DDB_LIST               22 /* 0x00400000 */
 499 #define AF_82XX_FW_DUMPED               24 /* 0x01000000 */
 500 #define AF_82XX_RST_OWNER               25 /* 0x02000000 */
 501 #define AF_82XX_DUMP_READING            26 /* 0x04000000 */
 502
 503         unsigned long dpc_flags;
 504
 505 #define DPC_RESET_HA                    1 /* 0x00000002 */
 506 #define DPC_RETRY_RESET_HA              2 /* 0x00000004 */
 507 #define DPC_RELOGIN_DEVICE              3 /* 0x00000008 */
 508 #define DPC_RESET_HA_FW_CONTEXT         4 /* 0x00000010 */
 509 #define DPC_RESET_HA_INTR               5 /* 0x00000020 */
 510 #define DPC_ISNS_RESTART                7 /* 0x00000080 */
 511 #define DPC_AEN                         9 /* 0x00000200 */
 512 #define DPC_GET_DHCP_IP_ADDR            15 /* 0x00008000 */
 513 #define DPC_LINK_CHANGED                18 /* 0x00040000 */
 514 #define DPC_RESET_ACTIVE                20 /* 0x00040000 */
 515 #define DPC_HA_UNRECOVERABLE            21 /* 0x00080000 ISP-82xx only*/
 516 #define DPC_HA_NEED_QUIESCENT           22 /* 0x00100000 ISP-82xx only*/
 517
 518
 519         struct Scsi_Host *host; /* pointer to host data */
 520         uint32_t tot_ddbs;
 521
 522         uint16_t iocb_cnt;
 523
 524         /* SRB cache. */
 525 #define SRB_MIN_REQ     128
 526         mempool_t *srb_mempool;
 527
 528         /* pci information */
 529         struct pci_dev *pdev;
 530
 531         struct isp_reg __iomem *reg; /* Base I/O address */
 532         unsigned long pio_address;
 533         unsigned long pio_length;
 534 #define MIN_IOBASE_LEN          0x100
 535
 536         uint16_t req_q_count;
 537
 538         unsigned long host_no;
 539
 540         /* NVRAM registers */
 541         struct eeprom_data *nvram;
 542         spinlock_t hardware_lock ____cacheline_aligned;
 543         uint32_t eeprom_cmd_data;
 544
 545         /* Counters for general statistics */
 546         uint64_t isr_count;
 547         uint64_t adapter_error_count;
 548         uint64_t device_error_count;
 549         uint64_t total_io_count;
 550         uint64_t total_mbytes_xferred;
 551         uint64_t link_failure_count;
 552         uint64_t invalid_crc_count;
 553         uint32_t bytes_xfered;
 554         uint32_t spurious_int_count;
 555         uint32_t aborted_io_count;
 556         uint32_t io_timeout_count;
 557         uint32_t mailbox_timeout_count;
 558         uint32_t seconds_since_last_intr;
 559         uint32_t seconds_since_last_heartbeat;
 560         uint32_t mac_index;
 561
 562         /* Info Needed for Management App */
 563         /* --- From GetFwVersion --- */
 564         uint32_t firmware_version[2];
 565         uint32_t patch_number;
 566         uint32_t build_number;
 567         uint32_t board_id;
 568
 569         /* --- From Init_FW --- */
 570         /* init_cb_t *init_cb; */
 571         uint16_t firmware_options;
 572         uint8_t alias[32];
 573         uint8_t name_string[256];
 574         uint8_t heartbeat_interval;
 575
 576         /* --- From FlashSysInfo --- */
 577         uint8_t my_mac[MAC_ADDR_LEN];
 578         uint8_t serial_number[16];
 579         uint16_t port_num;
 580         /* --- From GetFwState --- */
 581         uint32_t firmware_state;
 582         uint32_t addl_fw_state;
 583
 584         /* Linux kernel thread */
 585         struct workqueue_struct *dpc_thread;
 586         struct work_struct dpc_work;
 587
 588         /* Linux timer thread */
 589         struct timer_list timer;
 590         uint32_t timer_active;
 591
 592         /* Recovery Timers */
 593         atomic_t check_relogin_timeouts;
 594         uint32_t retry_reset_ha_cnt;
 595         uint32_t isp_reset_timer;       /* reset test timer */
 596         uint32_t nic_reset_timer;       /* simulated nic reset test timer */
 597         int eh_start;
 598         struct list_head free_srb_q;
 599         uint16_t free_srb_q_count;
 600         uint16_t num_srbs_allocated;
 601
 602         /* DMA Memory Block */
 603         void *queues;
 604         dma_addr_t queues_dma;
 605         unsigned long queues_len;
 606
 607 #define MEM_ALIGN_VALUE \
 608             ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
 609              sizeof(struct queue_entry))
 610         /* request and response queue variables */
 611         dma_addr_t request_dma;
 612         struct queue_entry *request_ring;
 613         struct queue_entry *request_ptr;
 614         dma_addr_t response_dma;
 615         struct queue_entry *response_ring;
 616         struct queue_entry *response_ptr;
 617         dma_addr_t shadow_regs_dma;
 618         struct shadow_regs *shadow_regs;
 619         uint16_t request_in;    /* Current indexes. */
 620         uint16_t request_out;
 621         uint16_t response_in;
 622         uint16_t response_out;
 623
 624         /* aen queue variables */
 625         uint16_t aen_q_count;   /* Number of available aen_q entries */
 626         uint16_t aen_in;        /* Current indexes */
 627         uint16_t aen_out;
 628         struct aen aen_q[MAX_AEN_ENTRIES];
 629
 630         struct ql4_aen_log aen_log;/* tracks all aens */
 631
 632         /* This mutex protects several threads to do mailbox commands
 633          * concurrently.
 634          */
 635         struct mutex  mbox_sem;
 636
 637         /* temporary mailbox status registers */
 638         volatile uint8_t mbox_status_count;
 639         volatile uint32_t mbox_status[MBOX_REG_COUNT];
 640
 641         /* FW ddb index map */
 642         struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
 643
 644         /* Saved srb for status continuation entry processing */
 645         struct srb *status_srb;
 646
 647         uint8_t acb_version;
 648
 649         /* qla82xx specific fields */
 650         struct device_reg_82xx  __iomem *qla4_8xxx_reg; /* Base I/O address */
 651         unsigned long nx_pcibase;       /* Base I/O address */
 652         uint8_t *nx_db_rd_ptr;          /* Doorbell read pointer */
 653         unsigned long nx_db_wr_ptr;     /* Door bell write pointer */
 654         unsigned long first_page_group_start;
 655         unsigned long first_page_group_end;
 656
 657         uint32_t crb_win;
 658         uint32_t curr_window;
 659         uint32_t ddr_mn_window;
 660         unsigned long mn_win_crb;
 661         unsigned long ms_win_crb;
 662         int qdr_sn_window;
 663         rwlock_t hw_lock;
 664         uint16_t func_num;
 665         int link_width;
 666
 667         struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
 668         u32 nx_crb_mask;
 669
 670         uint8_t revision_id;
 671         uint32_t fw_heartbeat_counter;
 672
 673         struct isp_operations *isp_ops;
 674         struct ql82xx_hw_data hw;
 675
 676         struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
 677
 678         uint32_t nx_dev_init_timeout;
 679         uint32_t nx_reset_timeout;
 680         void *fw_dump;
 681         uint32_t fw_dump_size;
 682         uint32_t fw_dump_capture_mask;
 683         void *fw_dump_tmplt_hdr;
 684         uint32_t fw_dump_tmplt_size;
 685
 686         struct completion mbx_intr_comp;
 687
 688         struct ipaddress_config ip_config;
 689         struct iscsi_iface *iface_ipv4;
 690         struct iscsi_iface *iface_ipv6_0;
 691         struct iscsi_iface *iface_ipv6_1;
 692
 693         /* --- From About Firmware --- */
 694         uint16_t iscsi_major;
 695         uint16_t iscsi_minor;
 696         uint16_t bootload_major;
 697         uint16_t bootload_minor;
 698         uint16_t bootload_patch;
 699         uint16_t bootload_build;
 700         uint16_t def_timeout; /* Default login timeout */
 701
 702         uint32_t flash_state;
 703 #define QLFLASH_WAITING         0
 704 #define QLFLASH_READING         1
 705 #define QLFLASH_WRITING         2
 706         struct dma_pool *chap_dma_pool;
 707         uint8_t *chap_list; /* CHAP table cache */
 708         struct mutex  chap_sem;
 709
 710 #define CHAP_DMA_BLOCK_SIZE    512
 711         struct workqueue_struct *task_wq;
 712         unsigned long ddb_idx_map[MAX_DDB_ENTRIES / BITS_PER_LONG];
 713 #define SYSFS_FLAG_FW_SEL_BOOT 2
 714         struct iscsi_boot_kset *boot_kset;
 715         struct ql4_boot_tgt_info boot_tgt;
 716         uint16_t phy_port_num;
 717         uint16_t phy_port_cnt;
 718         uint16_t iscsi_pci_func_cnt;
 719         uint8_t model_name[16];
 720         struct completion disable_acb_comp;
 721         struct dma_pool *fw_ddb_dma_pool;
 722 #define DDB_DMA_BLOCK_SIZE 512
 723         uint16_t pri_ddb_idx;
 724         uint16_t sec_ddb_idx;
 725         int is_reset;
 726         uint16_t temperature;
 727
 728         /* event work list */
 729         struct list_head work_list;
 730         spinlock_t work_lock;
 731
 732         /* mbox iocb */
 733 #define MAX_MRB         128
 734         struct mrb *active_mrb_array[MAX_MRB];
 735         uint32_t mrb_index;
 736 };
 737
 738 struct ql4_task_data {
 739         struct scsi_qla_host *ha;
 740         uint8_t iocb_req_cnt;
 741         dma_addr_t data_dma;
 742         void *req_buffer;
 743         dma_addr_t req_dma;
 744         uint32_t req_len;
 745         void *resp_buffer;
 746         dma_addr_t resp_dma;
 747         uint32_t resp_len;
 748         struct iscsi_task *task;
 749         struct passthru_status sts;
 750         struct work_struct task_work;
 751 };
 752
 753 struct qla_endpoint {
 754         struct Scsi_Host *host;
 755         struct sockaddr dst_addr;
 756 };
 757
 758 struct qla_conn {
 759         struct qla_endpoint *qla_ep;
 760 };
 761
 762 static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
 763 {
 764         return ((ha->ip_config.ipv4_options & IPOPT_IPV4_PROTOCOL_ENABLE) != 0);
 765 }
 766
 767 static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
 768 {
 769         return ((ha->ip_config.ipv6_options &
 770                 IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
 771 }
 772
 773 static inline int is_qla4010(struct scsi_qla_host *ha)
 774 {
 775         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
 776 }
 777
 778 static inline int is_qla4022(struct scsi_qla_host *ha)
 779 {
 780         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
 781 }
 782
 783 static inline int is_qla4032(struct scsi_qla_host *ha)
 784 {
 785         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
 786 }
 787
 788 static inline int is_qla40XX(struct scsi_qla_host *ha)
 789 {
 790         return is_qla4032(ha) || is_qla4022(ha) || is_qla4010(ha);
 791 }
 792
 793 static inline int is_qla8022(struct scsi_qla_host *ha)
 794 {
 795         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
 796 }
 797
 798 /* Note: Currently AER/EEH is now supported only for 8022 cards
 799  * This function needs to be updated when AER/EEH is enabled
 800  * for other cards.
 801  */
 802 static inline int is_aer_supported(struct scsi_qla_host *ha)
 803 {
 804         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
 805 }
 806
 807 static inline int adapter_up(struct scsi_qla_host *ha)
 808 {
 809         return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
 810                 (test_bit(AF_LINK_UP, &ha->flags) != 0);
 811 }
 812
 813 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
 814 {
 815         return (struct scsi_qla_host *)iscsi_host_priv(shost);
 816 }
 817
 818 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
 819 {
 820         return (is_qla4010(ha) ?
 821                 &ha->reg->u1.isp4010.nvram :
 822                 &ha->reg->u1.isp4022.semaphore);
 823 }
 824
 825 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
 826 {
 827         return (is_qla4010(ha) ?
 828                 &ha->reg->u1.isp4010.nvram :
 829                 &ha->reg->u1.isp4022.nvram);
 830 }
 831
 832 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
 833 {
 834         return (is_qla4010(ha) ?
 835                 &ha->reg->u2.isp4010.ext_hw_conf :
 836                 &ha->reg->u2.isp4022.p0.ext_hw_conf);
 837 }
 838
 839 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
 840 {
 841         return (is_qla4010(ha) ?
 842                 &ha->reg->u2.isp4010.port_status :
 843                 &ha->reg->u2.isp4022.p0.port_status);
 844 }
 845
 846 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
 847 {
 848         return (is_qla4010(ha) ?
 849                 &ha->reg->u2.isp4010.port_ctrl :
 850                 &ha->reg->u2.isp4022.p0.port_ctrl);
 851 }
 852
 853 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
 854 {
 855         return (is_qla4010(ha) ?
 856                 &ha->reg->u2.isp4010.port_err_status :
 857                 &ha->reg->u2.isp4022.p0.port_err_status);
 858 }
 859
 860 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
 861 {
 862         return (is_qla4010(ha) ?
 863                 &ha->reg->u2.isp4010.gp_out :
 864                 &ha->reg->u2.isp4022.p0.gp_out);
 865 }
 866
 867 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
 868 {
 869         return (is_qla4010(ha) ?
 870                 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
 871                 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
 872 }
 873
 874 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
 875 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
 876 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
 877
 878 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
 879 {
 880         if (is_qla4010(a))
 881                 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
 882                                            QL4010_FLASH_SEM_BITS);
 883         else
 884                 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
 885                                            (QL4022_RESOURCE_BITS_BASE_CODE |
 886                                             (a->mac_index)) << 13);
 887 }
 888
 889 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
 890 {
 891         if (is_qla4010(a))
 892                 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
 893         else
 894                 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
 895 }
 896
 897 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
 898 {
 899         if (is_qla4010(a))
 900                 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
 901                                            QL4010_NVRAM_SEM_BITS);
 902         else
 903                 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
 904                                            (QL4022_RESOURCE_BITS_BASE_CODE |
 905                                             (a->mac_index)) << 10);
 906 }
 907
 908 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
 909 {
 910         if (is_qla4010(a))
 911                 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
 912         else
 913                 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
 914 }
 915
 916 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
 917 {
 918         if (is_qla4010(a))
 919                 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
 920                                        QL4010_DRVR_SEM_BITS);
 921         else
 922                 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
 923                                        (QL4022_RESOURCE_BITS_BASE_CODE |
 924                                         (a->mac_index)) << 1);
 925 }
 926
 927 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
 928 {
 929         if (is_qla4010(a))
 930                 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
 931         else
 932                 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
 933 }
 934
 935 static inline int ql4xxx_reset_active(struct scsi_qla_host *ha)
 936 {
 937         return test_bit(DPC_RESET_ACTIVE, &ha->dpc_flags) ||
 938                test_bit(DPC_RESET_HA, &ha->dpc_flags) ||
 939                test_bit(DPC_RETRY_RESET_HA, &ha->dpc_flags) ||
 940                test_bit(DPC_RESET_HA_INTR, &ha->dpc_flags) ||
 941                test_bit(DPC_RESET_HA_FW_CONTEXT, &ha->dpc_flags) ||
 942                test_bit(DPC_HA_UNRECOVERABLE, &ha->dpc_flags);
 943
 944 }
 945 /*---------------------------------------------------------------------------*/
 946
 947 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
 948
 949 #define INIT_ADAPTER    0
 950 #define RESET_ADAPTER   1
 951
 952 #define PRESERVE_DDB_LIST       0
 953 #define REBUILD_DDB_LIST        1
 954
 955 /* Defines for process_aen() */
 956 #define PROCESS_ALL_AENS         0
 957 #define FLUSH_DDB_CHANGED_AENS   1
 958
 959 /* Defines for udev events */
 960 #define QL4_UEVENT_CODE_FW_DUMP         0
 961
 962 #endif  /*_QLA4XXX_H */