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Merge with http://kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
[deliverable/linux.git] / drivers / scsi / sata_mv.c
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/sched.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/device.h>
34 #include <scsi/scsi_host.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <linux/libata.h>
37 #include <asm/io.h>
38
39 #define DRV_NAME "sata_mv"
40 #define DRV_VERSION "0.5"
41
42 enum {
43 /* BAR's are enumerated in terms of pci_resource_start() terms */
44 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
45 MV_IO_BAR = 2, /* offset 0x18: IO space */
46 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
47
48 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
49 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50
51 MV_PCI_REG_BASE = 0,
52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
53 MV_SATAHC0_REG_BASE = 0x20000,
54 MV_FLASH_CTL = 0x1046c,
55 MV_GPIO_PORT_CTL = 0x104f0,
56 MV_RESET_CFG = 0x180d8,
57
58 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
59 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
60 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
61 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
62
63 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
64
65 MV_MAX_Q_DEPTH = 32,
66 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
67
68 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
69 * CRPB needs alignment on a 256B boundary. Size == 256B
70 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
71 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
72 */
73 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
74 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
75 MV_MAX_SG_CT = 176,
76 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
77 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
78
79 MV_PORTS_PER_HC = 4,
80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
81 MV_PORT_HC_SHIFT = 2,
82 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
83 MV_PORT_MASK = 3,
84
85 /* Host Flags */
86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
88 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
89 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
90 ATA_FLAG_NO_ATAPI),
91 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
92
93 CRQB_FLAG_READ = (1 << 0),
94 CRQB_TAG_SHIFT = 1,
95 CRQB_CMD_ADDR_SHIFT = 8,
96 CRQB_CMD_CS = (0x2 << 11),
97 CRQB_CMD_LAST = (1 << 15),
98
99 CRPB_FLAG_STATUS_SHIFT = 8,
100
101 EPRD_FLAG_END_OF_TBL = (1 << 31),
102
103 /* PCI interface registers */
104
105 PCI_COMMAND_OFS = 0xc00,
106
107 PCI_MAIN_CMD_STS_OFS = 0xd30,
108 STOP_PCI_MASTER = (1 << 2),
109 PCI_MASTER_EMPTY = (1 << 3),
110 GLOB_SFT_RST = (1 << 4),
111
112 MV_PCI_MODE = 0xd00,
113 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
114 MV_PCI_DISC_TIMER = 0xd04,
115 MV_PCI_MSI_TRIGGER = 0xc38,
116 MV_PCI_SERR_MASK = 0xc28,
117 MV_PCI_XBAR_TMOUT = 0x1d04,
118 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
119 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
120 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
121 MV_PCI_ERR_COMMAND = 0x1d50,
122
123 PCI_IRQ_CAUSE_OFS = 0x1d58,
124 PCI_IRQ_MASK_OFS = 0x1d5c,
125 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
126
127 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
128 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
129 PORT0_ERR = (1 << 0), /* shift by port # */
130 PORT0_DONE = (1 << 1), /* shift by port # */
131 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
132 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
133 PCI_ERR = (1 << 18),
134 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
135 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
136 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
137 GPIO_INT = (1 << 22),
138 SELF_INT = (1 << 23),
139 TWSI_INT = (1 << 24),
140 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
141 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
142 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
143 HC_MAIN_RSVD),
144
145 /* SATAHC registers */
146 HC_CFG_OFS = 0,
147
148 HC_IRQ_CAUSE_OFS = 0x14,
149 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
150 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
151 DEV_IRQ = (1 << 8), /* shift by port # */
152
153 /* Shadow block registers */
154 SHD_BLK_OFS = 0x100,
155 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
156
157 /* SATA registers */
158 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
159 SATA_ACTIVE_OFS = 0x350,
160 PHY_MODE3 = 0x310,
161 PHY_MODE4 = 0x314,
162 PHY_MODE2 = 0x330,
163 MV5_PHY_MODE = 0x74,
164 MV5_LT_MODE = 0x30,
165 MV5_PHY_CTL = 0x0C,
166 SATA_INTERFACE_CTL = 0x050,
167
168 MV_M2_PREAMP_MASK = 0x7e0,
169
170 /* Port registers */
171 EDMA_CFG_OFS = 0,
172 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
173 EDMA_CFG_NCQ = (1 << 5),
174 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
175 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
176 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
177
178 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
179 EDMA_ERR_IRQ_MASK_OFS = 0xc,
180 EDMA_ERR_D_PAR = (1 << 0),
181 EDMA_ERR_PRD_PAR = (1 << 1),
182 EDMA_ERR_DEV = (1 << 2),
183 EDMA_ERR_DEV_DCON = (1 << 3),
184 EDMA_ERR_DEV_CON = (1 << 4),
185 EDMA_ERR_SERR = (1 << 5),
186 EDMA_ERR_SELF_DIS = (1 << 7),
187 EDMA_ERR_BIST_ASYNC = (1 << 8),
188 EDMA_ERR_CRBQ_PAR = (1 << 9),
189 EDMA_ERR_CRPB_PAR = (1 << 10),
190 EDMA_ERR_INTRL_PAR = (1 << 11),
191 EDMA_ERR_IORDY = (1 << 12),
192 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
193 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
194 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
195 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
196 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
197 EDMA_ERR_TRANS_PROTO = (1 << 31),
198 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
199 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
200 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
201 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
202 EDMA_ERR_LNK_DATA_RX |
203 EDMA_ERR_LNK_DATA_TX |
204 EDMA_ERR_TRANS_PROTO),
205
206 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
207 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
208
209 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
210 EDMA_REQ_Q_PTR_SHIFT = 5,
211
212 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
213 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
214 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
215 EDMA_RSP_Q_PTR_SHIFT = 3,
216
217 EDMA_CMD_OFS = 0x28,
218 EDMA_EN = (1 << 0),
219 EDMA_DS = (1 << 1),
220 ATA_RST = (1 << 2),
221
222 EDMA_IORDY_TMOUT = 0x34,
223 EDMA_ARB_CFG = 0x38,
224
225 /* Host private flags (hp_flags) */
226 MV_HP_FLAG_MSI = (1 << 0),
227 MV_HP_ERRATA_50XXB0 = (1 << 1),
228 MV_HP_ERRATA_50XXB2 = (1 << 2),
229 MV_HP_ERRATA_60X1B2 = (1 << 3),
230 MV_HP_ERRATA_60X1C0 = (1 << 4),
231 MV_HP_50XX = (1 << 5),
232
233 /* Port private flags (pp_flags) */
234 MV_PP_FLAG_EDMA_EN = (1 << 0),
235 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
236 };
237
238 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
239 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
240
241 enum {
242 /* Our DMA boundary is determined by an ePRD being unable to handle
243 * anything larger than 64KB
244 */
245 MV_DMA_BOUNDARY = 0xffffU,
246
247 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
248
249 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
250 };
251
252 enum chip_type {
253 chip_504x,
254 chip_508x,
255 chip_5080,
256 chip_604x,
257 chip_608x,
258 };
259
260 /* Command ReQuest Block: 32B */
261 struct mv_crqb {
262 u32 sg_addr;
263 u32 sg_addr_hi;
264 u16 ctrl_flags;
265 u16 ata_cmd[11];
266 };
267
268 /* Command ResPonse Block: 8B */
269 struct mv_crpb {
270 u16 id;
271 u16 flags;
272 u32 tmstmp;
273 };
274
275 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
276 struct mv_sg {
277 u32 addr;
278 u32 flags_size;
279 u32 addr_hi;
280 u32 reserved;
281 };
282
283 struct mv_port_priv {
284 struct mv_crqb *crqb;
285 dma_addr_t crqb_dma;
286 struct mv_crpb *crpb;
287 dma_addr_t crpb_dma;
288 struct mv_sg *sg_tbl;
289 dma_addr_t sg_tbl_dma;
290
291 unsigned req_producer; /* cp of req_in_ptr */
292 unsigned rsp_consumer; /* cp of rsp_out_ptr */
293 u32 pp_flags;
294 };
295
296 struct mv_port_signal {
297 u32 amps;
298 u32 pre;
299 };
300
301 struct mv_host_priv;
302 struct mv_hw_ops {
303 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
304 unsigned int port);
305 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
306 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
307 void __iomem *mmio);
308 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
309 unsigned int n_hc);
310 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
311 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
312 };
313
314 struct mv_host_priv {
315 u32 hp_flags;
316 struct mv_port_signal signal[8];
317 const struct mv_hw_ops *ops;
318 };
319
320 static void mv_irq_clear(struct ata_port *ap);
321 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
322 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
323 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
324 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
325 static void mv_phy_reset(struct ata_port *ap);
326 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
327 static void mv_host_stop(struct ata_host_set *host_set);
328 static int mv_port_start(struct ata_port *ap);
329 static void mv_port_stop(struct ata_port *ap);
330 static void mv_qc_prep(struct ata_queued_cmd *qc);
331 static int mv_qc_issue(struct ata_queued_cmd *qc);
332 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
333 struct pt_regs *regs);
334 static void mv_eng_timeout(struct ata_port *ap);
335 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
336
337 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
338 unsigned int port);
339 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
340 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
341 void __iomem *mmio);
342 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
343 unsigned int n_hc);
344 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
345 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
346
347 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
348 unsigned int port);
349 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
350 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
351 void __iomem *mmio);
352 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
353 unsigned int n_hc);
354 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
355 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
356 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
357 unsigned int port_no);
358 static void mv_stop_and_reset(struct ata_port *ap);
359
360 static struct scsi_host_template mv_sht = {
361 .module = THIS_MODULE,
362 .name = DRV_NAME,
363 .ioctl = ata_scsi_ioctl,
364 .queuecommand = ata_scsi_queuecmd,
365 .eh_strategy_handler = ata_scsi_error,
366 .can_queue = MV_USE_Q_DEPTH,
367 .this_id = ATA_SHT_THIS_ID,
368 .sg_tablesize = MV_MAX_SG_CT / 2,
369 .max_sectors = ATA_MAX_SECTORS,
370 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
371 .emulated = ATA_SHT_EMULATED,
372 .use_clustering = ATA_SHT_USE_CLUSTERING,
373 .proc_name = DRV_NAME,
374 .dma_boundary = MV_DMA_BOUNDARY,
375 .slave_configure = ata_scsi_slave_config,
376 .bios_param = ata_std_bios_param,
377 .ordered_flush = 1,
378 };
379
380 static const struct ata_port_operations mv5_ops = {
381 .port_disable = ata_port_disable,
382
383 .tf_load = ata_tf_load,
384 .tf_read = ata_tf_read,
385 .check_status = ata_check_status,
386 .exec_command = ata_exec_command,
387 .dev_select = ata_std_dev_select,
388
389 .phy_reset = mv_phy_reset,
390
391 .qc_prep = mv_qc_prep,
392 .qc_issue = mv_qc_issue,
393
394 .eng_timeout = mv_eng_timeout,
395
396 .irq_handler = mv_interrupt,
397 .irq_clear = mv_irq_clear,
398
399 .scr_read = mv5_scr_read,
400 .scr_write = mv5_scr_write,
401
402 .port_start = mv_port_start,
403 .port_stop = mv_port_stop,
404 .host_stop = mv_host_stop,
405 };
406
407 static const struct ata_port_operations mv6_ops = {
408 .port_disable = ata_port_disable,
409
410 .tf_load = ata_tf_load,
411 .tf_read = ata_tf_read,
412 .check_status = ata_check_status,
413 .exec_command = ata_exec_command,
414 .dev_select = ata_std_dev_select,
415
416 .phy_reset = mv_phy_reset,
417
418 .qc_prep = mv_qc_prep,
419 .qc_issue = mv_qc_issue,
420
421 .eng_timeout = mv_eng_timeout,
422
423 .irq_handler = mv_interrupt,
424 .irq_clear = mv_irq_clear,
425
426 .scr_read = mv_scr_read,
427 .scr_write = mv_scr_write,
428
429 .port_start = mv_port_start,
430 .port_stop = mv_port_stop,
431 .host_stop = mv_host_stop,
432 };
433
434 static const struct ata_port_info mv_port_info[] = {
435 { /* chip_504x */
436 .sht = &mv_sht,
437 .host_flags = MV_COMMON_FLAGS,
438 .pio_mask = 0x1f, /* pio0-4 */
439 .udma_mask = 0x7f, /* udma0-6 */
440 .port_ops = &mv5_ops,
441 },
442 { /* chip_508x */
443 .sht = &mv_sht,
444 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
445 .pio_mask = 0x1f, /* pio0-4 */
446 .udma_mask = 0x7f, /* udma0-6 */
447 .port_ops = &mv5_ops,
448 },
449 { /* chip_5080 */
450 .sht = &mv_sht,
451 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
452 .pio_mask = 0x1f, /* pio0-4 */
453 .udma_mask = 0x7f, /* udma0-6 */
454 .port_ops = &mv5_ops,
455 },
456 { /* chip_604x */
457 .sht = &mv_sht,
458 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
459 .pio_mask = 0x1f, /* pio0-4 */
460 .udma_mask = 0x7f, /* udma0-6 */
461 .port_ops = &mv6_ops,
462 },
463 { /* chip_608x */
464 .sht = &mv_sht,
465 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
466 MV_FLAG_DUAL_HC),
467 .pio_mask = 0x1f, /* pio0-4 */
468 .udma_mask = 0x7f, /* udma0-6 */
469 .port_ops = &mv6_ops,
470 },
471 };
472
473 static const struct pci_device_id mv_pci_tbl[] = {
474 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
475 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
476 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
477 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
478
479 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
480 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
481 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
482 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
483
484 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
485 {} /* terminate list */
486 };
487
488 static struct pci_driver mv_pci_driver = {
489 .name = DRV_NAME,
490 .id_table = mv_pci_tbl,
491 .probe = mv_init_one,
492 .remove = ata_pci_remove_one,
493 };
494
495 static const struct mv_hw_ops mv5xxx_ops = {
496 .phy_errata = mv5_phy_errata,
497 .enable_leds = mv5_enable_leds,
498 .read_preamp = mv5_read_preamp,
499 .reset_hc = mv5_reset_hc,
500 .reset_flash = mv5_reset_flash,
501 .reset_bus = mv5_reset_bus,
502 };
503
504 static const struct mv_hw_ops mv6xxx_ops = {
505 .phy_errata = mv6_phy_errata,
506 .enable_leds = mv6_enable_leds,
507 .read_preamp = mv6_read_preamp,
508 .reset_hc = mv6_reset_hc,
509 .reset_flash = mv6_reset_flash,
510 .reset_bus = mv_reset_pci_bus,
511 };
512
513 /*
514 * Functions
515 */
516
517 static inline void writelfl(unsigned long data, void __iomem *addr)
518 {
519 writel(data, addr);
520 (void) readl(addr); /* flush to avoid PCI posted write */
521 }
522
523 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
524 {
525 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
526 }
527
528 static inline unsigned int mv_hc_from_port(unsigned int port)
529 {
530 return port >> MV_PORT_HC_SHIFT;
531 }
532
533 static inline unsigned int mv_hardport_from_port(unsigned int port)
534 {
535 return port & MV_PORT_MASK;
536 }
537
538 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
539 unsigned int port)
540 {
541 return mv_hc_base(base, mv_hc_from_port(port));
542 }
543
544 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
545 {
546 return mv_hc_base_from_port(base, port) +
547 MV_SATAHC_ARBTR_REG_SZ +
548 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
549 }
550
551 static inline void __iomem *mv_ap_base(struct ata_port *ap)
552 {
553 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
554 }
555
556 static inline int mv_get_hc_count(unsigned long host_flags)
557 {
558 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
559 }
560
561 static void mv_irq_clear(struct ata_port *ap)
562 {
563 }
564
565 /**
566 * mv_start_dma - Enable eDMA engine
567 * @base: port base address
568 * @pp: port private data
569 *
570 * Verify the local cache of the eDMA state is accurate with an
571 * assert.
572 *
573 * LOCKING:
574 * Inherited from caller.
575 */
576 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
577 {
578 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
579 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
580 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
581 }
582 assert(EDMA_EN & readl(base + EDMA_CMD_OFS));
583 }
584
585 /**
586 * mv_stop_dma - Disable eDMA engine
587 * @ap: ATA channel to manipulate
588 *
589 * Verify the local cache of the eDMA state is accurate with an
590 * assert.
591 *
592 * LOCKING:
593 * Inherited from caller.
594 */
595 static void mv_stop_dma(struct ata_port *ap)
596 {
597 void __iomem *port_mmio = mv_ap_base(ap);
598 struct mv_port_priv *pp = ap->private_data;
599 u32 reg;
600 int i;
601
602 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
603 /* Disable EDMA if active. The disable bit auto clears.
604 */
605 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
606 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
607 } else {
608 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
609 }
610
611 /* now properly wait for the eDMA to stop */
612 for (i = 1000; i > 0; i--) {
613 reg = readl(port_mmio + EDMA_CMD_OFS);
614 if (!(EDMA_EN & reg)) {
615 break;
616 }
617 udelay(100);
618 }
619
620 if (EDMA_EN & reg) {
621 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
622 /* FIXME: Consider doing a reset here to recover */
623 }
624 }
625
626 #ifdef ATA_DEBUG
627 static void mv_dump_mem(void __iomem *start, unsigned bytes)
628 {
629 int b, w;
630 for (b = 0; b < bytes; ) {
631 DPRINTK("%p: ", start + b);
632 for (w = 0; b < bytes && w < 4; w++) {
633 printk("%08x ",readl(start + b));
634 b += sizeof(u32);
635 }
636 printk("\n");
637 }
638 }
639 #endif
640
641 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
642 {
643 #ifdef ATA_DEBUG
644 int b, w;
645 u32 dw;
646 for (b = 0; b < bytes; ) {
647 DPRINTK("%02x: ", b);
648 for (w = 0; b < bytes && w < 4; w++) {
649 (void) pci_read_config_dword(pdev,b,&dw);
650 printk("%08x ",dw);
651 b += sizeof(u32);
652 }
653 printk("\n");
654 }
655 #endif
656 }
657 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
658 struct pci_dev *pdev)
659 {
660 #ifdef ATA_DEBUG
661 void __iomem *hc_base = mv_hc_base(mmio_base,
662 port >> MV_PORT_HC_SHIFT);
663 void __iomem *port_base;
664 int start_port, num_ports, p, start_hc, num_hcs, hc;
665
666 if (0 > port) {
667 start_hc = start_port = 0;
668 num_ports = 8; /* shld be benign for 4 port devs */
669 num_hcs = 2;
670 } else {
671 start_hc = port >> MV_PORT_HC_SHIFT;
672 start_port = port;
673 num_ports = num_hcs = 1;
674 }
675 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
676 num_ports > 1 ? num_ports - 1 : start_port);
677
678 if (NULL != pdev) {
679 DPRINTK("PCI config space regs:\n");
680 mv_dump_pci_cfg(pdev, 0x68);
681 }
682 DPRINTK("PCI regs:\n");
683 mv_dump_mem(mmio_base+0xc00, 0x3c);
684 mv_dump_mem(mmio_base+0xd00, 0x34);
685 mv_dump_mem(mmio_base+0xf00, 0x4);
686 mv_dump_mem(mmio_base+0x1d00, 0x6c);
687 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
688 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
689 DPRINTK("HC regs (HC %i):\n", hc);
690 mv_dump_mem(hc_base, 0x1c);
691 }
692 for (p = start_port; p < start_port + num_ports; p++) {
693 port_base = mv_port_base(mmio_base, p);
694 DPRINTK("EDMA regs (port %i):\n",p);
695 mv_dump_mem(port_base, 0x54);
696 DPRINTK("SATA regs (port %i):\n",p);
697 mv_dump_mem(port_base+0x300, 0x60);
698 }
699 #endif
700 }
701
702 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
703 {
704 unsigned int ofs;
705
706 switch (sc_reg_in) {
707 case SCR_STATUS:
708 case SCR_CONTROL:
709 case SCR_ERROR:
710 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
711 break;
712 case SCR_ACTIVE:
713 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
714 break;
715 default:
716 ofs = 0xffffffffU;
717 break;
718 }
719 return ofs;
720 }
721
722 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
723 {
724 unsigned int ofs = mv_scr_offset(sc_reg_in);
725
726 if (0xffffffffU != ofs) {
727 return readl(mv_ap_base(ap) + ofs);
728 } else {
729 return (u32) ofs;
730 }
731 }
732
733 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
734 {
735 unsigned int ofs = mv_scr_offset(sc_reg_in);
736
737 if (0xffffffffU != ofs) {
738 writelfl(val, mv_ap_base(ap) + ofs);
739 }
740 }
741
742 /**
743 * mv_host_stop - Host specific cleanup/stop routine.
744 * @host_set: host data structure
745 *
746 * Disable ints, cleanup host memory, call general purpose
747 * host_stop.
748 *
749 * LOCKING:
750 * Inherited from caller.
751 */
752 static void mv_host_stop(struct ata_host_set *host_set)
753 {
754 struct mv_host_priv *hpriv = host_set->private_data;
755 struct pci_dev *pdev = to_pci_dev(host_set->dev);
756
757 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
758 pci_disable_msi(pdev);
759 } else {
760 pci_intx(pdev, 0);
761 }
762 kfree(hpriv);
763 ata_host_stop(host_set);
764 }
765
766 static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
767 {
768 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
769 }
770
771 /**
772 * mv_port_start - Port specific init/start routine.
773 * @ap: ATA channel to manipulate
774 *
775 * Allocate and point to DMA memory, init port private memory,
776 * zero indices.
777 *
778 * LOCKING:
779 * Inherited from caller.
780 */
781 static int mv_port_start(struct ata_port *ap)
782 {
783 struct device *dev = ap->host_set->dev;
784 struct mv_port_priv *pp;
785 void __iomem *port_mmio = mv_ap_base(ap);
786 void *mem;
787 dma_addr_t mem_dma;
788 int rc = -ENOMEM;
789
790 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
791 if (!pp)
792 goto err_out;
793 memset(pp, 0, sizeof(*pp));
794
795 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
796 GFP_KERNEL);
797 if (!mem)
798 goto err_out_pp;
799 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
800
801 rc = ata_pad_alloc(ap, dev);
802 if (rc)
803 goto err_out_priv;
804
805 /* First item in chunk of DMA memory:
806 * 32-slot command request table (CRQB), 32 bytes each in size
807 */
808 pp->crqb = mem;
809 pp->crqb_dma = mem_dma;
810 mem += MV_CRQB_Q_SZ;
811 mem_dma += MV_CRQB_Q_SZ;
812
813 /* Second item:
814 * 32-slot command response table (CRPB), 8 bytes each in size
815 */
816 pp->crpb = mem;
817 pp->crpb_dma = mem_dma;
818 mem += MV_CRPB_Q_SZ;
819 mem_dma += MV_CRPB_Q_SZ;
820
821 /* Third item:
822 * Table of scatter-gather descriptors (ePRD), 16 bytes each
823 */
824 pp->sg_tbl = mem;
825 pp->sg_tbl_dma = mem_dma;
826
827 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
828 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
829
830 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
831 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
832 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
833
834 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
835 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
836
837 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
838 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
839 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
840
841 pp->req_producer = pp->rsp_consumer = 0;
842
843 /* Don't turn on EDMA here...do it before DMA commands only. Else
844 * we'll be unable to send non-data, PIO, etc due to restricted access
845 * to shadow regs.
846 */
847 ap->private_data = pp;
848 return 0;
849
850 err_out_priv:
851 mv_priv_free(pp, dev);
852 err_out_pp:
853 kfree(pp);
854 err_out:
855 return rc;
856 }
857
858 /**
859 * mv_port_stop - Port specific cleanup/stop routine.
860 * @ap: ATA channel to manipulate
861 *
862 * Stop DMA, cleanup port memory.
863 *
864 * LOCKING:
865 * This routine uses the host_set lock to protect the DMA stop.
866 */
867 static void mv_port_stop(struct ata_port *ap)
868 {
869 struct device *dev = ap->host_set->dev;
870 struct mv_port_priv *pp = ap->private_data;
871 unsigned long flags;
872
873 spin_lock_irqsave(&ap->host_set->lock, flags);
874 mv_stop_dma(ap);
875 spin_unlock_irqrestore(&ap->host_set->lock, flags);
876
877 ap->private_data = NULL;
878 ata_pad_free(ap, dev);
879 mv_priv_free(pp, dev);
880 kfree(pp);
881 }
882
883 /**
884 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
885 * @qc: queued command whose SG list to source from
886 *
887 * Populate the SG list and mark the last entry.
888 *
889 * LOCKING:
890 * Inherited from caller.
891 */
892 static void mv_fill_sg(struct ata_queued_cmd *qc)
893 {
894 struct mv_port_priv *pp = qc->ap->private_data;
895 unsigned int i = 0;
896 struct scatterlist *sg;
897
898 ata_for_each_sg(sg, qc) {
899 dma_addr_t addr;
900 u32 sg_len, len, offset;
901
902 addr = sg_dma_address(sg);
903 sg_len = sg_dma_len(sg);
904
905 while (sg_len) {
906 offset = addr & MV_DMA_BOUNDARY;
907 len = sg_len;
908 if ((offset + sg_len) > 0x10000)
909 len = 0x10000 - offset;
910
911 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
912 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
913 pp->sg_tbl[i].flags_size = cpu_to_le32(len);
914
915 sg_len -= len;
916 addr += len;
917
918 if (!sg_len && ata_sg_is_last(sg, qc))
919 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
920
921 i++;
922 }
923 }
924 }
925
926 static inline unsigned mv_inc_q_index(unsigned *index)
927 {
928 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
929 return *index;
930 }
931
932 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
933 {
934 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
935 (last ? CRQB_CMD_LAST : 0);
936 }
937
938 /**
939 * mv_qc_prep - Host specific command preparation.
940 * @qc: queued command to prepare
941 *
942 * This routine simply redirects to the general purpose routine
943 * if command is not DMA. Else, it handles prep of the CRQB
944 * (command request block), does some sanity checking, and calls
945 * the SG load routine.
946 *
947 * LOCKING:
948 * Inherited from caller.
949 */
950 static void mv_qc_prep(struct ata_queued_cmd *qc)
951 {
952 struct ata_port *ap = qc->ap;
953 struct mv_port_priv *pp = ap->private_data;
954 u16 *cw;
955 struct ata_taskfile *tf;
956 u16 flags = 0;
957
958 if (ATA_PROT_DMA != qc->tf.protocol) {
959 return;
960 }
961
962 /* the req producer index should be the same as we remember it */
963 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
964 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
965 pp->req_producer);
966
967 /* Fill in command request block
968 */
969 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
970 flags |= CRQB_FLAG_READ;
971 }
972 assert(MV_MAX_Q_DEPTH > qc->tag);
973 flags |= qc->tag << CRQB_TAG_SHIFT;
974
975 pp->crqb[pp->req_producer].sg_addr =
976 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
977 pp->crqb[pp->req_producer].sg_addr_hi =
978 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
979 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
980
981 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
982 tf = &qc->tf;
983
984 /* Sadly, the CRQB cannot accomodate all registers--there are
985 * only 11 bytes...so we must pick and choose required
986 * registers based on the command. So, we drop feature and
987 * hob_feature for [RW] DMA commands, but they are needed for
988 * NCQ. NCQ will drop hob_nsect.
989 */
990 switch (tf->command) {
991 case ATA_CMD_READ:
992 case ATA_CMD_READ_EXT:
993 case ATA_CMD_WRITE:
994 case ATA_CMD_WRITE_EXT:
995 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
996 break;
997 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
998 case ATA_CMD_FPDMA_READ:
999 case ATA_CMD_FPDMA_WRITE:
1000 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1001 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1002 break;
1003 #endif /* FIXME: remove this line when NCQ added */
1004 default:
1005 /* The only other commands EDMA supports in non-queued and
1006 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1007 * of which are defined/used by Linux. If we get here, this
1008 * driver needs work.
1009 *
1010 * FIXME: modify libata to give qc_prep a return value and
1011 * return error here.
1012 */
1013 BUG_ON(tf->command);
1014 break;
1015 }
1016 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1017 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1018 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1019 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1020 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1021 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1022 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1023 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1024 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1025
1026 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
1027 return;
1028 }
1029 mv_fill_sg(qc);
1030 }
1031
1032 /**
1033 * mv_qc_issue - Initiate a command to the host
1034 * @qc: queued command to start
1035 *
1036 * This routine simply redirects to the general purpose routine
1037 * if command is not DMA. Else, it sanity checks our local
1038 * caches of the request producer/consumer indices then enables
1039 * DMA and bumps the request producer index.
1040 *
1041 * LOCKING:
1042 * Inherited from caller.
1043 */
1044 static int mv_qc_issue(struct ata_queued_cmd *qc)
1045 {
1046 void __iomem *port_mmio = mv_ap_base(qc->ap);
1047 struct mv_port_priv *pp = qc->ap->private_data;
1048 u32 in_ptr;
1049
1050 if (ATA_PROT_DMA != qc->tf.protocol) {
1051 /* We're about to send a non-EDMA capable command to the
1052 * port. Turn off EDMA so there won't be problems accessing
1053 * shadow block, etc registers.
1054 */
1055 mv_stop_dma(qc->ap);
1056 return ata_qc_issue_prot(qc);
1057 }
1058
1059 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1060
1061 /* the req producer index should be the same as we remember it */
1062 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1063 pp->req_producer);
1064 /* until we do queuing, the queue should be empty at this point */
1065 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1066 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
1067 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1068
1069 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
1070
1071 mv_start_dma(port_mmio, pp);
1072
1073 /* and write the request in pointer to kick the EDMA to life */
1074 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1075 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
1076 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1077
1078 return 0;
1079 }
1080
1081 /**
1082 * mv_get_crpb_status - get status from most recently completed cmd
1083 * @ap: ATA channel to manipulate
1084 *
1085 * This routine is for use when the port is in DMA mode, when it
1086 * will be using the CRPB (command response block) method of
1087 * returning command completion information. We assert indices
1088 * are good, grab status, and bump the response consumer index to
1089 * prove that we're up to date.
1090 *
1091 * LOCKING:
1092 * Inherited from caller.
1093 */
1094 static u8 mv_get_crpb_status(struct ata_port *ap)
1095 {
1096 void __iomem *port_mmio = mv_ap_base(ap);
1097 struct mv_port_priv *pp = ap->private_data;
1098 u32 out_ptr;
1099
1100 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1101
1102 /* the response consumer index should be the same as we remember it */
1103 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1104 pp->rsp_consumer);
1105
1106 /* increment our consumer index... */
1107 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
1108
1109 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1110 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
1111 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1112 pp->rsp_consumer);
1113
1114 /* write out our inc'd consumer index so EDMA knows we're caught up */
1115 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1116 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
1117 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1118
1119 /* Return ATA status register for completed CRPB */
1120 return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT);
1121 }
1122
1123 /**
1124 * mv_err_intr - Handle error interrupts on the port
1125 * @ap: ATA channel to manipulate
1126 *
1127 * In most cases, just clear the interrupt and move on. However,
1128 * some cases require an eDMA reset, which is done right before
1129 * the COMRESET in mv_phy_reset(). The SERR case requires a
1130 * clear of pending errors in the SATA SERROR register. Finally,
1131 * if the port disabled DMA, update our cached copy to match.
1132 *
1133 * LOCKING:
1134 * Inherited from caller.
1135 */
1136 static void mv_err_intr(struct ata_port *ap)
1137 {
1138 void __iomem *port_mmio = mv_ap_base(ap);
1139 u32 edma_err_cause, serr = 0;
1140
1141 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1142
1143 if (EDMA_ERR_SERR & edma_err_cause) {
1144 serr = scr_read(ap, SCR_ERROR);
1145 scr_write_flush(ap, SCR_ERROR, serr);
1146 }
1147 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1148 struct mv_port_priv *pp = ap->private_data;
1149 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1150 }
1151 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1152 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1153
1154 /* Clear EDMA now that SERR cleanup done */
1155 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1156
1157 /* check for fatal here and recover if needed */
1158 if (EDMA_ERR_FATAL & edma_err_cause) {
1159 mv_stop_and_reset(ap);
1160 }
1161 }
1162
1163 /**
1164 * mv_host_intr - Handle all interrupts on the given host controller
1165 * @host_set: host specific structure
1166 * @relevant: port error bits relevant to this host controller
1167 * @hc: which host controller we're to look at
1168 *
1169 * Read then write clear the HC interrupt status then walk each
1170 * port connected to the HC and see if it needs servicing. Port
1171 * success ints are reported in the HC interrupt status reg, the
1172 * port error ints are reported in the higher level main
1173 * interrupt status register and thus are passed in via the
1174 * 'relevant' argument.
1175 *
1176 * LOCKING:
1177 * Inherited from caller.
1178 */
1179 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1180 unsigned int hc)
1181 {
1182 void __iomem *mmio = host_set->mmio_base;
1183 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1184 struct ata_port *ap;
1185 struct ata_queued_cmd *qc;
1186 u32 hc_irq_cause;
1187 int shift, port, port0, hard_port, handled;
1188 unsigned int err_mask;
1189 u8 ata_status = 0;
1190
1191 if (hc == 0) {
1192 port0 = 0;
1193 } else {
1194 port0 = MV_PORTS_PER_HC;
1195 }
1196
1197 /* we'll need the HC success int register in most cases */
1198 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1199 if (hc_irq_cause) {
1200 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1201 }
1202
1203 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1204 hc,relevant,hc_irq_cause);
1205
1206 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1207 ap = host_set->ports[port];
1208 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1209 handled = 0; /* ensure ata_status is set if handled++ */
1210
1211 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1212 /* new CRPB on the queue; just one at a time until NCQ
1213 */
1214 ata_status = mv_get_crpb_status(ap);
1215 handled++;
1216 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1217 /* received ATA IRQ; read the status reg to clear INTRQ
1218 */
1219 ata_status = readb((void __iomem *)
1220 ap->ioaddr.status_addr);
1221 handled++;
1222 }
1223
1224 if (ap &&
1225 (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))
1226 continue;
1227
1228 err_mask = ac_err_mask(ata_status);
1229
1230 shift = port << 1; /* (port * 2) */
1231 if (port >= MV_PORTS_PER_HC) {
1232 shift++; /* skip bit 8 in the HC Main IRQ reg */
1233 }
1234 if ((PORT0_ERR << shift) & relevant) {
1235 mv_err_intr(ap);
1236 err_mask |= AC_ERR_OTHER;
1237 handled++;
1238 }
1239
1240 if (handled && ap) {
1241 qc = ata_qc_from_tag(ap, ap->active_tag);
1242 if (NULL != qc) {
1243 VPRINTK("port %u IRQ found for qc, "
1244 "ata_status 0x%x\n", port,ata_status);
1245 /* mark qc status appropriately */
1246 if (!(qc->tf.ctl & ATA_NIEN)) {
1247 qc->err_mask |= err_mask;
1248 ata_qc_complete(qc);
1249 }
1250 }
1251 }
1252 }
1253 VPRINTK("EXIT\n");
1254 }
1255
1256 /**
1257 * mv_interrupt -
1258 * @irq: unused
1259 * @dev_instance: private data; in this case the host structure
1260 * @regs: unused
1261 *
1262 * Read the read only register to determine if any host
1263 * controllers have pending interrupts. If so, call lower level
1264 * routine to handle. Also check for PCI errors which are only
1265 * reported here.
1266 *
1267 * LOCKING:
1268 * This routine holds the host_set lock while processing pending
1269 * interrupts.
1270 */
1271 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1272 struct pt_regs *regs)
1273 {
1274 struct ata_host_set *host_set = dev_instance;
1275 unsigned int hc, handled = 0, n_hcs;
1276 void __iomem *mmio = host_set->mmio_base;
1277 u32 irq_stat;
1278
1279 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1280
1281 /* check the cases where we either have nothing pending or have read
1282 * a bogus register value which can indicate HW removal or PCI fault
1283 */
1284 if (!irq_stat || (0xffffffffU == irq_stat)) {
1285 return IRQ_NONE;
1286 }
1287
1288 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1289 spin_lock(&host_set->lock);
1290
1291 for (hc = 0; hc < n_hcs; hc++) {
1292 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1293 if (relevant) {
1294 mv_host_intr(host_set, relevant, hc);
1295 handled++;
1296 }
1297 }
1298 if (PCI_ERR & irq_stat) {
1299 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1300 readl(mmio + PCI_IRQ_CAUSE_OFS));
1301
1302 DPRINTK("All regs @ PCI error\n");
1303 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1304
1305 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1306 handled++;
1307 }
1308 spin_unlock(&host_set->lock);
1309
1310 return IRQ_RETVAL(handled);
1311 }
1312
1313 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1314 {
1315 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1316 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1317
1318 return hc_mmio + ofs;
1319 }
1320
1321 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1322 {
1323 unsigned int ofs;
1324
1325 switch (sc_reg_in) {
1326 case SCR_STATUS:
1327 case SCR_ERROR:
1328 case SCR_CONTROL:
1329 ofs = sc_reg_in * sizeof(u32);
1330 break;
1331 default:
1332 ofs = 0xffffffffU;
1333 break;
1334 }
1335 return ofs;
1336 }
1337
1338 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1339 {
1340 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1341 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1342
1343 if (ofs != 0xffffffffU)
1344 return readl(mmio + ofs);
1345 else
1346 return (u32) ofs;
1347 }
1348
1349 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1350 {
1351 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1352 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1353
1354 if (ofs != 0xffffffffU)
1355 writelfl(val, mmio + ofs);
1356 }
1357
1358 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1359 {
1360 u8 rev_id;
1361 int early_5080;
1362
1363 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1364
1365 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1366
1367 if (!early_5080) {
1368 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1369 tmp |= (1 << 0);
1370 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1371 }
1372
1373 mv_reset_pci_bus(pdev, mmio);
1374 }
1375
1376 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1377 {
1378 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1379 }
1380
1381 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1382 void __iomem *mmio)
1383 {
1384 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1385 u32 tmp;
1386
1387 tmp = readl(phy_mmio + MV5_PHY_MODE);
1388
1389 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1390 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1391 }
1392
1393 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1394 {
1395 u32 tmp;
1396
1397 writel(0, mmio + MV_GPIO_PORT_CTL);
1398
1399 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1400
1401 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1402 tmp |= ~(1 << 0);
1403 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1404 }
1405
1406 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1407 unsigned int port)
1408 {
1409 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1410 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1411 u32 tmp;
1412 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1413
1414 if (fix_apm_sq) {
1415 tmp = readl(phy_mmio + MV5_LT_MODE);
1416 tmp |= (1 << 19);
1417 writel(tmp, phy_mmio + MV5_LT_MODE);
1418
1419 tmp = readl(phy_mmio + MV5_PHY_CTL);
1420 tmp &= ~0x3;
1421 tmp |= 0x1;
1422 writel(tmp, phy_mmio + MV5_PHY_CTL);
1423 }
1424
1425 tmp = readl(phy_mmio + MV5_PHY_MODE);
1426 tmp &= ~mask;
1427 tmp |= hpriv->signal[port].pre;
1428 tmp |= hpriv->signal[port].amps;
1429 writel(tmp, phy_mmio + MV5_PHY_MODE);
1430 }
1431
1432
1433 #undef ZERO
1434 #define ZERO(reg) writel(0, port_mmio + (reg))
1435 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1436 unsigned int port)
1437 {
1438 void __iomem *port_mmio = mv_port_base(mmio, port);
1439
1440 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1441
1442 mv_channel_reset(hpriv, mmio, port);
1443
1444 ZERO(0x028); /* command */
1445 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1446 ZERO(0x004); /* timer */
1447 ZERO(0x008); /* irq err cause */
1448 ZERO(0x00c); /* irq err mask */
1449 ZERO(0x010); /* rq bah */
1450 ZERO(0x014); /* rq inp */
1451 ZERO(0x018); /* rq outp */
1452 ZERO(0x01c); /* respq bah */
1453 ZERO(0x024); /* respq outp */
1454 ZERO(0x020); /* respq inp */
1455 ZERO(0x02c); /* test control */
1456 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1457 }
1458 #undef ZERO
1459
1460 #define ZERO(reg) writel(0, hc_mmio + (reg))
1461 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1462 unsigned int hc)
1463 {
1464 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1465 u32 tmp;
1466
1467 ZERO(0x00c);
1468 ZERO(0x010);
1469 ZERO(0x014);
1470 ZERO(0x018);
1471
1472 tmp = readl(hc_mmio + 0x20);
1473 tmp &= 0x1c1c1c1c;
1474 tmp |= 0x03030303;
1475 writel(tmp, hc_mmio + 0x20);
1476 }
1477 #undef ZERO
1478
1479 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1480 unsigned int n_hc)
1481 {
1482 unsigned int hc, port;
1483
1484 for (hc = 0; hc < n_hc; hc++) {
1485 for (port = 0; port < MV_PORTS_PER_HC; port++)
1486 mv5_reset_hc_port(hpriv, mmio,
1487 (hc * MV_PORTS_PER_HC) + port);
1488
1489 mv5_reset_one_hc(hpriv, mmio, hc);
1490 }
1491
1492 return 0;
1493 }
1494
1495 #undef ZERO
1496 #define ZERO(reg) writel(0, mmio + (reg))
1497 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1498 {
1499 u32 tmp;
1500
1501 tmp = readl(mmio + MV_PCI_MODE);
1502 tmp &= 0xff00ffff;
1503 writel(tmp, mmio + MV_PCI_MODE);
1504
1505 ZERO(MV_PCI_DISC_TIMER);
1506 ZERO(MV_PCI_MSI_TRIGGER);
1507 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1508 ZERO(HC_MAIN_IRQ_MASK_OFS);
1509 ZERO(MV_PCI_SERR_MASK);
1510 ZERO(PCI_IRQ_CAUSE_OFS);
1511 ZERO(PCI_IRQ_MASK_OFS);
1512 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1513 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1514 ZERO(MV_PCI_ERR_ATTRIBUTE);
1515 ZERO(MV_PCI_ERR_COMMAND);
1516 }
1517 #undef ZERO
1518
1519 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1520 {
1521 u32 tmp;
1522
1523 mv5_reset_flash(hpriv, mmio);
1524
1525 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1526 tmp &= 0x3;
1527 tmp |= (1 << 5) | (1 << 6);
1528 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1529 }
1530
1531 /**
1532 * mv6_reset_hc - Perform the 6xxx global soft reset
1533 * @mmio: base address of the HBA
1534 *
1535 * This routine only applies to 6xxx parts.
1536 *
1537 * LOCKING:
1538 * Inherited from caller.
1539 */
1540 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1541 unsigned int n_hc)
1542 {
1543 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1544 int i, rc = 0;
1545 u32 t;
1546
1547 /* Following procedure defined in PCI "main command and status
1548 * register" table.
1549 */
1550 t = readl(reg);
1551 writel(t | STOP_PCI_MASTER, reg);
1552
1553 for (i = 0; i < 1000; i++) {
1554 udelay(1);
1555 t = readl(reg);
1556 if (PCI_MASTER_EMPTY & t) {
1557 break;
1558 }
1559 }
1560 if (!(PCI_MASTER_EMPTY & t)) {
1561 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1562 rc = 1;
1563 goto done;
1564 }
1565
1566 /* set reset */
1567 i = 5;
1568 do {
1569 writel(t | GLOB_SFT_RST, reg);
1570 t = readl(reg);
1571 udelay(1);
1572 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1573
1574 if (!(GLOB_SFT_RST & t)) {
1575 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1576 rc = 1;
1577 goto done;
1578 }
1579
1580 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1581 i = 5;
1582 do {
1583 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1584 t = readl(reg);
1585 udelay(1);
1586 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1587
1588 if (GLOB_SFT_RST & t) {
1589 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1590 rc = 1;
1591 }
1592 done:
1593 return rc;
1594 }
1595
1596 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1597 void __iomem *mmio)
1598 {
1599 void __iomem *port_mmio;
1600 u32 tmp;
1601
1602 tmp = readl(mmio + MV_RESET_CFG);
1603 if ((tmp & (1 << 0)) == 0) {
1604 hpriv->signal[idx].amps = 0x7 << 8;
1605 hpriv->signal[idx].pre = 0x1 << 5;
1606 return;
1607 }
1608
1609 port_mmio = mv_port_base(mmio, idx);
1610 tmp = readl(port_mmio + PHY_MODE2);
1611
1612 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1613 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1614 }
1615
1616 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1617 {
1618 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1619 }
1620
1621 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1622 unsigned int port)
1623 {
1624 void __iomem *port_mmio = mv_port_base(mmio, port);
1625
1626 u32 hp_flags = hpriv->hp_flags;
1627 int fix_phy_mode2 =
1628 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1629 int fix_phy_mode4 =
1630 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1631 u32 m2, tmp;
1632
1633 if (fix_phy_mode2) {
1634 m2 = readl(port_mmio + PHY_MODE2);
1635 m2 &= ~(1 << 16);
1636 m2 |= (1 << 31);
1637 writel(m2, port_mmio + PHY_MODE2);
1638
1639 udelay(200);
1640
1641 m2 = readl(port_mmio + PHY_MODE2);
1642 m2 &= ~((1 << 16) | (1 << 31));
1643 writel(m2, port_mmio + PHY_MODE2);
1644
1645 udelay(200);
1646 }
1647
1648 /* who knows what this magic does */
1649 tmp = readl(port_mmio + PHY_MODE3);
1650 tmp &= ~0x7F800000;
1651 tmp |= 0x2A800000;
1652 writel(tmp, port_mmio + PHY_MODE3);
1653
1654 if (fix_phy_mode4) {
1655 u32 m4;
1656
1657 m4 = readl(port_mmio + PHY_MODE4);
1658
1659 if (hp_flags & MV_HP_ERRATA_60X1B2)
1660 tmp = readl(port_mmio + 0x310);
1661
1662 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1663
1664 writel(m4, port_mmio + PHY_MODE4);
1665
1666 if (hp_flags & MV_HP_ERRATA_60X1B2)
1667 writel(tmp, port_mmio + 0x310);
1668 }
1669
1670 /* Revert values of pre-emphasis and signal amps to the saved ones */
1671 m2 = readl(port_mmio + PHY_MODE2);
1672
1673 m2 &= ~MV_M2_PREAMP_MASK;
1674 m2 |= hpriv->signal[port].amps;
1675 m2 |= hpriv->signal[port].pre;
1676 m2 &= ~(1 << 16);
1677
1678 writel(m2, port_mmio + PHY_MODE2);
1679 }
1680
1681 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1682 unsigned int port_no)
1683 {
1684 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1685
1686 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1687
1688 if (IS_60XX(hpriv)) {
1689 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1690 ifctl |= (1 << 12) | (1 << 7);
1691 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1692 }
1693
1694 udelay(25); /* allow reset propagation */
1695
1696 /* Spec never mentions clearing the bit. Marvell's driver does
1697 * clear the bit, however.
1698 */
1699 writelfl(0, port_mmio + EDMA_CMD_OFS);
1700
1701 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1702
1703 if (IS_50XX(hpriv))
1704 mdelay(1);
1705 }
1706
1707 static void mv_stop_and_reset(struct ata_port *ap)
1708 {
1709 struct mv_host_priv *hpriv = ap->host_set->private_data;
1710 void __iomem *mmio = ap->host_set->mmio_base;
1711
1712 mv_stop_dma(ap);
1713
1714 mv_channel_reset(hpriv, mmio, ap->port_no);
1715
1716 __mv_phy_reset(ap, 0);
1717 }
1718
1719 static inline void __msleep(unsigned int msec, int can_sleep)
1720 {
1721 if (can_sleep)
1722 msleep(msec);
1723 else
1724 mdelay(msec);
1725 }
1726
1727 /**
1728 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1729 * @ap: ATA channel to manipulate
1730 *
1731 * Part of this is taken from __sata_phy_reset and modified to
1732 * not sleep since this routine gets called from interrupt level.
1733 *
1734 * LOCKING:
1735 * Inherited from caller. This is coded to safe to call at
1736 * interrupt level, i.e. it does not sleep.
1737 */
1738 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1739 {
1740 struct mv_port_priv *pp = ap->private_data;
1741 struct mv_host_priv *hpriv = ap->host_set->private_data;
1742 void __iomem *port_mmio = mv_ap_base(ap);
1743 struct ata_taskfile tf;
1744 struct ata_device *dev = &ap->device[0];
1745 unsigned long timeout;
1746 int retry = 5;
1747 u32 sstatus;
1748
1749 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1750
1751 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1752 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1753 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1754
1755 /* Issue COMRESET via SControl */
1756 comreset_retry:
1757 scr_write_flush(ap, SCR_CONTROL, 0x301);
1758 __msleep(1, can_sleep);
1759
1760 scr_write_flush(ap, SCR_CONTROL, 0x300);
1761 __msleep(20, can_sleep);
1762
1763 timeout = jiffies + msecs_to_jiffies(200);
1764 do {
1765 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1766 if ((sstatus == 3) || (sstatus == 0))
1767 break;
1768
1769 __msleep(1, can_sleep);
1770 } while (time_before(jiffies, timeout));
1771
1772 /* work around errata */
1773 if (IS_60XX(hpriv) &&
1774 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1775 (retry-- > 0))
1776 goto comreset_retry;
1777
1778 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1779 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1780 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1781
1782 if (sata_dev_present(ap)) {
1783 ata_port_probe(ap);
1784 } else {
1785 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1786 ap->id, scr_read(ap, SCR_STATUS));
1787 ata_port_disable(ap);
1788 return;
1789 }
1790 ap->cbl = ATA_CBL_SATA;
1791
1792 /* even after SStatus reflects that device is ready,
1793 * it seems to take a while for link to be fully
1794 * established (and thus Status no longer 0x80/0x7F),
1795 * so we poll a bit for that, here.
1796 */
1797 retry = 20;
1798 while (1) {
1799 u8 drv_stat = ata_check_status(ap);
1800 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1801 break;
1802 __msleep(500, can_sleep);
1803 if (retry-- <= 0)
1804 break;
1805 }
1806
1807 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1808 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1809 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1810 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1811
1812 dev->class = ata_dev_classify(&tf);
1813 if (!ata_dev_present(dev)) {
1814 VPRINTK("Port disabled post-sig: No device present.\n");
1815 ata_port_disable(ap);
1816 }
1817
1818 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1819
1820 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1821
1822 VPRINTK("EXIT\n");
1823 }
1824
1825 static void mv_phy_reset(struct ata_port *ap)
1826 {
1827 __mv_phy_reset(ap, 1);
1828 }
1829
1830 /**
1831 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1832 * @ap: ATA channel to manipulate
1833 *
1834 * Intent is to clear all pending error conditions, reset the
1835 * chip/bus, fail the command, and move on.
1836 *
1837 * LOCKING:
1838 * This routine holds the host_set lock while failing the command.
1839 */
1840 static void mv_eng_timeout(struct ata_port *ap)
1841 {
1842 struct ata_queued_cmd *qc;
1843 unsigned long flags;
1844
1845 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1846 DPRINTK("All regs @ start of eng_timeout\n");
1847 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1848 to_pci_dev(ap->host_set->dev));
1849
1850 qc = ata_qc_from_tag(ap, ap->active_tag);
1851 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1852 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1853 &qc->scsicmd->cmnd);
1854
1855 mv_err_intr(ap);
1856 mv_stop_and_reset(ap);
1857
1858 if (!qc) {
1859 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1860 ap->id);
1861 } else {
1862 /* hack alert! We cannot use the supplied completion
1863 * function from inside the ->eh_strategy_handler() thread.
1864 * libata is the only user of ->eh_strategy_handler() in
1865 * any kernel, so the default scsi_done() assumes it is
1866 * not being called from the SCSI EH.
1867 */
1868 spin_lock_irqsave(&ap->host_set->lock, flags);
1869 qc->scsidone = scsi_finish_command;
1870 qc->err_mask |= AC_ERR_OTHER;
1871 ata_qc_complete(qc);
1872 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1873 }
1874 }
1875
1876 /**
1877 * mv_port_init - Perform some early initialization on a single port.
1878 * @port: libata data structure storing shadow register addresses
1879 * @port_mmio: base address of the port
1880 *
1881 * Initialize shadow register mmio addresses, clear outstanding
1882 * interrupts on the port, and unmask interrupts for the future
1883 * start of the port.
1884 *
1885 * LOCKING:
1886 * Inherited from caller.
1887 */
1888 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1889 {
1890 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1891 unsigned serr_ofs;
1892
1893 /* PIO related setup
1894 */
1895 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1896 port->error_addr =
1897 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1898 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1899 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1900 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1901 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1902 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1903 port->status_addr =
1904 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1905 /* special case: control/altstatus doesn't have ATA_REG_ address */
1906 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
1907
1908 /* unused: */
1909 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
1910
1911 /* Clear any currently outstanding port interrupt conditions */
1912 serr_ofs = mv_scr_offset(SCR_ERROR);
1913 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
1914 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1915
1916 /* unmask all EDMA error interrupts */
1917 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1918
1919 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1920 readl(port_mmio + EDMA_CFG_OFS),
1921 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1922 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1923 }
1924
1925 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
1926 unsigned int board_idx)
1927 {
1928 u8 rev_id;
1929 u32 hp_flags = hpriv->hp_flags;
1930
1931 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1932
1933 switch(board_idx) {
1934 case chip_5080:
1935 hpriv->ops = &mv5xxx_ops;
1936 hp_flags |= MV_HP_50XX;
1937
1938 switch (rev_id) {
1939 case 0x1:
1940 hp_flags |= MV_HP_ERRATA_50XXB0;
1941 break;
1942 case 0x3:
1943 hp_flags |= MV_HP_ERRATA_50XXB2;
1944 break;
1945 default:
1946 dev_printk(KERN_WARNING, &pdev->dev,
1947 "Applying 50XXB2 workarounds to unknown rev\n");
1948 hp_flags |= MV_HP_ERRATA_50XXB2;
1949 break;
1950 }
1951 break;
1952
1953 case chip_504x:
1954 case chip_508x:
1955 hpriv->ops = &mv5xxx_ops;
1956 hp_flags |= MV_HP_50XX;
1957
1958 switch (rev_id) {
1959 case 0x0:
1960 hp_flags |= MV_HP_ERRATA_50XXB0;
1961 break;
1962 case 0x3:
1963 hp_flags |= MV_HP_ERRATA_50XXB2;
1964 break;
1965 default:
1966 dev_printk(KERN_WARNING, &pdev->dev,
1967 "Applying B2 workarounds to unknown rev\n");
1968 hp_flags |= MV_HP_ERRATA_50XXB2;
1969 break;
1970 }
1971 break;
1972
1973 case chip_604x:
1974 case chip_608x:
1975 hpriv->ops = &mv6xxx_ops;
1976
1977 switch (rev_id) {
1978 case 0x7:
1979 hp_flags |= MV_HP_ERRATA_60X1B2;
1980 break;
1981 case 0x9:
1982 hp_flags |= MV_HP_ERRATA_60X1C0;
1983 break;
1984 default:
1985 dev_printk(KERN_WARNING, &pdev->dev,
1986 "Applying B2 workarounds to unknown rev\n");
1987 hp_flags |= MV_HP_ERRATA_60X1B2;
1988 break;
1989 }
1990 break;
1991
1992 default:
1993 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
1994 return 1;
1995 }
1996
1997 hpriv->hp_flags = hp_flags;
1998
1999 return 0;
2000 }
2001
2002 /**
2003 * mv_init_host - Perform some early initialization of the host.
2004 * @pdev: host PCI device
2005 * @probe_ent: early data struct representing the host
2006 *
2007 * If possible, do an early global reset of the host. Then do
2008 * our port init and clear/unmask all/relevant host interrupts.
2009 *
2010 * LOCKING:
2011 * Inherited from caller.
2012 */
2013 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2014 unsigned int board_idx)
2015 {
2016 int rc = 0, n_hc, port, hc;
2017 void __iomem *mmio = probe_ent->mmio_base;
2018 struct mv_host_priv *hpriv = probe_ent->private_data;
2019
2020 /* global interrupt mask */
2021 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2022
2023 rc = mv_chip_id(pdev, hpriv, board_idx);
2024 if (rc)
2025 goto done;
2026
2027 n_hc = mv_get_hc_count(probe_ent->host_flags);
2028 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2029
2030 for (port = 0; port < probe_ent->n_ports; port++)
2031 hpriv->ops->read_preamp(hpriv, port, mmio);
2032
2033 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2034 if (rc)
2035 goto done;
2036
2037 hpriv->ops->reset_flash(hpriv, mmio);
2038 hpriv->ops->reset_bus(pdev, mmio);
2039 hpriv->ops->enable_leds(hpriv, mmio);
2040
2041 for (port = 0; port < probe_ent->n_ports; port++) {
2042 if (IS_60XX(hpriv)) {
2043 void __iomem *port_mmio = mv_port_base(mmio, port);
2044
2045 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2046 ifctl |= (1 << 12);
2047 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2048 }
2049
2050 hpriv->ops->phy_errata(hpriv, mmio, port);
2051 }
2052
2053 for (port = 0; port < probe_ent->n_ports; port++) {
2054 void __iomem *port_mmio = mv_port_base(mmio, port);
2055 mv_port_init(&probe_ent->port[port], port_mmio);
2056 }
2057
2058 for (hc = 0; hc < n_hc; hc++) {
2059 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2060
2061 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2062 "(before clear)=0x%08x\n", hc,
2063 readl(hc_mmio + HC_CFG_OFS),
2064 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2065
2066 /* Clear any currently outstanding hc interrupt conditions */
2067 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2068 }
2069
2070 /* Clear any currently outstanding host interrupt conditions */
2071 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2072
2073 /* and unmask interrupt generation for host regs */
2074 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2075 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2076
2077 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2078 "PCI int cause/mask=0x%08x/0x%08x\n",
2079 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2080 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2081 readl(mmio + PCI_IRQ_CAUSE_OFS),
2082 readl(mmio + PCI_IRQ_MASK_OFS));
2083
2084 done:
2085 return rc;
2086 }
2087
2088 /**
2089 * mv_print_info - Dump key info to kernel log for perusal.
2090 * @probe_ent: early data struct representing the host
2091 *
2092 * FIXME: complete this.
2093 *
2094 * LOCKING:
2095 * Inherited from caller.
2096 */
2097 static void mv_print_info(struct ata_probe_ent *probe_ent)
2098 {
2099 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2100 struct mv_host_priv *hpriv = probe_ent->private_data;
2101 u8 rev_id, scc;
2102 const char *scc_s;
2103
2104 /* Use this to determine the HW stepping of the chip so we know
2105 * what errata to workaround
2106 */
2107 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2108
2109 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2110 if (scc == 0)
2111 scc_s = "SCSI";
2112 else if (scc == 0x01)
2113 scc_s = "RAID";
2114 else
2115 scc_s = "unknown";
2116
2117 dev_printk(KERN_INFO, &pdev->dev,
2118 "%u slots %u ports %s mode IRQ via %s\n",
2119 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2120 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2121 }
2122
2123 /**
2124 * mv_init_one - handle a positive probe of a Marvell host
2125 * @pdev: PCI device found
2126 * @ent: PCI device ID entry for the matched host
2127 *
2128 * LOCKING:
2129 * Inherited from caller.
2130 */
2131 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2132 {
2133 static int printed_version = 0;
2134 struct ata_probe_ent *probe_ent = NULL;
2135 struct mv_host_priv *hpriv;
2136 unsigned int board_idx = (unsigned int)ent->driver_data;
2137 void __iomem *mmio_base;
2138 int pci_dev_busy = 0, rc;
2139
2140 if (!printed_version++)
2141 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2142
2143 rc = pci_enable_device(pdev);
2144 if (rc) {
2145 return rc;
2146 }
2147
2148 rc = pci_request_regions(pdev, DRV_NAME);
2149 if (rc) {
2150 pci_dev_busy = 1;
2151 goto err_out;
2152 }
2153
2154 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
2155 if (probe_ent == NULL) {
2156 rc = -ENOMEM;
2157 goto err_out_regions;
2158 }
2159
2160 memset(probe_ent, 0, sizeof(*probe_ent));
2161 probe_ent->dev = pci_dev_to_dev(pdev);
2162 INIT_LIST_HEAD(&probe_ent->node);
2163
2164 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
2165 if (mmio_base == NULL) {
2166 rc = -ENOMEM;
2167 goto err_out_free_ent;
2168 }
2169
2170 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
2171 if (!hpriv) {
2172 rc = -ENOMEM;
2173 goto err_out_iounmap;
2174 }
2175 memset(hpriv, 0, sizeof(*hpriv));
2176
2177 probe_ent->sht = mv_port_info[board_idx].sht;
2178 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
2179 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2180 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2181 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2182
2183 probe_ent->irq = pdev->irq;
2184 probe_ent->irq_flags = SA_SHIRQ;
2185 probe_ent->mmio_base = mmio_base;
2186 probe_ent->private_data = hpriv;
2187
2188 /* initialize adapter */
2189 rc = mv_init_host(pdev, probe_ent, board_idx);
2190 if (rc) {
2191 goto err_out_hpriv;
2192 }
2193
2194 /* Enable interrupts */
2195 if (pci_enable_msi(pdev) == 0) {
2196 hpriv->hp_flags |= MV_HP_FLAG_MSI;
2197 } else {
2198 pci_intx(pdev, 1);
2199 }
2200
2201 mv_dump_pci_cfg(pdev, 0x68);
2202 mv_print_info(probe_ent);
2203
2204 if (ata_device_add(probe_ent) == 0) {
2205 rc = -ENODEV; /* No devices discovered */
2206 goto err_out_dev_add;
2207 }
2208
2209 kfree(probe_ent);
2210 return 0;
2211
2212 err_out_dev_add:
2213 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
2214 pci_disable_msi(pdev);
2215 } else {
2216 pci_intx(pdev, 0);
2217 }
2218 err_out_hpriv:
2219 kfree(hpriv);
2220 err_out_iounmap:
2221 pci_iounmap(pdev, mmio_base);
2222 err_out_free_ent:
2223 kfree(probe_ent);
2224 err_out_regions:
2225 pci_release_regions(pdev);
2226 err_out:
2227 if (!pci_dev_busy) {
2228 pci_disable_device(pdev);
2229 }
2230
2231 return rc;
2232 }
2233
2234 static int __init mv_init(void)
2235 {
2236 return pci_module_init(&mv_pci_driver);
2237 }
2238
2239 static void __exit mv_exit(void)
2240 {
2241 pci_unregister_driver(&mv_pci_driver);
2242 }
2243
2244 MODULE_AUTHOR("Brett Russ");
2245 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2246 MODULE_LICENSE("GPL");
2247 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2248 MODULE_VERSION(DRV_VERSION);
2249
2250 module_init(mv_init);
2251 module_exit(mv_exit);
Linux kernel - Deliverables
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