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[deliverable/linux.git] / drivers / scsi / sata_nv.c
1 /*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
30 * hotplug info, etc.
31 *
32 */
33
34 #include <linux/config.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
45
46 #define DRV_NAME "sata_nv"
47 #define DRV_VERSION "0.9"
48
49 enum {
50 NV_PORTS = 2,
51 NV_PIO_MASK = 0x1f,
52 NV_MWDMA_MASK = 0x07,
53 NV_UDMA_MASK = 0x7f,
54 NV_PORT0_SCR_REG_OFFSET = 0x00,
55 NV_PORT1_SCR_REG_OFFSET = 0x40,
56
57 /* INT_STATUS/ENABLE */
58 NV_INT_STATUS = 0x10,
59 NV_INT_ENABLE = 0x11,
60 NV_INT_STATUS_CK804 = 0x440,
61 NV_INT_ENABLE_CK804 = 0x441,
62
63 /* INT_STATUS/ENABLE bits */
64 NV_INT_DEV = 0x01,
65 NV_INT_PM = 0x02,
66 NV_INT_ADDED = 0x04,
67 NV_INT_REMOVED = 0x08,
68
69 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
70
71 /* INT_CONFIG */
72 NV_INT_CONFIG = 0x12,
73 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
74
75 // For PCI config register 20
76 NV_MCP_SATA_CFG_20 = 0x50,
77 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
78 };
79
80 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
81 static void nv_ck804_host_stop(struct ata_host_set *host_set);
82 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
83 struct pt_regs *regs);
84 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
85 struct pt_regs *regs);
86 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
87 struct pt_regs *regs);
88 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
89 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
90
91 enum nv_host_type
92 {
93 GENERIC,
94 NFORCE2,
95 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
96 CK804
97 };
98
99 static const struct pci_device_id nv_pci_tbl[] = {
100 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
102 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
104 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
106 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
108 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
110 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
112 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
114 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
116 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
128 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
129 PCI_ANY_ID, PCI_ANY_ID,
130 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
131 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
132 PCI_ANY_ID, PCI_ANY_ID,
133 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
134 { 0, } /* terminate list */
135 };
136
137 static struct pci_driver nv_pci_driver = {
138 .name = DRV_NAME,
139 .id_table = nv_pci_tbl,
140 .probe = nv_init_one,
141 .remove = ata_pci_remove_one,
142 };
143
144 static struct scsi_host_template nv_sht = {
145 .module = THIS_MODULE,
146 .name = DRV_NAME,
147 .ioctl = ata_scsi_ioctl,
148 .queuecommand = ata_scsi_queuecmd,
149 .can_queue = ATA_DEF_QUEUE,
150 .this_id = ATA_SHT_THIS_ID,
151 .sg_tablesize = LIBATA_MAX_PRD,
152 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
153 .emulated = ATA_SHT_EMULATED,
154 .use_clustering = ATA_SHT_USE_CLUSTERING,
155 .proc_name = DRV_NAME,
156 .dma_boundary = ATA_DMA_BOUNDARY,
157 .slave_configure = ata_scsi_slave_config,
158 .slave_destroy = ata_scsi_slave_destroy,
159 .bios_param = ata_std_bios_param,
160 };
161
162 static const struct ata_port_operations nv_generic_ops = {
163 .port_disable = ata_port_disable,
164 .tf_load = ata_tf_load,
165 .tf_read = ata_tf_read,
166 .exec_command = ata_exec_command,
167 .check_status = ata_check_status,
168 .dev_select = ata_std_dev_select,
169 .phy_reset = sata_phy_reset,
170 .bmdma_setup = ata_bmdma_setup,
171 .bmdma_start = ata_bmdma_start,
172 .bmdma_stop = ata_bmdma_stop,
173 .bmdma_status = ata_bmdma_status,
174 .qc_prep = ata_qc_prep,
175 .qc_issue = ata_qc_issue_prot,
176 .eng_timeout = ata_eng_timeout,
177 .data_xfer = ata_pio_data_xfer,
178 .irq_handler = nv_generic_interrupt,
179 .irq_clear = ata_bmdma_irq_clear,
180 .scr_read = nv_scr_read,
181 .scr_write = nv_scr_write,
182 .port_start = ata_port_start,
183 .port_stop = ata_port_stop,
184 .host_stop = ata_pci_host_stop,
185 };
186
187 static const struct ata_port_operations nv_nf2_ops = {
188 .port_disable = ata_port_disable,
189 .tf_load = ata_tf_load,
190 .tf_read = ata_tf_read,
191 .exec_command = ata_exec_command,
192 .check_status = ata_check_status,
193 .dev_select = ata_std_dev_select,
194 .phy_reset = sata_phy_reset,
195 .bmdma_setup = ata_bmdma_setup,
196 .bmdma_start = ata_bmdma_start,
197 .bmdma_stop = ata_bmdma_stop,
198 .bmdma_status = ata_bmdma_status,
199 .qc_prep = ata_qc_prep,
200 .qc_issue = ata_qc_issue_prot,
201 .eng_timeout = ata_eng_timeout,
202 .data_xfer = ata_pio_data_xfer,
203 .irq_handler = nv_nf2_interrupt,
204 .irq_clear = ata_bmdma_irq_clear,
205 .scr_read = nv_scr_read,
206 .scr_write = nv_scr_write,
207 .port_start = ata_port_start,
208 .port_stop = ata_port_stop,
209 .host_stop = ata_pci_host_stop,
210 };
211
212 static const struct ata_port_operations nv_ck804_ops = {
213 .port_disable = ata_port_disable,
214 .tf_load = ata_tf_load,
215 .tf_read = ata_tf_read,
216 .exec_command = ata_exec_command,
217 .check_status = ata_check_status,
218 .dev_select = ata_std_dev_select,
219 .phy_reset = sata_phy_reset,
220 .bmdma_setup = ata_bmdma_setup,
221 .bmdma_start = ata_bmdma_start,
222 .bmdma_stop = ata_bmdma_stop,
223 .bmdma_status = ata_bmdma_status,
224 .qc_prep = ata_qc_prep,
225 .qc_issue = ata_qc_issue_prot,
226 .eng_timeout = ata_eng_timeout,
227 .data_xfer = ata_pio_data_xfer,
228 .irq_handler = nv_ck804_interrupt,
229 .irq_clear = ata_bmdma_irq_clear,
230 .scr_read = nv_scr_read,
231 .scr_write = nv_scr_write,
232 .port_start = ata_port_start,
233 .port_stop = ata_port_stop,
234 .host_stop = nv_ck804_host_stop,
235 };
236
237 /* FIXME: The hardware provides the necessary SATA PHY controls
238 * to support ATA_FLAG_SATA_RESET. However, it is currently
239 * necessary to disable that flag, to solve misdetection problems.
240 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
241 *
242 * This problem really needs to be investigated further. But in the
243 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
244 */
245 static struct ata_port_info nv_port_info[] = {
246 /* generic */
247 {
248 .sht = &nv_sht,
249 .host_flags = ATA_FLAG_SATA |
250 /* ATA_FLAG_SATA_RESET | */
251 ATA_FLAG_SRST |
252 ATA_FLAG_NO_LEGACY,
253 .pio_mask = NV_PIO_MASK,
254 .mwdma_mask = NV_MWDMA_MASK,
255 .udma_mask = NV_UDMA_MASK,
256 .port_ops = &nv_generic_ops,
257 },
258 /* nforce2/3 */
259 {
260 .sht = &nv_sht,
261 .host_flags = ATA_FLAG_SATA |
262 /* ATA_FLAG_SATA_RESET | */
263 ATA_FLAG_SRST |
264 ATA_FLAG_NO_LEGACY,
265 .pio_mask = NV_PIO_MASK,
266 .mwdma_mask = NV_MWDMA_MASK,
267 .udma_mask = NV_UDMA_MASK,
268 .port_ops = &nv_nf2_ops,
269 },
270 /* ck804 */
271 {
272 .sht = &nv_sht,
273 .host_flags = ATA_FLAG_SATA |
274 /* ATA_FLAG_SATA_RESET | */
275 ATA_FLAG_SRST |
276 ATA_FLAG_NO_LEGACY,
277 .pio_mask = NV_PIO_MASK,
278 .mwdma_mask = NV_MWDMA_MASK,
279 .udma_mask = NV_UDMA_MASK,
280 .port_ops = &nv_ck804_ops,
281 },
282 };
283
284 MODULE_AUTHOR("NVIDIA");
285 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
286 MODULE_LICENSE("GPL");
287 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
288 MODULE_VERSION(DRV_VERSION);
289
290 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
291 struct pt_regs *regs)
292 {
293 struct ata_host_set *host_set = dev_instance;
294 unsigned int i;
295 unsigned int handled = 0;
296 unsigned long flags;
297
298 spin_lock_irqsave(&host_set->lock, flags);
299
300 for (i = 0; i < host_set->n_ports; i++) {
301 struct ata_port *ap;
302
303 ap = host_set->ports[i];
304 if (ap &&
305 !(ap->flags & ATA_FLAG_DISABLED)) {
306 struct ata_queued_cmd *qc;
307
308 qc = ata_qc_from_tag(ap, ap->active_tag);
309 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
310 handled += ata_host_intr(ap, qc);
311 else
312 // No request pending? Clear interrupt status
313 // anyway, in case there's one pending.
314 ap->ops->check_status(ap);
315 }
316
317 }
318
319 spin_unlock_irqrestore(&host_set->lock, flags);
320
321 return IRQ_RETVAL(handled);
322 }
323
324 static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
325 {
326 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
327 int handled;
328
329 /* bail out if not our interrupt */
330 if (!(irq_stat & NV_INT_DEV))
331 return 0;
332
333 /* DEV interrupt w/ no active qc? */
334 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
335 ata_check_status(ap);
336 return 1;
337 }
338
339 /* handle interrupt */
340 handled = ata_host_intr(ap, qc);
341 if (unlikely(!handled)) {
342 /* spurious, clear it */
343 ata_check_status(ap);
344 }
345
346 return 1;
347 }
348
349 static irqreturn_t nv_do_interrupt(struct ata_host_set *host_set, u8 irq_stat)
350 {
351 int i, handled = 0;
352
353 for (i = 0; i < host_set->n_ports; i++) {
354 struct ata_port *ap = host_set->ports[i];
355
356 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
357 handled += nv_host_intr(ap, irq_stat);
358
359 irq_stat >>= NV_INT_PORT_SHIFT;
360 }
361
362 return IRQ_RETVAL(handled);
363 }
364
365 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
366 struct pt_regs *regs)
367 {
368 struct ata_host_set *host_set = dev_instance;
369 unsigned long flags;
370 u8 irq_stat;
371 irqreturn_t ret;
372
373 spin_lock_irqsave(&host_set->lock, flags);
374 irq_stat = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
375 ret = nv_do_interrupt(host_set, irq_stat);
376 spin_unlock_irqrestore(&host_set->lock, flags);
377
378 return ret;
379 }
380
381 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
382 struct pt_regs *regs)
383 {
384 struct ata_host_set *host_set = dev_instance;
385 unsigned long flags;
386 u8 irq_stat;
387 irqreturn_t ret;
388
389 spin_lock_irqsave(&host_set->lock, flags);
390 irq_stat = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
391 ret = nv_do_interrupt(host_set, irq_stat);
392 spin_unlock_irqrestore(&host_set->lock, flags);
393
394 return ret;
395 }
396
397 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
398 {
399 if (sc_reg > SCR_CONTROL)
400 return 0xffffffffU;
401
402 return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
403 }
404
405 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
406 {
407 if (sc_reg > SCR_CONTROL)
408 return;
409
410 iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
411 }
412
413 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
414 {
415 static int printed_version = 0;
416 struct ata_port_info *ppi;
417 struct ata_probe_ent *probe_ent;
418 int pci_dev_busy = 0;
419 int rc;
420 u32 bar;
421 unsigned long base;
422
423 // Make sure this is a SATA controller by counting the number of bars
424 // (NVIDIA SATA controllers will always have six bars). Otherwise,
425 // it's an IDE controller and we ignore it.
426 for (bar=0; bar<6; bar++)
427 if (pci_resource_start(pdev, bar) == 0)
428 return -ENODEV;
429
430 if (!printed_version++)
431 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
432
433 rc = pci_enable_device(pdev);
434 if (rc)
435 goto err_out;
436
437 rc = pci_request_regions(pdev, DRV_NAME);
438 if (rc) {
439 pci_dev_busy = 1;
440 goto err_out_disable;
441 }
442
443 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
444 if (rc)
445 goto err_out_regions;
446 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
447 if (rc)
448 goto err_out_regions;
449
450 rc = -ENOMEM;
451
452 ppi = &nv_port_info[ent->driver_data];
453 probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
454 if (!probe_ent)
455 goto err_out_regions;
456
457 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
458 if (!probe_ent->mmio_base) {
459 rc = -EIO;
460 goto err_out_free_ent;
461 }
462
463 base = (unsigned long)probe_ent->mmio_base;
464
465 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
466 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
467
468 /* enable SATA space for CK804 */
469 if (ent->driver_data == CK804) {
470 u8 regval;
471
472 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
473 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
474 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
475 }
476
477 pci_set_master(pdev);
478
479 rc = ata_device_add(probe_ent);
480 if (rc != NV_PORTS)
481 goto err_out_iounmap;
482
483 kfree(probe_ent);
484
485 return 0;
486
487 err_out_iounmap:
488 pci_iounmap(pdev, probe_ent->mmio_base);
489 err_out_free_ent:
490 kfree(probe_ent);
491 err_out_regions:
492 pci_release_regions(pdev);
493 err_out_disable:
494 if (!pci_dev_busy)
495 pci_disable_device(pdev);
496 err_out:
497 return rc;
498 }
499
500 static void nv_ck804_host_stop(struct ata_host_set *host_set)
501 {
502 struct pci_dev *pdev = to_pci_dev(host_set->dev);
503 u8 regval;
504
505 /* disable SATA space for CK804 */
506 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
507 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
508 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
509
510 ata_pci_host_stop(host_set);
511 }
512
513 static int __init nv_init(void)
514 {
515 return pci_module_init(&nv_pci_driver);
516 }
517
518 static void __exit nv_exit(void)
519 {
520 pci_unregister_driver(&nv_pci_driver);
521 }
522
523 module_init(nv_init);
524 module_exit(nv_exit);
Linux kernel - Deliverables
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