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[libata] license change, other bits
[deliverable/linux.git] / drivers / scsi / sata_promise.c
1 /*
2 * sata_promise.c - Promise SATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware information only available under NDA.
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include "scsi.h"
42 #include <scsi/scsi_host.h>
43 #include <linux/libata.h>
44 #include <asm/io.h>
45 #include "sata_promise.h"
46
47 #define DRV_NAME "sata_promise"
48 #define DRV_VERSION "1.02"
49
50
51 enum {
52 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
53 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
54 PDC_TBG_MODE = 0x41, /* TBG mode */
55 PDC_FLASH_CTL = 0x44, /* Flash control register */
56 PDC_PCI_CTL = 0x48, /* PCI control and status register */
57 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
58 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
59 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
60 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
61
62 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
63 (1<<8) | (1<<9) | (1<<10),
64
65 board_2037x = 0, /* FastTrak S150 TX2plus */
66 board_20319 = 1, /* FastTrak S150 TX4 */
67 board_20619 = 2, /* FastTrak TX4000 */
68
69 PDC_HAS_PATA = (1 << 1), /* PDC20375 has PATA */
70
71 PDC_RESET = (1 << 11), /* HDMA reset */
72 };
73
74
75 struct pdc_port_priv {
76 u8 *pkt;
77 dma_addr_t pkt_dma;
78 };
79
80 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
81 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
82 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
83 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
84 static void pdc_eng_timeout(struct ata_port *ap);
85 static int pdc_port_start(struct ata_port *ap);
86 static void pdc_port_stop(struct ata_port *ap);
87 static void pdc_phy_reset(struct ata_port *ap);
88 static void pdc_qc_prep(struct ata_queued_cmd *qc);
89 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
90 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
91 static void pdc_irq_clear(struct ata_port *ap);
92 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
93
94 static Scsi_Host_Template pdc_ata_sht = {
95 .module = THIS_MODULE,
96 .name = DRV_NAME,
97 .ioctl = ata_scsi_ioctl,
98 .queuecommand = ata_scsi_queuecmd,
99 .eh_strategy_handler = ata_scsi_error,
100 .can_queue = ATA_DEF_QUEUE,
101 .this_id = ATA_SHT_THIS_ID,
102 .sg_tablesize = LIBATA_MAX_PRD,
103 .max_sectors = ATA_MAX_SECTORS,
104 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
105 .emulated = ATA_SHT_EMULATED,
106 .use_clustering = ATA_SHT_USE_CLUSTERING,
107 .proc_name = DRV_NAME,
108 .dma_boundary = ATA_DMA_BOUNDARY,
109 .slave_configure = ata_scsi_slave_config,
110 .bios_param = ata_std_bios_param,
111 .ordered_flush = 1,
112 };
113
114 static struct ata_port_operations pdc_ata_ops = {
115 .port_disable = ata_port_disable,
116 .tf_load = pdc_tf_load_mmio,
117 .tf_read = ata_tf_read,
118 .check_status = ata_check_status,
119 .exec_command = pdc_exec_command_mmio,
120 .dev_select = ata_std_dev_select,
121 .phy_reset = pdc_phy_reset,
122 .qc_prep = pdc_qc_prep,
123 .qc_issue = pdc_qc_issue_prot,
124 .eng_timeout = pdc_eng_timeout,
125 .irq_handler = pdc_interrupt,
126 .irq_clear = pdc_irq_clear,
127 .scr_read = pdc_sata_scr_read,
128 .scr_write = pdc_sata_scr_write,
129 .port_start = pdc_port_start,
130 .port_stop = pdc_port_stop,
131 .host_stop = ata_host_stop,
132 };
133
134 static struct ata_port_info pdc_port_info[] = {
135 /* board_2037x */
136 {
137 .sht = &pdc_ata_sht,
138 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
139 ATA_FLAG_SRST | ATA_FLAG_MMIO,
140 .pio_mask = 0x1f, /* pio0-4 */
141 .mwdma_mask = 0x07, /* mwdma0-2 */
142 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
143 .port_ops = &pdc_ata_ops,
144 },
145
146 /* board_20319 */
147 {
148 .sht = &pdc_ata_sht,
149 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
150 ATA_FLAG_SRST | ATA_FLAG_MMIO,
151 .pio_mask = 0x1f, /* pio0-4 */
152 .mwdma_mask = 0x07, /* mwdma0-2 */
153 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
154 .port_ops = &pdc_ata_ops,
155 },
156
157 /* board_20619 */
158 {
159 .sht = &pdc_ata_sht,
160 .host_flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
161 ATA_FLAG_MMIO | ATA_FLAG_SLAVE_POSS,
162 .pio_mask = 0x1f, /* pio0-4 */
163 .mwdma_mask = 0x07, /* mwdma0-2 */
164 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
165 .port_ops = &pdc_ata_ops,
166 },
167 };
168
169 static struct pci_device_id pdc_ata_pci_tbl[] = {
170 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
171 board_2037x },
172 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
173 board_2037x },
174 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
175 board_2037x },
176 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
177 board_2037x },
178 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
179 board_2037x },
180 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
181 board_2037x },
182 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
183 board_2037x },
184
185 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
186 board_20319 },
187 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
188 board_20319 },
189 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
190 board_20319 },
191
192 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
193 board_20619 },
194
195 { } /* terminate list */
196 };
197
198
199 static struct pci_driver pdc_ata_pci_driver = {
200 .name = DRV_NAME,
201 .id_table = pdc_ata_pci_tbl,
202 .probe = pdc_ata_init_one,
203 .remove = ata_pci_remove_one,
204 };
205
206
207 static int pdc_port_start(struct ata_port *ap)
208 {
209 struct device *dev = ap->host_set->dev;
210 struct pdc_port_priv *pp;
211 int rc;
212
213 rc = ata_port_start(ap);
214 if (rc)
215 return rc;
216
217 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
218 if (!pp) {
219 rc = -ENOMEM;
220 goto err_out;
221 }
222 memset(pp, 0, sizeof(*pp));
223
224 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
225 if (!pp->pkt) {
226 rc = -ENOMEM;
227 goto err_out_kfree;
228 }
229
230 ap->private_data = pp;
231
232 return 0;
233
234 err_out_kfree:
235 kfree(pp);
236 err_out:
237 ata_port_stop(ap);
238 return rc;
239 }
240
241
242 static void pdc_port_stop(struct ata_port *ap)
243 {
244 struct device *dev = ap->host_set->dev;
245 struct pdc_port_priv *pp = ap->private_data;
246
247 ap->private_data = NULL;
248 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
249 kfree(pp);
250 ata_port_stop(ap);
251 }
252
253
254 static void pdc_reset_port(struct ata_port *ap)
255 {
256 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
257 unsigned int i;
258 u32 tmp;
259
260 for (i = 11; i > 0; i--) {
261 tmp = readl(mmio);
262 if (tmp & PDC_RESET)
263 break;
264
265 udelay(100);
266
267 tmp |= PDC_RESET;
268 writel(tmp, mmio);
269 }
270
271 tmp &= ~PDC_RESET;
272 writel(tmp, mmio);
273 readl(mmio); /* flush */
274 }
275
276 static void pdc_phy_reset(struct ata_port *ap)
277 {
278 pdc_reset_port(ap);
279 sata_phy_reset(ap);
280 }
281
282 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
283 {
284 if (sc_reg > SCR_CONTROL)
285 return 0xffffffffU;
286 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
287 }
288
289
290 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
291 u32 val)
292 {
293 if (sc_reg > SCR_CONTROL)
294 return;
295 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
296 }
297
298 static void pdc_qc_prep(struct ata_queued_cmd *qc)
299 {
300 struct pdc_port_priv *pp = qc->ap->private_data;
301 unsigned int i;
302
303 VPRINTK("ENTER\n");
304
305 switch (qc->tf.protocol) {
306 case ATA_PROT_DMA:
307 ata_qc_prep(qc);
308 /* fall through */
309
310 case ATA_PROT_NODATA:
311 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
312 qc->dev->devno, pp->pkt);
313
314 if (qc->tf.flags & ATA_TFLAG_LBA48)
315 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
316 else
317 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
318
319 pdc_pkt_footer(&qc->tf, pp->pkt, i);
320 break;
321
322 default:
323 break;
324 }
325 }
326
327 static void pdc_eng_timeout(struct ata_port *ap)
328 {
329 u8 drv_stat;
330 struct ata_queued_cmd *qc;
331
332 DPRINTK("ENTER\n");
333
334 qc = ata_qc_from_tag(ap, ap->active_tag);
335 if (!qc) {
336 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
337 ap->id);
338 goto out;
339 }
340
341 /* hack alert! We cannot use the supplied completion
342 * function from inside the ->eh_strategy_handler() thread.
343 * libata is the only user of ->eh_strategy_handler() in
344 * any kernel, so the default scsi_done() assumes it is
345 * not being called from the SCSI EH.
346 */
347 qc->scsidone = scsi_finish_command;
348
349 switch (qc->tf.protocol) {
350 case ATA_PROT_DMA:
351 case ATA_PROT_NODATA:
352 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
353 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
354 break;
355
356 default:
357 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
358
359 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
360 ap->id, qc->tf.command, drv_stat);
361
362 ata_qc_complete(qc, drv_stat);
363 break;
364 }
365
366 out:
367 DPRINTK("EXIT\n");
368 }
369
370 static inline unsigned int pdc_host_intr( struct ata_port *ap,
371 struct ata_queued_cmd *qc)
372 {
373 u8 status;
374 unsigned int handled = 0, have_err = 0;
375 u32 tmp;
376 void *mmio = (void *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
377
378 tmp = readl(mmio);
379 if (tmp & PDC_ERR_MASK) {
380 have_err = 1;
381 pdc_reset_port(ap);
382 }
383
384 switch (qc->tf.protocol) {
385 case ATA_PROT_DMA:
386 case ATA_PROT_NODATA:
387 status = ata_wait_idle(ap);
388 if (have_err)
389 status |= ATA_ERR;
390 ata_qc_complete(qc, status);
391 handled = 1;
392 break;
393
394 default:
395 ap->stats.idle_irq++;
396 break;
397 }
398
399 return handled;
400 }
401
402 static void pdc_irq_clear(struct ata_port *ap)
403 {
404 struct ata_host_set *host_set = ap->host_set;
405 void *mmio = host_set->mmio_base;
406
407 readl(mmio + PDC_INT_SEQMASK);
408 }
409
410 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
411 {
412 struct ata_host_set *host_set = dev_instance;
413 struct ata_port *ap;
414 u32 mask = 0;
415 unsigned int i, tmp;
416 unsigned int handled = 0;
417 void *mmio_base;
418
419 VPRINTK("ENTER\n");
420
421 if (!host_set || !host_set->mmio_base) {
422 VPRINTK("QUICK EXIT\n");
423 return IRQ_NONE;
424 }
425
426 mmio_base = host_set->mmio_base;
427
428 /* reading should also clear interrupts */
429 mask = readl(mmio_base + PDC_INT_SEQMASK);
430
431 if (mask == 0xffffffff) {
432 VPRINTK("QUICK EXIT 2\n");
433 return IRQ_NONE;
434 }
435 mask &= 0xffff; /* only 16 tags possible */
436 if (!mask) {
437 VPRINTK("QUICK EXIT 3\n");
438 return IRQ_NONE;
439 }
440
441 spin_lock(&host_set->lock);
442
443 writel(mask, mmio_base + PDC_INT_SEQMASK);
444
445 for (i = 0; i < host_set->n_ports; i++) {
446 VPRINTK("port %u\n", i);
447 ap = host_set->ports[i];
448 tmp = mask & (1 << (i + 1));
449 if (tmp && ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
450 struct ata_queued_cmd *qc;
451
452 qc = ata_qc_from_tag(ap, ap->active_tag);
453 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
454 handled += pdc_host_intr(ap, qc);
455 }
456 }
457
458 spin_unlock(&host_set->lock);
459
460 VPRINTK("EXIT\n");
461
462 return IRQ_RETVAL(handled);
463 }
464
465 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
466 {
467 struct ata_port *ap = qc->ap;
468 struct pdc_port_priv *pp = ap->private_data;
469 unsigned int port_no = ap->port_no;
470 u8 seq = (u8) (port_no + 1);
471
472 VPRINTK("ENTER, ap %p\n", ap);
473
474 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
475 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
476
477 pp->pkt[2] = seq;
478 wmb(); /* flush PRD, pkt writes */
479 writel(pp->pkt_dma, (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
480 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
481 }
482
483 static int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
484 {
485 switch (qc->tf.protocol) {
486 case ATA_PROT_DMA:
487 case ATA_PROT_NODATA:
488 pdc_packet_start(qc);
489 return 0;
490
491 case ATA_PROT_ATAPI_DMA:
492 BUG();
493 break;
494
495 default:
496 break;
497 }
498
499 return ata_qc_issue_prot(qc);
500 }
501
502 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
503 {
504 WARN_ON (tf->protocol == ATA_PROT_DMA ||
505 tf->protocol == ATA_PROT_NODATA);
506 ata_tf_load(ap, tf);
507 }
508
509
510 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
511 {
512 WARN_ON (tf->protocol == ATA_PROT_DMA ||
513 tf->protocol == ATA_PROT_NODATA);
514 ata_exec_command(ap, tf);
515 }
516
517
518 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
519 {
520 port->cmd_addr = base;
521 port->data_addr = base;
522 port->feature_addr =
523 port->error_addr = base + 0x4;
524 port->nsect_addr = base + 0x8;
525 port->lbal_addr = base + 0xc;
526 port->lbam_addr = base + 0x10;
527 port->lbah_addr = base + 0x14;
528 port->device_addr = base + 0x18;
529 port->command_addr =
530 port->status_addr = base + 0x1c;
531 port->altstatus_addr =
532 port->ctl_addr = base + 0x38;
533 }
534
535
536 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
537 {
538 void *mmio = pe->mmio_base;
539 u32 tmp;
540
541 /*
542 * Except for the hotplug stuff, this is voodoo from the
543 * Promise driver. Label this entire section
544 * "TODO: figure out why we do this"
545 */
546
547 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
548 tmp = readl(mmio + PDC_FLASH_CTL);
549 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
550 writel(tmp, mmio + PDC_FLASH_CTL);
551
552 /* clear plug/unplug flags for all ports */
553 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
554 writel(tmp | 0xff, mmio + PDC_SATA_PLUG_CSR);
555
556 /* mask plug/unplug ints */
557 tmp = readl(mmio + PDC_SATA_PLUG_CSR);
558 writel(tmp | 0xff0000, mmio + PDC_SATA_PLUG_CSR);
559
560 /* reduce TBG clock to 133 Mhz. */
561 tmp = readl(mmio + PDC_TBG_MODE);
562 tmp &= ~0x30000; /* clear bit 17, 16*/
563 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
564 writel(tmp, mmio + PDC_TBG_MODE);
565
566 readl(mmio + PDC_TBG_MODE); /* flush */
567 msleep(10);
568
569 /* adjust slew rate control register. */
570 tmp = readl(mmio + PDC_SLEW_CTL);
571 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
572 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
573 writel(tmp, mmio + PDC_SLEW_CTL);
574 }
575
576 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
577 {
578 static int printed_version;
579 struct ata_probe_ent *probe_ent = NULL;
580 unsigned long base;
581 void *mmio_base;
582 unsigned int board_idx = (unsigned int) ent->driver_data;
583 int pci_dev_busy = 0;
584 int rc;
585
586 if (!printed_version++)
587 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
588
589 /*
590 * If this driver happens to only be useful on Apple's K2, then
591 * we should check that here as it has a normal Serverworks ID
592 */
593 rc = pci_enable_device(pdev);
594 if (rc)
595 return rc;
596
597 rc = pci_request_regions(pdev, DRV_NAME);
598 if (rc) {
599 pci_dev_busy = 1;
600 goto err_out;
601 }
602
603 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
604 if (rc)
605 goto err_out_regions;
606 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
607 if (rc)
608 goto err_out_regions;
609
610 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
611 if (probe_ent == NULL) {
612 rc = -ENOMEM;
613 goto err_out_regions;
614 }
615
616 memset(probe_ent, 0, sizeof(*probe_ent));
617 probe_ent->dev = pci_dev_to_dev(pdev);
618 INIT_LIST_HEAD(&probe_ent->node);
619
620 mmio_base = ioremap(pci_resource_start(pdev, 3),
621 pci_resource_len(pdev, 3));
622 if (mmio_base == NULL) {
623 rc = -ENOMEM;
624 goto err_out_free_ent;
625 }
626 base = (unsigned long) mmio_base;
627
628 probe_ent->sht = pdc_port_info[board_idx].sht;
629 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
630 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
631 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
632 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
633 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
634
635 probe_ent->irq = pdev->irq;
636 probe_ent->irq_flags = SA_SHIRQ;
637 probe_ent->mmio_base = mmio_base;
638
639 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
640 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
641
642 probe_ent->port[0].scr_addr = base + 0x400;
643 probe_ent->port[1].scr_addr = base + 0x500;
644
645 /* notice 4-port boards */
646 switch (board_idx) {
647 case board_20319:
648 probe_ent->n_ports = 4;
649
650 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
651 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
652
653 probe_ent->port[2].scr_addr = base + 0x600;
654 probe_ent->port[3].scr_addr = base + 0x700;
655 break;
656 case board_2037x:
657 probe_ent->n_ports = 2;
658 break;
659 case board_20619:
660 probe_ent->n_ports = 4;
661
662 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
663 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
664
665 probe_ent->port[2].scr_addr = base + 0x600;
666 probe_ent->port[3].scr_addr = base + 0x700;
667 break;
668 default:
669 BUG();
670 break;
671 }
672
673 pci_set_master(pdev);
674
675 /* initialize adapter */
676 pdc_host_init(board_idx, probe_ent);
677
678 /* FIXME: check ata_device_add return value */
679 ata_device_add(probe_ent);
680 kfree(probe_ent);
681
682 return 0;
683
684 err_out_free_ent:
685 kfree(probe_ent);
686 err_out_regions:
687 pci_release_regions(pdev);
688 err_out:
689 if (!pci_dev_busy)
690 pci_disable_device(pdev);
691 return rc;
692 }
693
694
695 static int __init pdc_ata_init(void)
696 {
697 return pci_module_init(&pdc_ata_pci_driver);
698 }
699
700
701 static void __exit pdc_ata_exit(void)
702 {
703 pci_unregister_driver(&pdc_ata_pci_driver);
704 }
705
706
707 MODULE_AUTHOR("Jeff Garzik");
708 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
709 MODULE_LICENSE("GPL");
710 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
711 MODULE_VERSION(DRV_VERSION);
712
713 module_init(pdc_ata_init);
714 module_exit(pdc_ata_exit);
Linux kernel - Deliverables
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