2 * sata_sil.c - Silicon Image SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2005 Red Hat, Inc.
9 * Copyright 2003 Benjamin Herrenschmidt
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
35 #include <linux/init.h>
36 #include <linux/blkdev.h>
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
40 #include <scsi/scsi_host.h>
41 #include <linux/libata.h>
43 #define DRV_NAME "sata_sil"
44 #define DRV_VERSION "0.9"
60 SIL_MASK_IDE0_INT
= (1 << 22),
61 SIL_MASK_IDE1_INT
= (1 << 23),
62 SIL_MASK_IDE2_INT
= (1 << 24),
63 SIL_MASK_IDE3_INT
= (1 << 25),
64 SIL_MASK_2PORT
= SIL_MASK_IDE0_INT
| SIL_MASK_IDE1_INT
,
65 SIL_MASK_4PORT
= SIL_MASK_2PORT
|
66 SIL_MASK_IDE2_INT
| SIL_MASK_IDE3_INT
,
68 SIL_IDE2_BMDMA
= 0x200,
70 SIL_INTR_STEERING
= (1 << 1),
71 SIL_QUIRK_MOD15WRITE
= (1 << 0),
72 SIL_QUIRK_UDMA5MAX
= (1 << 1),
75 static int sil_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
76 static void sil_dev_config(struct ata_port
*ap
, struct ata_device
*dev
);
77 static u32
sil_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
78 static void sil_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
79 static void sil_post_set_mode (struct ata_port
*ap
);
81 static struct pci_device_id sil_pci_tbl
[] = {
82 { 0x1095, 0x3112, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112
},
83 { 0x1095, 0x0240, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112
},
84 { 0x1095, 0x3512, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112
},
85 { 0x1095, 0x3114, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3114
},
86 { 0x1002, 0x436e, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112
},
87 { 0x1002, 0x4379, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112
},
88 { 0x1002, 0x437a, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, sil_3112
},
89 { } /* terminate list */
93 /* TODO firmware versions should be added - eric */
94 static const struct sil_drivelist
{
97 } sil_blacklist
[] = {
98 { "ST320012AS", SIL_QUIRK_MOD15WRITE
},
99 { "ST330013AS", SIL_QUIRK_MOD15WRITE
},
100 { "ST340017AS", SIL_QUIRK_MOD15WRITE
},
101 { "ST360015AS", SIL_QUIRK_MOD15WRITE
},
102 { "ST380013AS", SIL_QUIRK_MOD15WRITE
},
103 { "ST380023AS", SIL_QUIRK_MOD15WRITE
},
104 { "ST3120023AS", SIL_QUIRK_MOD15WRITE
},
105 { "ST3160023AS", SIL_QUIRK_MOD15WRITE
},
106 { "ST3120026AS", SIL_QUIRK_MOD15WRITE
},
107 { "ST3200822AS", SIL_QUIRK_MOD15WRITE
},
108 { "ST340014ASL", SIL_QUIRK_MOD15WRITE
},
109 { "ST360014ASL", SIL_QUIRK_MOD15WRITE
},
110 { "ST380011ASL", SIL_QUIRK_MOD15WRITE
},
111 { "ST3120022ASL", SIL_QUIRK_MOD15WRITE
},
112 { "ST3160021ASL", SIL_QUIRK_MOD15WRITE
},
113 { "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX
},
117 static struct pci_driver sil_pci_driver
= {
119 .id_table
= sil_pci_tbl
,
120 .probe
= sil_init_one
,
121 .remove
= ata_pci_remove_one
,
124 static Scsi_Host_Template sil_sht
= {
125 .module
= THIS_MODULE
,
127 .ioctl
= ata_scsi_ioctl
,
128 .queuecommand
= ata_scsi_queuecmd
,
129 .eh_strategy_handler
= ata_scsi_error
,
130 .can_queue
= ATA_DEF_QUEUE
,
131 .this_id
= ATA_SHT_THIS_ID
,
132 .sg_tablesize
= LIBATA_MAX_PRD
,
133 .max_sectors
= ATA_MAX_SECTORS
,
134 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
135 .emulated
= ATA_SHT_EMULATED
,
136 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
137 .proc_name
= DRV_NAME
,
138 .dma_boundary
= ATA_DMA_BOUNDARY
,
139 .slave_configure
= ata_scsi_slave_config
,
140 .bios_param
= ata_std_bios_param
,
144 static struct ata_port_operations sil_ops
= {
145 .port_disable
= ata_port_disable
,
146 .dev_config
= sil_dev_config
,
147 .tf_load
= ata_tf_load
,
148 .tf_read
= ata_tf_read
,
149 .check_status
= ata_check_status
,
150 .exec_command
= ata_exec_command
,
151 .dev_select
= ata_std_dev_select
,
152 .phy_reset
= sata_phy_reset
,
153 .post_set_mode
= sil_post_set_mode
,
154 .bmdma_setup
= ata_bmdma_setup
,
155 .bmdma_start
= ata_bmdma_start
,
156 .bmdma_stop
= ata_bmdma_stop
,
157 .bmdma_status
= ata_bmdma_status
,
158 .qc_prep
= ata_qc_prep
,
159 .qc_issue
= ata_qc_issue_prot
,
160 .eng_timeout
= ata_eng_timeout
,
161 .irq_handler
= ata_interrupt
,
162 .irq_clear
= ata_bmdma_irq_clear
,
163 .scr_read
= sil_scr_read
,
164 .scr_write
= sil_scr_write
,
165 .port_start
= ata_port_start
,
166 .port_stop
= ata_port_stop
,
167 .host_stop
= ata_host_stop
,
170 static struct ata_port_info sil_port_info
[] = {
174 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
175 ATA_FLAG_SRST
| ATA_FLAG_MMIO
,
176 .pio_mask
= 0x1f, /* pio0-4 */
177 .mwdma_mask
= 0x07, /* mwdma0-2 */
178 .udma_mask
= 0x3f, /* udma0-5 */
179 .port_ops
= &sil_ops
,
183 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
184 ATA_FLAG_SRST
| ATA_FLAG_MMIO
,
185 .pio_mask
= 0x1f, /* pio0-4 */
186 .mwdma_mask
= 0x07, /* mwdma0-2 */
187 .udma_mask
= 0x3f, /* udma0-5 */
188 .port_ops
= &sil_ops
,
192 /* per-port register offsets */
193 /* TODO: we can probably calculate rather than use a table */
194 static const struct {
195 unsigned long tf
; /* ATA taskfile register block */
196 unsigned long ctl
; /* ATA control/altstatus register block */
197 unsigned long bmdma
; /* DMA register block */
198 unsigned long scr
; /* SATA control register block */
199 unsigned long sien
; /* SATA Interrupt Enable register */
200 unsigned long xfer_mode
;/* data transfer mode register */
203 { 0x80, 0x8A, 0x00, 0x100, 0x148, 0xb4 },
204 { 0xC0, 0xCA, 0x08, 0x180, 0x1c8, 0xf4 },
205 { 0x280, 0x28A, 0x200, 0x300, 0x348, 0x2b4 },
206 { 0x2C0, 0x2CA, 0x208, 0x380, 0x3c8, 0x2f4 },
210 MODULE_AUTHOR("Jeff Garzik");
211 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
212 MODULE_LICENSE("GPL");
213 MODULE_DEVICE_TABLE(pci
, sil_pci_tbl
);
214 MODULE_VERSION(DRV_VERSION
);
216 static unsigned char sil_get_device_cache_line(struct pci_dev
*pdev
)
219 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &cache_line
);
223 static void sil_post_set_mode (struct ata_port
*ap
)
225 struct ata_host_set
*host_set
= ap
->host_set
;
226 struct ata_device
*dev
;
227 void *addr
= host_set
->mmio_base
+ sil_port
[ap
->port_no
].xfer_mode
;
228 u32 tmp
, dev_mode
[2];
231 for (i
= 0; i
< 2; i
++) {
232 dev
= &ap
->device
[i
];
233 if (!ata_dev_present(dev
))
234 dev_mode
[i
] = 0; /* PIO0/1/2 */
235 else if (dev
->flags
& ATA_DFLAG_PIO
)
236 dev_mode
[i
] = 1; /* PIO3/4 */
238 dev_mode
[i
] = 3; /* UDMA */
239 /* value 2 indicates MDMA */
243 tmp
&= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
245 tmp
|= (dev_mode
[1] << 4);
247 readl(addr
); /* flush */
250 static inline unsigned long sil_scr_addr(struct ata_port
*ap
, unsigned int sc_reg
)
252 unsigned long offset
= ap
->ioaddr
.scr_addr
;
269 static u32
sil_scr_read (struct ata_port
*ap
, unsigned int sc_reg
)
271 void *mmio
= (void *) sil_scr_addr(ap
, sc_reg
);
277 static void sil_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
)
279 void *mmio
= (void *) sil_scr_addr(ap
, sc_reg
);
285 * sil_dev_config - Apply device/host-specific errata fixups
286 * @ap: Port containing device to be examined
287 * @dev: Device to be examined
289 * After the IDENTIFY [PACKET] DEVICE step is complete, and a
290 * device is known to be present, this function is called.
291 * We apply two errata fixups which are specific to Silicon Image,
292 * a Seagate and a Maxtor fixup.
294 * For certain Seagate devices, we must limit the maximum sectors
297 * For certain Maxtor devices, we must not program the drive
300 * Both fixups are unfairly pessimistic. As soon as I get more
301 * information on these errata, I will create a more exhaustive
302 * list, and apply the fixups to only the specific
303 * devices/hosts/firmwares that need it.
305 * 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
306 * The Maxtor quirk is in the blacklist, but I'm keeping the original
307 * pessimistic fix for the following reasons...
308 * - There seems to be less info on it, only one device gleaned off the
309 * Windows driver, maybe only one is affected. More info would be greatly
311 * - But then again UDMA5 is hardly anything to complain about
313 static void sil_dev_config(struct ata_port
*ap
, struct ata_device
*dev
)
315 unsigned int n
, quirks
= 0;
316 unsigned char model_num
[40];
320 ata_dev_id_string(dev
->id
, model_num
, ATA_ID_PROD_OFS
,
323 len
= strnlen(s
, sizeof(model_num
));
325 /* ATAPI specifies that empty space is blank-filled; remove blanks */
326 while ((len
> 0) && (s
[len
- 1] == ' '))
329 for (n
= 0; sil_blacklist
[n
].product
; n
++)
330 if (!memcmp(sil_blacklist
[n
].product
, s
,
331 strlen(sil_blacklist
[n
].product
))) {
332 quirks
= sil_blacklist
[n
].quirk
;
336 /* limit requests to 15 sectors */
337 if (quirks
& SIL_QUIRK_MOD15WRITE
) {
338 printk(KERN_INFO
"ata%u(%u): applying Seagate errata fix\n",
340 ap
->host
->max_sectors
= 15;
341 ap
->host
->hostt
->max_sectors
= 15;
342 dev
->flags
|= ATA_DFLAG_LOCK_SECTORS
;
347 if (quirks
& SIL_QUIRK_UDMA5MAX
) {
348 printk(KERN_INFO
"ata%u(%u): applying Maxtor errata fix %s\n",
349 ap
->id
, dev
->devno
, s
);
350 ap
->udma_mask
&= ATA_UDMA5
;
355 static int sil_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
357 static int printed_version
;
358 struct ata_probe_ent
*probe_ent
= NULL
;
363 int pci_dev_busy
= 0;
367 if (!printed_version
++)
368 printk(KERN_DEBUG DRV_NAME
" version " DRV_VERSION
"\n");
371 * If this driver happens to only be useful on Apple's K2, then
372 * we should check that here as it has a normal Serverworks ID
374 rc
= pci_enable_device(pdev
);
378 rc
= pci_request_regions(pdev
, DRV_NAME
);
384 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
386 goto err_out_regions
;
387 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
389 goto err_out_regions
;
391 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
392 if (probe_ent
== NULL
) {
394 goto err_out_regions
;
397 memset(probe_ent
, 0, sizeof(*probe_ent
));
398 INIT_LIST_HEAD(&probe_ent
->node
);
399 probe_ent
->dev
= pci_dev_to_dev(pdev
);
400 probe_ent
->port_ops
= sil_port_info
[ent
->driver_data
].port_ops
;
401 probe_ent
->sht
= sil_port_info
[ent
->driver_data
].sht
;
402 probe_ent
->n_ports
= (ent
->driver_data
== sil_3114
) ? 4 : 2;
403 probe_ent
->pio_mask
= sil_port_info
[ent
->driver_data
].pio_mask
;
404 probe_ent
->mwdma_mask
= sil_port_info
[ent
->driver_data
].mwdma_mask
;
405 probe_ent
->udma_mask
= sil_port_info
[ent
->driver_data
].udma_mask
;
406 probe_ent
->irq
= pdev
->irq
;
407 probe_ent
->irq_flags
= SA_SHIRQ
;
408 probe_ent
->host_flags
= sil_port_info
[ent
->driver_data
].host_flags
;
410 mmio_base
= ioremap(pci_resource_start(pdev
, 5),
411 pci_resource_len(pdev
, 5));
412 if (mmio_base
== NULL
) {
414 goto err_out_free_ent
;
417 probe_ent
->mmio_base
= mmio_base
;
419 base
= (unsigned long) mmio_base
;
421 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
422 probe_ent
->port
[i
].cmd_addr
= base
+ sil_port
[i
].tf
;
423 probe_ent
->port
[i
].altstatus_addr
=
424 probe_ent
->port
[i
].ctl_addr
= base
+ sil_port
[i
].ctl
;
425 probe_ent
->port
[i
].bmdma_addr
= base
+ sil_port
[i
].bmdma
;
426 probe_ent
->port
[i
].scr_addr
= base
+ sil_port
[i
].scr
;
427 ata_std_ports(&probe_ent
->port
[i
]);
430 /* Initialize FIFO PCI bus arbitration */
431 cls
= sil_get_device_cache_line(pdev
);
434 cls
++; /* cls = (line_size/8)+1 */
435 writeb(cls
, mmio_base
+ SIL_FIFO_R0
);
436 writeb(cls
, mmio_base
+ SIL_FIFO_W0
);
437 writeb(cls
, mmio_base
+ SIL_FIFO_R1
);
438 writeb(cls
, mmio_base
+ SIL_FIFO_W1
);
439 if (ent
->driver_data
== sil_3114
) {
440 writeb(cls
, mmio_base
+ SIL_FIFO_R2
);
441 writeb(cls
, mmio_base
+ SIL_FIFO_W2
);
442 writeb(cls
, mmio_base
+ SIL_FIFO_R3
);
443 writeb(cls
, mmio_base
+ SIL_FIFO_W3
);
446 printk(KERN_WARNING DRV_NAME
"(%s): cache line size not set. Driver may not function\n",
449 if (ent
->driver_data
== sil_3114
) {
450 irq_mask
= SIL_MASK_4PORT
;
452 /* flip the magic "make 4 ports work" bit */
453 tmp
= readl(mmio_base
+ SIL_IDE2_BMDMA
);
454 if ((tmp
& SIL_INTR_STEERING
) == 0)
455 writel(tmp
| SIL_INTR_STEERING
,
456 mmio_base
+ SIL_IDE2_BMDMA
);
459 irq_mask
= SIL_MASK_2PORT
;
462 /* make sure IDE0/1/2/3 interrupts are not masked */
463 tmp
= readl(mmio_base
+ SIL_SYSCFG
);
464 if (tmp
& irq_mask
) {
466 writel(tmp
, mmio_base
+ SIL_SYSCFG
);
467 readl(mmio_base
+ SIL_SYSCFG
); /* flush */
470 /* mask all SATA phy-related interrupts */
471 /* TODO: unmask bit 6 (SError N bit) for hotplug */
472 for (i
= 0; i
< probe_ent
->n_ports
; i
++)
473 writel(0, mmio_base
+ sil_port
[i
].sien
);
475 pci_set_master(pdev
);
477 /* FIXME: check ata_device_add return value */
478 ata_device_add(probe_ent
);
486 pci_release_regions(pdev
);
489 pci_disable_device(pdev
);
493 static int __init
sil_init(void)
495 return pci_module_init(&sil_pci_driver
);
498 static void __exit
sil_exit(void)
500 pci_unregister_driver(&sil_pci_driver
);
504 module_init(sil_init
);
505 module_exit(sil_exit
);