drivers/scsi/sata_sil.c

   1 /*
   2  *  sata_sil.c - Silicon Image SATA
   3  *
   4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2003-2005 Red Hat, Inc.
   9  *  Copyright 2003 Benjamin Herrenschmidt
  10  *
  11  *
  12  *  This program is free software; you can redistribute it and/or modify
  13  *  it under the terms of the GNU General Public License as published by
  14  *  the Free Software Foundation; either version 2, or (at your option)
  15  *  any later version.
  16  *
  17  *  This program is distributed in the hope that it will be useful,
  18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *  GNU General Public License for more details.
  21  *
  22  *  You should have received a copy of the GNU General Public License
  23  *  along with this program; see the file COPYING.  If not, write to
  24  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  *
  27  *  libata documentation is available via 'make {ps|pdf}docs',
  28  *  as Documentation/DocBook/libata.*
  29  *
  30  *  Documentation for SiI 3112:
  31  *  http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
  32  *
  33  *  Other errata and documentation available under NDA.
  34  *
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/init.h>
  41 #include <linux/blkdev.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/device.h>
  45 #include <scsi/scsi_host.h>
  46 #include <linux/libata.h>
  47
  48 #define DRV_NAME        "sata_sil"
  49 #define DRV_VERSION     "1.0"
  50
  51 enum {
  52         /*
  53          * host flags
  54          */
  55         SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29),
  56         SIL_FLAG_MOD15WRITE     = (1 << 30),
  57         SIL_DFL_HOST_FLAGS      = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  58                                   ATA_FLAG_MMIO,
  59
  60         /*
  61          * Controller IDs
  62          */
  63         sil_3112                = 0,
  64         sil_3512                = 1,
  65         sil_3114                = 2,
  66
  67         /*
  68          * Register offsets
  69          */
  70         SIL_SYSCFG              = 0x48,
  71
  72         /*
  73          * Register bits
  74          */
  75         /* SYSCFG */
  76         SIL_MASK_IDE0_INT       = (1 << 22),
  77         SIL_MASK_IDE1_INT       = (1 << 23),
  78         SIL_MASK_IDE2_INT       = (1 << 24),
  79         SIL_MASK_IDE3_INT       = (1 << 25),
  80         SIL_MASK_2PORT          = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT,
  81         SIL_MASK_4PORT          = SIL_MASK_2PORT |
  82                                   SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT,
  83
  84         /* BMDMA/BMDMA2 */
  85         SIL_INTR_STEERING       = (1 << 1),
  86
  87         /*
  88          * Others
  89          */
  90         SIL_QUIRK_MOD15WRITE    = (1 << 0),
  91         SIL_QUIRK_UDMA5MAX      = (1 << 1),
  92 };
  93
  94 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
  95 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev);
  96 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg);
  97 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
  98 static void sil_post_set_mode (struct ata_port *ap);
  99
 100
 101 static const struct pci_device_id sil_pci_tbl[] = {
 102         { 0x1095, 0x3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
 103         { 0x1095, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
 104         { 0x1095, 0x3512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3512 },
 105         { 0x1095, 0x3114, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3114 },
 106         { 0x1002, 0x436e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
 107         { 0x1002, 0x4379, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
 108         { 0x1002, 0x437a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sil_3112 },
 109         { }     /* terminate list */
 110 };
 111
 112
 113 /* TODO firmware versions should be added - eric */
 114 static const struct sil_drivelist {
 115         const char * product;
 116         unsigned int quirk;
 117 } sil_blacklist [] = {
 118         { "ST320012AS",         SIL_QUIRK_MOD15WRITE },
 119         { "ST330013AS",         SIL_QUIRK_MOD15WRITE },
 120         { "ST340017AS",         SIL_QUIRK_MOD15WRITE },
 121         { "ST360015AS",         SIL_QUIRK_MOD15WRITE },
 122         { "ST380013AS",         SIL_QUIRK_MOD15WRITE },
 123         { "ST380023AS",         SIL_QUIRK_MOD15WRITE },
 124         { "ST3120023AS",        SIL_QUIRK_MOD15WRITE },
 125         { "ST3160023AS",        SIL_QUIRK_MOD15WRITE },
 126         { "ST3120026AS",        SIL_QUIRK_MOD15WRITE },
 127         { "ST3200822AS",        SIL_QUIRK_MOD15WRITE },
 128         { "ST340014ASL",        SIL_QUIRK_MOD15WRITE },
 129         { "ST360014ASL",        SIL_QUIRK_MOD15WRITE },
 130         { "ST380011ASL",        SIL_QUIRK_MOD15WRITE },
 131         { "ST3120022ASL",       SIL_QUIRK_MOD15WRITE },
 132         { "ST3160021ASL",       SIL_QUIRK_MOD15WRITE },
 133         { "Maxtor 4D060H3",     SIL_QUIRK_UDMA5MAX },
 134         { }
 135 };
 136
 137 static struct pci_driver sil_pci_driver = {
 138         .name                   = DRV_NAME,
 139         .id_table               = sil_pci_tbl,
 140         .probe                  = sil_init_one,
 141         .remove                 = ata_pci_remove_one,
 142 };
 143
 144 static struct scsi_host_template sil_sht = {
 145         .module                 = THIS_MODULE,
 146         .name                   = DRV_NAME,
 147         .ioctl                  = ata_scsi_ioctl,
 148         .queuecommand           = ata_scsi_queuecmd,
 149         .can_queue              = ATA_DEF_QUEUE,
 150         .this_id                = ATA_SHT_THIS_ID,
 151         .sg_tablesize           = LIBATA_MAX_PRD,
 152         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 153         .emulated               = ATA_SHT_EMULATED,
 154         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 155         .proc_name              = DRV_NAME,
 156         .dma_boundary           = ATA_DMA_BOUNDARY,
 157         .slave_configure        = ata_scsi_slave_config,
 158         .bios_param             = ata_std_bios_param,
 159 };
 160
 161 static const struct ata_port_operations sil_ops = {
 162         .port_disable           = ata_port_disable,
 163         .dev_config             = sil_dev_config,
 164         .tf_load                = ata_tf_load,
 165         .tf_read                = ata_tf_read,
 166         .check_status           = ata_check_status,
 167         .exec_command           = ata_exec_command,
 168         .dev_select             = ata_std_dev_select,
 169         .probe_reset            = ata_std_probe_reset,
 170         .post_set_mode          = sil_post_set_mode,
 171         .bmdma_setup            = ata_bmdma_setup,
 172         .bmdma_start            = ata_bmdma_start,
 173         .bmdma_stop             = ata_bmdma_stop,
 174         .bmdma_status           = ata_bmdma_status,
 175         .qc_prep                = ata_qc_prep,
 176         .qc_issue               = ata_qc_issue_prot,
 177         .eng_timeout            = ata_eng_timeout,
 178         .irq_handler            = ata_interrupt,
 179         .irq_clear              = ata_bmdma_irq_clear,
 180         .scr_read               = sil_scr_read,
 181         .scr_write              = sil_scr_write,
 182         .port_start             = ata_port_start,
 183         .port_stop              = ata_port_stop,
 184         .host_stop              = ata_pci_host_stop,
 185 };
 186
 187 static const struct ata_port_info sil_port_info[] = {
 188         /* sil_3112 */
 189         {
 190                 .sht            = &sil_sht,
 191                 .host_flags     = SIL_DFL_HOST_FLAGS | SIL_FLAG_MOD15WRITE,
 192                 .pio_mask       = 0x1f,                 /* pio0-4 */
 193                 .mwdma_mask     = 0x07,                 /* mwdma0-2 */
 194                 .udma_mask      = 0x3f,                 /* udma0-5 */
 195                 .port_ops       = &sil_ops,
 196         },
 197         /* sil_3512 */
 198         {
 199                 .sht            = &sil_sht,
 200                 .host_flags     = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
 201                 .pio_mask       = 0x1f,                 /* pio0-4 */
 202                 .mwdma_mask     = 0x07,                 /* mwdma0-2 */
 203                 .udma_mask      = 0x3f,                 /* udma0-5 */
 204                 .port_ops       = &sil_ops,
 205         },
 206         /* sil_3114 */
 207         {
 208                 .sht            = &sil_sht,
 209                 .host_flags     = SIL_DFL_HOST_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT,
 210                 .pio_mask       = 0x1f,                 /* pio0-4 */
 211                 .mwdma_mask     = 0x07,                 /* mwdma0-2 */
 212                 .udma_mask      = 0x3f,                 /* udma0-5 */
 213                 .port_ops       = &sil_ops,
 214         },
 215 };
 216
 217 /* per-port register offsets */
 218 /* TODO: we can probably calculate rather than use a table */
 219 static const struct {
 220         unsigned long tf;       /* ATA taskfile register block */
 221         unsigned long ctl;      /* ATA control/altstatus register block */
 222         unsigned long bmdma;    /* DMA register block */
 223         unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */
 224         unsigned long scr;      /* SATA control register block */
 225         unsigned long sien;     /* SATA Interrupt Enable register */
 226         unsigned long xfer_mode;/* data transfer mode register */
 227         unsigned long sfis_cfg; /* SATA FIS reception config register */
 228 } sil_port[] = {
 229         /* port 0 ... */
 230         { 0x80, 0x8A, 0x00, 0x40, 0x100, 0x148, 0xb4, 0x14c },
 231         { 0xC0, 0xCA, 0x08, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc },
 232         { 0x280, 0x28A, 0x200, 0x240, 0x300, 0x348, 0x2b4, 0x34c },
 233         { 0x2C0, 0x2CA, 0x208, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc },
 234         /* ... port 3 */
 235 };
 236
 237 MODULE_AUTHOR("Jeff Garzik");
 238 MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller");
 239 MODULE_LICENSE("GPL");
 240 MODULE_DEVICE_TABLE(pci, sil_pci_tbl);
 241 MODULE_VERSION(DRV_VERSION);
 242
 243 static int slow_down = 0;
 244 module_param(slow_down, int, 0444);
 245 MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)");
 246
 247
 248 static unsigned char sil_get_device_cache_line(struct pci_dev *pdev)
 249 {
 250         u8 cache_line = 0;
 251         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line);
 252         return cache_line;
 253 }
 254
 255 static void sil_post_set_mode (struct ata_port *ap)
 256 {
 257         struct ata_host_set *host_set = ap->host_set;
 258         struct ata_device *dev;
 259         void __iomem *addr =
 260                 host_set->mmio_base + sil_port[ap->port_no].xfer_mode;
 261         u32 tmp, dev_mode[2];
 262         unsigned int i;
 263
 264         for (i = 0; i < 2; i++) {
 265                 dev = &ap->device[i];
 266                 if (!ata_dev_enabled(dev))
 267                         dev_mode[i] = 0;        /* PIO0/1/2 */
 268                 else if (dev->flags & ATA_DFLAG_PIO)
 269                         dev_mode[i] = 1;        /* PIO3/4 */
 270                 else
 271                         dev_mode[i] = 3;        /* UDMA */
 272                 /* value 2 indicates MDMA */
 273         }
 274
 275         tmp = readl(addr);
 276         tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0));
 277         tmp |= dev_mode[0];
 278         tmp |= (dev_mode[1] << 4);
 279         writel(tmp, addr);
 280         readl(addr);    /* flush */
 281 }
 282
 283 static inline unsigned long sil_scr_addr(struct ata_port *ap, unsigned int sc_reg)
 284 {
 285         unsigned long offset = ap->ioaddr.scr_addr;
 286
 287         switch (sc_reg) {
 288         case SCR_STATUS:
 289                 return offset + 4;
 290         case SCR_ERROR:
 291                 return offset + 8;
 292         case SCR_CONTROL:
 293                 return offset;
 294         default:
 295                 /* do nothing */
 296                 break;
 297         }
 298
 299         return 0;
 300 }
 301
 302 static u32 sil_scr_read (struct ata_port *ap, unsigned int sc_reg)
 303 {
 304         void __iomem *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
 305         if (mmio)
 306                 return readl(mmio);
 307         return 0xffffffffU;
 308 }
 309
 310 static void sil_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
 311 {
 312         void *mmio = (void __iomem *) sil_scr_addr(ap, sc_reg);
 313         if (mmio)
 314                 writel(val, mmio);
 315 }
 316
 317 /**
 318  *      sil_dev_config - Apply device/host-specific errata fixups
 319  *      @ap: Port containing device to be examined
 320  *      @dev: Device to be examined
 321  *
 322  *      After the IDENTIFY [PACKET] DEVICE step is complete, and a
 323  *      device is known to be present, this function is called.
 324  *      We apply two errata fixups which are specific to Silicon Image,
 325  *      a Seagate and a Maxtor fixup.
 326  *
 327  *      For certain Seagate devices, we must limit the maximum sectors
 328  *      to under 8K.
 329  *
 330  *      For certain Maxtor devices, we must not program the drive
 331  *      beyond udma5.
 332  *
 333  *      Both fixups are unfairly pessimistic.  As soon as I get more
 334  *      information on these errata, I will create a more exhaustive
 335  *      list, and apply the fixups to only the specific
 336  *      devices/hosts/firmwares that need it.
 337  *
 338  *      20040111 - Seagate drives affected by the Mod15Write bug are blacklisted
 339  *      The Maxtor quirk is in the blacklist, but I'm keeping the original
 340  *      pessimistic fix for the following reasons...
 341  *      - There seems to be less info on it, only one device gleaned off the
 342  *      Windows driver, maybe only one is affected.  More info would be greatly
 343  *      appreciated.
 344  *      - But then again UDMA5 is hardly anything to complain about
 345  */
 346 static void sil_dev_config(struct ata_port *ap, struct ata_device *dev)
 347 {
 348         unsigned int n, quirks = 0;
 349         unsigned char model_num[41];
 350
 351         ata_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
 352
 353         for (n = 0; sil_blacklist[n].product; n++)
 354                 if (!strcmp(sil_blacklist[n].product, model_num)) {
 355                         quirks = sil_blacklist[n].quirk;
 356                         break;
 357                 }
 358
 359         /* limit requests to 15 sectors */
 360         if (slow_down ||
 361             ((ap->flags & SIL_FLAG_MOD15WRITE) &&
 362              (quirks & SIL_QUIRK_MOD15WRITE))) {
 363                 printk(KERN_INFO "ata%u(%u): applying Seagate errata fix (mod15write workaround)\n",
 364                        ap->id, dev->devno);
 365                 dev->max_sectors = 15;
 366                 return;
 367         }
 368
 369         /* limit to udma5 */
 370         if (quirks & SIL_QUIRK_UDMA5MAX) {
 371                 printk(KERN_INFO "ata%u(%u): applying Maxtor errata fix %s\n",
 372                        ap->id, dev->devno, model_num);
 373                 dev->udma_mask &= ATA_UDMA5;
 374                 return;
 375         }
 376 }
 377
 378 static int sil_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 379 {
 380         static int printed_version;
 381         struct ata_probe_ent *probe_ent = NULL;
 382         unsigned long base;
 383         void __iomem *mmio_base;
 384         int rc;
 385         unsigned int i;
 386         int pci_dev_busy = 0;
 387         u32 tmp, irq_mask;
 388         u8 cls;
 389
 390         if (!printed_version++)
 391                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
 392
 393         rc = pci_enable_device(pdev);
 394         if (rc)
 395                 return rc;
 396
 397         rc = pci_request_regions(pdev, DRV_NAME);
 398         if (rc) {
 399                 pci_dev_busy = 1;
 400                 goto err_out;
 401         }
 402
 403         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
 404         if (rc)
 405                 goto err_out_regions;
 406         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
 407         if (rc)
 408                 goto err_out_regions;
 409
 410         probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
 411         if (probe_ent == NULL) {
 412                 rc = -ENOMEM;
 413                 goto err_out_regions;
 414         }
 415
 416         INIT_LIST_HEAD(&probe_ent->node);
 417         probe_ent->dev = pci_dev_to_dev(pdev);
 418         probe_ent->port_ops = sil_port_info[ent->driver_data].port_ops;
 419         probe_ent->sht = sil_port_info[ent->driver_data].sht;
 420         probe_ent->n_ports = (ent->driver_data == sil_3114) ? 4 : 2;
 421         probe_ent->pio_mask = sil_port_info[ent->driver_data].pio_mask;
 422         probe_ent->mwdma_mask = sil_port_info[ent->driver_data].mwdma_mask;
 423         probe_ent->udma_mask = sil_port_info[ent->driver_data].udma_mask;
 424         probe_ent->irq = pdev->irq;
 425         probe_ent->irq_flags = SA_SHIRQ;
 426         probe_ent->host_flags = sil_port_info[ent->driver_data].host_flags;
 427
 428         mmio_base = pci_iomap(pdev, 5, 0);
 429         if (mmio_base == NULL) {
 430                 rc = -ENOMEM;
 431                 goto err_out_free_ent;
 432         }
 433
 434         probe_ent->mmio_base = mmio_base;
 435
 436         base = (unsigned long) mmio_base;
 437
 438         for (i = 0; i < probe_ent->n_ports; i++) {
 439                 probe_ent->port[i].cmd_addr = base + sil_port[i].tf;
 440                 probe_ent->port[i].altstatus_addr =
 441                 probe_ent->port[i].ctl_addr = base + sil_port[i].ctl;
 442                 probe_ent->port[i].bmdma_addr = base + sil_port[i].bmdma;
 443                 probe_ent->port[i].scr_addr = base + sil_port[i].scr;
 444                 ata_std_ports(&probe_ent->port[i]);
 445         }
 446
 447         /* Initialize FIFO PCI bus arbitration */
 448         cls = sil_get_device_cache_line(pdev);
 449         if (cls) {
 450                 cls >>= 3;
 451                 cls++;  /* cls = (line_size/8)+1 */
 452                 for (i = 0; i < probe_ent->n_ports; i++)
 453                         writew(cls << 8 | cls,
 454                                mmio_base + sil_port[i].fifo_cfg);
 455         } else
 456                 dev_printk(KERN_WARNING, &pdev->dev,
 457                            "cache line size not set.  Driver may not function\n");
 458
 459         /* Apply R_ERR on DMA activate FIS errata workaround */
 460         if (probe_ent->host_flags & SIL_FLAG_RERR_ON_DMA_ACT) {
 461                 int cnt;
 462
 463                 for (i = 0, cnt = 0; i < probe_ent->n_ports; i++) {
 464                         tmp = readl(mmio_base + sil_port[i].sfis_cfg);
 465                         if ((tmp & 0x3) != 0x01)
 466                                 continue;
 467                         if (!cnt)
 468                                 dev_printk(KERN_INFO, &pdev->dev,
 469                                            "Applying R_ERR on DMA activate "
 470                                            "FIS errata fix\n");
 471                         writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg);
 472                         cnt++;
 473                 }
 474         }
 475
 476         if (ent->driver_data == sil_3114) {
 477                 irq_mask = SIL_MASK_4PORT;
 478
 479                 /* flip the magic "make 4 ports work" bit */
 480                 tmp = readl(mmio_base + sil_port[2].bmdma);
 481                 if ((tmp & SIL_INTR_STEERING) == 0)
 482                         writel(tmp | SIL_INTR_STEERING,
 483                                mmio_base + sil_port[2].bmdma);
 484
 485         } else {
 486                 irq_mask = SIL_MASK_2PORT;
 487         }
 488
 489         /* make sure IDE0/1/2/3 interrupts are not masked */
 490         tmp = readl(mmio_base + SIL_SYSCFG);
 491         if (tmp & irq_mask) {
 492                 tmp &= ~irq_mask;
 493                 writel(tmp, mmio_base + SIL_SYSCFG);
 494                 readl(mmio_base + SIL_SYSCFG);  /* flush */
 495         }
 496
 497         /* mask all SATA phy-related interrupts */
 498         /* TODO: unmask bit 6 (SError N bit) for hotplug */
 499         for (i = 0; i < probe_ent->n_ports; i++)
 500                 writel(0, mmio_base + sil_port[i].sien);
 501
 502         pci_set_master(pdev);
 503
 504         /* FIXME: check ata_device_add return value */
 505         ata_device_add(probe_ent);
 506         kfree(probe_ent);
 507
 508         return 0;
 509
 510 err_out_free_ent:
 511         kfree(probe_ent);
 512 err_out_regions:
 513         pci_release_regions(pdev);
 514 err_out:
 515         if (!pci_dev_busy)
 516                 pci_disable_device(pdev);
 517         return rc;
 518 }
 519
 520 static int __init sil_init(void)
 521 {
 522         return pci_module_init(&sil_pci_driver);
 523 }
 524
 525 static void __exit sil_exit(void)
 526 {
 527         pci_unregister_driver(&sil_pci_driver);
 528 }
 529
 530
 531 module_init(sil_init);
 532 module_exit(sil_exit);