2 * sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
4 * Maintained by: Jeremy Higdon @ SGI
5 * Please ALWAYS copy linux-ide@vger.kernel.org
10 * Bits from Jeff Garzik, Copyright RedHat, Inc.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; see the file COPYING. If not, write to
25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
28 * libata documentation is available via 'make {ps|pdf}docs',
29 * as Documentation/DocBook/libata.*
31 * Vitesse hardware documentation presumably available under NDA.
32 * Intel 31244 (same hardware interface) documentation presumably
33 * available from http://developer.intel.com/
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/device.h>
46 #include <scsi/scsi_host.h>
47 #include <linux/libata.h>
49 #define DRV_NAME "sata_vsc"
50 #define DRV_VERSION "1.1"
52 /* Interrupt register offsets (from chip base address) */
53 #define VSC_SATA_INT_STAT_OFFSET 0x00
54 #define VSC_SATA_INT_MASK_OFFSET 0x04
56 /* Taskfile registers offsets */
57 #define VSC_SATA_TF_CMD_OFFSET 0x00
58 #define VSC_SATA_TF_DATA_OFFSET 0x00
59 #define VSC_SATA_TF_ERROR_OFFSET 0x04
60 #define VSC_SATA_TF_FEATURE_OFFSET 0x06
61 #define VSC_SATA_TF_NSECT_OFFSET 0x08
62 #define VSC_SATA_TF_LBAL_OFFSET 0x0c
63 #define VSC_SATA_TF_LBAM_OFFSET 0x10
64 #define VSC_SATA_TF_LBAH_OFFSET 0x14
65 #define VSC_SATA_TF_DEVICE_OFFSET 0x18
66 #define VSC_SATA_TF_STATUS_OFFSET 0x1c
67 #define VSC_SATA_TF_COMMAND_OFFSET 0x1d
68 #define VSC_SATA_TF_ALTSTATUS_OFFSET 0x28
69 #define VSC_SATA_TF_CTL_OFFSET 0x29
72 #define VSC_SATA_UP_DESCRIPTOR_OFFSET 0x64
73 #define VSC_SATA_UP_DATA_BUFFER_OFFSET 0x6C
74 #define VSC_SATA_DMA_CMD_OFFSET 0x70
77 #define VSC_SATA_SCR_STATUS_OFFSET 0x100
78 #define VSC_SATA_SCR_ERROR_OFFSET 0x104
79 #define VSC_SATA_SCR_CONTROL_OFFSET 0x108
82 #define VSC_SATA_PORT_OFFSET 0x200
84 /* Error interrupt status bit offsets */
85 #define VSC_SATA_INT_ERROR_E_OFFSET 2
86 #define VSC_SATA_INT_ERROR_P_OFFSET 4
87 #define VSC_SATA_INT_ERROR_T_OFFSET 5
88 #define VSC_SATA_INT_ERROR_M_OFFSET 1
89 #define is_vsc_sata_int_err(port_idx, int_status) \
90 (int_status & ((1 << (VSC_SATA_INT_ERROR_E_OFFSET + (8 * port_idx))) | \
91 (1 << (VSC_SATA_INT_ERROR_P_OFFSET + (8 * port_idx))) | \
92 (1 << (VSC_SATA_INT_ERROR_T_OFFSET + (8 * port_idx))) | \
93 (1 << (VSC_SATA_INT_ERROR_M_OFFSET + (8 * port_idx))) \
98 static u32
vsc_sata_scr_read (struct ata_port
*ap
, unsigned int sc_reg
)
100 if (sc_reg
> SCR_CONTROL
)
102 return readl((void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
106 static void vsc_sata_scr_write (struct ata_port
*ap
, unsigned int sc_reg
,
109 if (sc_reg
> SCR_CONTROL
)
111 writel(val
, (void __iomem
*) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
115 static void vsc_intr_mask_update(struct ata_port
*ap
, u8 ctl
)
117 void __iomem
*mask_addr
;
120 mask_addr
= ap
->host_set
->mmio_base
+
121 VSC_SATA_INT_MASK_OFFSET
+ ap
->port_no
;
122 mask
= readb(mask_addr
);
127 writeb(mask
, mask_addr
);
131 static void vsc_sata_tf_load(struct ata_port
*ap
, const struct ata_taskfile
*tf
)
133 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
134 unsigned int is_addr
= tf
->flags
& ATA_TFLAG_ISADDR
;
137 * The only thing the ctl register is used for is SRST.
138 * That is not enabled or disabled via tf_load.
139 * However, if ATA_NIEN is changed, then we need to change the interrupt register.
141 if ((tf
->ctl
& ATA_NIEN
) != (ap
->last_ctl
& ATA_NIEN
)) {
142 ap
->last_ctl
= tf
->ctl
;
143 vsc_intr_mask_update(ap
, tf
->ctl
& ATA_NIEN
);
145 if (is_addr
&& (tf
->flags
& ATA_TFLAG_LBA48
)) {
146 writew(tf
->feature
| (((u16
)tf
->hob_feature
) << 8), ioaddr
->feature_addr
);
147 writew(tf
->nsect
| (((u16
)tf
->hob_nsect
) << 8), ioaddr
->nsect_addr
);
148 writew(tf
->lbal
| (((u16
)tf
->hob_lbal
) << 8), ioaddr
->lbal_addr
);
149 writew(tf
->lbam
| (((u16
)tf
->hob_lbam
) << 8), ioaddr
->lbam_addr
);
150 writew(tf
->lbah
| (((u16
)tf
->hob_lbah
) << 8), ioaddr
->lbah_addr
);
151 } else if (is_addr
) {
152 writew(tf
->feature
, ioaddr
->feature_addr
);
153 writew(tf
->nsect
, ioaddr
->nsect_addr
);
154 writew(tf
->lbal
, ioaddr
->lbal_addr
);
155 writew(tf
->lbam
, ioaddr
->lbam_addr
);
156 writew(tf
->lbah
, ioaddr
->lbah_addr
);
159 if (tf
->flags
& ATA_TFLAG_DEVICE
)
160 writeb(tf
->device
, ioaddr
->device_addr
);
166 static void vsc_sata_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
168 struct ata_ioports
*ioaddr
= &ap
->ioaddr
;
169 u16 nsect
, lbal
, lbam
, lbah
, feature
;
171 tf
->command
= ata_check_status(ap
);
172 tf
->device
= readw(ioaddr
->device_addr
);
173 feature
= readw(ioaddr
->error_addr
);
174 nsect
= readw(ioaddr
->nsect_addr
);
175 lbal
= readw(ioaddr
->lbal_addr
);
176 lbam
= readw(ioaddr
->lbam_addr
);
177 lbah
= readw(ioaddr
->lbah_addr
);
179 tf
->feature
= feature
;
185 if (tf
->flags
& ATA_TFLAG_LBA48
) {
186 tf
->hob_feature
= feature
>> 8;
187 tf
->hob_nsect
= nsect
>> 8;
188 tf
->hob_lbal
= lbal
>> 8;
189 tf
->hob_lbam
= lbam
>> 8;
190 tf
->hob_lbah
= lbah
>> 8;
198 * Read the interrupt register and process for the devices that have them pending.
200 static irqreturn_t
vsc_sata_interrupt (int irq
, void *dev_instance
,
201 struct pt_regs
*regs
)
203 struct ata_host_set
*host_set
= dev_instance
;
205 unsigned int handled
= 0;
208 spin_lock(&host_set
->lock
);
210 int_status
= readl(host_set
->mmio_base
+ VSC_SATA_INT_STAT_OFFSET
);
212 for (i
= 0; i
< host_set
->n_ports
; i
++) {
213 if (int_status
& ((u32
) 0xFF << (8 * i
))) {
216 ap
= host_set
->ports
[i
];
218 if (is_vsc_sata_int_err(i
, int_status
)) {
220 printk(KERN_DEBUG
"%s: ignoring interrupt(s)\n", __FUNCTION__
);
221 err_status
= ap
? vsc_sata_scr_read(ap
, SCR_ERROR
) : 0;
222 vsc_sata_scr_write(ap
, SCR_ERROR
, err_status
);
226 if (ap
&& !(ap
->flags
& ATA_FLAG_PORT_DISABLED
)) {
227 struct ata_queued_cmd
*qc
;
229 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
230 if (qc
&& (!(qc
->tf
.flags
& ATA_TFLAG_POLLING
)))
231 handled
+= ata_host_intr(ap
, qc
);
233 printk(KERN_DEBUG
"%s: ignoring interrupt(s)\n", __FUNCTION__
);
242 spin_unlock(&host_set
->lock
);
244 return IRQ_RETVAL(handled
);
248 static struct scsi_host_template vsc_sata_sht
= {
249 .module
= THIS_MODULE
,
251 .ioctl
= ata_scsi_ioctl
,
252 .queuecommand
= ata_scsi_queuecmd
,
253 .eh_timed_out
= ata_scsi_timed_out
,
254 .eh_strategy_handler
= ata_scsi_error
,
255 .can_queue
= ATA_DEF_QUEUE
,
256 .this_id
= ATA_SHT_THIS_ID
,
257 .sg_tablesize
= LIBATA_MAX_PRD
,
258 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
259 .emulated
= ATA_SHT_EMULATED
,
260 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
261 .proc_name
= DRV_NAME
,
262 .dma_boundary
= ATA_DMA_BOUNDARY
,
263 .slave_configure
= ata_scsi_slave_config
,
264 .bios_param
= ata_std_bios_param
,
268 static const struct ata_port_operations vsc_sata_ops
= {
269 .port_disable
= ata_port_disable
,
270 .tf_load
= vsc_sata_tf_load
,
271 .tf_read
= vsc_sata_tf_read
,
272 .exec_command
= ata_exec_command
,
273 .check_status
= ata_check_status
,
274 .dev_select
= ata_std_dev_select
,
275 .phy_reset
= sata_phy_reset
,
276 .bmdma_setup
= ata_bmdma_setup
,
277 .bmdma_start
= ata_bmdma_start
,
278 .bmdma_stop
= ata_bmdma_stop
,
279 .bmdma_status
= ata_bmdma_status
,
280 .qc_prep
= ata_qc_prep
,
281 .qc_issue
= ata_qc_issue_prot
,
282 .eng_timeout
= ata_eng_timeout
,
283 .irq_handler
= vsc_sata_interrupt
,
284 .irq_clear
= ata_bmdma_irq_clear
,
285 .scr_read
= vsc_sata_scr_read
,
286 .scr_write
= vsc_sata_scr_write
,
287 .port_start
= ata_port_start
,
288 .port_stop
= ata_port_stop
,
289 .host_stop
= ata_pci_host_stop
,
292 static void __devinit
vsc_sata_setup_port(struct ata_ioports
*port
, unsigned long base
)
294 port
->cmd_addr
= base
+ VSC_SATA_TF_CMD_OFFSET
;
295 port
->data_addr
= base
+ VSC_SATA_TF_DATA_OFFSET
;
296 port
->error_addr
= base
+ VSC_SATA_TF_ERROR_OFFSET
;
297 port
->feature_addr
= base
+ VSC_SATA_TF_FEATURE_OFFSET
;
298 port
->nsect_addr
= base
+ VSC_SATA_TF_NSECT_OFFSET
;
299 port
->lbal_addr
= base
+ VSC_SATA_TF_LBAL_OFFSET
;
300 port
->lbam_addr
= base
+ VSC_SATA_TF_LBAM_OFFSET
;
301 port
->lbah_addr
= base
+ VSC_SATA_TF_LBAH_OFFSET
;
302 port
->device_addr
= base
+ VSC_SATA_TF_DEVICE_OFFSET
;
303 port
->status_addr
= base
+ VSC_SATA_TF_STATUS_OFFSET
;
304 port
->command_addr
= base
+ VSC_SATA_TF_COMMAND_OFFSET
;
305 port
->altstatus_addr
= base
+ VSC_SATA_TF_ALTSTATUS_OFFSET
;
306 port
->ctl_addr
= base
+ VSC_SATA_TF_CTL_OFFSET
;
307 port
->bmdma_addr
= base
+ VSC_SATA_DMA_CMD_OFFSET
;
308 port
->scr_addr
= base
+ VSC_SATA_SCR_STATUS_OFFSET
;
309 writel(0, base
+ VSC_SATA_UP_DESCRIPTOR_OFFSET
);
310 writel(0, base
+ VSC_SATA_UP_DATA_BUFFER_OFFSET
);
314 static int __devinit
vsc_sata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
316 static int printed_version
;
317 struct ata_probe_ent
*probe_ent
= NULL
;
319 int pci_dev_busy
= 0;
320 void __iomem
*mmio_base
;
323 if (!printed_version
++)
324 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
326 rc
= pci_enable_device(pdev
);
331 * Check if we have needed resource mapped.
333 if (pci_resource_len(pdev
, 0) == 0) {
338 rc
= pci_request_regions(pdev
, DRV_NAME
);
345 * Use 32 bit DMA mask, because 64 bit address support is poor.
347 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
349 goto err_out_regions
;
350 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
352 goto err_out_regions
;
354 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
355 if (probe_ent
== NULL
) {
357 goto err_out_regions
;
359 memset(probe_ent
, 0, sizeof(*probe_ent
));
360 probe_ent
->dev
= pci_dev_to_dev(pdev
);
361 INIT_LIST_HEAD(&probe_ent
->node
);
363 mmio_base
= pci_iomap(pdev
, 0, 0);
364 if (mmio_base
== NULL
) {
366 goto err_out_free_ent
;
368 base
= (unsigned long) mmio_base
;
371 * Due to a bug in the chip, the default cache line size can't be used
373 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x80);
375 probe_ent
->sht
= &vsc_sata_sht
;
376 probe_ent
->host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
377 ATA_FLAG_MMIO
| ATA_FLAG_SATA_RESET
;
378 probe_ent
->port_ops
= &vsc_sata_ops
;
379 probe_ent
->n_ports
= 4;
380 probe_ent
->irq
= pdev
->irq
;
381 probe_ent
->irq_flags
= SA_SHIRQ
;
382 probe_ent
->mmio_base
= mmio_base
;
384 /* We don't care much about the PIO/UDMA masks, but the core won't like us
385 * if we don't fill these
387 probe_ent
->pio_mask
= 0x1f;
388 probe_ent
->mwdma_mask
= 0x07;
389 probe_ent
->udma_mask
= 0x7f;
391 /* We have 4 ports per PCI function */
392 vsc_sata_setup_port(&probe_ent
->port
[0], base
+ 1 * VSC_SATA_PORT_OFFSET
);
393 vsc_sata_setup_port(&probe_ent
->port
[1], base
+ 2 * VSC_SATA_PORT_OFFSET
);
394 vsc_sata_setup_port(&probe_ent
->port
[2], base
+ 3 * VSC_SATA_PORT_OFFSET
);
395 vsc_sata_setup_port(&probe_ent
->port
[3], base
+ 4 * VSC_SATA_PORT_OFFSET
);
397 pci_set_master(pdev
);
400 * Config offset 0x98 is "Extended Control and Status Register 0"
401 * Default value is (1 << 28). All bits except bit 28 are reserved in
402 * DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
403 * If bit 28 is clear, each port has its own LED.
405 pci_write_config_dword(pdev
, 0x98, 0);
407 /* FIXME: check ata_device_add return value */
408 ata_device_add(probe_ent
);
416 pci_release_regions(pdev
);
419 pci_disable_device(pdev
);
425 * 0x1725/0x7174 is the Vitesse VSC-7174
426 * 0x8086/0x3200 is the Intel 31244, which is supposed to be identical
427 * compatibility is untested as of yet
429 static const struct pci_device_id vsc_sata_pci_tbl
[] = {
430 { 0x1725, 0x7174, PCI_ANY_ID
, PCI_ANY_ID
, 0x10600, 0xFFFFFF, 0 },
431 { 0x8086, 0x3200, PCI_ANY_ID
, PCI_ANY_ID
, 0x10600, 0xFFFFFF, 0 },
436 static struct pci_driver vsc_sata_pci_driver
= {
438 .id_table
= vsc_sata_pci_tbl
,
439 .probe
= vsc_sata_init_one
,
440 .remove
= ata_pci_remove_one
,
444 static int __init
vsc_sata_init(void)
446 return pci_module_init(&vsc_sata_pci_driver
);
450 static void __exit
vsc_sata_exit(void)
452 pci_unregister_driver(&vsc_sata_pci_driver
);
456 MODULE_AUTHOR("Jeremy Higdon");
457 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
458 MODULE_LICENSE("GPL");
459 MODULE_DEVICE_TABLE(pci
, vsc_sata_pci_tbl
);
460 MODULE_VERSION(DRV_VERSION
);
462 module_init(vsc_sata_init
);
463 module_exit(vsc_sata_exit
);