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[SCSI] stex: change wait loop code
[deliverable/linux.git] / drivers / scsi / stex.c
1 /*
2 * SuperTrak EX Series Storage Controller driver for Linux
3 *
4 * Copyright (C) 2005, 2006 Promise Technology Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Written By:
12 * Ed Lin <promise_linux@promise.com>
13 *
14 * Version: 3.0.0.1
15 *
16 */
17
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/sched.h>
23 #include <linux/time.h>
24 #include <linux/pci.h>
25 #include <linux/blkdev.h>
26 #include <linux/interrupt.h>
27 #include <linux/types.h>
28 #include <linux/module.h>
29 #include <linux/spinlock.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <asm/byteorder.h>
33 #include <scsi/scsi.h>
34 #include <scsi/scsi_device.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <scsi/scsi_host.h>
37 #include <scsi/scsi_tcq.h>
38
39 #define DRV_NAME "stex"
40 #define ST_DRIVER_VERSION "3.0.0.1"
41 #define ST_VER_MAJOR 3
42 #define ST_VER_MINOR 0
43 #define ST_OEM 0
44 #define ST_BUILD_VER 1
45
46 enum {
47 /* MU register offset */
48 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
49 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
50 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
51 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
52 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
53 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
54 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
55 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
56 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
57 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
58
59 /* MU register value */
60 MU_INBOUND_DOORBELL_HANDSHAKE = 1,
61 MU_INBOUND_DOORBELL_REQHEADCHANGED = 2,
62 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4,
63 MU_INBOUND_DOORBELL_HMUSTOPPED = 8,
64 MU_INBOUND_DOORBELL_RESET = 16,
65
66 MU_OUTBOUND_DOORBELL_HANDSHAKE = 1,
67 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
68 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4,
69 MU_OUTBOUND_DOORBELL_BUSCHANGE = 8,
70 MU_OUTBOUND_DOORBELL_HASEVENT = 16,
71
72 /* MU status code */
73 MU_STATE_STARTING = 1,
74 MU_STATE_FMU_READY_FOR_HANDSHAKE = 2,
75 MU_STATE_SEND_HANDSHAKE_FRAME = 3,
76 MU_STATE_STARTED = 4,
77 MU_STATE_RESETTING = 5,
78
79 MU_MAX_DELAY = 120,
80 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
81 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
82 MU_HARD_RESET_WAIT = 30000,
83 HMU_PARTNER_TYPE = 2,
84
85 /* firmware returned values */
86 SRB_STATUS_SUCCESS = 0x01,
87 SRB_STATUS_ERROR = 0x04,
88 SRB_STATUS_BUSY = 0x05,
89 SRB_STATUS_INVALID_REQUEST = 0x06,
90 SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
91 SRB_SEE_SENSE = 0x80,
92
93 /* task attribute */
94 TASK_ATTRIBUTE_SIMPLE = 0x0,
95 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
96 TASK_ATTRIBUTE_ORDERED = 0x2,
97 TASK_ATTRIBUTE_ACA = 0x4,
98
99 /* request count, etc. */
100 MU_MAX_REQUEST = 32,
101
102 /* one message wasted, use MU_MAX_REQUEST+1
103 to handle MU_MAX_REQUEST messages */
104 MU_REQ_COUNT = (MU_MAX_REQUEST + 1),
105 MU_STATUS_COUNT = (MU_MAX_REQUEST + 1),
106
107 STEX_CDB_LENGTH = MAX_COMMAND_SIZE,
108 REQ_VARIABLE_LEN = 1024,
109 STATUS_VAR_LEN = 128,
110 ST_CAN_QUEUE = MU_MAX_REQUEST,
111 ST_CMD_PER_LUN = MU_MAX_REQUEST,
112 ST_MAX_SG = 32,
113
114 /* sg flags */
115 SG_CF_EOT = 0x80, /* end of table */
116 SG_CF_64B = 0x40, /* 64 bit item */
117 SG_CF_HOST = 0x20, /* sg in host memory */
118
119 ST_MAX_ARRAY_SUPPORTED = 16,
120 ST_MAX_TARGET_NUM = (ST_MAX_ARRAY_SUPPORTED+1),
121 ST_MAX_LUN_PER_TARGET = 16,
122
123 st_shasta = 0,
124 st_vsc = 1,
125 st_vsc1 = 2,
126 st_yosemite = 3,
127
128 PASSTHRU_REQ_TYPE = 0x00000001,
129 PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
130 ST_INTERNAL_TIMEOUT = 30,
131
132 ST_TO_CMD = 0,
133 ST_FROM_CMD = 1,
134
135 /* vendor specific commands of Promise */
136 MGT_CMD = 0xd8,
137 SINBAND_MGT_CMD = 0xd9,
138 ARRAY_CMD = 0xe0,
139 CONTROLLER_CMD = 0xe1,
140 DEBUGGING_CMD = 0xe2,
141 PASSTHRU_CMD = 0xe3,
142
143 PASSTHRU_GET_ADAPTER = 0x05,
144 PASSTHRU_GET_DRVVER = 0x10,
145
146 CTLR_CONFIG_CMD = 0x03,
147 CTLR_SHUTDOWN = 0x0d,
148
149 CTLR_POWER_STATE_CHANGE = 0x0e,
150 CTLR_POWER_SAVING = 0x01,
151
152 PASSTHRU_SIGNATURE = 0x4e415041,
153 MGT_CMD_SIGNATURE = 0xba,
154
155 INQUIRY_EVPD = 0x01,
156
157 ST_ADDITIONAL_MEM = 0x200000,
158 };
159
160 /* SCSI inquiry data */
161 typedef struct st_inq {
162 u8 DeviceType :5;
163 u8 DeviceTypeQualifier :3;
164 u8 DeviceTypeModifier :7;
165 u8 RemovableMedia :1;
166 u8 Versions;
167 u8 ResponseDataFormat :4;
168 u8 HiSupport :1;
169 u8 NormACA :1;
170 u8 ReservedBit :1;
171 u8 AERC :1;
172 u8 AdditionalLength;
173 u8 Reserved[2];
174 u8 SoftReset :1;
175 u8 CommandQueue :1;
176 u8 Reserved2 :1;
177 u8 LinkedCommands :1;
178 u8 Synchronous :1;
179 u8 Wide16Bit :1;
180 u8 Wide32Bit :1;
181 u8 RelativeAddressing :1;
182 u8 VendorId[8];
183 u8 ProductId[16];
184 u8 ProductRevisionLevel[4];
185 u8 VendorSpecific[20];
186 u8 Reserved3[40];
187 } ST_INQ;
188
189 struct st_sgitem {
190 u8 ctrl; /* SG_CF_xxx */
191 u8 reserved[3];
192 __le32 count;
193 __le32 addr;
194 __le32 addr_hi;
195 };
196
197 struct st_sgtable {
198 __le16 sg_count;
199 __le16 max_sg_count;
200 __le32 sz_in_byte;
201 struct st_sgitem table[ST_MAX_SG];
202 };
203
204 struct handshake_frame {
205 __le32 rb_phy; /* request payload queue physical address */
206 __le32 rb_phy_hi;
207 __le16 req_sz; /* size of each request payload */
208 __le16 req_cnt; /* count of reqs the buffer can hold */
209 __le16 status_sz; /* size of each status payload */
210 __le16 status_cnt; /* count of status the buffer can hold */
211 __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */
212 __le32 hosttime_hi;
213 u8 partner_type; /* who sends this frame */
214 u8 reserved0[7];
215 __le32 partner_ver_major;
216 __le32 partner_ver_minor;
217 __le32 partner_ver_oem;
218 __le32 partner_ver_build;
219 __le32 extra_offset; /* NEW */
220 __le32 extra_size; /* NEW */
221 u32 reserved1[2];
222 };
223
224 struct req_msg {
225 __le16 tag;
226 u8 lun;
227 u8 target;
228 u8 task_attr;
229 u8 task_manage;
230 u8 prd_entry;
231 u8 payload_sz; /* payload size in 4-byte, not used */
232 u8 cdb[STEX_CDB_LENGTH];
233 u8 variable[REQ_VARIABLE_LEN];
234 };
235
236 struct status_msg {
237 __le16 tag;
238 u8 lun;
239 u8 target;
240 u8 srb_status;
241 u8 scsi_status;
242 u8 reserved;
243 u8 payload_sz; /* payload size in 4-byte */
244 u8 variable[STATUS_VAR_LEN];
245 };
246
247 struct ver_info {
248 u32 major;
249 u32 minor;
250 u32 oem;
251 u32 build;
252 u32 reserved[2];
253 };
254
255 struct st_frame {
256 u32 base[6];
257 u32 rom_addr;
258
259 struct ver_info drv_ver;
260 struct ver_info bios_ver;
261
262 u32 bus;
263 u32 slot;
264 u32 irq_level;
265 u32 irq_vec;
266 u32 id;
267 u32 subid;
268
269 u32 dimm_size;
270 u8 dimm_type;
271 u8 reserved[3];
272
273 u32 channel;
274 u32 reserved1;
275 };
276
277 struct st_drvver {
278 u32 major;
279 u32 minor;
280 u32 oem;
281 u32 build;
282 u32 signature[2];
283 u8 console_id;
284 u8 host_no;
285 u8 reserved0[2];
286 u32 reserved[3];
287 };
288
289 #define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg))
290 #define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg))
291 #define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
292 #define STEX_EXTRA_SIZE max(sizeof(struct st_frame), sizeof(ST_INQ))
293 #define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
294
295 struct st_ccb {
296 struct req_msg *req;
297 struct scsi_cmnd *cmd;
298
299 void *sense_buffer;
300 unsigned int sense_bufflen;
301 int sg_count;
302
303 u32 req_type;
304 u8 srb_status;
305 u8 scsi_status;
306 };
307
308 struct st_hba {
309 void __iomem *mmio_base; /* iomapped PCI memory space */
310 void *dma_mem;
311 dma_addr_t dma_handle;
312 size_t dma_size;
313
314 struct Scsi_Host *host;
315 struct pci_dev *pdev;
316
317 u32 req_head;
318 u32 req_tail;
319 u32 status_head;
320 u32 status_tail;
321
322 struct status_msg *status_buffer;
323 void *copy_buffer; /* temp buffer for driver-handled commands */
324 struct st_ccb ccb[MU_MAX_REQUEST];
325 struct st_ccb *wait_ccb;
326 wait_queue_head_t waitq;
327
328 unsigned int mu_status;
329 int out_req_cnt;
330
331 unsigned int cardtype;
332 };
333
334 static const char console_inq_page[] =
335 {
336 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
337 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
338 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
339 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
340 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
341 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
342 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
343 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
344 };
345
346 MODULE_AUTHOR("Ed Lin");
347 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
348 MODULE_LICENSE("GPL");
349 MODULE_VERSION(ST_DRIVER_VERSION);
350
351 static void stex_gettime(__le32 *time)
352 {
353 struct timeval tv;
354 do_gettimeofday(&tv);
355
356 *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
357 *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
358 }
359
360 static struct status_msg *stex_get_status(struct st_hba *hba)
361 {
362 struct status_msg *status =
363 hba->status_buffer + hba->status_tail;
364
365 ++hba->status_tail;
366 hba->status_tail %= MU_STATUS_COUNT;
367
368 return status;
369 }
370
371 static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
372 {
373 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
374
375 cmd->sense_buffer[0] = 0x70; /* fixed format, current */
376 cmd->sense_buffer[2] = sk;
377 cmd->sense_buffer[7] = 18 - 8; /* additional sense length */
378 cmd->sense_buffer[12] = asc;
379 cmd->sense_buffer[13] = ascq;
380 }
381
382 static void stex_invalid_field(struct scsi_cmnd *cmd,
383 void (*done)(struct scsi_cmnd *))
384 {
385 /* "Invalid field in cbd" */
386 stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
387 done(cmd);
388 }
389
390 static struct req_msg *stex_alloc_req(struct st_hba *hba)
391 {
392 struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
393 hba->req_head;
394
395 ++hba->req_head;
396 hba->req_head %= MU_REQ_COUNT;
397
398 return req;
399 }
400
401 static int stex_map_sg(struct st_hba *hba,
402 struct req_msg *req, struct st_ccb *ccb)
403 {
404 struct pci_dev *pdev = hba->pdev;
405 struct scsi_cmnd *cmd;
406 dma_addr_t dma_handle;
407 struct scatterlist *src;
408 struct st_sgtable *dst;
409 int i;
410
411 cmd = ccb->cmd;
412 dst = (struct st_sgtable *)req->variable;
413 dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
414 dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
415
416 if (cmd->use_sg) {
417 int n_elem;
418
419 src = (struct scatterlist *) cmd->request_buffer;
420 n_elem = pci_map_sg(pdev, src,
421 cmd->use_sg, cmd->sc_data_direction);
422 if (n_elem <= 0)
423 return -EIO;
424
425 ccb->sg_count = n_elem;
426 dst->sg_count = cpu_to_le16((u16)n_elem);
427
428 for (i = 0; i < n_elem; i++, src++) {
429 dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
430 dst->table[i].addr =
431 cpu_to_le32(sg_dma_address(src) & 0xffffffff);
432 dst->table[i].addr_hi =
433 cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
434 dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
435 }
436 dst->table[--i].ctrl |= SG_CF_EOT;
437 return 0;
438 }
439
440 dma_handle = pci_map_single(pdev, cmd->request_buffer,
441 cmd->request_bufflen, cmd->sc_data_direction);
442 cmd->SCp.dma_handle = dma_handle;
443
444 ccb->sg_count = 1;
445 dst->sg_count = cpu_to_le16(1);
446 dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
447 dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
448 dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
449 dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
450
451 return 0;
452 }
453
454 static void stex_internal_copy(struct scsi_cmnd *cmd,
455 const void *src, size_t *count, int sg_count, int direction)
456 {
457 size_t lcount;
458 size_t len;
459 void *s, *d, *base = NULL;
460 if (*count > cmd->request_bufflen)
461 *count = cmd->request_bufflen;
462 lcount = *count;
463 while (lcount) {
464 len = lcount;
465 s = (void *)src;
466 if (cmd->use_sg) {
467 size_t offset = *count - lcount;
468 s += offset;
469 base = scsi_kmap_atomic_sg(cmd->request_buffer,
470 sg_count, &offset, &len);
471 if (base == NULL) {
472 *count -= lcount;
473 return;
474 }
475 d = base + offset;
476 } else
477 d = cmd->request_buffer;
478
479 if (direction == ST_TO_CMD)
480 memcpy(d, s, len);
481 else
482 memcpy(s, d, len);
483
484 lcount -= len;
485 if (cmd->use_sg)
486 scsi_kunmap_atomic_sg(base);
487 }
488 }
489
490 static int stex_direct_copy(struct scsi_cmnd *cmd,
491 const void *src, size_t count)
492 {
493 struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
494 size_t cp_len = count;
495 int n_elem = 0;
496
497 if (cmd->use_sg) {
498 n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
499 cmd->use_sg, cmd->sc_data_direction);
500 if (n_elem <= 0)
501 return 0;
502 }
503
504 stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD);
505
506 if (cmd->use_sg)
507 pci_unmap_sg(hba->pdev, cmd->request_buffer,
508 cmd->use_sg, cmd->sc_data_direction);
509 return cp_len == count;
510 }
511
512 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
513 {
514 struct st_frame *p;
515 size_t count = sizeof(struct st_frame);
516
517 p = hba->copy_buffer;
518 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD);
519 memset(p->base, 0, sizeof(u32)*6);
520 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
521 p->rom_addr = 0;
522
523 p->drv_ver.major = ST_VER_MAJOR;
524 p->drv_ver.minor = ST_VER_MINOR;
525 p->drv_ver.oem = ST_OEM;
526 p->drv_ver.build = ST_BUILD_VER;
527
528 p->bus = hba->pdev->bus->number;
529 p->slot = hba->pdev->devfn;
530 p->irq_level = 0;
531 p->irq_vec = hba->pdev->irq;
532 p->id = hba->pdev->vendor << 16 | hba->pdev->device;
533 p->subid =
534 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
535
536 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD);
537 }
538
539 static void
540 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
541 {
542 req->tag = cpu_to_le16(tag);
543 req->task_attr = TASK_ATTRIBUTE_SIMPLE;
544 req->task_manage = 0; /* not supported yet */
545
546 hba->ccb[tag].req = req;
547 hba->out_req_cnt++;
548
549 writel(hba->req_head, hba->mmio_base + IMR0);
550 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
551 readl(hba->mmio_base + IDBL); /* flush */
552 }
553
554 static int
555 stex_slave_alloc(struct scsi_device *sdev)
556 {
557 /* Cheat: usually extracted from Inquiry data */
558 sdev->tagged_supported = 1;
559
560 scsi_activate_tcq(sdev, sdev->host->can_queue);
561
562 return 0;
563 }
564
565 static int
566 stex_slave_config(struct scsi_device *sdev)
567 {
568 sdev->use_10_for_rw = 1;
569 sdev->use_10_for_ms = 1;
570 sdev->timeout = 60 * HZ;
571 sdev->tagged_supported = 1;
572
573 return 0;
574 }
575
576 static void
577 stex_slave_destroy(struct scsi_device *sdev)
578 {
579 scsi_deactivate_tcq(sdev, 1);
580 }
581
582 static int
583 stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
584 {
585 struct st_hba *hba;
586 struct Scsi_Host *host;
587 unsigned int id,lun;
588 struct req_msg *req;
589 u16 tag;
590 host = cmd->device->host;
591 id = cmd->device->id;
592 lun = cmd->device->channel; /* firmware lun issue work around */
593 hba = (struct st_hba *) &host->hostdata[0];
594
595 switch (cmd->cmnd[0]) {
596 case MODE_SENSE_10:
597 {
598 static char ms10_caching_page[12] =
599 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
600 unsigned char page;
601 page = cmd->cmnd[2] & 0x3f;
602 if (page == 0x8 || page == 0x3f) {
603 stex_direct_copy(cmd, ms10_caching_page,
604 sizeof(ms10_caching_page));
605 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
606 done(cmd);
607 } else
608 stex_invalid_field(cmd, done);
609 return 0;
610 }
611 case INQUIRY:
612 if (id != ST_MAX_ARRAY_SUPPORTED)
613 break;
614 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
615 stex_direct_copy(cmd, console_inq_page,
616 sizeof(console_inq_page));
617 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
618 done(cmd);
619 } else
620 stex_invalid_field(cmd, done);
621 return 0;
622 case PASSTHRU_CMD:
623 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
624 struct st_drvver ver;
625 ver.major = ST_VER_MAJOR;
626 ver.minor = ST_VER_MINOR;
627 ver.oem = ST_OEM;
628 ver.build = ST_BUILD_VER;
629 ver.signature[0] = PASSTHRU_SIGNATURE;
630 ver.console_id = ST_MAX_ARRAY_SUPPORTED;
631 ver.host_no = hba->host->host_no;
632 cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
633 DID_OK << 16 | COMMAND_COMPLETE << 8 :
634 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
635 done(cmd);
636 return 0;
637 }
638 default:
639 break;
640 }
641
642 cmd->scsi_done = done;
643
644 tag = cmd->request->tag;
645
646 if (unlikely(tag >= host->can_queue))
647 return SCSI_MLQUEUE_HOST_BUSY;
648
649 req = stex_alloc_req(hba);
650
651 if (hba->cardtype == st_yosemite) {
652 req->lun = lun * (ST_MAX_TARGET_NUM - 1) + id;
653 req->target = 0;
654 } else {
655 req->lun = lun;
656 req->target = id;
657 }
658
659 /* cdb */
660 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
661
662 hba->ccb[tag].cmd = cmd;
663 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
664 hba->ccb[tag].sense_buffer = cmd->sense_buffer;
665 hba->ccb[tag].req_type = 0;
666
667 if (cmd->sc_data_direction != DMA_NONE)
668 stex_map_sg(hba, req, &hba->ccb[tag]);
669
670 stex_send_cmd(hba, req, tag);
671 return 0;
672 }
673
674 static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
675 {
676 if (cmd->sc_data_direction != DMA_NONE) {
677 if (cmd->use_sg)
678 pci_unmap_sg(hba->pdev, cmd->request_buffer,
679 cmd->use_sg, cmd->sc_data_direction);
680 else
681 pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
682 cmd->request_bufflen, cmd->sc_data_direction);
683 }
684 }
685
686 static void stex_scsi_done(struct st_ccb *ccb)
687 {
688 struct scsi_cmnd *cmd = ccb->cmd;
689 int result;
690
691 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
692 result = ccb->scsi_status;
693 switch (ccb->scsi_status) {
694 case SAM_STAT_GOOD:
695 result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
696 break;
697 case SAM_STAT_CHECK_CONDITION:
698 result |= DRIVER_SENSE << 24;
699 break;
700 case SAM_STAT_BUSY:
701 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
702 break;
703 default:
704 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
705 break;
706 }
707 }
708 else if (ccb->srb_status & SRB_SEE_SENSE)
709 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
710 else switch (ccb->srb_status) {
711 case SRB_STATUS_SELECTION_TIMEOUT:
712 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
713 break;
714 case SRB_STATUS_BUSY:
715 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
716 break;
717 case SRB_STATUS_INVALID_REQUEST:
718 case SRB_STATUS_ERROR:
719 default:
720 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
721 break;
722 }
723
724 cmd->result = result;
725 cmd->scsi_done(cmd);
726 }
727
728 static void stex_copy_data(struct st_ccb *ccb,
729 struct status_msg *resp, unsigned int variable)
730 {
731 size_t count = variable;
732 if (resp->scsi_status != SAM_STAT_GOOD) {
733 if (ccb->sense_buffer != NULL)
734 memcpy(ccb->sense_buffer, resp->variable,
735 min(variable, ccb->sense_bufflen));
736 return;
737 }
738
739 if (ccb->cmd == NULL)
740 return;
741 stex_internal_copy(ccb->cmd,
742 resp->variable, &count, ccb->sg_count, ST_TO_CMD);
743 }
744
745 static void stex_ys_commands(struct st_hba *hba,
746 struct st_ccb *ccb, struct status_msg *resp)
747 {
748 size_t count;
749
750 if (ccb->cmd->cmnd[0] == MGT_CMD &&
751 resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
752 ccb->cmd->request_bufflen =
753 le32_to_cpu(*(__le32 *)&resp->variable[0]);
754 return;
755 }
756
757 if (resp->srb_status != 0)
758 return;
759
760 /* determine inquiry command status by DeviceTypeQualifier */
761 if (ccb->cmd->cmnd[0] == INQUIRY &&
762 resp->scsi_status == SAM_STAT_GOOD) {
763 ST_INQ *inq_data;
764
765 count = STEX_EXTRA_SIZE;
766 stex_internal_copy(ccb->cmd, hba->copy_buffer,
767 &count, ccb->sg_count, ST_FROM_CMD);
768 inq_data = (ST_INQ *)hba->copy_buffer;
769 if (inq_data->DeviceTypeQualifier != 0)
770 ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
771 else
772 ccb->srb_status = SRB_STATUS_SUCCESS;
773 } else if (ccb->cmd->cmnd[0] == REPORT_LUNS) {
774 u8 *report_lun_data = (u8 *)hba->copy_buffer;
775
776 count = STEX_EXTRA_SIZE;
777 stex_internal_copy(ccb->cmd, report_lun_data,
778 &count, ccb->sg_count, ST_FROM_CMD);
779 if (report_lun_data[2] || report_lun_data[3]) {
780 report_lun_data[2] = 0x00;
781 report_lun_data[3] = 0x08;
782 stex_internal_copy(ccb->cmd, report_lun_data,
783 &count, ccb->sg_count, ST_TO_CMD);
784 }
785 }
786 }
787
788 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
789 {
790 void __iomem *base = hba->mmio_base;
791 struct status_msg *resp;
792 struct st_ccb *ccb;
793 unsigned int size;
794 u16 tag;
795
796 if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
797 return;
798
799 /* status payloads */
800 hba->status_head = readl(base + OMR1);
801 if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
802 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
803 pci_name(hba->pdev));
804 return;
805 }
806
807 /*
808 * it's not a valid status payload if:
809 * 1. there are no pending requests(e.g. during init stage)
810 * 2. there are some pending requests, but the controller is in
811 * reset status, and its type is not st_yosemite
812 * firmware of st_yosemite in reset status will return pending requests
813 * to driver, so we allow it to pass
814 */
815 if (unlikely(hba->out_req_cnt <= 0 ||
816 (hba->mu_status == MU_STATE_RESETTING &&
817 hba->cardtype != st_yosemite))) {
818 hba->status_tail = hba->status_head;
819 goto update_status;
820 }
821
822 while (hba->status_tail != hba->status_head) {
823 resp = stex_get_status(hba);
824 tag = le16_to_cpu(resp->tag);
825 if (unlikely(tag >= hba->host->can_queue)) {
826 printk(KERN_WARNING DRV_NAME
827 "(%s): invalid tag\n", pci_name(hba->pdev));
828 continue;
829 }
830
831 ccb = &hba->ccb[tag];
832 if (hba->wait_ccb == ccb)
833 hba->wait_ccb = NULL;
834 if (unlikely(ccb->req == NULL)) {
835 printk(KERN_WARNING DRV_NAME
836 "(%s): lagging req\n", pci_name(hba->pdev));
837 hba->out_req_cnt--;
838 continue;
839 }
840
841 size = resp->payload_sz * sizeof(u32); /* payload size */
842 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
843 size > sizeof(*resp))) {
844 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
845 pci_name(hba->pdev));
846 } else {
847 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
848 if (size)
849 stex_copy_data(ccb, resp, size);
850 }
851
852 ccb->srb_status = resp->srb_status;
853 ccb->scsi_status = resp->scsi_status;
854
855 if (likely(ccb->cmd != NULL)) {
856 if (hba->cardtype == st_yosemite)
857 stex_ys_commands(hba, ccb, resp);
858
859 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
860 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
861 stex_controller_info(hba, ccb);
862
863 stex_unmap_sg(hba, ccb->cmd);
864 stex_scsi_done(ccb);
865 hba->out_req_cnt--;
866 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
867 hba->out_req_cnt--;
868 if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
869 ccb->req_type = 0;
870 continue;
871 }
872 ccb->req_type = 0;
873 if (waitqueue_active(&hba->waitq))
874 wake_up(&hba->waitq);
875 }
876 }
877
878 update_status:
879 writel(hba->status_head, base + IMR1);
880 readl(base + IMR1); /* flush */
881 }
882
883 static irqreturn_t stex_intr(int irq, void *__hba)
884 {
885 struct st_hba *hba = __hba;
886 void __iomem *base = hba->mmio_base;
887 u32 data;
888 unsigned long flags;
889 int handled = 0;
890
891 spin_lock_irqsave(hba->host->host_lock, flags);
892
893 data = readl(base + ODBL);
894
895 if (data && data != 0xffffffff) {
896 /* clear the interrupt */
897 writel(data, base + ODBL);
898 readl(base + ODBL); /* flush */
899 stex_mu_intr(hba, data);
900 handled = 1;
901 }
902
903 spin_unlock_irqrestore(hba->host->host_lock, flags);
904
905 return IRQ_RETVAL(handled);
906 }
907
908 static int stex_handshake(struct st_hba *hba)
909 {
910 void __iomem *base = hba->mmio_base;
911 struct handshake_frame *h;
912 dma_addr_t status_phys;
913 u32 data;
914 unsigned long before;
915
916 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
917 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
918 readl(base + IDBL);
919 before = jiffies;
920 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
921 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
922 printk(KERN_ERR DRV_NAME
923 "(%s): no handshake signature\n",
924 pci_name(hba->pdev));
925 return -1;
926 }
927 rmb();
928 msleep(1);
929 }
930 }
931
932 udelay(10);
933
934 data = readl(base + OMR1);
935 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
936 data &= 0x0000ffff;
937 if (hba->host->can_queue > data)
938 hba->host->can_queue = data;
939 }
940
941 h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
942 h->rb_phy = cpu_to_le32(hba->dma_handle);
943 h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
944 h->req_sz = cpu_to_le16(sizeof(struct req_msg));
945 h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
946 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
947 h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
948 stex_gettime(&h->hosttime);
949 h->partner_type = HMU_PARTNER_TYPE;
950 if (hba->dma_size > STEX_BUFFER_SIZE) {
951 h->extra_offset = cpu_to_le32(STEX_BUFFER_SIZE);
952 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
953 } else
954 h->extra_offset = h->extra_size = 0;
955
956 status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
957 writel(status_phys, base + IMR0);
958 readl(base + IMR0);
959 writel((status_phys >> 16) >> 16, base + IMR1);
960 readl(base + IMR1);
961
962 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
963 readl(base + OMR0);
964 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
965 readl(base + IDBL); /* flush */
966
967 udelay(10);
968 before = jiffies;
969 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
970 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
971 printk(KERN_ERR DRV_NAME
972 "(%s): no signature after handshake frame\n",
973 pci_name(hba->pdev));
974 return -1;
975 }
976 rmb();
977 msleep(1);
978 }
979
980 writel(0, base + IMR0);
981 readl(base + IMR0);
982 writel(0, base + OMR0);
983 readl(base + OMR0);
984 writel(0, base + IMR1);
985 readl(base + IMR1);
986 writel(0, base + OMR1);
987 readl(base + OMR1); /* flush */
988 hba->mu_status = MU_STATE_STARTED;
989 return 0;
990 }
991
992 static int stex_abort(struct scsi_cmnd *cmd)
993 {
994 struct Scsi_Host *host = cmd->device->host;
995 struct st_hba *hba = (struct st_hba *)host->hostdata;
996 u16 tag = cmd->request->tag;
997 void __iomem *base;
998 u32 data;
999 int result = SUCCESS;
1000 unsigned long flags;
1001 base = hba->mmio_base;
1002 spin_lock_irqsave(host->host_lock, flags);
1003 if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
1004 hba->wait_ccb = &hba->ccb[tag];
1005 else {
1006 for (tag = 0; tag < host->can_queue; tag++)
1007 if (hba->ccb[tag].cmd == cmd) {
1008 hba->wait_ccb = &hba->ccb[tag];
1009 break;
1010 }
1011 if (tag >= host->can_queue)
1012 goto out;
1013 }
1014
1015 data = readl(base + ODBL);
1016 if (data == 0 || data == 0xffffffff)
1017 goto fail_out;
1018
1019 writel(data, base + ODBL);
1020 readl(base + ODBL); /* flush */
1021
1022 stex_mu_intr(hba, data);
1023
1024 if (hba->wait_ccb == NULL) {
1025 printk(KERN_WARNING DRV_NAME
1026 "(%s): lost interrupt\n", pci_name(hba->pdev));
1027 goto out;
1028 }
1029
1030 fail_out:
1031 stex_unmap_sg(hba, cmd);
1032 hba->wait_ccb->req = NULL; /* nullify the req's future return */
1033 hba->wait_ccb = NULL;
1034 result = FAILED;
1035 out:
1036 spin_unlock_irqrestore(host->host_lock, flags);
1037 return result;
1038 }
1039
1040 static void stex_hard_reset(struct st_hba *hba)
1041 {
1042 struct pci_bus *bus;
1043 int i;
1044 u16 pci_cmd;
1045 u8 pci_bctl;
1046
1047 for (i = 0; i < 16; i++)
1048 pci_read_config_dword(hba->pdev, i * 4,
1049 &hba->pdev->saved_config_space[i]);
1050
1051 /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1052 secondary bus. Consult Intel 80331/3 developer's manual for detail */
1053 bus = hba->pdev->bus;
1054 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1055 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1056 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1057 msleep(1);
1058 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1059 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1060
1061 for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1062 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1063 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1064 break;
1065 msleep(1);
1066 }
1067
1068 ssleep(5);
1069 for (i = 0; i < 16; i++)
1070 pci_write_config_dword(hba->pdev, i * 4,
1071 hba->pdev->saved_config_space[i]);
1072 }
1073
1074 static int stex_reset(struct scsi_cmnd *cmd)
1075 {
1076 struct st_hba *hba;
1077 unsigned long flags;
1078 unsigned long before;
1079 hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1080
1081 hba->mu_status = MU_STATE_RESETTING;
1082
1083 if (hba->cardtype == st_shasta)
1084 stex_hard_reset(hba);
1085
1086 if (hba->cardtype != st_yosemite) {
1087 if (stex_handshake(hba)) {
1088 printk(KERN_WARNING DRV_NAME
1089 "(%s): resetting: handshake failed\n",
1090 pci_name(hba->pdev));
1091 return FAILED;
1092 }
1093 spin_lock_irqsave(hba->host->host_lock, flags);
1094 hba->req_head = 0;
1095 hba->req_tail = 0;
1096 hba->status_head = 0;
1097 hba->status_tail = 0;
1098 hba->out_req_cnt = 0;
1099 spin_unlock_irqrestore(hba->host->host_lock, flags);
1100 return SUCCESS;
1101 }
1102
1103 /* st_yosemite */
1104 writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
1105 readl(hba->mmio_base + IDBL); /* flush */
1106 before = jiffies;
1107 while (hba->out_req_cnt > 0) {
1108 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1109 printk(KERN_WARNING DRV_NAME
1110 "(%s): reset timeout\n", pci_name(hba->pdev));
1111 return FAILED;
1112 }
1113 msleep(1);
1114 }
1115
1116 hba->mu_status = MU_STATE_STARTED;
1117 return SUCCESS;
1118 }
1119
1120 static int stex_biosparam(struct scsi_device *sdev,
1121 struct block_device *bdev, sector_t capacity, int geom[])
1122 {
1123 int heads = 255, sectors = 63;
1124
1125 if (capacity < 0x200000) {
1126 heads = 64;
1127 sectors = 32;
1128 }
1129
1130 sector_div(capacity, heads * sectors);
1131
1132 geom[0] = heads;
1133 geom[1] = sectors;
1134 geom[2] = capacity;
1135
1136 return 0;
1137 }
1138
1139 static struct scsi_host_template driver_template = {
1140 .module = THIS_MODULE,
1141 .name = DRV_NAME,
1142 .proc_name = DRV_NAME,
1143 .bios_param = stex_biosparam,
1144 .queuecommand = stex_queuecommand,
1145 .slave_alloc = stex_slave_alloc,
1146 .slave_configure = stex_slave_config,
1147 .slave_destroy = stex_slave_destroy,
1148 .eh_abort_handler = stex_abort,
1149 .eh_host_reset_handler = stex_reset,
1150 .can_queue = ST_CAN_QUEUE,
1151 .this_id = -1,
1152 .sg_tablesize = ST_MAX_SG,
1153 .cmd_per_lun = ST_CMD_PER_LUN,
1154 };
1155
1156 static int stex_set_dma_mask(struct pci_dev * pdev)
1157 {
1158 int ret;
1159 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1160 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1161 return 0;
1162 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1163 if (!ret)
1164 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1165 return ret;
1166 }
1167
1168 static int __devinit
1169 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1170 {
1171 struct st_hba *hba;
1172 struct Scsi_Host *host;
1173 int err;
1174
1175 err = pci_enable_device(pdev);
1176 if (err)
1177 return err;
1178
1179 pci_set_master(pdev);
1180
1181 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1182
1183 if (!host) {
1184 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1185 pci_name(pdev));
1186 err = -ENOMEM;
1187 goto out_disable;
1188 }
1189
1190 hba = (struct st_hba *)host->hostdata;
1191 memset(hba, 0, sizeof(struct st_hba));
1192
1193 err = pci_request_regions(pdev, DRV_NAME);
1194 if (err < 0) {
1195 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1196 pci_name(pdev));
1197 goto out_scsi_host_put;
1198 }
1199
1200 hba->mmio_base = ioremap(pci_resource_start(pdev, 0),
1201 pci_resource_len(pdev, 0));
1202 if ( !hba->mmio_base) {
1203 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1204 pci_name(pdev));
1205 err = -ENOMEM;
1206 goto out_release_regions;
1207 }
1208
1209 err = stex_set_dma_mask(pdev);
1210 if (err) {
1211 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1212 pci_name(pdev));
1213 goto out_iounmap;
1214 }
1215
1216 hba->cardtype = (unsigned int) id->driver_data;
1217 if (hba->cardtype == st_vsc && (pdev->subsystem_device & 0xf) == 0x1)
1218 hba->cardtype = st_vsc1;
1219 hba->dma_size = (hba->cardtype == st_vsc1) ?
1220 (STEX_BUFFER_SIZE + ST_ADDITIONAL_MEM) : (STEX_BUFFER_SIZE);
1221 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1222 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1223 if (!hba->dma_mem) {
1224 err = -ENOMEM;
1225 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1226 pci_name(pdev));
1227 goto out_iounmap;
1228 }
1229
1230 hba->status_buffer =
1231 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1232 hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1233 hba->mu_status = MU_STATE_STARTING;
1234
1235 /* firmware uses id/lun pair for a logical drive, but lun would be
1236 always 0 if CONFIG_SCSI_MULTI_LUN not configured, so we use
1237 channel to map lun here */
1238 host->max_channel = ST_MAX_LUN_PER_TARGET - 1;
1239 host->max_id = ST_MAX_TARGET_NUM;
1240 host->max_lun = 1;
1241 host->unique_id = host->host_no;
1242 host->max_cmd_len = STEX_CDB_LENGTH;
1243
1244 hba->host = host;
1245 hba->pdev = pdev;
1246 init_waitqueue_head(&hba->waitq);
1247
1248 err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1249 if (err) {
1250 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1251 pci_name(pdev));
1252 goto out_pci_free;
1253 }
1254
1255 err = stex_handshake(hba);
1256 if (err)
1257 goto out_free_irq;
1258
1259 err = scsi_init_shared_tag_map(host, host->can_queue);
1260 if (err) {
1261 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1262 pci_name(pdev));
1263 goto out_free_irq;
1264 }
1265
1266 pci_set_drvdata(pdev, hba);
1267
1268 err = scsi_add_host(host, &pdev->dev);
1269 if (err) {
1270 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1271 pci_name(pdev));
1272 goto out_free_irq;
1273 }
1274
1275 scsi_scan_host(host);
1276
1277 return 0;
1278
1279 out_free_irq:
1280 free_irq(pdev->irq, hba);
1281 out_pci_free:
1282 dma_free_coherent(&pdev->dev, hba->dma_size,
1283 hba->dma_mem, hba->dma_handle);
1284 out_iounmap:
1285 iounmap(hba->mmio_base);
1286 out_release_regions:
1287 pci_release_regions(pdev);
1288 out_scsi_host_put:
1289 scsi_host_put(host);
1290 out_disable:
1291 pci_disable_device(pdev);
1292
1293 return err;
1294 }
1295
1296 static void stex_hba_stop(struct st_hba *hba)
1297 {
1298 struct req_msg *req;
1299 unsigned long flags;
1300 unsigned long before;
1301 u16 tag = 0;
1302
1303 spin_lock_irqsave(hba->host->host_lock, flags);
1304 req = stex_alloc_req(hba);
1305 memset(req->cdb, 0, STEX_CDB_LENGTH);
1306
1307 if (hba->cardtype == st_yosemite) {
1308 req->cdb[0] = MGT_CMD;
1309 req->cdb[1] = MGT_CMD_SIGNATURE;
1310 req->cdb[2] = CTLR_CONFIG_CMD;
1311 req->cdb[3] = CTLR_SHUTDOWN;
1312 } else {
1313 req->cdb[0] = CONTROLLER_CMD;
1314 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1315 req->cdb[2] = CTLR_POWER_SAVING;
1316 }
1317
1318 hba->ccb[tag].cmd = NULL;
1319 hba->ccb[tag].sg_count = 0;
1320 hba->ccb[tag].sense_bufflen = 0;
1321 hba->ccb[tag].sense_buffer = NULL;
1322 hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
1323
1324 stex_send_cmd(hba, req, tag);
1325 spin_unlock_irqrestore(hba->host->host_lock, flags);
1326
1327 before = jiffies;
1328 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1329 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
1330 return;
1331 msleep(10);
1332 }
1333 }
1334
1335 static void stex_hba_free(struct st_hba *hba)
1336 {
1337 free_irq(hba->pdev->irq, hba);
1338
1339 iounmap(hba->mmio_base);
1340
1341 pci_release_regions(hba->pdev);
1342
1343 dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1344 hba->dma_mem, hba->dma_handle);
1345 }
1346
1347 static void stex_remove(struct pci_dev *pdev)
1348 {
1349 struct st_hba *hba = pci_get_drvdata(pdev);
1350
1351 scsi_remove_host(hba->host);
1352
1353 pci_set_drvdata(pdev, NULL);
1354
1355 stex_hba_stop(hba);
1356
1357 stex_hba_free(hba);
1358
1359 scsi_host_put(hba->host);
1360
1361 pci_disable_device(pdev);
1362 }
1363
1364 static void stex_shutdown(struct pci_dev *pdev)
1365 {
1366 struct st_hba *hba = pci_get_drvdata(pdev);
1367
1368 stex_hba_stop(hba);
1369 }
1370
1371 static struct pci_device_id stex_pci_tbl[] = {
1372 /* st_shasta */
1373 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1374 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1375 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1376 st_shasta }, /* SuperTrak EX12350 */
1377 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1378 st_shasta }, /* SuperTrak EX4350 */
1379 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1380 st_shasta }, /* SuperTrak EX24350 */
1381
1382 /* st_vsc */
1383 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1384
1385 /* st_yosemite */
1386 { 0x105a, 0x8650, PCI_ANY_ID, 0x4600, 0, 0,
1387 st_yosemite }, /* SuperTrak EX4650 */
1388 { 0x105a, 0x8650, PCI_ANY_ID, 0x4610, 0, 0,
1389 st_yosemite }, /* SuperTrak EX4650o */
1390 { 0x105a, 0x8650, PCI_ANY_ID, 0x8600, 0, 0,
1391 st_yosemite }, /* SuperTrak EX8650EL */
1392 { 0x105a, 0x8650, PCI_ANY_ID, 0x8601, 0, 0,
1393 st_yosemite }, /* SuperTrak EX8650 */
1394 { 0x105a, 0x8650, PCI_ANY_ID, 0x8602, 0, 0,
1395 st_yosemite }, /* SuperTrak EX8654 */
1396 { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1397 st_yosemite }, /* generic st_yosemite */
1398 { } /* terminate list */
1399 };
1400 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1401
1402 static struct pci_driver stex_pci_driver = {
1403 .name = DRV_NAME,
1404 .id_table = stex_pci_tbl,
1405 .probe = stex_probe,
1406 .remove = __devexit_p(stex_remove),
1407 .shutdown = stex_shutdown,
1408 };
1409
1410 static int __init stex_init(void)
1411 {
1412 printk(KERN_INFO DRV_NAME
1413 ": Promise SuperTrak EX Driver version: %s\n",
1414 ST_DRIVER_VERSION);
1415
1416 return pci_register_driver(&stex_pci_driver);
1417 }
1418
1419 static void __exit stex_exit(void)
1420 {
1421 pci_unregister_driver(&stex_pci_driver);
1422 }
1423
1424 module_init(stex_init);
1425 module_exit(stex_exit);
Linux kernel - Deliverables
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