sparc: Make SBUS DMA interfaces take struct device.
[deliverable/linux.git] / drivers / scsi / sun_esp.c
1 /* sun_esp.c: ESP front-end for Sparc SBUS systems.
2 *
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/types.h>
8 #include <linux/delay.h>
9 #include <linux/module.h>
10 #include <linux/mm.h>
11 #include <linux/init.h>
12
13 #include <asm/irq.h>
14 #include <asm/io.h>
15 #include <asm/dma.h>
16
17 #include <asm/sbus.h>
18
19 #include <scsi/scsi_host.h>
20
21 #include "esp_scsi.h"
22
23 #define DRV_MODULE_NAME "sun_esp"
24 #define PFX DRV_MODULE_NAME ": "
25 #define DRV_VERSION "1.000"
26 #define DRV_MODULE_RELDATE "April 19, 2007"
27
28 #define dma_read32(REG) \
29 sbus_readl(esp->dma_regs + (REG))
30 #define dma_write32(VAL, REG) \
31 sbus_writel((VAL), esp->dma_regs + (REG))
32
33 /* DVMA chip revisions */
34 enum dvma_rev {
35 dvmarev0,
36 dvmaesc1,
37 dvmarev1,
38 dvmarev2,
39 dvmarev3,
40 dvmarevplus,
41 dvmahme
42 };
43
44 static int __devinit esp_sbus_setup_dma(struct esp *esp,
45 struct of_device *dma_of)
46 {
47 esp->dma = dma_of;
48
49 esp->dma_regs = of_ioremap(&dma_of->resource[0], 0,
50 resource_size(&dma_of->resource[0]),
51 "espdma");
52 if (!esp->dma_regs)
53 return -ENOMEM;
54
55 switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
56 case DMA_VERS0:
57 esp->dmarev = dvmarev0;
58 break;
59 case DMA_ESCV1:
60 esp->dmarev = dvmaesc1;
61 break;
62 case DMA_VERS1:
63 esp->dmarev = dvmarev1;
64 break;
65 case DMA_VERS2:
66 esp->dmarev = dvmarev2;
67 break;
68 case DMA_VERHME:
69 esp->dmarev = dvmahme;
70 break;
71 case DMA_VERSPLUS:
72 esp->dmarev = dvmarevplus;
73 break;
74 }
75
76 return 0;
77
78 }
79
80 static int __devinit esp_sbus_map_regs(struct esp *esp, int hme)
81 {
82 struct sbus_dev *sdev = esp->dev;
83 struct resource *res;
84
85 /* On HME, two reg sets exist, first is DVMA,
86 * second is ESP registers.
87 */
88 if (hme)
89 res = &sdev->resource[1];
90 else
91 res = &sdev->resource[0];
92
93 esp->regs = sbus_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP");
94 if (!esp->regs)
95 return -ENOMEM;
96
97 return 0;
98 }
99
100 static int __devinit esp_sbus_map_command_block(struct esp *esp)
101 {
102 struct sbus_dev *sdev = esp->dev;
103
104 esp->command_block = sbus_alloc_consistent(&sdev->ofdev.dev, 16,
105 &esp->command_block_dma);
106 if (!esp->command_block)
107 return -ENOMEM;
108 return 0;
109 }
110
111 static int __devinit esp_sbus_register_irq(struct esp *esp)
112 {
113 struct Scsi_Host *host = esp->host;
114 struct sbus_dev *sdev = esp->dev;
115
116 host->irq = sdev->irqs[0];
117 return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp);
118 }
119
120 static void __devinit esp_get_scsi_id(struct esp *esp)
121 {
122 struct sbus_dev *sdev = esp->dev;
123 struct device_node *dp = sdev->ofdev.node;
124
125 esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff);
126 if (esp->scsi_id != 0xff)
127 goto done;
128
129 esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff);
130 if (esp->scsi_id != 0xff)
131 goto done;
132
133 if (!sdev->bus) {
134 /* SUN4 */
135 esp->scsi_id = 7;
136 goto done;
137 }
138
139 esp->scsi_id = of_getintprop_default(sdev->bus->ofdev.node,
140 "scsi-initiator-id", 7);
141
142 done:
143 esp->host->this_id = esp->scsi_id;
144 esp->scsi_id_mask = (1 << esp->scsi_id);
145 }
146
147 static void __devinit esp_get_differential(struct esp *esp)
148 {
149 struct sbus_dev *sdev = esp->dev;
150 struct device_node *dp = sdev->ofdev.node;
151
152 if (of_find_property(dp, "differential", NULL))
153 esp->flags |= ESP_FLAG_DIFFERENTIAL;
154 else
155 esp->flags &= ~ESP_FLAG_DIFFERENTIAL;
156 }
157
158 static void __devinit esp_get_clock_params(struct esp *esp)
159 {
160 struct sbus_dev *sdev = esp->dev;
161 struct device_node *dp = sdev->ofdev.node;
162 struct device_node *bus_dp;
163 int fmhz;
164
165 bus_dp = NULL;
166 if (sdev != NULL && sdev->bus != NULL)
167 bus_dp = sdev->bus->ofdev.node;
168
169 fmhz = of_getintprop_default(dp, "clock-frequency", 0);
170 if (fmhz == 0)
171 fmhz = (!bus_dp) ? 0 :
172 of_getintprop_default(bus_dp, "clock-frequency", 0);
173
174 esp->cfreq = fmhz;
175 }
176
177 static void __devinit esp_get_bursts(struct esp *esp, struct of_device *dma_of)
178 {
179 struct device_node *dma_dp = dma_of->node;
180 struct sbus_dev *sdev = esp->dev;
181 struct device_node *dp;
182 u8 bursts, val;
183
184 dp = sdev->ofdev.node;
185 bursts = of_getintprop_default(dp, "burst-sizes", 0xff);
186 val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
187 if (val != 0xff)
188 bursts &= val;
189
190 if (sdev->bus) {
191 u8 val = of_getintprop_default(sdev->bus->ofdev.node,
192 "burst-sizes", 0xff);
193 if (val != 0xff)
194 bursts &= val;
195 }
196
197 if (bursts == 0xff ||
198 (bursts & DMA_BURST16) == 0 ||
199 (bursts & DMA_BURST32) == 0)
200 bursts = (DMA_BURST32 - 1);
201
202 esp->bursts = bursts;
203 }
204
205 static void __devinit esp_sbus_get_props(struct esp *esp, struct of_device *espdma)
206 {
207 esp_get_scsi_id(esp);
208 esp_get_differential(esp);
209 esp_get_clock_params(esp);
210 esp_get_bursts(esp, espdma);
211 }
212
213 static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
214 {
215 sbus_writeb(val, esp->regs + (reg * 4UL));
216 }
217
218 static u8 sbus_esp_read8(struct esp *esp, unsigned long reg)
219 {
220 return sbus_readb(esp->regs + (reg * 4UL));
221 }
222
223 static dma_addr_t sbus_esp_map_single(struct esp *esp, void *buf,
224 size_t sz, int dir)
225 {
226 struct sbus_dev *sdev = esp->dev;
227
228 return sbus_map_single(&sdev->ofdev.dev, buf, sz, dir);
229 }
230
231 static int sbus_esp_map_sg(struct esp *esp, struct scatterlist *sg,
232 int num_sg, int dir)
233 {
234 struct sbus_dev *sdev = esp->dev;
235
236 return sbus_map_sg(&sdev->ofdev.dev, sg, num_sg, dir);
237 }
238
239 static void sbus_esp_unmap_single(struct esp *esp, dma_addr_t addr,
240 size_t sz, int dir)
241 {
242 struct sbus_dev *sdev = esp->dev;
243
244 sbus_unmap_single(&sdev->ofdev.dev, addr, sz, dir);
245 }
246
247 static void sbus_esp_unmap_sg(struct esp *esp, struct scatterlist *sg,
248 int num_sg, int dir)
249 {
250 struct sbus_dev *sdev = esp->dev;
251
252 sbus_unmap_sg(&sdev->ofdev.dev, sg, num_sg, dir);
253 }
254
255 static int sbus_esp_irq_pending(struct esp *esp)
256 {
257 if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
258 return 1;
259 return 0;
260 }
261
262 static void sbus_esp_reset_dma(struct esp *esp)
263 {
264 int can_do_burst16, can_do_burst32, can_do_burst64;
265 int can_do_sbus64, lim;
266 u32 val;
267
268 can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
269 can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
270 can_do_burst64 = 0;
271 can_do_sbus64 = 0;
272 if (sbus_can_dma_64bit(esp->dev))
273 can_do_sbus64 = 1;
274 if (sbus_can_burst64(esp->sdev))
275 can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;
276
277 /* Put the DVMA into a known state. */
278 if (esp->dmarev != dvmahme) {
279 val = dma_read32(DMA_CSR);
280 dma_write32(val | DMA_RST_SCSI, DMA_CSR);
281 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
282 }
283 switch (esp->dmarev) {
284 case dvmahme:
285 dma_write32(DMA_RESET_FAS366, DMA_CSR);
286 dma_write32(DMA_RST_SCSI, DMA_CSR);
287
288 esp->prev_hme_dmacsr = (DMA_PARITY_OFF | DMA_2CLKS |
289 DMA_SCSI_DISAB | DMA_INT_ENAB);
290
291 esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE |
292 DMA_BRST_SZ);
293
294 if (can_do_burst64)
295 esp->prev_hme_dmacsr |= DMA_BRST64;
296 else if (can_do_burst32)
297 esp->prev_hme_dmacsr |= DMA_BRST32;
298
299 if (can_do_sbus64) {
300 esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64;
301 sbus_set_sbus64(esp->dev, esp->bursts);
302 }
303
304 lim = 1000;
305 while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
306 if (--lim == 0) {
307 printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
308 "will not clear!\n",
309 esp->host->unique_id);
310 break;
311 }
312 udelay(1);
313 }
314
315 dma_write32(0, DMA_CSR);
316 dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
317
318 dma_write32(0, DMA_ADDR);
319 break;
320
321 case dvmarev2:
322 if (esp->rev != ESP100) {
323 val = dma_read32(DMA_CSR);
324 dma_write32(val | DMA_3CLKS, DMA_CSR);
325 }
326 break;
327
328 case dvmarev3:
329 val = dma_read32(DMA_CSR);
330 val &= ~DMA_3CLKS;
331 val |= DMA_2CLKS;
332 if (can_do_burst32) {
333 val &= ~DMA_BRST_SZ;
334 val |= DMA_BRST32;
335 }
336 dma_write32(val, DMA_CSR);
337 break;
338
339 case dvmaesc1:
340 val = dma_read32(DMA_CSR);
341 val |= DMA_ADD_ENABLE;
342 val &= ~DMA_BCNT_ENAB;
343 if (!can_do_burst32 && can_do_burst16) {
344 val |= DMA_ESC_BURST;
345 } else {
346 val &= ~(DMA_ESC_BURST);
347 }
348 dma_write32(val, DMA_CSR);
349 break;
350
351 default:
352 break;
353 }
354
355 /* Enable interrupts. */
356 val = dma_read32(DMA_CSR);
357 dma_write32(val | DMA_INT_ENAB, DMA_CSR);
358 }
359
360 static void sbus_esp_dma_drain(struct esp *esp)
361 {
362 u32 csr;
363 int lim;
364
365 if (esp->dmarev == dvmahme)
366 return;
367
368 csr = dma_read32(DMA_CSR);
369 if (!(csr & DMA_FIFO_ISDRAIN))
370 return;
371
372 if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1)
373 dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
374
375 lim = 1000;
376 while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
377 if (--lim == 0) {
378 printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
379 esp->host->unique_id);
380 break;
381 }
382 udelay(1);
383 }
384 }
385
386 static void sbus_esp_dma_invalidate(struct esp *esp)
387 {
388 if (esp->dmarev == dvmahme) {
389 dma_write32(DMA_RST_SCSI, DMA_CSR);
390
391 esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr |
392 (DMA_PARITY_OFF | DMA_2CLKS |
393 DMA_SCSI_DISAB | DMA_INT_ENAB)) &
394 ~(DMA_ST_WRITE | DMA_ENABLE));
395
396 dma_write32(0, DMA_CSR);
397 dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
398
399 /* This is necessary to avoid having the SCSI channel
400 * engine lock up on us.
401 */
402 dma_write32(0, DMA_ADDR);
403 } else {
404 u32 val;
405 int lim;
406
407 lim = 1000;
408 while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
409 if (--lim == 0) {
410 printk(KERN_ALERT PFX "esp%d: DMA will not "
411 "invalidate!\n", esp->host->unique_id);
412 break;
413 }
414 udelay(1);
415 }
416
417 val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
418 val |= DMA_FIFO_INV;
419 dma_write32(val, DMA_CSR);
420 val &= ~DMA_FIFO_INV;
421 dma_write32(val, DMA_CSR);
422 }
423 }
424
425 static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
426 u32 dma_count, int write, u8 cmd)
427 {
428 u32 csr;
429
430 BUG_ON(!(cmd & ESP_CMD_DMA));
431
432 sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
433 sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
434 if (esp->rev == FASHME) {
435 sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO);
436 sbus_esp_write8(esp, 0, FAS_RHI);
437
438 scsi_esp_cmd(esp, cmd);
439
440 csr = esp->prev_hme_dmacsr;
441 csr |= DMA_SCSI_DISAB | DMA_ENABLE;
442 if (write)
443 csr |= DMA_ST_WRITE;
444 else
445 csr &= ~DMA_ST_WRITE;
446 esp->prev_hme_dmacsr = csr;
447
448 dma_write32(dma_count, DMA_COUNT);
449 dma_write32(addr, DMA_ADDR);
450 dma_write32(csr, DMA_CSR);
451 } else {
452 csr = dma_read32(DMA_CSR);
453 csr |= DMA_ENABLE;
454 if (write)
455 csr |= DMA_ST_WRITE;
456 else
457 csr &= ~DMA_ST_WRITE;
458 dma_write32(csr, DMA_CSR);
459 if (esp->dmarev == dvmaesc1) {
460 u32 end = PAGE_ALIGN(addr + dma_count + 16U);
461 dma_write32(end - addr, DMA_COUNT);
462 }
463 dma_write32(addr, DMA_ADDR);
464
465 scsi_esp_cmd(esp, cmd);
466 }
467
468 }
469
470 static int sbus_esp_dma_error(struct esp *esp)
471 {
472 u32 csr = dma_read32(DMA_CSR);
473
474 if (csr & DMA_HNDL_ERROR)
475 return 1;
476
477 return 0;
478 }
479
480 static const struct esp_driver_ops sbus_esp_ops = {
481 .esp_write8 = sbus_esp_write8,
482 .esp_read8 = sbus_esp_read8,
483 .map_single = sbus_esp_map_single,
484 .map_sg = sbus_esp_map_sg,
485 .unmap_single = sbus_esp_unmap_single,
486 .unmap_sg = sbus_esp_unmap_sg,
487 .irq_pending = sbus_esp_irq_pending,
488 .reset_dma = sbus_esp_reset_dma,
489 .dma_drain = sbus_esp_dma_drain,
490 .dma_invalidate = sbus_esp_dma_invalidate,
491 .send_dma_cmd = sbus_esp_send_dma_cmd,
492 .dma_error = sbus_esp_dma_error,
493 };
494
495 static int __devinit esp_sbus_probe_one(struct device *dev,
496 struct sbus_dev *esp_dev,
497 struct of_device *espdma,
498 struct sbus_bus *sbus,
499 int hme)
500 {
501 struct scsi_host_template *tpnt = &scsi_esp_template;
502 struct Scsi_Host *host;
503 struct esp *esp;
504 int err;
505
506 host = scsi_host_alloc(tpnt, sizeof(struct esp));
507
508 err = -ENOMEM;
509 if (!host)
510 goto fail;
511
512 host->max_id = (hme ? 16 : 8);
513 esp = shost_priv(host);
514
515 esp->host = host;
516 esp->dev = esp_dev;
517 esp->ops = &sbus_esp_ops;
518
519 if (hme)
520 esp->flags |= ESP_FLAG_WIDE_CAPABLE;
521
522 err = esp_sbus_setup_dma(esp, espdma);
523 if (err < 0)
524 goto fail_unlink;
525
526 err = esp_sbus_map_regs(esp, hme);
527 if (err < 0)
528 goto fail_unlink;
529
530 err = esp_sbus_map_command_block(esp);
531 if (err < 0)
532 goto fail_unmap_regs;
533
534 err = esp_sbus_register_irq(esp);
535 if (err < 0)
536 goto fail_unmap_command_block;
537
538 esp_sbus_get_props(esp, espdma);
539
540 /* Before we try to touch the ESP chip, ESC1 dma can
541 * come up with the reset bit set, so make sure that
542 * is clear first.
543 */
544 if (esp->dmarev == dvmaesc1) {
545 u32 val = dma_read32(DMA_CSR);
546
547 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
548 }
549
550 dev_set_drvdata(&esp_dev->ofdev.dev, esp);
551
552 err = scsi_esp_register(esp, dev);
553 if (err)
554 goto fail_free_irq;
555
556 return 0;
557
558 fail_free_irq:
559 free_irq(host->irq, esp);
560 fail_unmap_command_block:
561 sbus_free_consistent(&esp_dev->ofdev.dev, 16,
562 esp->command_block,
563 esp->command_block_dma);
564 fail_unmap_regs:
565 sbus_iounmap(esp->regs, SBUS_ESP_REG_SIZE);
566 fail_unlink:
567 scsi_host_put(host);
568 fail:
569 return err;
570 }
571
572 static int __devinit esp_sbus_probe(struct of_device *dev, const struct of_device_id *match)
573 {
574 struct sbus_dev *sdev = to_sbus_device(&dev->dev);
575 struct device_node *dma_node = NULL;
576 struct device_node *dp = dev->node;
577 struct of_device *dma_of = NULL;
578 int hme = 0;
579
580 if (dp->parent &&
581 (!strcmp(dp->parent->name, "espdma") ||
582 !strcmp(dp->parent->name, "dma")))
583 dma_node = dp->parent;
584 else if (!strcmp(dp->name, "SUNW,fas")) {
585 dma_node = sdev->ofdev.node;
586 hme = 1;
587 }
588 if (dma_node)
589 dma_of = of_find_device_by_node(dma_node);
590 if (!dma_of)
591 return -ENODEV;
592
593 return esp_sbus_probe_one(&dev->dev, sdev, dma_of,
594 sdev->bus, hme);
595 }
596
597 static int __devexit esp_sbus_remove(struct of_device *dev)
598 {
599 struct esp *esp = dev_get_drvdata(&dev->dev);
600 struct sbus_dev *sdev = esp->dev;
601 struct of_device *dma_of = esp->dma;
602 unsigned int irq = esp->host->irq;
603 u32 val;
604
605 scsi_esp_unregister(esp);
606
607 /* Disable interrupts. */
608 val = dma_read32(DMA_CSR);
609 dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
610
611 free_irq(irq, esp);
612 sbus_free_consistent(&sdev->ofdev.dev, 16,
613 esp->command_block,
614 esp->command_block_dma);
615 sbus_iounmap(esp->regs, SBUS_ESP_REG_SIZE);
616 of_iounmap(&dma_of->resource[0], esp->dma_regs,
617 resource_size(&dma_of->resource[0]));
618
619 scsi_host_put(esp->host);
620
621 return 0;
622 }
623
624 static struct of_device_id esp_match[] = {
625 {
626 .name = "SUNW,esp",
627 },
628 {
629 .name = "SUNW,fas",
630 },
631 {
632 .name = "esp",
633 },
634 {},
635 };
636 MODULE_DEVICE_TABLE(of, esp_match);
637
638 static struct of_platform_driver esp_sbus_driver = {
639 .name = "esp",
640 .match_table = esp_match,
641 .probe = esp_sbus_probe,
642 .remove = __devexit_p(esp_sbus_remove),
643 };
644
645 static int __init sunesp_init(void)
646 {
647 return of_register_driver(&esp_sbus_driver, &sbus_bus_type);
648 }
649
650 static void __exit sunesp_exit(void)
651 {
652 of_unregister_driver(&esp_sbus_driver);
653 }
654
655 MODULE_DESCRIPTION("Sun ESP SCSI driver");
656 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
657 MODULE_LICENSE("GPL");
658 MODULE_VERSION(DRV_VERSION);
659
660 module_init(sunesp_init);
661 module_exit(sunesp_exit);
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