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[SERIAL] AMD Alchemy UART: claim memory range
[deliverable/linux.git] / drivers / serial / 8250.c
1 /*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22 #include <linux/config.h>
23
24 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25 #define SUPPORT_SYSRQ
26 #endif
27
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/ioport.h>
31 #include <linux/init.h>
32 #include <linux/console.h>
33 #include <linux/sysrq.h>
34 #include <linux/delay.h>
35 #include <linux/platform_device.h>
36 #include <linux/tty.h>
37 #include <linux/tty_flip.h>
38 #include <linux/serial_reg.h>
39 #include <linux/serial_core.h>
40 #include <linux/serial.h>
41 #include <linux/serial_8250.h>
42 #include <linux/nmi.h>
43 #include <linux/mutex.h>
44
45 #include <asm/io.h>
46 #include <asm/irq.h>
47
48 #include "8250.h"
49
50 /*
51 * Configuration:
52 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
54 */
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
56
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
59 /*
60 * Debugging.
61 */
62 #if 0
63 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
64 #else
65 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
66 #endif
67
68 #if 0
69 #define DEBUG_INTR(fmt...) printk(fmt)
70 #else
71 #define DEBUG_INTR(fmt...) do { } while (0)
72 #endif
73
74 #define PASS_LIMIT 256
75
76 /*
77 * We default to IRQ0 for the "no irq" hack. Some
78 * machine types want others as well - they're free
79 * to redefine this in their header file.
80 */
81 #define is_real_interrupt(irq) ((irq) != 0)
82
83 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
84 #define CONFIG_SERIAL_DETECT_IRQ 1
85 #endif
86 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
87 #define CONFIG_SERIAL_MANY_PORTS 1
88 #endif
89
90 /*
91 * HUB6 is always on. This will be removed once the header
92 * files have been cleaned.
93 */
94 #define CONFIG_HUB6 1
95
96 #include <asm/serial.h>
97
98 /*
99 * SERIAL_PORT_DFNS tells us about built-in ports that have no
100 * standard enumeration mechanism. Platforms that can find all
101 * serial ports via mechanisms like ACPI or PCI need not supply it.
102 */
103 #ifndef SERIAL_PORT_DFNS
104 #define SERIAL_PORT_DFNS
105 #endif
106
107 static const struct old_serial_port old_serial_port[] = {
108 SERIAL_PORT_DFNS /* defined in asm/serial.h */
109 };
110
111 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
112
113 #ifdef CONFIG_SERIAL_8250_RSA
114
115 #define PORT_RSA_MAX 4
116 static unsigned long probe_rsa[PORT_RSA_MAX];
117 static unsigned int probe_rsa_count;
118 #endif /* CONFIG_SERIAL_8250_RSA */
119
120 struct uart_8250_port {
121 struct uart_port port;
122 struct timer_list timer; /* "no irq" timer */
123 struct list_head list; /* ports on this IRQ */
124 unsigned short capabilities; /* port capabilities */
125 unsigned short bugs; /* port bugs */
126 unsigned int tx_loadsz; /* transmit fifo load size */
127 unsigned char acr;
128 unsigned char ier;
129 unsigned char lcr;
130 unsigned char mcr;
131 unsigned char mcr_mask; /* mask of user bits */
132 unsigned char mcr_force; /* mask of forced bits */
133 unsigned char lsr_break_flag;
134
135 /*
136 * We provide a per-port pm hook.
137 */
138 void (*pm)(struct uart_port *port,
139 unsigned int state, unsigned int old);
140 };
141
142 struct irq_info {
143 spinlock_t lock;
144 struct list_head *head;
145 };
146
147 static struct irq_info irq_lists[NR_IRQS];
148
149 /*
150 * Here we define the default xmit fifo size used for each type of UART.
151 */
152 static const struct serial8250_config uart_config[] = {
153 [PORT_UNKNOWN] = {
154 .name = "unknown",
155 .fifo_size = 1,
156 .tx_loadsz = 1,
157 },
158 [PORT_8250] = {
159 .name = "8250",
160 .fifo_size = 1,
161 .tx_loadsz = 1,
162 },
163 [PORT_16450] = {
164 .name = "16450",
165 .fifo_size = 1,
166 .tx_loadsz = 1,
167 },
168 [PORT_16550] = {
169 .name = "16550",
170 .fifo_size = 1,
171 .tx_loadsz = 1,
172 },
173 [PORT_16550A] = {
174 .name = "16550A",
175 .fifo_size = 16,
176 .tx_loadsz = 16,
177 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
178 .flags = UART_CAP_FIFO,
179 },
180 [PORT_CIRRUS] = {
181 .name = "Cirrus",
182 .fifo_size = 1,
183 .tx_loadsz = 1,
184 },
185 [PORT_16650] = {
186 .name = "ST16650",
187 .fifo_size = 1,
188 .tx_loadsz = 1,
189 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
190 },
191 [PORT_16650V2] = {
192 .name = "ST16650V2",
193 .fifo_size = 32,
194 .tx_loadsz = 16,
195 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
196 UART_FCR_T_TRIG_00,
197 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
198 },
199 [PORT_16750] = {
200 .name = "TI16750",
201 .fifo_size = 64,
202 .tx_loadsz = 64,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
204 UART_FCR7_64BYTE,
205 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
206 },
207 [PORT_STARTECH] = {
208 .name = "Startech",
209 .fifo_size = 1,
210 .tx_loadsz = 1,
211 },
212 [PORT_16C950] = {
213 .name = "16C950/954",
214 .fifo_size = 128,
215 .tx_loadsz = 128,
216 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
217 .flags = UART_CAP_FIFO,
218 },
219 [PORT_16654] = {
220 .name = "ST16654",
221 .fifo_size = 64,
222 .tx_loadsz = 32,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
224 UART_FCR_T_TRIG_10,
225 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
226 },
227 [PORT_16850] = {
228 .name = "XR16850",
229 .fifo_size = 128,
230 .tx_loadsz = 128,
231 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
232 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
233 },
234 [PORT_RSA] = {
235 .name = "RSA",
236 .fifo_size = 2048,
237 .tx_loadsz = 2048,
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
239 .flags = UART_CAP_FIFO,
240 },
241 [PORT_NS16550A] = {
242 .name = "NS16550A",
243 .fifo_size = 16,
244 .tx_loadsz = 16,
245 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_NATSEMI,
247 },
248 [PORT_XSCALE] = {
249 .name = "XScale",
250 .fifo_size = 32,
251 .tx_loadsz = 32,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_UUE,
254 },
255 };
256
257 #ifdef CONFIG_SERIAL_8250_AU1X00
258
259 /* Au1x00 UART hardware has a weird register layout */
260 static const u8 au_io_in_map[] = {
261 [UART_RX] = 0,
262 [UART_IER] = 2,
263 [UART_IIR] = 3,
264 [UART_LCR] = 5,
265 [UART_MCR] = 6,
266 [UART_LSR] = 7,
267 [UART_MSR] = 8,
268 };
269
270 static const u8 au_io_out_map[] = {
271 [UART_TX] = 1,
272 [UART_IER] = 2,
273 [UART_FCR] = 4,
274 [UART_LCR] = 5,
275 [UART_MCR] = 6,
276 };
277
278 /* sane hardware needs no mapping */
279 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
280 {
281 if (up->port.iotype != UPIO_AU)
282 return offset;
283 return au_io_in_map[offset];
284 }
285
286 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
287 {
288 if (up->port.iotype != UPIO_AU)
289 return offset;
290 return au_io_out_map[offset];
291 }
292
293 #else
294
295 /* sane hardware needs no mapping */
296 #define map_8250_in_reg(up, offset) (offset)
297 #define map_8250_out_reg(up, offset) (offset)
298
299 #endif
300
301 static unsigned int serial_in(struct uart_8250_port *up, int offset)
302 {
303 offset = map_8250_in_reg(up, offset) << up->port.regshift;
304
305 switch (up->port.iotype) {
306 case UPIO_HUB6:
307 outb(up->port.hub6 - 1 + offset, up->port.iobase);
308 return inb(up->port.iobase + 1);
309
310 case UPIO_MEM:
311 return readb(up->port.membase + offset);
312
313 case UPIO_MEM32:
314 return readl(up->port.membase + offset);
315
316 #ifdef CONFIG_SERIAL_8250_AU1X00
317 case UPIO_AU:
318 return __raw_readl(up->port.membase + offset);
319 #endif
320
321 default:
322 return inb(up->port.iobase + offset);
323 }
324 }
325
326 static void
327 serial_out(struct uart_8250_port *up, int offset, int value)
328 {
329 offset = map_8250_out_reg(up, offset) << up->port.regshift;
330
331 switch (up->port.iotype) {
332 case UPIO_HUB6:
333 outb(up->port.hub6 - 1 + offset, up->port.iobase);
334 outb(value, up->port.iobase + 1);
335 break;
336
337 case UPIO_MEM:
338 writeb(value, up->port.membase + offset);
339 break;
340
341 case UPIO_MEM32:
342 writel(value, up->port.membase + offset);
343 break;
344
345 #ifdef CONFIG_SERIAL_8250_AU1X00
346 case UPIO_AU:
347 __raw_writel(value, up->port.membase + offset);
348 break;
349 #endif
350
351 default:
352 outb(value, up->port.iobase + offset);
353 }
354 }
355
356 /*
357 * We used to support using pause I/O for certain machines. We
358 * haven't supported this for a while, but just in case it's badly
359 * needed for certain old 386 machines, I've left these #define's
360 * in....
361 */
362 #define serial_inp(up, offset) serial_in(up, offset)
363 #define serial_outp(up, offset, value) serial_out(up, offset, value)
364
365
366 /*
367 * For the 16C950
368 */
369 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
370 {
371 serial_out(up, UART_SCR, offset);
372 serial_out(up, UART_ICR, value);
373 }
374
375 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
376 {
377 unsigned int value;
378
379 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
380 serial_out(up, UART_SCR, offset);
381 value = serial_in(up, UART_ICR);
382 serial_icr_write(up, UART_ACR, up->acr);
383
384 return value;
385 }
386
387 /*
388 * FIFO support.
389 */
390 static inline void serial8250_clear_fifos(struct uart_8250_port *p)
391 {
392 if (p->capabilities & UART_CAP_FIFO) {
393 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
394 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
395 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
396 serial_outp(p, UART_FCR, 0);
397 }
398 }
399
400 /*
401 * IER sleep support. UARTs which have EFRs need the "extended
402 * capability" bit enabled. Note that on XR16C850s, we need to
403 * reset LCR to write to IER.
404 */
405 static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
406 {
407 if (p->capabilities & UART_CAP_SLEEP) {
408 if (p->capabilities & UART_CAP_EFR) {
409 serial_outp(p, UART_LCR, 0xBF);
410 serial_outp(p, UART_EFR, UART_EFR_ECB);
411 serial_outp(p, UART_LCR, 0);
412 }
413 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
414 if (p->capabilities & UART_CAP_EFR) {
415 serial_outp(p, UART_LCR, 0xBF);
416 serial_outp(p, UART_EFR, 0);
417 serial_outp(p, UART_LCR, 0);
418 }
419 }
420 }
421
422 #ifdef CONFIG_SERIAL_8250_RSA
423 /*
424 * Attempts to turn on the RSA FIFO. Returns zero on failure.
425 * We set the port uart clock rate if we succeed.
426 */
427 static int __enable_rsa(struct uart_8250_port *up)
428 {
429 unsigned char mode;
430 int result;
431
432 mode = serial_inp(up, UART_RSA_MSR);
433 result = mode & UART_RSA_MSR_FIFO;
434
435 if (!result) {
436 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
437 mode = serial_inp(up, UART_RSA_MSR);
438 result = mode & UART_RSA_MSR_FIFO;
439 }
440
441 if (result)
442 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
443
444 return result;
445 }
446
447 static void enable_rsa(struct uart_8250_port *up)
448 {
449 if (up->port.type == PORT_RSA) {
450 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
451 spin_lock_irq(&up->port.lock);
452 __enable_rsa(up);
453 spin_unlock_irq(&up->port.lock);
454 }
455 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
456 serial_outp(up, UART_RSA_FRR, 0);
457 }
458 }
459
460 /*
461 * Attempts to turn off the RSA FIFO. Returns zero on failure.
462 * It is unknown why interrupts were disabled in here. However,
463 * the caller is expected to preserve this behaviour by grabbing
464 * the spinlock before calling this function.
465 */
466 static void disable_rsa(struct uart_8250_port *up)
467 {
468 unsigned char mode;
469 int result;
470
471 if (up->port.type == PORT_RSA &&
472 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
473 spin_lock_irq(&up->port.lock);
474
475 mode = serial_inp(up, UART_RSA_MSR);
476 result = !(mode & UART_RSA_MSR_FIFO);
477
478 if (!result) {
479 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
480 mode = serial_inp(up, UART_RSA_MSR);
481 result = !(mode & UART_RSA_MSR_FIFO);
482 }
483
484 if (result)
485 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
486 spin_unlock_irq(&up->port.lock);
487 }
488 }
489 #endif /* CONFIG_SERIAL_8250_RSA */
490
491 /*
492 * This is a quickie test to see how big the FIFO is.
493 * It doesn't work at all the time, more's the pity.
494 */
495 static int size_fifo(struct uart_8250_port *up)
496 {
497 unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr;
498 int count;
499
500 old_lcr = serial_inp(up, UART_LCR);
501 serial_outp(up, UART_LCR, 0);
502 old_fcr = serial_inp(up, UART_FCR);
503 old_mcr = serial_inp(up, UART_MCR);
504 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
505 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
506 serial_outp(up, UART_MCR, UART_MCR_LOOP);
507 serial_outp(up, UART_LCR, UART_LCR_DLAB);
508 old_dll = serial_inp(up, UART_DLL);
509 old_dlm = serial_inp(up, UART_DLM);
510 serial_outp(up, UART_DLL, 0x01);
511 serial_outp(up, UART_DLM, 0x00);
512 serial_outp(up, UART_LCR, 0x03);
513 for (count = 0; count < 256; count++)
514 serial_outp(up, UART_TX, count);
515 mdelay(20);/* FIXME - schedule_timeout */
516 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
517 (count < 256); count++)
518 serial_inp(up, UART_RX);
519 serial_outp(up, UART_FCR, old_fcr);
520 serial_outp(up, UART_MCR, old_mcr);
521 serial_outp(up, UART_LCR, UART_LCR_DLAB);
522 serial_outp(up, UART_DLL, old_dll);
523 serial_outp(up, UART_DLM, old_dlm);
524 serial_outp(up, UART_LCR, old_lcr);
525
526 return count;
527 }
528
529 /*
530 * Read UART ID using the divisor method - set DLL and DLM to zero
531 * and the revision will be in DLL and device type in DLM. We
532 * preserve the device state across this.
533 */
534 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
535 {
536 unsigned char old_dll, old_dlm, old_lcr;
537 unsigned int id;
538
539 old_lcr = serial_inp(p, UART_LCR);
540 serial_outp(p, UART_LCR, UART_LCR_DLAB);
541
542 old_dll = serial_inp(p, UART_DLL);
543 old_dlm = serial_inp(p, UART_DLM);
544
545 serial_outp(p, UART_DLL, 0);
546 serial_outp(p, UART_DLM, 0);
547
548 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
549
550 serial_outp(p, UART_DLL, old_dll);
551 serial_outp(p, UART_DLM, old_dlm);
552 serial_outp(p, UART_LCR, old_lcr);
553
554 return id;
555 }
556
557 /*
558 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
559 * When this function is called we know it is at least a StarTech
560 * 16650 V2, but it might be one of several StarTech UARTs, or one of
561 * its clones. (We treat the broken original StarTech 16650 V1 as a
562 * 16550, and why not? Startech doesn't seem to even acknowledge its
563 * existence.)
564 *
565 * What evil have men's minds wrought...
566 */
567 static void autoconfig_has_efr(struct uart_8250_port *up)
568 {
569 unsigned int id1, id2, id3, rev;
570
571 /*
572 * Everything with an EFR has SLEEP
573 */
574 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
575
576 /*
577 * First we check to see if it's an Oxford Semiconductor UART.
578 *
579 * If we have to do this here because some non-National
580 * Semiconductor clone chips lock up if you try writing to the
581 * LSR register (which serial_icr_read does)
582 */
583
584 /*
585 * Check for Oxford Semiconductor 16C950.
586 *
587 * EFR [4] must be set else this test fails.
588 *
589 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
590 * claims that it's needed for 952 dual UART's (which are not
591 * recommended for new designs).
592 */
593 up->acr = 0;
594 serial_out(up, UART_LCR, 0xBF);
595 serial_out(up, UART_EFR, UART_EFR_ECB);
596 serial_out(up, UART_LCR, 0x00);
597 id1 = serial_icr_read(up, UART_ID1);
598 id2 = serial_icr_read(up, UART_ID2);
599 id3 = serial_icr_read(up, UART_ID3);
600 rev = serial_icr_read(up, UART_REV);
601
602 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
603
604 if (id1 == 0x16 && id2 == 0xC9 &&
605 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
606 up->port.type = PORT_16C950;
607
608 /*
609 * Enable work around for the Oxford Semiconductor 952 rev B
610 * chip which causes it to seriously miscalculate baud rates
611 * when DLL is 0.
612 */
613 if (id3 == 0x52 && rev == 0x01)
614 up->bugs |= UART_BUG_QUOT;
615 return;
616 }
617
618 /*
619 * We check for a XR16C850 by setting DLL and DLM to 0, and then
620 * reading back DLL and DLM. The chip type depends on the DLM
621 * value read back:
622 * 0x10 - XR16C850 and the DLL contains the chip revision.
623 * 0x12 - XR16C2850.
624 * 0x14 - XR16C854.
625 */
626 id1 = autoconfig_read_divisor_id(up);
627 DEBUG_AUTOCONF("850id=%04x ", id1);
628
629 id2 = id1 >> 8;
630 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
631 up->port.type = PORT_16850;
632 return;
633 }
634
635 /*
636 * It wasn't an XR16C850.
637 *
638 * We distinguish between the '654 and the '650 by counting
639 * how many bytes are in the FIFO. I'm using this for now,
640 * since that's the technique that was sent to me in the
641 * serial driver update, but I'm not convinced this works.
642 * I've had problems doing this in the past. -TYT
643 */
644 if (size_fifo(up) == 64)
645 up->port.type = PORT_16654;
646 else
647 up->port.type = PORT_16650V2;
648 }
649
650 /*
651 * We detected a chip without a FIFO. Only two fall into
652 * this category - the original 8250 and the 16450. The
653 * 16450 has a scratch register (accessible with LCR=0)
654 */
655 static void autoconfig_8250(struct uart_8250_port *up)
656 {
657 unsigned char scratch, status1, status2;
658
659 up->port.type = PORT_8250;
660
661 scratch = serial_in(up, UART_SCR);
662 serial_outp(up, UART_SCR, 0xa5);
663 status1 = serial_in(up, UART_SCR);
664 serial_outp(up, UART_SCR, 0x5a);
665 status2 = serial_in(up, UART_SCR);
666 serial_outp(up, UART_SCR, scratch);
667
668 if (status1 == 0xa5 && status2 == 0x5a)
669 up->port.type = PORT_16450;
670 }
671
672 static int broken_efr(struct uart_8250_port *up)
673 {
674 /*
675 * Exar ST16C2550 "A2" devices incorrectly detect as
676 * having an EFR, and report an ID of 0x0201. See
677 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
678 */
679 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
680 return 1;
681
682 return 0;
683 }
684
685 /*
686 * We know that the chip has FIFOs. Does it have an EFR? The
687 * EFR is located in the same register position as the IIR and
688 * we know the top two bits of the IIR are currently set. The
689 * EFR should contain zero. Try to read the EFR.
690 */
691 static void autoconfig_16550a(struct uart_8250_port *up)
692 {
693 unsigned char status1, status2;
694 unsigned int iersave;
695
696 up->port.type = PORT_16550A;
697 up->capabilities |= UART_CAP_FIFO;
698
699 /*
700 * Check for presence of the EFR when DLAB is set.
701 * Only ST16C650V1 UARTs pass this test.
702 */
703 serial_outp(up, UART_LCR, UART_LCR_DLAB);
704 if (serial_in(up, UART_EFR) == 0) {
705 serial_outp(up, UART_EFR, 0xA8);
706 if (serial_in(up, UART_EFR) != 0) {
707 DEBUG_AUTOCONF("EFRv1 ");
708 up->port.type = PORT_16650;
709 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
710 } else {
711 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
712 }
713 serial_outp(up, UART_EFR, 0);
714 return;
715 }
716
717 /*
718 * Maybe it requires 0xbf to be written to the LCR.
719 * (other ST16C650V2 UARTs, TI16C752A, etc)
720 */
721 serial_outp(up, UART_LCR, 0xBF);
722 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
723 DEBUG_AUTOCONF("EFRv2 ");
724 autoconfig_has_efr(up);
725 return;
726 }
727
728 /*
729 * Check for a National Semiconductor SuperIO chip.
730 * Attempt to switch to bank 2, read the value of the LOOP bit
731 * from EXCR1. Switch back to bank 0, change it in MCR. Then
732 * switch back to bank 2, read it from EXCR1 again and check
733 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
734 */
735 serial_outp(up, UART_LCR, 0);
736 status1 = serial_in(up, UART_MCR);
737 serial_outp(up, UART_LCR, 0xE0);
738 status2 = serial_in(up, 0x02); /* EXCR1 */
739
740 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
741 serial_outp(up, UART_LCR, 0);
742 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
743 serial_outp(up, UART_LCR, 0xE0);
744 status2 = serial_in(up, 0x02); /* EXCR1 */
745 serial_outp(up, UART_LCR, 0);
746 serial_outp(up, UART_MCR, status1);
747
748 if ((status2 ^ status1) & UART_MCR_LOOP) {
749 unsigned short quot;
750
751 serial_outp(up, UART_LCR, 0xE0);
752
753 quot = serial_inp(up, UART_DLM) << 8;
754 quot += serial_inp(up, UART_DLL);
755 quot <<= 3;
756
757 status1 = serial_in(up, 0x04); /* EXCR1 */
758 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
759 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
760 serial_outp(up, 0x04, status1);
761
762 serial_outp(up, UART_DLL, quot & 0xff);
763 serial_outp(up, UART_DLM, quot >> 8);
764
765 serial_outp(up, UART_LCR, 0);
766
767 up->port.uartclk = 921600*16;
768 up->port.type = PORT_NS16550A;
769 up->capabilities |= UART_NATSEMI;
770 return;
771 }
772 }
773
774 /*
775 * No EFR. Try to detect a TI16750, which only sets bit 5 of
776 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
777 * Try setting it with and without DLAB set. Cheap clones
778 * set bit 5 without DLAB set.
779 */
780 serial_outp(up, UART_LCR, 0);
781 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
782 status1 = serial_in(up, UART_IIR) >> 5;
783 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
784 serial_outp(up, UART_LCR, UART_LCR_DLAB);
785 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
786 status2 = serial_in(up, UART_IIR) >> 5;
787 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
788 serial_outp(up, UART_LCR, 0);
789
790 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
791
792 if (status1 == 6 && status2 == 7) {
793 up->port.type = PORT_16750;
794 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
795 return;
796 }
797
798 /*
799 * Try writing and reading the UART_IER_UUE bit (b6).
800 * If it works, this is probably one of the Xscale platform's
801 * internal UARTs.
802 * We're going to explicitly set the UUE bit to 0 before
803 * trying to write and read a 1 just to make sure it's not
804 * already a 1 and maybe locked there before we even start start.
805 */
806 iersave = serial_in(up, UART_IER);
807 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
808 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
809 /*
810 * OK it's in a known zero state, try writing and reading
811 * without disturbing the current state of the other bits.
812 */
813 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
814 if (serial_in(up, UART_IER) & UART_IER_UUE) {
815 /*
816 * It's an Xscale.
817 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
818 */
819 DEBUG_AUTOCONF("Xscale ");
820 up->port.type = PORT_XSCALE;
821 up->capabilities |= UART_CAP_UUE;
822 return;
823 }
824 } else {
825 /*
826 * If we got here we couldn't force the IER_UUE bit to 0.
827 * Log it and continue.
828 */
829 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
830 }
831 serial_outp(up, UART_IER, iersave);
832 }
833
834 /*
835 * This routine is called by rs_init() to initialize a specific serial
836 * port. It determines what type of UART chip this serial port is
837 * using: 8250, 16450, 16550, 16550A. The important question is
838 * whether or not this UART is a 16550A or not, since this will
839 * determine whether or not we can use its FIFO features or not.
840 */
841 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
842 {
843 unsigned char status1, scratch, scratch2, scratch3;
844 unsigned char save_lcr, save_mcr;
845 unsigned long flags;
846
847 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
848 return;
849
850 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
851 up->port.line, up->port.iobase, up->port.membase);
852
853 /*
854 * We really do need global IRQs disabled here - we're going to
855 * be frobbing the chips IRQ enable register to see if it exists.
856 */
857 spin_lock_irqsave(&up->port.lock, flags);
858 // save_flags(flags); cli();
859
860 up->capabilities = 0;
861 up->bugs = 0;
862
863 if (!(up->port.flags & UPF_BUGGY_UART)) {
864 /*
865 * Do a simple existence test first; if we fail this,
866 * there's no point trying anything else.
867 *
868 * 0x80 is used as a nonsense port to prevent against
869 * false positives due to ISA bus float. The
870 * assumption is that 0x80 is a non-existent port;
871 * which should be safe since include/asm/io.h also
872 * makes this assumption.
873 *
874 * Note: this is safe as long as MCR bit 4 is clear
875 * and the device is in "PC" mode.
876 */
877 scratch = serial_inp(up, UART_IER);
878 serial_outp(up, UART_IER, 0);
879 #ifdef __i386__
880 outb(0xff, 0x080);
881 #endif
882 scratch2 = serial_inp(up, UART_IER);
883 serial_outp(up, UART_IER, 0x0F);
884 #ifdef __i386__
885 outb(0, 0x080);
886 #endif
887 scratch3 = serial_inp(up, UART_IER);
888 serial_outp(up, UART_IER, scratch);
889 if (scratch2 != 0 || scratch3 != 0x0F) {
890 /*
891 * We failed; there's nothing here
892 */
893 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
894 scratch2, scratch3);
895 goto out;
896 }
897 }
898
899 save_mcr = serial_in(up, UART_MCR);
900 save_lcr = serial_in(up, UART_LCR);
901
902 /*
903 * Check to see if a UART is really there. Certain broken
904 * internal modems based on the Rockwell chipset fail this
905 * test, because they apparently don't implement the loopback
906 * test mode. So this test is skipped on the COM 1 through
907 * COM 4 ports. This *should* be safe, since no board
908 * manufacturer would be stupid enough to design a board
909 * that conflicts with COM 1-4 --- we hope!
910 */
911 if (!(up->port.flags & UPF_SKIP_TEST)) {
912 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
913 status1 = serial_inp(up, UART_MSR) & 0xF0;
914 serial_outp(up, UART_MCR, save_mcr);
915 if (status1 != 0x90) {
916 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
917 status1);
918 goto out;
919 }
920 }
921
922 /*
923 * We're pretty sure there's a port here. Lets find out what
924 * type of port it is. The IIR top two bits allows us to find
925 * out if it's 8250 or 16450, 16550, 16550A or later. This
926 * determines what we test for next.
927 *
928 * We also initialise the EFR (if any) to zero for later. The
929 * EFR occupies the same register location as the FCR and IIR.
930 */
931 serial_outp(up, UART_LCR, 0xBF);
932 serial_outp(up, UART_EFR, 0);
933 serial_outp(up, UART_LCR, 0);
934
935 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
936 scratch = serial_in(up, UART_IIR) >> 6;
937
938 DEBUG_AUTOCONF("iir=%d ", scratch);
939
940 switch (scratch) {
941 case 0:
942 autoconfig_8250(up);
943 break;
944 case 1:
945 up->port.type = PORT_UNKNOWN;
946 break;
947 case 2:
948 up->port.type = PORT_16550;
949 break;
950 case 3:
951 autoconfig_16550a(up);
952 break;
953 }
954
955 #ifdef CONFIG_SERIAL_8250_RSA
956 /*
957 * Only probe for RSA ports if we got the region.
958 */
959 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
960 int i;
961
962 for (i = 0 ; i < probe_rsa_count; ++i) {
963 if (probe_rsa[i] == up->port.iobase &&
964 __enable_rsa(up)) {
965 up->port.type = PORT_RSA;
966 break;
967 }
968 }
969 }
970 #endif
971
972 #ifdef CONFIG_SERIAL_8250_AU1X00
973 /* if access method is AU, it is a 16550 with a quirk */
974 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
975 up->bugs |= UART_BUG_NOMSR;
976 #endif
977
978 serial_outp(up, UART_LCR, save_lcr);
979
980 if (up->capabilities != uart_config[up->port.type].flags) {
981 printk(KERN_WARNING
982 "ttyS%d: detected caps %08x should be %08x\n",
983 up->port.line, up->capabilities,
984 uart_config[up->port.type].flags);
985 }
986
987 up->port.fifosize = uart_config[up->port.type].fifo_size;
988 up->capabilities = uart_config[up->port.type].flags;
989 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
990
991 if (up->port.type == PORT_UNKNOWN)
992 goto out;
993
994 /*
995 * Reset the UART.
996 */
997 #ifdef CONFIG_SERIAL_8250_RSA
998 if (up->port.type == PORT_RSA)
999 serial_outp(up, UART_RSA_FRR, 0);
1000 #endif
1001 serial_outp(up, UART_MCR, save_mcr);
1002 serial8250_clear_fifos(up);
1003 (void)serial_in(up, UART_RX);
1004 if (up->capabilities & UART_CAP_UUE)
1005 serial_outp(up, UART_IER, UART_IER_UUE);
1006 else
1007 serial_outp(up, UART_IER, 0);
1008
1009 out:
1010 spin_unlock_irqrestore(&up->port.lock, flags);
1011 // restore_flags(flags);
1012 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1013 }
1014
1015 static void autoconfig_irq(struct uart_8250_port *up)
1016 {
1017 unsigned char save_mcr, save_ier;
1018 unsigned char save_ICP = 0;
1019 unsigned int ICP = 0;
1020 unsigned long irqs;
1021 int irq;
1022
1023 if (up->port.flags & UPF_FOURPORT) {
1024 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1025 save_ICP = inb_p(ICP);
1026 outb_p(0x80, ICP);
1027 (void) inb_p(ICP);
1028 }
1029
1030 /* forget possible initially masked and pending IRQ */
1031 probe_irq_off(probe_irq_on());
1032 save_mcr = serial_inp(up, UART_MCR);
1033 save_ier = serial_inp(up, UART_IER);
1034 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1035
1036 irqs = probe_irq_on();
1037 serial_outp(up, UART_MCR, 0);
1038 udelay (10);
1039 if (up->port.flags & UPF_FOURPORT) {
1040 serial_outp(up, UART_MCR,
1041 UART_MCR_DTR | UART_MCR_RTS);
1042 } else {
1043 serial_outp(up, UART_MCR,
1044 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1045 }
1046 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1047 (void)serial_inp(up, UART_LSR);
1048 (void)serial_inp(up, UART_RX);
1049 (void)serial_inp(up, UART_IIR);
1050 (void)serial_inp(up, UART_MSR);
1051 serial_outp(up, UART_TX, 0xFF);
1052 udelay (20);
1053 irq = probe_irq_off(irqs);
1054
1055 serial_outp(up, UART_MCR, save_mcr);
1056 serial_outp(up, UART_IER, save_ier);
1057
1058 if (up->port.flags & UPF_FOURPORT)
1059 outb_p(save_ICP, ICP);
1060
1061 up->port.irq = (irq > 0) ? irq : 0;
1062 }
1063
1064 static inline void __stop_tx(struct uart_8250_port *p)
1065 {
1066 if (p->ier & UART_IER_THRI) {
1067 p->ier &= ~UART_IER_THRI;
1068 serial_out(p, UART_IER, p->ier);
1069 }
1070 }
1071
1072 static void serial8250_stop_tx(struct uart_port *port)
1073 {
1074 struct uart_8250_port *up = (struct uart_8250_port *)port;
1075
1076 __stop_tx(up);
1077
1078 /*
1079 * We really want to stop the transmitter from sending.
1080 */
1081 if (up->port.type == PORT_16C950) {
1082 up->acr |= UART_ACR_TXDIS;
1083 serial_icr_write(up, UART_ACR, up->acr);
1084 }
1085 }
1086
1087 static void transmit_chars(struct uart_8250_port *up);
1088
1089 static void serial8250_start_tx(struct uart_port *port)
1090 {
1091 struct uart_8250_port *up = (struct uart_8250_port *)port;
1092
1093 if (!(up->ier & UART_IER_THRI)) {
1094 up->ier |= UART_IER_THRI;
1095 serial_out(up, UART_IER, up->ier);
1096
1097 if (up->bugs & UART_BUG_TXEN) {
1098 unsigned char lsr, iir;
1099 lsr = serial_in(up, UART_LSR);
1100 iir = serial_in(up, UART_IIR);
1101 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1102 transmit_chars(up);
1103 }
1104 }
1105
1106 /*
1107 * Re-enable the transmitter if we disabled it.
1108 */
1109 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1110 up->acr &= ~UART_ACR_TXDIS;
1111 serial_icr_write(up, UART_ACR, up->acr);
1112 }
1113 }
1114
1115 static void serial8250_stop_rx(struct uart_port *port)
1116 {
1117 struct uart_8250_port *up = (struct uart_8250_port *)port;
1118
1119 up->ier &= ~UART_IER_RLSI;
1120 up->port.read_status_mask &= ~UART_LSR_DR;
1121 serial_out(up, UART_IER, up->ier);
1122 }
1123
1124 static void serial8250_enable_ms(struct uart_port *port)
1125 {
1126 struct uart_8250_port *up = (struct uart_8250_port *)port;
1127
1128 /* no MSR capabilities */
1129 if (up->bugs & UART_BUG_NOMSR)
1130 return;
1131
1132 up->ier |= UART_IER_MSI;
1133 serial_out(up, UART_IER, up->ier);
1134 }
1135
1136 static void
1137 receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1138 {
1139 struct tty_struct *tty = up->port.info->tty;
1140 unsigned char ch, lsr = *status;
1141 int max_count = 256;
1142 char flag;
1143
1144 do {
1145 ch = serial_inp(up, UART_RX);
1146 flag = TTY_NORMAL;
1147 up->port.icount.rx++;
1148
1149 #ifdef CONFIG_SERIAL_8250_CONSOLE
1150 /*
1151 * Recover the break flag from console xmit
1152 */
1153 if (up->port.line == up->port.cons->index) {
1154 lsr |= up->lsr_break_flag;
1155 up->lsr_break_flag = 0;
1156 }
1157 #endif
1158
1159 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1160 UART_LSR_FE | UART_LSR_OE))) {
1161 /*
1162 * For statistics only
1163 */
1164 if (lsr & UART_LSR_BI) {
1165 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1166 up->port.icount.brk++;
1167 /*
1168 * We do the SysRQ and SAK checking
1169 * here because otherwise the break
1170 * may get masked by ignore_status_mask
1171 * or read_status_mask.
1172 */
1173 if (uart_handle_break(&up->port))
1174 goto ignore_char;
1175 } else if (lsr & UART_LSR_PE)
1176 up->port.icount.parity++;
1177 else if (lsr & UART_LSR_FE)
1178 up->port.icount.frame++;
1179 if (lsr & UART_LSR_OE)
1180 up->port.icount.overrun++;
1181
1182 /*
1183 * Mask off conditions which should be ignored.
1184 */
1185 lsr &= up->port.read_status_mask;
1186
1187 if (lsr & UART_LSR_BI) {
1188 DEBUG_INTR("handling break....");
1189 flag = TTY_BREAK;
1190 } else if (lsr & UART_LSR_PE)
1191 flag = TTY_PARITY;
1192 else if (lsr & UART_LSR_FE)
1193 flag = TTY_FRAME;
1194 }
1195 if (uart_handle_sysrq_char(&up->port, ch, regs))
1196 goto ignore_char;
1197
1198 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1199
1200 ignore_char:
1201 lsr = serial_inp(up, UART_LSR);
1202 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1203 spin_unlock(&up->port.lock);
1204 tty_flip_buffer_push(tty);
1205 spin_lock(&up->port.lock);
1206 *status = lsr;
1207 }
1208
1209 static void transmit_chars(struct uart_8250_port *up)
1210 {
1211 struct circ_buf *xmit = &up->port.info->xmit;
1212 int count;
1213
1214 if (up->port.x_char) {
1215 serial_outp(up, UART_TX, up->port.x_char);
1216 up->port.icount.tx++;
1217 up->port.x_char = 0;
1218 return;
1219 }
1220 if (uart_tx_stopped(&up->port)) {
1221 serial8250_stop_tx(&up->port);
1222 return;
1223 }
1224 if (uart_circ_empty(xmit)) {
1225 __stop_tx(up);
1226 return;
1227 }
1228
1229 count = up->tx_loadsz;
1230 do {
1231 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1232 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1233 up->port.icount.tx++;
1234 if (uart_circ_empty(xmit))
1235 break;
1236 } while (--count > 0);
1237
1238 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1239 uart_write_wakeup(&up->port);
1240
1241 DEBUG_INTR("THRE...");
1242
1243 if (uart_circ_empty(xmit))
1244 __stop_tx(up);
1245 }
1246
1247 static unsigned int check_modem_status(struct uart_8250_port *up)
1248 {
1249 unsigned int status = serial_in(up, UART_MSR);
1250
1251 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI) {
1252 if (status & UART_MSR_TERI)
1253 up->port.icount.rng++;
1254 if (status & UART_MSR_DDSR)
1255 up->port.icount.dsr++;
1256 if (status & UART_MSR_DDCD)
1257 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1258 if (status & UART_MSR_DCTS)
1259 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1260
1261 wake_up_interruptible(&up->port.info->delta_msr_wait);
1262 }
1263
1264 return status;
1265 }
1266
1267 /*
1268 * This handles the interrupt from one port.
1269 */
1270 static inline void
1271 serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1272 {
1273 unsigned int status;
1274
1275 spin_lock(&up->port.lock);
1276
1277 status = serial_inp(up, UART_LSR);
1278
1279 DEBUG_INTR("status = %x...", status);
1280
1281 if (status & UART_LSR_DR)
1282 receive_chars(up, &status, regs);
1283 check_modem_status(up);
1284 if (status & UART_LSR_THRE)
1285 transmit_chars(up);
1286
1287 spin_unlock(&up->port.lock);
1288 }
1289
1290 /*
1291 * This is the serial driver's interrupt routine.
1292 *
1293 * Arjan thinks the old way was overly complex, so it got simplified.
1294 * Alan disagrees, saying that need the complexity to handle the weird
1295 * nature of ISA shared interrupts. (This is a special exception.)
1296 *
1297 * In order to handle ISA shared interrupts properly, we need to check
1298 * that all ports have been serviced, and therefore the ISA interrupt
1299 * line has been de-asserted.
1300 *
1301 * This means we need to loop through all ports. checking that they
1302 * don't have an interrupt pending.
1303 */
1304 static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1305 {
1306 struct irq_info *i = dev_id;
1307 struct list_head *l, *end = NULL;
1308 int pass_counter = 0, handled = 0;
1309
1310 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1311
1312 spin_lock(&i->lock);
1313
1314 l = i->head;
1315 do {
1316 struct uart_8250_port *up;
1317 unsigned int iir;
1318
1319 up = list_entry(l, struct uart_8250_port, list);
1320
1321 iir = serial_in(up, UART_IIR);
1322 if (!(iir & UART_IIR_NO_INT)) {
1323 serial8250_handle_port(up, regs);
1324
1325 handled = 1;
1326
1327 end = NULL;
1328 } else if (end == NULL)
1329 end = l;
1330
1331 l = l->next;
1332
1333 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1334 /* If we hit this, we're dead. */
1335 printk(KERN_ERR "serial8250: too much work for "
1336 "irq%d\n", irq);
1337 break;
1338 }
1339 } while (l != end);
1340
1341 spin_unlock(&i->lock);
1342
1343 DEBUG_INTR("end.\n");
1344
1345 return IRQ_RETVAL(handled);
1346 }
1347
1348 /*
1349 * To support ISA shared interrupts, we need to have one interrupt
1350 * handler that ensures that the IRQ line has been deasserted
1351 * before returning. Failing to do this will result in the IRQ
1352 * line being stuck active, and, since ISA irqs are edge triggered,
1353 * no more IRQs will be seen.
1354 */
1355 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1356 {
1357 spin_lock_irq(&i->lock);
1358
1359 if (!list_empty(i->head)) {
1360 if (i->head == &up->list)
1361 i->head = i->head->next;
1362 list_del(&up->list);
1363 } else {
1364 BUG_ON(i->head != &up->list);
1365 i->head = NULL;
1366 }
1367
1368 spin_unlock_irq(&i->lock);
1369 }
1370
1371 static int serial_link_irq_chain(struct uart_8250_port *up)
1372 {
1373 struct irq_info *i = irq_lists + up->port.irq;
1374 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1375
1376 spin_lock_irq(&i->lock);
1377
1378 if (i->head) {
1379 list_add(&up->list, i->head);
1380 spin_unlock_irq(&i->lock);
1381
1382 ret = 0;
1383 } else {
1384 INIT_LIST_HEAD(&up->list);
1385 i->head = &up->list;
1386 spin_unlock_irq(&i->lock);
1387
1388 ret = request_irq(up->port.irq, serial8250_interrupt,
1389 irq_flags, "serial", i);
1390 if (ret < 0)
1391 serial_do_unlink(i, up);
1392 }
1393
1394 return ret;
1395 }
1396
1397 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1398 {
1399 struct irq_info *i = irq_lists + up->port.irq;
1400
1401 BUG_ON(i->head == NULL);
1402
1403 if (list_empty(i->head))
1404 free_irq(up->port.irq, i);
1405
1406 serial_do_unlink(i, up);
1407 }
1408
1409 /*
1410 * This function is used to handle ports that do not have an
1411 * interrupt. This doesn't work very well for 16450's, but gives
1412 * barely passable results for a 16550A. (Although at the expense
1413 * of much CPU overhead).
1414 */
1415 static void serial8250_timeout(unsigned long data)
1416 {
1417 struct uart_8250_port *up = (struct uart_8250_port *)data;
1418 unsigned int timeout;
1419 unsigned int iir;
1420
1421 iir = serial_in(up, UART_IIR);
1422 if (!(iir & UART_IIR_NO_INT))
1423 serial8250_handle_port(up, NULL);
1424
1425 timeout = up->port.timeout;
1426 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1427 mod_timer(&up->timer, jiffies + timeout);
1428 }
1429
1430 static unsigned int serial8250_tx_empty(struct uart_port *port)
1431 {
1432 struct uart_8250_port *up = (struct uart_8250_port *)port;
1433 unsigned long flags;
1434 unsigned int ret;
1435
1436 spin_lock_irqsave(&up->port.lock, flags);
1437 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1438 spin_unlock_irqrestore(&up->port.lock, flags);
1439
1440 return ret;
1441 }
1442
1443 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1444 {
1445 struct uart_8250_port *up = (struct uart_8250_port *)port;
1446 unsigned int status;
1447 unsigned int ret;
1448
1449 status = check_modem_status(up);
1450
1451 ret = 0;
1452 if (status & UART_MSR_DCD)
1453 ret |= TIOCM_CAR;
1454 if (status & UART_MSR_RI)
1455 ret |= TIOCM_RNG;
1456 if (status & UART_MSR_DSR)
1457 ret |= TIOCM_DSR;
1458 if (status & UART_MSR_CTS)
1459 ret |= TIOCM_CTS;
1460 return ret;
1461 }
1462
1463 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1464 {
1465 struct uart_8250_port *up = (struct uart_8250_port *)port;
1466 unsigned char mcr = 0;
1467
1468 if (mctrl & TIOCM_RTS)
1469 mcr |= UART_MCR_RTS;
1470 if (mctrl & TIOCM_DTR)
1471 mcr |= UART_MCR_DTR;
1472 if (mctrl & TIOCM_OUT1)
1473 mcr |= UART_MCR_OUT1;
1474 if (mctrl & TIOCM_OUT2)
1475 mcr |= UART_MCR_OUT2;
1476 if (mctrl & TIOCM_LOOP)
1477 mcr |= UART_MCR_LOOP;
1478
1479 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1480
1481 serial_out(up, UART_MCR, mcr);
1482 }
1483
1484 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1485 {
1486 struct uart_8250_port *up = (struct uart_8250_port *)port;
1487 unsigned long flags;
1488
1489 spin_lock_irqsave(&up->port.lock, flags);
1490 if (break_state == -1)
1491 up->lcr |= UART_LCR_SBC;
1492 else
1493 up->lcr &= ~UART_LCR_SBC;
1494 serial_out(up, UART_LCR, up->lcr);
1495 spin_unlock_irqrestore(&up->port.lock, flags);
1496 }
1497
1498 static int serial8250_startup(struct uart_port *port)
1499 {
1500 struct uart_8250_port *up = (struct uart_8250_port *)port;
1501 unsigned long flags;
1502 unsigned char lsr, iir;
1503 int retval;
1504
1505 up->capabilities = uart_config[up->port.type].flags;
1506 up->mcr = 0;
1507
1508 if (up->port.type == PORT_16C950) {
1509 /* Wake up and initialize UART */
1510 up->acr = 0;
1511 serial_outp(up, UART_LCR, 0xBF);
1512 serial_outp(up, UART_EFR, UART_EFR_ECB);
1513 serial_outp(up, UART_IER, 0);
1514 serial_outp(up, UART_LCR, 0);
1515 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1516 serial_outp(up, UART_LCR, 0xBF);
1517 serial_outp(up, UART_EFR, UART_EFR_ECB);
1518 serial_outp(up, UART_LCR, 0);
1519 }
1520
1521 #ifdef CONFIG_SERIAL_8250_RSA
1522 /*
1523 * If this is an RSA port, see if we can kick it up to the
1524 * higher speed clock.
1525 */
1526 enable_rsa(up);
1527 #endif
1528
1529 /*
1530 * Clear the FIFO buffers and disable them.
1531 * (they will be reenabled in set_termios())
1532 */
1533 serial8250_clear_fifos(up);
1534
1535 /*
1536 * Clear the interrupt registers.
1537 */
1538 (void) serial_inp(up, UART_LSR);
1539 (void) serial_inp(up, UART_RX);
1540 (void) serial_inp(up, UART_IIR);
1541 (void) serial_inp(up, UART_MSR);
1542
1543 /*
1544 * At this point, there's no way the LSR could still be 0xff;
1545 * if it is, then bail out, because there's likely no UART
1546 * here.
1547 */
1548 if (!(up->port.flags & UPF_BUGGY_UART) &&
1549 (serial_inp(up, UART_LSR) == 0xff)) {
1550 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1551 return -ENODEV;
1552 }
1553
1554 /*
1555 * For a XR16C850, we need to set the trigger levels
1556 */
1557 if (up->port.type == PORT_16850) {
1558 unsigned char fctr;
1559
1560 serial_outp(up, UART_LCR, 0xbf);
1561
1562 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1563 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1564 serial_outp(up, UART_TRG, UART_TRG_96);
1565 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1566 serial_outp(up, UART_TRG, UART_TRG_96);
1567
1568 serial_outp(up, UART_LCR, 0);
1569 }
1570
1571 /*
1572 * If the "interrupt" for this port doesn't correspond with any
1573 * hardware interrupt, we use a timer-based system. The original
1574 * driver used to do this with IRQ0.
1575 */
1576 if (!is_real_interrupt(up->port.irq)) {
1577 unsigned int timeout = up->port.timeout;
1578
1579 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1580
1581 up->timer.data = (unsigned long)up;
1582 mod_timer(&up->timer, jiffies + timeout);
1583 } else {
1584 retval = serial_link_irq_chain(up);
1585 if (retval)
1586 return retval;
1587 }
1588
1589 /*
1590 * Now, initialize the UART
1591 */
1592 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1593
1594 spin_lock_irqsave(&up->port.lock, flags);
1595 if (up->port.flags & UPF_FOURPORT) {
1596 if (!is_real_interrupt(up->port.irq))
1597 up->port.mctrl |= TIOCM_OUT1;
1598 } else
1599 /*
1600 * Most PC uarts need OUT2 raised to enable interrupts.
1601 */
1602 if (is_real_interrupt(up->port.irq))
1603 up->port.mctrl |= TIOCM_OUT2;
1604
1605 serial8250_set_mctrl(&up->port, up->port.mctrl);
1606
1607 /*
1608 * Do a quick test to see if we receive an
1609 * interrupt when we enable the TX irq.
1610 */
1611 serial_outp(up, UART_IER, UART_IER_THRI);
1612 lsr = serial_in(up, UART_LSR);
1613 iir = serial_in(up, UART_IIR);
1614 serial_outp(up, UART_IER, 0);
1615
1616 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1617 if (!(up->bugs & UART_BUG_TXEN)) {
1618 up->bugs |= UART_BUG_TXEN;
1619 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1620 port->line);
1621 }
1622 } else {
1623 up->bugs &= ~UART_BUG_TXEN;
1624 }
1625
1626 spin_unlock_irqrestore(&up->port.lock, flags);
1627
1628 /*
1629 * Finally, enable interrupts. Note: Modem status interrupts
1630 * are set via set_termios(), which will be occurring imminently
1631 * anyway, so we don't enable them here.
1632 */
1633 up->ier = UART_IER_RLSI | UART_IER_RDI;
1634 serial_outp(up, UART_IER, up->ier);
1635
1636 if (up->port.flags & UPF_FOURPORT) {
1637 unsigned int icp;
1638 /*
1639 * Enable interrupts on the AST Fourport board
1640 */
1641 icp = (up->port.iobase & 0xfe0) | 0x01f;
1642 outb_p(0x80, icp);
1643 (void) inb_p(icp);
1644 }
1645
1646 /*
1647 * And clear the interrupt registers again for luck.
1648 */
1649 (void) serial_inp(up, UART_LSR);
1650 (void) serial_inp(up, UART_RX);
1651 (void) serial_inp(up, UART_IIR);
1652 (void) serial_inp(up, UART_MSR);
1653
1654 return 0;
1655 }
1656
1657 static void serial8250_shutdown(struct uart_port *port)
1658 {
1659 struct uart_8250_port *up = (struct uart_8250_port *)port;
1660 unsigned long flags;
1661
1662 /*
1663 * Disable interrupts from this port
1664 */
1665 up->ier = 0;
1666 serial_outp(up, UART_IER, 0);
1667
1668 spin_lock_irqsave(&up->port.lock, flags);
1669 if (up->port.flags & UPF_FOURPORT) {
1670 /* reset interrupts on the AST Fourport board */
1671 inb((up->port.iobase & 0xfe0) | 0x1f);
1672 up->port.mctrl |= TIOCM_OUT1;
1673 } else
1674 up->port.mctrl &= ~TIOCM_OUT2;
1675
1676 serial8250_set_mctrl(&up->port, up->port.mctrl);
1677 spin_unlock_irqrestore(&up->port.lock, flags);
1678
1679 /*
1680 * Disable break condition and FIFOs
1681 */
1682 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1683 serial8250_clear_fifos(up);
1684
1685 #ifdef CONFIG_SERIAL_8250_RSA
1686 /*
1687 * Reset the RSA board back to 115kbps compat mode.
1688 */
1689 disable_rsa(up);
1690 #endif
1691
1692 /*
1693 * Read data port to reset things, and then unlink from
1694 * the IRQ chain.
1695 */
1696 (void) serial_in(up, UART_RX);
1697
1698 if (!is_real_interrupt(up->port.irq))
1699 del_timer_sync(&up->timer);
1700 else
1701 serial_unlink_irq_chain(up);
1702 }
1703
1704 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1705 {
1706 unsigned int quot;
1707
1708 /*
1709 * Handle magic divisors for baud rates above baud_base on
1710 * SMSC SuperIO chips.
1711 */
1712 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1713 baud == (port->uartclk/4))
1714 quot = 0x8001;
1715 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1716 baud == (port->uartclk/8))
1717 quot = 0x8002;
1718 else
1719 quot = uart_get_divisor(port, baud);
1720
1721 return quot;
1722 }
1723
1724 static void
1725 serial8250_set_termios(struct uart_port *port, struct termios *termios,
1726 struct termios *old)
1727 {
1728 struct uart_8250_port *up = (struct uart_8250_port *)port;
1729 unsigned char cval, fcr = 0;
1730 unsigned long flags;
1731 unsigned int baud, quot;
1732
1733 switch (termios->c_cflag & CSIZE) {
1734 case CS5:
1735 cval = UART_LCR_WLEN5;
1736 break;
1737 case CS6:
1738 cval = UART_LCR_WLEN6;
1739 break;
1740 case CS7:
1741 cval = UART_LCR_WLEN7;
1742 break;
1743 default:
1744 case CS8:
1745 cval = UART_LCR_WLEN8;
1746 break;
1747 }
1748
1749 if (termios->c_cflag & CSTOPB)
1750 cval |= UART_LCR_STOP;
1751 if (termios->c_cflag & PARENB)
1752 cval |= UART_LCR_PARITY;
1753 if (!(termios->c_cflag & PARODD))
1754 cval |= UART_LCR_EPAR;
1755 #ifdef CMSPAR
1756 if (termios->c_cflag & CMSPAR)
1757 cval |= UART_LCR_SPAR;
1758 #endif
1759
1760 /*
1761 * Ask the core to calculate the divisor for us.
1762 */
1763 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1764 quot = serial8250_get_divisor(port, baud);
1765
1766 /*
1767 * Oxford Semi 952 rev B workaround
1768 */
1769 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1770 quot ++;
1771
1772 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1773 if (baud < 2400)
1774 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1775 else
1776 fcr = uart_config[up->port.type].fcr;
1777 }
1778
1779 /*
1780 * MCR-based auto flow control. When AFE is enabled, RTS will be
1781 * deasserted when the receive FIFO contains more characters than
1782 * the trigger, or the MCR RTS bit is cleared. In the case where
1783 * the remote UART is not using CTS auto flow control, we must
1784 * have sufficient FIFO entries for the latency of the remote
1785 * UART to respond. IOW, at least 32 bytes of FIFO.
1786 */
1787 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1788 up->mcr &= ~UART_MCR_AFE;
1789 if (termios->c_cflag & CRTSCTS)
1790 up->mcr |= UART_MCR_AFE;
1791 }
1792
1793 /*
1794 * Ok, we're now changing the port state. Do it with
1795 * interrupts disabled.
1796 */
1797 spin_lock_irqsave(&up->port.lock, flags);
1798
1799 /*
1800 * Update the per-port timeout.
1801 */
1802 uart_update_timeout(port, termios->c_cflag, baud);
1803
1804 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1805 if (termios->c_iflag & INPCK)
1806 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1807 if (termios->c_iflag & (BRKINT | PARMRK))
1808 up->port.read_status_mask |= UART_LSR_BI;
1809
1810 /*
1811 * Characteres to ignore
1812 */
1813 up->port.ignore_status_mask = 0;
1814 if (termios->c_iflag & IGNPAR)
1815 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1816 if (termios->c_iflag & IGNBRK) {
1817 up->port.ignore_status_mask |= UART_LSR_BI;
1818 /*
1819 * If we're ignoring parity and break indicators,
1820 * ignore overruns too (for real raw support).
1821 */
1822 if (termios->c_iflag & IGNPAR)
1823 up->port.ignore_status_mask |= UART_LSR_OE;
1824 }
1825
1826 /*
1827 * ignore all characters if CREAD is not set
1828 */
1829 if ((termios->c_cflag & CREAD) == 0)
1830 up->port.ignore_status_mask |= UART_LSR_DR;
1831
1832 /*
1833 * CTS flow control flag and modem status interrupts
1834 */
1835 up->ier &= ~UART_IER_MSI;
1836 if (!(up->bugs & UART_BUG_NOMSR) &&
1837 UART_ENABLE_MS(&up->port, termios->c_cflag))
1838 up->ier |= UART_IER_MSI;
1839 if (up->capabilities & UART_CAP_UUE)
1840 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1841
1842 serial_out(up, UART_IER, up->ier);
1843
1844 if (up->capabilities & UART_CAP_EFR) {
1845 unsigned char efr = 0;
1846 /*
1847 * TI16C752/Startech hardware flow control. FIXME:
1848 * - TI16C752 requires control thresholds to be set.
1849 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1850 */
1851 if (termios->c_cflag & CRTSCTS)
1852 efr |= UART_EFR_CTS;
1853
1854 serial_outp(up, UART_LCR, 0xBF);
1855 serial_outp(up, UART_EFR, efr);
1856 }
1857
1858 if (up->capabilities & UART_NATSEMI) {
1859 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1860 serial_outp(up, UART_LCR, 0xe0);
1861 } else {
1862 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1863 }
1864
1865 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
1866 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
1867
1868 /*
1869 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1870 * is written without DLAB set, this mode will be disabled.
1871 */
1872 if (up->port.type == PORT_16750)
1873 serial_outp(up, UART_FCR, fcr);
1874
1875 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1876 up->lcr = cval; /* Save LCR */
1877 if (up->port.type != PORT_16750) {
1878 if (fcr & UART_FCR_ENABLE_FIFO) {
1879 /* emulated UARTs (Lucent Venus 167x) need two steps */
1880 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1881 }
1882 serial_outp(up, UART_FCR, fcr); /* set fcr */
1883 }
1884 serial8250_set_mctrl(&up->port, up->port.mctrl);
1885 spin_unlock_irqrestore(&up->port.lock, flags);
1886 }
1887
1888 static void
1889 serial8250_pm(struct uart_port *port, unsigned int state,
1890 unsigned int oldstate)
1891 {
1892 struct uart_8250_port *p = (struct uart_8250_port *)port;
1893
1894 serial8250_set_sleep(p, state != 0);
1895
1896 if (p->pm)
1897 p->pm(port, state, oldstate);
1898 }
1899
1900 /*
1901 * Resource handling.
1902 */
1903 static int serial8250_request_std_resource(struct uart_8250_port *up)
1904 {
1905 unsigned int size = 8 << up->port.regshift;
1906 int ret = 0;
1907
1908 switch (up->port.iotype) {
1909 case UPIO_AU:
1910 size = 0x100000;
1911 /* fall thru */
1912 case UPIO_MEM:
1913 if (!up->port.mapbase)
1914 break;
1915
1916 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1917 ret = -EBUSY;
1918 break;
1919 }
1920
1921 if (up->port.flags & UPF_IOREMAP) {
1922 up->port.membase = ioremap(up->port.mapbase, size);
1923 if (!up->port.membase) {
1924 release_mem_region(up->port.mapbase, size);
1925 ret = -ENOMEM;
1926 }
1927 }
1928 break;
1929
1930 case UPIO_HUB6:
1931 case UPIO_PORT:
1932 if (!request_region(up->port.iobase, size, "serial"))
1933 ret = -EBUSY;
1934 break;
1935 }
1936 return ret;
1937 }
1938
1939 static void serial8250_release_std_resource(struct uart_8250_port *up)
1940 {
1941 unsigned int size = 8 << up->port.regshift;
1942
1943 switch (up->port.iotype) {
1944 case UPIO_AU:
1945 size = 0x100000;
1946 /* fall thru */
1947 case UPIO_MEM:
1948 if (!up->port.mapbase)
1949 break;
1950
1951 if (up->port.flags & UPF_IOREMAP) {
1952 iounmap(up->port.membase);
1953 up->port.membase = NULL;
1954 }
1955
1956 release_mem_region(up->port.mapbase, size);
1957 break;
1958
1959 case UPIO_HUB6:
1960 case UPIO_PORT:
1961 release_region(up->port.iobase, size);
1962 break;
1963 }
1964 }
1965
1966 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1967 {
1968 unsigned long start = UART_RSA_BASE << up->port.regshift;
1969 unsigned int size = 8 << up->port.regshift;
1970 int ret = 0;
1971
1972 switch (up->port.iotype) {
1973 case UPIO_MEM:
1974 ret = -EINVAL;
1975 break;
1976
1977 case UPIO_HUB6:
1978 case UPIO_PORT:
1979 start += up->port.iobase;
1980 if (!request_region(start, size, "serial-rsa"))
1981 ret = -EBUSY;
1982 break;
1983 }
1984
1985 return ret;
1986 }
1987
1988 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
1989 {
1990 unsigned long offset = UART_RSA_BASE << up->port.regshift;
1991 unsigned int size = 8 << up->port.regshift;
1992
1993 switch (up->port.iotype) {
1994 case UPIO_MEM:
1995 break;
1996
1997 case UPIO_HUB6:
1998 case UPIO_PORT:
1999 release_region(up->port.iobase + offset, size);
2000 break;
2001 }
2002 }
2003
2004 static void serial8250_release_port(struct uart_port *port)
2005 {
2006 struct uart_8250_port *up = (struct uart_8250_port *)port;
2007
2008 serial8250_release_std_resource(up);
2009 if (up->port.type == PORT_RSA)
2010 serial8250_release_rsa_resource(up);
2011 }
2012
2013 static int serial8250_request_port(struct uart_port *port)
2014 {
2015 struct uart_8250_port *up = (struct uart_8250_port *)port;
2016 int ret = 0;
2017
2018 ret = serial8250_request_std_resource(up);
2019 if (ret == 0 && up->port.type == PORT_RSA) {
2020 ret = serial8250_request_rsa_resource(up);
2021 if (ret < 0)
2022 serial8250_release_std_resource(up);
2023 }
2024
2025 return ret;
2026 }
2027
2028 static void serial8250_config_port(struct uart_port *port, int flags)
2029 {
2030 struct uart_8250_port *up = (struct uart_8250_port *)port;
2031 int probeflags = PROBE_ANY;
2032 int ret;
2033
2034 /*
2035 * Find the region that we can probe for. This in turn
2036 * tells us whether we can probe for the type of port.
2037 */
2038 ret = serial8250_request_std_resource(up);
2039 if (ret < 0)
2040 return;
2041
2042 ret = serial8250_request_rsa_resource(up);
2043 if (ret < 0)
2044 probeflags &= ~PROBE_RSA;
2045
2046 if (flags & UART_CONFIG_TYPE)
2047 autoconfig(up, probeflags);
2048 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2049 autoconfig_irq(up);
2050
2051 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2052 serial8250_release_rsa_resource(up);
2053 if (up->port.type == PORT_UNKNOWN)
2054 serial8250_release_std_resource(up);
2055 }
2056
2057 static int
2058 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2059 {
2060 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2061 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2062 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2063 ser->type == PORT_STARTECH)
2064 return -EINVAL;
2065 return 0;
2066 }
2067
2068 static const char *
2069 serial8250_type(struct uart_port *port)
2070 {
2071 int type = port->type;
2072
2073 if (type >= ARRAY_SIZE(uart_config))
2074 type = 0;
2075 return uart_config[type].name;
2076 }
2077
2078 static struct uart_ops serial8250_pops = {
2079 .tx_empty = serial8250_tx_empty,
2080 .set_mctrl = serial8250_set_mctrl,
2081 .get_mctrl = serial8250_get_mctrl,
2082 .stop_tx = serial8250_stop_tx,
2083 .start_tx = serial8250_start_tx,
2084 .stop_rx = serial8250_stop_rx,
2085 .enable_ms = serial8250_enable_ms,
2086 .break_ctl = serial8250_break_ctl,
2087 .startup = serial8250_startup,
2088 .shutdown = serial8250_shutdown,
2089 .set_termios = serial8250_set_termios,
2090 .pm = serial8250_pm,
2091 .type = serial8250_type,
2092 .release_port = serial8250_release_port,
2093 .request_port = serial8250_request_port,
2094 .config_port = serial8250_config_port,
2095 .verify_port = serial8250_verify_port,
2096 };
2097
2098 static struct uart_8250_port serial8250_ports[UART_NR];
2099
2100 static void __init serial8250_isa_init_ports(void)
2101 {
2102 struct uart_8250_port *up;
2103 static int first = 1;
2104 int i;
2105
2106 if (!first)
2107 return;
2108 first = 0;
2109
2110 for (i = 0; i < nr_uarts; i++) {
2111 struct uart_8250_port *up = &serial8250_ports[i];
2112
2113 up->port.line = i;
2114 spin_lock_init(&up->port.lock);
2115
2116 init_timer(&up->timer);
2117 up->timer.function = serial8250_timeout;
2118
2119 /*
2120 * ALPHA_KLUDGE_MCR needs to be killed.
2121 */
2122 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2123 up->mcr_force = ALPHA_KLUDGE_MCR;
2124
2125 up->port.ops = &serial8250_pops;
2126 }
2127
2128 for (i = 0, up = serial8250_ports;
2129 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2130 i++, up++) {
2131 up->port.iobase = old_serial_port[i].port;
2132 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2133 up->port.uartclk = old_serial_port[i].baud_base * 16;
2134 up->port.flags = old_serial_port[i].flags;
2135 up->port.hub6 = old_serial_port[i].hub6;
2136 up->port.membase = old_serial_port[i].iomem_base;
2137 up->port.iotype = old_serial_port[i].io_type;
2138 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2139 if (share_irqs)
2140 up->port.flags |= UPF_SHARE_IRQ;
2141 }
2142 }
2143
2144 static void __init
2145 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2146 {
2147 int i;
2148
2149 serial8250_isa_init_ports();
2150
2151 for (i = 0; i < nr_uarts; i++) {
2152 struct uart_8250_port *up = &serial8250_ports[i];
2153
2154 up->port.dev = dev;
2155 uart_add_one_port(drv, &up->port);
2156 }
2157 }
2158
2159 #ifdef CONFIG_SERIAL_8250_CONSOLE
2160
2161 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2162
2163 /*
2164 * Wait for transmitter & holding register to empty
2165 */
2166 static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
2167 {
2168 unsigned int status, tmout = 10000;
2169
2170 /* Wait up to 10ms for the character(s) to be sent. */
2171 do {
2172 status = serial_in(up, UART_LSR);
2173
2174 if (status & UART_LSR_BI)
2175 up->lsr_break_flag = UART_LSR_BI;
2176
2177 if (--tmout == 0)
2178 break;
2179 udelay(1);
2180 } while ((status & bits) != bits);
2181
2182 /* Wait up to 1s for flow control if necessary */
2183 if (up->port.flags & UPF_CONS_FLOW) {
2184 tmout = 1000000;
2185 while (--tmout &&
2186 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2187 udelay(1);
2188 }
2189 }
2190
2191 static void serial8250_console_putchar(struct uart_port *port, int ch)
2192 {
2193 struct uart_8250_port *up = (struct uart_8250_port *)port;
2194
2195 wait_for_xmitr(up, UART_LSR_THRE);
2196 serial_out(up, UART_TX, ch);
2197 }
2198
2199 /*
2200 * Print a string to the serial port trying not to disturb
2201 * any possible real use of the port...
2202 *
2203 * The console_lock must be held when we get here.
2204 */
2205 static void
2206 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2207 {
2208 struct uart_8250_port *up = &serial8250_ports[co->index];
2209 unsigned int ier;
2210
2211 touch_nmi_watchdog();
2212
2213 /*
2214 * First save the IER then disable the interrupts
2215 */
2216 ier = serial_in(up, UART_IER);
2217
2218 if (up->capabilities & UART_CAP_UUE)
2219 serial_out(up, UART_IER, UART_IER_UUE);
2220 else
2221 serial_out(up, UART_IER, 0);
2222
2223 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2224
2225 /*
2226 * Finally, wait for transmitter to become empty
2227 * and restore the IER
2228 */
2229 wait_for_xmitr(up, BOTH_EMPTY);
2230 up->ier |= UART_IER_THRI;
2231 serial_out(up, UART_IER, ier | UART_IER_THRI);
2232 }
2233
2234 static int serial8250_console_setup(struct console *co, char *options)
2235 {
2236 struct uart_port *port;
2237 int baud = 9600;
2238 int bits = 8;
2239 int parity = 'n';
2240 int flow = 'n';
2241
2242 /*
2243 * Check whether an invalid uart number has been specified, and
2244 * if so, search for the first available port that does have
2245 * console support.
2246 */
2247 if (co->index >= nr_uarts)
2248 co->index = 0;
2249 port = &serial8250_ports[co->index].port;
2250 if (!port->iobase && !port->membase)
2251 return -ENODEV;
2252
2253 if (options)
2254 uart_parse_options(options, &baud, &parity, &bits, &flow);
2255
2256 return uart_set_options(port, co, baud, parity, bits, flow);
2257 }
2258
2259 static struct uart_driver serial8250_reg;
2260 static struct console serial8250_console = {
2261 .name = "ttyS",
2262 .write = serial8250_console_write,
2263 .device = uart_console_device,
2264 .setup = serial8250_console_setup,
2265 .flags = CON_PRINTBUFFER,
2266 .index = -1,
2267 .data = &serial8250_reg,
2268 };
2269
2270 static int __init serial8250_console_init(void)
2271 {
2272 serial8250_isa_init_ports();
2273 register_console(&serial8250_console);
2274 return 0;
2275 }
2276 console_initcall(serial8250_console_init);
2277
2278 static int __init find_port(struct uart_port *p)
2279 {
2280 int line;
2281 struct uart_port *port;
2282
2283 for (line = 0; line < nr_uarts; line++) {
2284 port = &serial8250_ports[line].port;
2285 if (uart_match_port(p, port))
2286 return line;
2287 }
2288 return -ENODEV;
2289 }
2290
2291 int __init serial8250_start_console(struct uart_port *port, char *options)
2292 {
2293 int line;
2294
2295 line = find_port(port);
2296 if (line < 0)
2297 return -ENODEV;
2298
2299 add_preferred_console("ttyS", line, options);
2300 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2301 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2302 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2303 (unsigned long) port->iobase, options);
2304 if (!(serial8250_console.flags & CON_ENABLED)) {
2305 serial8250_console.flags &= ~CON_PRINTBUFFER;
2306 register_console(&serial8250_console);
2307 }
2308 return line;
2309 }
2310
2311 #define SERIAL8250_CONSOLE &serial8250_console
2312 #else
2313 #define SERIAL8250_CONSOLE NULL
2314 #endif
2315
2316 static struct uart_driver serial8250_reg = {
2317 .owner = THIS_MODULE,
2318 .driver_name = "serial",
2319 .devfs_name = "tts/",
2320 .dev_name = "ttyS",
2321 .major = TTY_MAJOR,
2322 .minor = 64,
2323 .nr = UART_NR,
2324 .cons = SERIAL8250_CONSOLE,
2325 };
2326
2327 /*
2328 * early_serial_setup - early registration for 8250 ports
2329 *
2330 * Setup an 8250 port structure prior to console initialisation. Use
2331 * after console initialisation will cause undefined behaviour.
2332 */
2333 int __init early_serial_setup(struct uart_port *port)
2334 {
2335 if (port->line >= ARRAY_SIZE(serial8250_ports))
2336 return -ENODEV;
2337
2338 serial8250_isa_init_ports();
2339 serial8250_ports[port->line].port = *port;
2340 serial8250_ports[port->line].port.ops = &serial8250_pops;
2341 return 0;
2342 }
2343
2344 /**
2345 * serial8250_suspend_port - suspend one serial port
2346 * @line: serial line number
2347 * @level: the level of port suspension, as per uart_suspend_port
2348 *
2349 * Suspend one serial port.
2350 */
2351 void serial8250_suspend_port(int line)
2352 {
2353 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2354 }
2355
2356 /**
2357 * serial8250_resume_port - resume one serial port
2358 * @line: serial line number
2359 * @level: the level of port resumption, as per uart_resume_port
2360 *
2361 * Resume one serial port.
2362 */
2363 void serial8250_resume_port(int line)
2364 {
2365 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2366 }
2367
2368 /*
2369 * Register a set of serial devices attached to a platform device. The
2370 * list is terminated with a zero flags entry, which means we expect
2371 * all entries to have at least UPF_BOOT_AUTOCONF set.
2372 */
2373 static int __devinit serial8250_probe(struct platform_device *dev)
2374 {
2375 struct plat_serial8250_port *p = dev->dev.platform_data;
2376 struct uart_port port;
2377 int ret, i;
2378
2379 memset(&port, 0, sizeof(struct uart_port));
2380
2381 for (i = 0; p && p->flags != 0; p++, i++) {
2382 port.iobase = p->iobase;
2383 port.membase = p->membase;
2384 port.irq = p->irq;
2385 port.uartclk = p->uartclk;
2386 port.regshift = p->regshift;
2387 port.iotype = p->iotype;
2388 port.flags = p->flags;
2389 port.mapbase = p->mapbase;
2390 port.hub6 = p->hub6;
2391 port.dev = &dev->dev;
2392 if (share_irqs)
2393 port.flags |= UPF_SHARE_IRQ;
2394 ret = serial8250_register_port(&port);
2395 if (ret < 0) {
2396 dev_err(&dev->dev, "unable to register port at index %d "
2397 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2398 p->iobase, p->mapbase, p->irq, ret);
2399 }
2400 }
2401 return 0;
2402 }
2403
2404 /*
2405 * Remove serial ports registered against a platform device.
2406 */
2407 static int __devexit serial8250_remove(struct platform_device *dev)
2408 {
2409 int i;
2410
2411 for (i = 0; i < nr_uarts; i++) {
2412 struct uart_8250_port *up = &serial8250_ports[i];
2413
2414 if (up->port.dev == &dev->dev)
2415 serial8250_unregister_port(i);
2416 }
2417 return 0;
2418 }
2419
2420 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2421 {
2422 int i;
2423
2424 for (i = 0; i < UART_NR; i++) {
2425 struct uart_8250_port *up = &serial8250_ports[i];
2426
2427 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2428 uart_suspend_port(&serial8250_reg, &up->port);
2429 }
2430
2431 return 0;
2432 }
2433
2434 static int serial8250_resume(struct platform_device *dev)
2435 {
2436 int i;
2437
2438 for (i = 0; i < UART_NR; i++) {
2439 struct uart_8250_port *up = &serial8250_ports[i];
2440
2441 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2442 uart_resume_port(&serial8250_reg, &up->port);
2443 }
2444
2445 return 0;
2446 }
2447
2448 static struct platform_driver serial8250_isa_driver = {
2449 .probe = serial8250_probe,
2450 .remove = __devexit_p(serial8250_remove),
2451 .suspend = serial8250_suspend,
2452 .resume = serial8250_resume,
2453 .driver = {
2454 .name = "serial8250",
2455 .owner = THIS_MODULE,
2456 },
2457 };
2458
2459 /*
2460 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2461 * in the table in include/asm/serial.h
2462 */
2463 static struct platform_device *serial8250_isa_devs;
2464
2465 /*
2466 * serial8250_register_port and serial8250_unregister_port allows for
2467 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2468 * modems and PCI multiport cards.
2469 */
2470 static DEFINE_MUTEX(serial_mutex);
2471
2472 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2473 {
2474 int i;
2475
2476 /*
2477 * First, find a port entry which matches.
2478 */
2479 for (i = 0; i < nr_uarts; i++)
2480 if (uart_match_port(&serial8250_ports[i].port, port))
2481 return &serial8250_ports[i];
2482
2483 /*
2484 * We didn't find a matching entry, so look for the first
2485 * free entry. We look for one which hasn't been previously
2486 * used (indicated by zero iobase).
2487 */
2488 for (i = 0; i < nr_uarts; i++)
2489 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2490 serial8250_ports[i].port.iobase == 0)
2491 return &serial8250_ports[i];
2492
2493 /*
2494 * That also failed. Last resort is to find any entry which
2495 * doesn't have a real port associated with it.
2496 */
2497 for (i = 0; i < nr_uarts; i++)
2498 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2499 return &serial8250_ports[i];
2500
2501 return NULL;
2502 }
2503
2504 /**
2505 * serial8250_register_port - register a serial port
2506 * @port: serial port template
2507 *
2508 * Configure the serial port specified by the request. If the
2509 * port exists and is in use, it is hung up and unregistered
2510 * first.
2511 *
2512 * The port is then probed and if necessary the IRQ is autodetected
2513 * If this fails an error is returned.
2514 *
2515 * On success the port is ready to use and the line number is returned.
2516 */
2517 int serial8250_register_port(struct uart_port *port)
2518 {
2519 struct uart_8250_port *uart;
2520 int ret = -ENOSPC;
2521
2522 if (port->uartclk == 0)
2523 return -EINVAL;
2524
2525 mutex_lock(&serial_mutex);
2526
2527 uart = serial8250_find_match_or_unused(port);
2528 if (uart) {
2529 uart_remove_one_port(&serial8250_reg, &uart->port);
2530
2531 uart->port.iobase = port->iobase;
2532 uart->port.membase = port->membase;
2533 uart->port.irq = port->irq;
2534 uart->port.uartclk = port->uartclk;
2535 uart->port.fifosize = port->fifosize;
2536 uart->port.regshift = port->regshift;
2537 uart->port.iotype = port->iotype;
2538 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2539 uart->port.mapbase = port->mapbase;
2540 if (port->dev)
2541 uart->port.dev = port->dev;
2542
2543 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2544 if (ret == 0)
2545 ret = uart->port.line;
2546 }
2547 mutex_unlock(&serial_mutex);
2548
2549 return ret;
2550 }
2551 EXPORT_SYMBOL(serial8250_register_port);
2552
2553 /**
2554 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2555 * @line: serial line number
2556 *
2557 * Remove one serial port. This may not be called from interrupt
2558 * context. We hand the port back to the our control.
2559 */
2560 void serial8250_unregister_port(int line)
2561 {
2562 struct uart_8250_port *uart = &serial8250_ports[line];
2563
2564 mutex_lock(&serial_mutex);
2565 uart_remove_one_port(&serial8250_reg, &uart->port);
2566 if (serial8250_isa_devs) {
2567 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2568 uart->port.type = PORT_UNKNOWN;
2569 uart->port.dev = &serial8250_isa_devs->dev;
2570 uart_add_one_port(&serial8250_reg, &uart->port);
2571 } else {
2572 uart->port.dev = NULL;
2573 }
2574 mutex_unlock(&serial_mutex);
2575 }
2576 EXPORT_SYMBOL(serial8250_unregister_port);
2577
2578 static int __init serial8250_init(void)
2579 {
2580 int ret, i;
2581
2582 if (nr_uarts > UART_NR)
2583 nr_uarts = UART_NR;
2584
2585 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2586 "%d ports, IRQ sharing %sabled\n", nr_uarts,
2587 share_irqs ? "en" : "dis");
2588
2589 for (i = 0; i < NR_IRQS; i++)
2590 spin_lock_init(&irq_lists[i].lock);
2591
2592 ret = uart_register_driver(&serial8250_reg);
2593 if (ret)
2594 goto out;
2595
2596 serial8250_isa_devs = platform_device_alloc("serial8250",
2597 PLAT8250_DEV_LEGACY);
2598 if (!serial8250_isa_devs) {
2599 ret = -ENOMEM;
2600 goto unreg_uart_drv;
2601 }
2602
2603 ret = platform_device_add(serial8250_isa_devs);
2604 if (ret)
2605 goto put_dev;
2606
2607 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2608
2609 ret = platform_driver_register(&serial8250_isa_driver);
2610 if (ret == 0)
2611 goto out;
2612
2613 platform_device_del(serial8250_isa_devs);
2614 put_dev:
2615 platform_device_put(serial8250_isa_devs);
2616 unreg_uart_drv:
2617 uart_unregister_driver(&serial8250_reg);
2618 out:
2619 return ret;
2620 }
2621
2622 static void __exit serial8250_exit(void)
2623 {
2624 struct platform_device *isa_dev = serial8250_isa_devs;
2625
2626 /*
2627 * This tells serial8250_unregister_port() not to re-register
2628 * the ports (thereby making serial8250_isa_driver permanently
2629 * in use.)
2630 */
2631 serial8250_isa_devs = NULL;
2632
2633 platform_driver_unregister(&serial8250_isa_driver);
2634 platform_device_unregister(isa_dev);
2635
2636 uart_unregister_driver(&serial8250_reg);
2637 }
2638
2639 module_init(serial8250_init);
2640 module_exit(serial8250_exit);
2641
2642 EXPORT_SYMBOL(serial8250_suspend_port);
2643 EXPORT_SYMBOL(serial8250_resume_port);
2644
2645 MODULE_LICENSE("GPL");
2646 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2647
2648 module_param(share_irqs, uint, 0644);
2649 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2650 " (unsafe)");
2651
2652 module_param(nr_uarts, uint, 0644);
2653 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2654
2655 #ifdef CONFIG_SERIAL_8250_RSA
2656 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2657 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2658 #endif
2659 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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