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c43de35a6c9dcd08b7fa0e5df2950f098f8f021b
[deliverable/linux.git] / drivers / serial / 8250_pci.c
1 /*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial_core.h>
26 #include <linux/8250_pci.h>
27 #include <linux/bitops.h>
28
29 #include <asm/byteorder.h>
30 #include <asm/io.h>
31
32 #include "8250.h"
33
34 #undef SERIAL_DEBUG_PCI
35
36 /*
37 * Definitions for PCI support.
38 */
39 #define FL_BASE_MASK 0x0007
40 #define FL_BASE0 0x0000
41 #define FL_BASE1 0x0001
42 #define FL_BASE2 0x0002
43 #define FL_BASE3 0x0003
44 #define FL_BASE4 0x0004
45 #define FL_GET_BASE(x) (x & FL_BASE_MASK)
46
47 /* Use successive BARs (PCI base address registers),
48 else use offset into some specified BAR */
49 #define FL_BASE_BARS 0x0008
50
51 /* do not assign an irq */
52 #define FL_NOIRQ 0x0080
53
54 /* Use the Base address register size to cap number of ports */
55 #define FL_REGION_SZ_CAP 0x0100
56
57 struct pciserial_board {
58 unsigned int flags;
59 unsigned int num_ports;
60 unsigned int base_baud;
61 unsigned int uart_offset;
62 unsigned int reg_shift;
63 unsigned int first_offset;
64 };
65
66 /*
67 * init function returns:
68 * > 0 - number of ports
69 * = 0 - use board->num_ports
70 * < 0 - error
71 */
72 struct pci_serial_quirk {
73 u32 vendor;
74 u32 device;
75 u32 subvendor;
76 u32 subdevice;
77 int (*init)(struct pci_dev *dev);
78 int (*setup)(struct pci_dev *dev, struct pciserial_board *,
79 struct uart_port *port, int idx);
80 void (*exit)(struct pci_dev *dev);
81 };
82
83 #define PCI_NUM_BAR_RESOURCES 6
84
85 struct serial_private {
86 unsigned int nr;
87 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
88 struct pci_serial_quirk *quirk;
89 int line[0];
90 };
91
92 static void moan_device(const char *str, struct pci_dev *dev)
93 {
94 printk(KERN_WARNING "%s: %s\n"
95 KERN_WARNING "Please send the output of lspci -vv, this\n"
96 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
97 KERN_WARNING "manufacturer and name of serial board or\n"
98 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
99 pci_name(dev), str, dev->vendor, dev->device,
100 dev->subsystem_vendor, dev->subsystem_device);
101 }
102
103 static int
104 setup_port(struct pci_dev *dev, struct uart_port *port,
105 int bar, int offset, int regshift)
106 {
107 struct serial_private *priv = pci_get_drvdata(dev);
108 unsigned long base, len;
109
110 if (bar >= PCI_NUM_BAR_RESOURCES)
111 return -EINVAL;
112
113 base = pci_resource_start(dev, bar);
114
115 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
116 len = pci_resource_len(dev, bar);
117
118 if (!priv->remapped_bar[bar])
119 priv->remapped_bar[bar] = ioremap(base, len);
120 if (!priv->remapped_bar[bar])
121 return -ENOMEM;
122
123 port->iotype = UPIO_MEM;
124 port->iobase = 0;
125 port->mapbase = base + offset;
126 port->membase = priv->remapped_bar[bar] + offset;
127 port->regshift = regshift;
128 } else {
129 port->iotype = UPIO_PORT;
130 port->iobase = base + offset;
131 port->mapbase = 0;
132 port->membase = NULL;
133 port->regshift = 0;
134 }
135 return 0;
136 }
137
138 /*
139 * AFAVLAB uses a different mixture of BARs and offsets
140 * Not that ugly ;) -- HW
141 */
142 static int
143 afavlab_setup(struct pci_dev *dev, struct pciserial_board *board,
144 struct uart_port *port, int idx)
145 {
146 unsigned int bar, offset = board->first_offset;
147
148 bar = FL_GET_BASE(board->flags);
149 if (idx < 4)
150 bar += idx;
151 else {
152 bar = 4;
153 offset += (idx - 4) * board->uart_offset;
154 }
155
156 return setup_port(dev, port, bar, offset, board->reg_shift);
157 }
158
159 /*
160 * HP's Remote Management Console. The Diva chip came in several
161 * different versions. N-class, L2000 and A500 have two Diva chips, each
162 * with 3 UARTs (the third UART on the second chip is unused). Superdome
163 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
164 * one Diva chip, but it has been expanded to 5 UARTs.
165 */
166 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
167 {
168 int rc = 0;
169
170 switch (dev->subsystem_device) {
171 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
172 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
173 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
174 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
175 rc = 3;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
178 rc = 2;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
181 rc = 4;
182 break;
183 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
184 rc = 1;
185 break;
186 }
187
188 return rc;
189 }
190
191 /*
192 * HP's Diva chip puts the 4th/5th serial port further out, and
193 * some serial ports are supposed to be hidden on certain models.
194 */
195 static int
196 pci_hp_diva_setup(struct pci_dev *dev, struct pciserial_board *board,
197 struct uart_port *port, int idx)
198 {
199 unsigned int offset = board->first_offset;
200 unsigned int bar = FL_GET_BASE(board->flags);
201
202 switch (dev->subsystem_device) {
203 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 if (idx == 3)
205 idx++;
206 break;
207 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
208 if (idx > 0)
209 idx++;
210 if (idx > 2)
211 idx++;
212 break;
213 }
214 if (idx > 2)
215 offset = 0x18;
216
217 offset += idx * board->uart_offset;
218
219 return setup_port(dev, port, bar, offset, board->reg_shift);
220 }
221
222 /*
223 * Added for EKF Intel i960 serial boards
224 */
225 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
226 {
227 unsigned long oldval;
228
229 if (!(dev->subsystem_device & 0x1000))
230 return -ENODEV;
231
232 /* is firmware started? */
233 pci_read_config_dword(dev, 0x44, (void*) &oldval);
234 if (oldval == 0x00001000L) { /* RESET value */
235 printk(KERN_DEBUG "Local i960 firmware missing");
236 return -ENODEV;
237 }
238 return 0;
239 }
240
241 /*
242 * Some PCI serial cards using the PLX 9050 PCI interface chip require
243 * that the card interrupt be explicitly enabled or disabled. This
244 * seems to be mainly needed on card using the PLX which also use I/O
245 * mapped memory.
246 */
247 static int __devinit pci_plx9050_init(struct pci_dev *dev)
248 {
249 u8 irq_config;
250 void __iomem *p;
251
252 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
253 moan_device("no memory in bar 0", dev);
254 return 0;
255 }
256
257 irq_config = 0x41;
258 if (dev->vendor == PCI_VENDOR_ID_PANACOM)
259 irq_config = 0x43;
260 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
261 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
262 /*
263 * As the megawolf cards have the int pins active
264 * high, and have 2 UART chips, both ints must be
265 * enabled on the 9050. Also, the UARTS are set in
266 * 16450 mode by default, so we have to enable the
267 * 16C950 'enhanced' mode so that we can use the
268 * deep FIFOs
269 */
270 irq_config = 0x5b;
271 }
272
273 /*
274 * enable/disable interrupts
275 */
276 p = ioremap(pci_resource_start(dev, 0), 0x80);
277 if (p == NULL)
278 return -ENOMEM;
279 writel(irq_config, p + 0x4c);
280
281 /*
282 * Read the register back to ensure that it took effect.
283 */
284 readl(p + 0x4c);
285 iounmap(p);
286
287 return 0;
288 }
289
290 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
291 {
292 u8 __iomem *p;
293
294 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295 return;
296
297 /*
298 * disable interrupts
299 */
300 p = ioremap(pci_resource_start(dev, 0), 0x80);
301 if (p != NULL) {
302 writel(0, p + 0x4c);
303
304 /*
305 * Read the register back to ensure that it took effect.
306 */
307 readl(p + 0x4c);
308 iounmap(p);
309 }
310 }
311
312 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
313 static int
314 sbs_setup(struct pci_dev *dev, struct pciserial_board *board,
315 struct uart_port *port, int idx)
316 {
317 unsigned int bar, offset = board->first_offset;
318
319 bar = 0;
320
321 if (idx < 4) {
322 /* first four channels map to 0, 0x100, 0x200, 0x300 */
323 offset += idx * board->uart_offset;
324 } else if (idx < 8) {
325 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
326 offset += idx * board->uart_offset + 0xC00;
327 } else /* we have only 8 ports on PMC-OCTALPRO */
328 return 1;
329
330 return setup_port(dev, port, bar, offset, board->reg_shift);
331 }
332
333 /*
334 * This does initialization for PMC OCTALPRO cards:
335 * maps the device memory, resets the UARTs (needed, bc
336 * if the module is removed and inserted again, the card
337 * is in the sleep mode) and enables global interrupt.
338 */
339
340 /* global control register offset for SBS PMC-OctalPro */
341 #define OCT_REG_CR_OFF 0x500
342
343 static int __devinit sbs_init(struct pci_dev *dev)
344 {
345 u8 __iomem *p;
346
347 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
348
349 if (p == NULL)
350 return -ENOMEM;
351 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
352 writeb(0x10,p + OCT_REG_CR_OFF);
353 udelay(50);
354 writeb(0x0,p + OCT_REG_CR_OFF);
355
356 /* Set bit-2 (INTENABLE) of Control Register */
357 writeb(0x4, p + OCT_REG_CR_OFF);
358 iounmap(p);
359
360 return 0;
361 }
362
363 /*
364 * Disables the global interrupt of PMC-OctalPro
365 */
366
367 static void __devexit sbs_exit(struct pci_dev *dev)
368 {
369 u8 __iomem *p;
370
371 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
372 if (p != NULL) {
373 writeb(0, p + OCT_REG_CR_OFF);
374 }
375 iounmap(p);
376 }
377
378 /*
379 * SIIG serial cards have an PCI interface chip which also controls
380 * the UART clocking frequency. Each UART can be clocked independently
381 * (except cards equiped with 4 UARTs) and initial clocking settings
382 * are stored in the EEPROM chip. It can cause problems because this
383 * version of serial driver doesn't support differently clocked UART's
384 * on single PCI card. To prevent this, initialization functions set
385 * high frequency clocking for all UART's on given card. It is safe (I
386 * hope) because it doesn't touch EEPROM settings to prevent conflicts
387 * with other OSes (like M$ DOS).
388 *
389 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
390 *
391 * There is two family of SIIG serial cards with different PCI
392 * interface chip and different configuration methods:
393 * - 10x cards have control registers in IO and/or memory space;
394 * - 20x cards have control registers in standard PCI configuration space.
395 *
396 * Note: all 10x cards have PCI device ids 0x10..
397 * all 20x cards have PCI device ids 0x20..
398 *
399 * There are also Quartet Serial cards which use Oxford Semiconductor
400 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
401 *
402 * Note: some SIIG cards are probed by the parport_serial object.
403 */
404
405 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
406 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
407
408 static int pci_siig10x_init(struct pci_dev *dev)
409 {
410 u16 data;
411 void __iomem *p;
412
413 switch (dev->device & 0xfff8) {
414 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
415 data = 0xffdf;
416 break;
417 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
418 data = 0xf7ff;
419 break;
420 default: /* 1S1P, 4S */
421 data = 0xfffb;
422 break;
423 }
424
425 p = ioremap(pci_resource_start(dev, 0), 0x80);
426 if (p == NULL)
427 return -ENOMEM;
428
429 writew(readw(p + 0x28) & data, p + 0x28);
430 readw(p + 0x28);
431 iounmap(p);
432 return 0;
433 }
434
435 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
436 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
437
438 static int pci_siig20x_init(struct pci_dev *dev)
439 {
440 u8 data;
441
442 /* Change clock frequency for the first UART. */
443 pci_read_config_byte(dev, 0x6f, &data);
444 pci_write_config_byte(dev, 0x6f, data & 0xef);
445
446 /* If this card has 2 UART, we have to do the same with second UART. */
447 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
448 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
449 pci_read_config_byte(dev, 0x73, &data);
450 pci_write_config_byte(dev, 0x73, data & 0xef);
451 }
452 return 0;
453 }
454
455 static int pci_siig_init(struct pci_dev *dev)
456 {
457 unsigned int type = dev->device & 0xff00;
458
459 if (type == 0x1000)
460 return pci_siig10x_init(dev);
461 else if (type == 0x2000)
462 return pci_siig20x_init(dev);
463
464 moan_device("Unknown SIIG card", dev);
465 return -ENODEV;
466 }
467
468 int pci_siig10x_fn(struct pci_dev *dev, int enable)
469 {
470 int ret = 0;
471 if (enable)
472 ret = pci_siig10x_init(dev);
473 return ret;
474 }
475
476 int pci_siig20x_fn(struct pci_dev *dev, int enable)
477 {
478 int ret = 0;
479 if (enable)
480 ret = pci_siig20x_init(dev);
481 return ret;
482 }
483
484 EXPORT_SYMBOL(pci_siig10x_fn);
485 EXPORT_SYMBOL(pci_siig20x_fn);
486
487 /*
488 * Timedia has an explosion of boards, and to avoid the PCI table from
489 * growing *huge*, we use this function to collapse some 70 entries
490 * in the PCI table into one, for sanity's and compactness's sake.
491 */
492 static unsigned short timedia_single_port[] = {
493 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
494 };
495
496 static unsigned short timedia_dual_port[] = {
497 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
498 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
499 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
500 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
501 0xD079, 0
502 };
503
504 static unsigned short timedia_quad_port[] = {
505 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
506 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
507 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
508 0xB157, 0
509 };
510
511 static unsigned short timedia_eight_port[] = {
512 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
513 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
514 };
515
516 static struct timedia_struct {
517 int num;
518 unsigned short *ids;
519 } timedia_data[] = {
520 { 1, timedia_single_port },
521 { 2, timedia_dual_port },
522 { 4, timedia_quad_port },
523 { 8, timedia_eight_port },
524 { 0, NULL }
525 };
526
527 static int __devinit pci_timedia_init(struct pci_dev *dev)
528 {
529 unsigned short *ids;
530 int i, j;
531
532 for (i = 0; timedia_data[i].num; i++) {
533 ids = timedia_data[i].ids;
534 for (j = 0; ids[j]; j++)
535 if (dev->subsystem_device == ids[j])
536 return timedia_data[i].num;
537 }
538 return 0;
539 }
540
541 /*
542 * Timedia/SUNIX uses a mixture of BARs and offsets
543 * Ugh, this is ugly as all hell --- TYT
544 */
545 static int
546 pci_timedia_setup(struct pci_dev *dev, struct pciserial_board *board,
547 struct uart_port *port, int idx)
548 {
549 unsigned int bar = 0, offset = board->first_offset;
550
551 switch (idx) {
552 case 0:
553 bar = 0;
554 break;
555 case 1:
556 offset = board->uart_offset;
557 bar = 0;
558 break;
559 case 2:
560 bar = 1;
561 break;
562 case 3:
563 offset = board->uart_offset;
564 bar = 1;
565 case 4: /* BAR 2 */
566 case 5: /* BAR 3 */
567 case 6: /* BAR 4 */
568 case 7: /* BAR 5 */
569 bar = idx - 2;
570 }
571
572 return setup_port(dev, port, bar, offset, board->reg_shift);
573 }
574
575 /*
576 * Some Titan cards are also a little weird
577 */
578 static int
579 titan_400l_800l_setup(struct pci_dev *dev,
580 struct pciserial_board *board,
581 struct uart_port *port, int idx)
582 {
583 unsigned int bar, offset = board->first_offset;
584
585 switch (idx) {
586 case 0:
587 bar = 1;
588 break;
589 case 1:
590 bar = 2;
591 break;
592 default:
593 bar = 4;
594 offset = (idx - 2) * board->uart_offset;
595 }
596
597 return setup_port(dev, port, bar, offset, board->reg_shift);
598 }
599
600 static int __devinit pci_xircom_init(struct pci_dev *dev)
601 {
602 msleep(100);
603 return 0;
604 }
605
606 static int __devinit pci_netmos_init(struct pci_dev *dev)
607 {
608 /* subdevice 0x00PS means <P> parallel, <S> serial */
609 unsigned int num_serial = dev->subsystem_device & 0xf;
610
611 if (num_serial == 0)
612 return -ENODEV;
613 return num_serial;
614 }
615
616 static int
617 pci_default_setup(struct pci_dev *dev, struct pciserial_board *board,
618 struct uart_port *port, int idx)
619 {
620 unsigned int bar, offset = board->first_offset, maxnr;
621
622 bar = FL_GET_BASE(board->flags);
623 if (board->flags & FL_BASE_BARS)
624 bar += idx;
625 else
626 offset += idx * board->uart_offset;
627
628 maxnr = (pci_resource_len(dev, bar) - board->first_offset) /
629 (8 << board->reg_shift);
630
631 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
632 return 1;
633
634 return setup_port(dev, port, bar, offset, board->reg_shift);
635 }
636
637 /* This should be in linux/pci_ids.h */
638 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
639 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
640 #define PCI_DEVICE_ID_OCTPRO 0x0001
641 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
642 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
643 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
644 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
645
646 /*
647 * Master list of serial port init/setup/exit quirks.
648 * This does not describe the general nature of the port.
649 * (ie, baud base, number and location of ports, etc)
650 *
651 * This list is ordered alphabetically by vendor then device.
652 * Specific entries must come before more generic entries.
653 */
654 static struct pci_serial_quirk pci_serial_quirks[] = {
655 /*
656 * AFAVLAB cards.
657 * It is not clear whether this applies to all products.
658 */
659 {
660 .vendor = PCI_VENDOR_ID_AFAVLAB,
661 .device = PCI_ANY_ID,
662 .subvendor = PCI_ANY_ID,
663 .subdevice = PCI_ANY_ID,
664 .setup = afavlab_setup,
665 },
666 /*
667 * HP Diva
668 */
669 {
670 .vendor = PCI_VENDOR_ID_HP,
671 .device = PCI_DEVICE_ID_HP_DIVA,
672 .subvendor = PCI_ANY_ID,
673 .subdevice = PCI_ANY_ID,
674 .init = pci_hp_diva_init,
675 .setup = pci_hp_diva_setup,
676 },
677 /*
678 * Intel
679 */
680 {
681 .vendor = PCI_VENDOR_ID_INTEL,
682 .device = PCI_DEVICE_ID_INTEL_80960_RP,
683 .subvendor = 0xe4bf,
684 .subdevice = PCI_ANY_ID,
685 .init = pci_inteli960ni_init,
686 .setup = pci_default_setup,
687 },
688 /*
689 * Panacom
690 */
691 {
692 .vendor = PCI_VENDOR_ID_PANACOM,
693 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
694 .subvendor = PCI_ANY_ID,
695 .subdevice = PCI_ANY_ID,
696 .init = pci_plx9050_init,
697 .setup = pci_default_setup,
698 .exit = __devexit_p(pci_plx9050_exit),
699 },
700 {
701 .vendor = PCI_VENDOR_ID_PANACOM,
702 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
703 .subvendor = PCI_ANY_ID,
704 .subdevice = PCI_ANY_ID,
705 .init = pci_plx9050_init,
706 .setup = pci_default_setup,
707 .exit = __devexit_p(pci_plx9050_exit),
708 },
709 /*
710 * PLX
711 */
712 {
713 .vendor = PCI_VENDOR_ID_PLX,
714 .device = PCI_DEVICE_ID_PLX_9050,
715 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
716 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
717 .init = pci_plx9050_init,
718 .setup = pci_default_setup,
719 .exit = __devexit_p(pci_plx9050_exit),
720 },
721 {
722 .vendor = PCI_VENDOR_ID_PLX,
723 .device = PCI_DEVICE_ID_PLX_ROMULUS,
724 .subvendor = PCI_VENDOR_ID_PLX,
725 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
726 .init = pci_plx9050_init,
727 .setup = pci_default_setup,
728 .exit = __devexit_p(pci_plx9050_exit),
729 },
730 /*
731 * SBS Technologies, Inc., PMC-OCTALPRO 232
732 */
733 {
734 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
735 .device = PCI_DEVICE_ID_OCTPRO,
736 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
737 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
738 .init = sbs_init,
739 .setup = sbs_setup,
740 .exit = __devexit_p(sbs_exit),
741 },
742 /*
743 * SBS Technologies, Inc., PMC-OCTALPRO 422
744 */
745 {
746 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
747 .device = PCI_DEVICE_ID_OCTPRO,
748 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
749 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
750 .init = sbs_init,
751 .setup = sbs_setup,
752 .exit = __devexit_p(sbs_exit),
753 },
754 /*
755 * SBS Technologies, Inc., P-Octal 232
756 */
757 {
758 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
759 .device = PCI_DEVICE_ID_OCTPRO,
760 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
761 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
762 .init = sbs_init,
763 .setup = sbs_setup,
764 .exit = __devexit_p(sbs_exit),
765 },
766 /*
767 * SBS Technologies, Inc., P-Octal 422
768 */
769 {
770 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
771 .device = PCI_DEVICE_ID_OCTPRO,
772 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
773 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
774 .init = sbs_init,
775 .setup = sbs_setup,
776 .exit = __devexit_p(sbs_exit),
777 },
778 /*
779 * SIIG cards.
780 */
781 {
782 .vendor = PCI_VENDOR_ID_SIIG,
783 .device = PCI_ANY_ID,
784 .subvendor = PCI_ANY_ID,
785 .subdevice = PCI_ANY_ID,
786 .init = pci_siig_init,
787 .setup = pci_default_setup,
788 },
789 /*
790 * Titan cards
791 */
792 {
793 .vendor = PCI_VENDOR_ID_TITAN,
794 .device = PCI_DEVICE_ID_TITAN_400L,
795 .subvendor = PCI_ANY_ID,
796 .subdevice = PCI_ANY_ID,
797 .setup = titan_400l_800l_setup,
798 },
799 {
800 .vendor = PCI_VENDOR_ID_TITAN,
801 .device = PCI_DEVICE_ID_TITAN_800L,
802 .subvendor = PCI_ANY_ID,
803 .subdevice = PCI_ANY_ID,
804 .setup = titan_400l_800l_setup,
805 },
806 /*
807 * Timedia cards
808 */
809 {
810 .vendor = PCI_VENDOR_ID_TIMEDIA,
811 .device = PCI_DEVICE_ID_TIMEDIA_1889,
812 .subvendor = PCI_VENDOR_ID_TIMEDIA,
813 .subdevice = PCI_ANY_ID,
814 .init = pci_timedia_init,
815 .setup = pci_timedia_setup,
816 },
817 {
818 .vendor = PCI_VENDOR_ID_TIMEDIA,
819 .device = PCI_ANY_ID,
820 .subvendor = PCI_ANY_ID,
821 .subdevice = PCI_ANY_ID,
822 .setup = pci_timedia_setup,
823 },
824 /*
825 * Xircom cards
826 */
827 {
828 .vendor = PCI_VENDOR_ID_XIRCOM,
829 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
830 .subvendor = PCI_ANY_ID,
831 .subdevice = PCI_ANY_ID,
832 .init = pci_xircom_init,
833 .setup = pci_default_setup,
834 },
835 /*
836 * Netmos cards
837 */
838 {
839 .vendor = PCI_VENDOR_ID_NETMOS,
840 .device = PCI_ANY_ID,
841 .subvendor = PCI_ANY_ID,
842 .subdevice = PCI_ANY_ID,
843 .init = pci_netmos_init,
844 .setup = pci_default_setup,
845 },
846 /*
847 * Default "match everything" terminator entry
848 */
849 {
850 .vendor = PCI_ANY_ID,
851 .device = PCI_ANY_ID,
852 .subvendor = PCI_ANY_ID,
853 .subdevice = PCI_ANY_ID,
854 .setup = pci_default_setup,
855 }
856 };
857
858 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
859 {
860 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
861 }
862
863 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
864 {
865 struct pci_serial_quirk *quirk;
866
867 for (quirk = pci_serial_quirks; ; quirk++)
868 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
869 quirk_id_matches(quirk->device, dev->device) &&
870 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
871 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
872 break;
873 return quirk;
874 }
875
876 static _INLINE_ int
877 get_pci_irq(struct pci_dev *dev, struct pciserial_board *board)
878 {
879 if (board->flags & FL_NOIRQ)
880 return 0;
881 else
882 return dev->irq;
883 }
884
885 /*
886 * This is the configuration table for all of the PCI serial boards
887 * which we support. It is directly indexed by the pci_board_num_t enum
888 * value, which is encoded in the pci_device_id PCI probe table's
889 * driver_data member.
890 *
891 * The makeup of these names are:
892 * pbn_bn{_bt}_n_baud
893 *
894 * bn = PCI BAR number
895 * bt = Index using PCI BARs
896 * n = number of serial ports
897 * baud = baud rate
898 *
899 * This table is sorted by (in order): baud, bt, bn, n.
900 *
901 * Please note: in theory if n = 1, _bt infix should make no difference.
902 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
903 */
904 enum pci_board_num_t {
905 pbn_default = 0,
906
907 pbn_b0_1_115200,
908 pbn_b0_2_115200,
909 pbn_b0_4_115200,
910 pbn_b0_5_115200,
911
912 pbn_b0_1_921600,
913 pbn_b0_2_921600,
914 pbn_b0_4_921600,
915
916 pbn_b0_4_1152000,
917
918 pbn_b0_bt_1_115200,
919 pbn_b0_bt_2_115200,
920 pbn_b0_bt_8_115200,
921
922 pbn_b0_bt_1_460800,
923 pbn_b0_bt_2_460800,
924 pbn_b0_bt_4_460800,
925
926 pbn_b0_bt_1_921600,
927 pbn_b0_bt_2_921600,
928 pbn_b0_bt_4_921600,
929 pbn_b0_bt_8_921600,
930
931 pbn_b1_1_115200,
932 pbn_b1_2_115200,
933 pbn_b1_4_115200,
934 pbn_b1_8_115200,
935
936 pbn_b1_1_921600,
937 pbn_b1_2_921600,
938 pbn_b1_4_921600,
939 pbn_b1_8_921600,
940
941 pbn_b1_bt_2_921600,
942
943 pbn_b1_1_1382400,
944 pbn_b1_2_1382400,
945 pbn_b1_4_1382400,
946 pbn_b1_8_1382400,
947
948 pbn_b2_1_115200,
949 pbn_b2_8_115200,
950
951 pbn_b2_1_460800,
952 pbn_b2_4_460800,
953 pbn_b2_8_460800,
954 pbn_b2_16_460800,
955
956 pbn_b2_1_921600,
957 pbn_b2_4_921600,
958 pbn_b2_8_921600,
959
960 pbn_b2_bt_1_115200,
961 pbn_b2_bt_2_115200,
962 pbn_b2_bt_4_115200,
963
964 pbn_b2_bt_2_921600,
965 pbn_b2_bt_4_921600,
966
967 pbn_b3_4_115200,
968 pbn_b3_8_115200,
969
970 /*
971 * Board-specific versions.
972 */
973 pbn_panacom,
974 pbn_panacom2,
975 pbn_panacom4,
976 pbn_plx_romulus,
977 pbn_oxsemi,
978 pbn_intel_i960,
979 pbn_sgi_ioc3,
980 pbn_nec_nile4,
981 pbn_computone_4,
982 pbn_computone_6,
983 pbn_computone_8,
984 pbn_sbsxrsio,
985 pbn_exar_XR17C152,
986 pbn_exar_XR17C154,
987 pbn_exar_XR17C158,
988 };
989
990 /*
991 * uart_offset - the space between channels
992 * reg_shift - describes how the UART registers are mapped
993 * to PCI memory by the card.
994 * For example IER register on SBS, Inc. PMC-OctPro is located at
995 * offset 0x10 from the UART base, while UART_IER is defined as 1
996 * in include/linux/serial_reg.h,
997 * see first lines of serial_in() and serial_out() in 8250.c
998 */
999
1000 static struct pciserial_board pci_boards[] __devinitdata = {
1001 [pbn_default] = {
1002 .flags = FL_BASE0,
1003 .num_ports = 1,
1004 .base_baud = 115200,
1005 .uart_offset = 8,
1006 },
1007 [pbn_b0_1_115200] = {
1008 .flags = FL_BASE0,
1009 .num_ports = 1,
1010 .base_baud = 115200,
1011 .uart_offset = 8,
1012 },
1013 [pbn_b0_2_115200] = {
1014 .flags = FL_BASE0,
1015 .num_ports = 2,
1016 .base_baud = 115200,
1017 .uart_offset = 8,
1018 },
1019 [pbn_b0_4_115200] = {
1020 .flags = FL_BASE0,
1021 .num_ports = 4,
1022 .base_baud = 115200,
1023 .uart_offset = 8,
1024 },
1025 [pbn_b0_5_115200] = {
1026 .flags = FL_BASE0,
1027 .num_ports = 5,
1028 .base_baud = 115200,
1029 .uart_offset = 8,
1030 },
1031
1032 [pbn_b0_1_921600] = {
1033 .flags = FL_BASE0,
1034 .num_ports = 1,
1035 .base_baud = 921600,
1036 .uart_offset = 8,
1037 },
1038 [pbn_b0_2_921600] = {
1039 .flags = FL_BASE0,
1040 .num_ports = 2,
1041 .base_baud = 921600,
1042 .uart_offset = 8,
1043 },
1044 [pbn_b0_4_921600] = {
1045 .flags = FL_BASE0,
1046 .num_ports = 4,
1047 .base_baud = 921600,
1048 .uart_offset = 8,
1049 },
1050 [pbn_b0_4_1152000] = {
1051 .flags = FL_BASE0,
1052 .num_ports = 4,
1053 .base_baud = 1152000,
1054 .uart_offset = 8,
1055 },
1056
1057 [pbn_b0_bt_1_115200] = {
1058 .flags = FL_BASE0|FL_BASE_BARS,
1059 .num_ports = 1,
1060 .base_baud = 115200,
1061 .uart_offset = 8,
1062 },
1063 [pbn_b0_bt_2_115200] = {
1064 .flags = FL_BASE0|FL_BASE_BARS,
1065 .num_ports = 2,
1066 .base_baud = 115200,
1067 .uart_offset = 8,
1068 },
1069 [pbn_b0_bt_8_115200] = {
1070 .flags = FL_BASE0|FL_BASE_BARS,
1071 .num_ports = 8,
1072 .base_baud = 115200,
1073 .uart_offset = 8,
1074 },
1075
1076 [pbn_b0_bt_1_460800] = {
1077 .flags = FL_BASE0|FL_BASE_BARS,
1078 .num_ports = 1,
1079 .base_baud = 460800,
1080 .uart_offset = 8,
1081 },
1082 [pbn_b0_bt_2_460800] = {
1083 .flags = FL_BASE0|FL_BASE_BARS,
1084 .num_ports = 2,
1085 .base_baud = 460800,
1086 .uart_offset = 8,
1087 },
1088 [pbn_b0_bt_4_460800] = {
1089 .flags = FL_BASE0|FL_BASE_BARS,
1090 .num_ports = 4,
1091 .base_baud = 460800,
1092 .uart_offset = 8,
1093 },
1094
1095 [pbn_b0_bt_1_921600] = {
1096 .flags = FL_BASE0|FL_BASE_BARS,
1097 .num_ports = 1,
1098 .base_baud = 921600,
1099 .uart_offset = 8,
1100 },
1101 [pbn_b0_bt_2_921600] = {
1102 .flags = FL_BASE0|FL_BASE_BARS,
1103 .num_ports = 2,
1104 .base_baud = 921600,
1105 .uart_offset = 8,
1106 },
1107 [pbn_b0_bt_4_921600] = {
1108 .flags = FL_BASE0|FL_BASE_BARS,
1109 .num_ports = 4,
1110 .base_baud = 921600,
1111 .uart_offset = 8,
1112 },
1113 [pbn_b0_bt_8_921600] = {
1114 .flags = FL_BASE0|FL_BASE_BARS,
1115 .num_ports = 8,
1116 .base_baud = 921600,
1117 .uart_offset = 8,
1118 },
1119
1120 [pbn_b1_1_115200] = {
1121 .flags = FL_BASE1,
1122 .num_ports = 1,
1123 .base_baud = 115200,
1124 .uart_offset = 8,
1125 },
1126 [pbn_b1_2_115200] = {
1127 .flags = FL_BASE1,
1128 .num_ports = 2,
1129 .base_baud = 115200,
1130 .uart_offset = 8,
1131 },
1132 [pbn_b1_4_115200] = {
1133 .flags = FL_BASE1,
1134 .num_ports = 4,
1135 .base_baud = 115200,
1136 .uart_offset = 8,
1137 },
1138 [pbn_b1_8_115200] = {
1139 .flags = FL_BASE1,
1140 .num_ports = 8,
1141 .base_baud = 115200,
1142 .uart_offset = 8,
1143 },
1144
1145 [pbn_b1_1_921600] = {
1146 .flags = FL_BASE1,
1147 .num_ports = 1,
1148 .base_baud = 921600,
1149 .uart_offset = 8,
1150 },
1151 [pbn_b1_2_921600] = {
1152 .flags = FL_BASE1,
1153 .num_ports = 2,
1154 .base_baud = 921600,
1155 .uart_offset = 8,
1156 },
1157 [pbn_b1_4_921600] = {
1158 .flags = FL_BASE1,
1159 .num_ports = 4,
1160 .base_baud = 921600,
1161 .uart_offset = 8,
1162 },
1163 [pbn_b1_8_921600] = {
1164 .flags = FL_BASE1,
1165 .num_ports = 8,
1166 .base_baud = 921600,
1167 .uart_offset = 8,
1168 },
1169
1170 [pbn_b1_bt_2_921600] = {
1171 .flags = FL_BASE1|FL_BASE_BARS,
1172 .num_ports = 2,
1173 .base_baud = 921600,
1174 .uart_offset = 8,
1175 },
1176
1177 [pbn_b1_1_1382400] = {
1178 .flags = FL_BASE1,
1179 .num_ports = 1,
1180 .base_baud = 1382400,
1181 .uart_offset = 8,
1182 },
1183 [pbn_b1_2_1382400] = {
1184 .flags = FL_BASE1,
1185 .num_ports = 2,
1186 .base_baud = 1382400,
1187 .uart_offset = 8,
1188 },
1189 [pbn_b1_4_1382400] = {
1190 .flags = FL_BASE1,
1191 .num_ports = 4,
1192 .base_baud = 1382400,
1193 .uart_offset = 8,
1194 },
1195 [pbn_b1_8_1382400] = {
1196 .flags = FL_BASE1,
1197 .num_ports = 8,
1198 .base_baud = 1382400,
1199 .uart_offset = 8,
1200 },
1201
1202 [pbn_b2_1_115200] = {
1203 .flags = FL_BASE2,
1204 .num_ports = 1,
1205 .base_baud = 115200,
1206 .uart_offset = 8,
1207 },
1208 [pbn_b2_8_115200] = {
1209 .flags = FL_BASE2,
1210 .num_ports = 8,
1211 .base_baud = 115200,
1212 .uart_offset = 8,
1213 },
1214
1215 [pbn_b2_1_460800] = {
1216 .flags = FL_BASE2,
1217 .num_ports = 1,
1218 .base_baud = 460800,
1219 .uart_offset = 8,
1220 },
1221 [pbn_b2_4_460800] = {
1222 .flags = FL_BASE2,
1223 .num_ports = 4,
1224 .base_baud = 460800,
1225 .uart_offset = 8,
1226 },
1227 [pbn_b2_8_460800] = {
1228 .flags = FL_BASE2,
1229 .num_ports = 8,
1230 .base_baud = 460800,
1231 .uart_offset = 8,
1232 },
1233 [pbn_b2_16_460800] = {
1234 .flags = FL_BASE2,
1235 .num_ports = 16,
1236 .base_baud = 460800,
1237 .uart_offset = 8,
1238 },
1239
1240 [pbn_b2_1_921600] = {
1241 .flags = FL_BASE2,
1242 .num_ports = 1,
1243 .base_baud = 921600,
1244 .uart_offset = 8,
1245 },
1246 [pbn_b2_4_921600] = {
1247 .flags = FL_BASE2,
1248 .num_ports = 4,
1249 .base_baud = 921600,
1250 .uart_offset = 8,
1251 },
1252 [pbn_b2_8_921600] = {
1253 .flags = FL_BASE2,
1254 .num_ports = 8,
1255 .base_baud = 921600,
1256 .uart_offset = 8,
1257 },
1258
1259 [pbn_b2_bt_1_115200] = {
1260 .flags = FL_BASE2|FL_BASE_BARS,
1261 .num_ports = 1,
1262 .base_baud = 115200,
1263 .uart_offset = 8,
1264 },
1265 [pbn_b2_bt_2_115200] = {
1266 .flags = FL_BASE2|FL_BASE_BARS,
1267 .num_ports = 2,
1268 .base_baud = 115200,
1269 .uart_offset = 8,
1270 },
1271 [pbn_b2_bt_4_115200] = {
1272 .flags = FL_BASE2|FL_BASE_BARS,
1273 .num_ports = 4,
1274 .base_baud = 115200,
1275 .uart_offset = 8,
1276 },
1277
1278 [pbn_b2_bt_2_921600] = {
1279 .flags = FL_BASE2|FL_BASE_BARS,
1280 .num_ports = 2,
1281 .base_baud = 921600,
1282 .uart_offset = 8,
1283 },
1284 [pbn_b2_bt_4_921600] = {
1285 .flags = FL_BASE2|FL_BASE_BARS,
1286 .num_ports = 4,
1287 .base_baud = 921600,
1288 .uart_offset = 8,
1289 },
1290
1291 [pbn_b3_4_115200] = {
1292 .flags = FL_BASE3,
1293 .num_ports = 4,
1294 .base_baud = 115200,
1295 .uart_offset = 8,
1296 },
1297 [pbn_b3_8_115200] = {
1298 .flags = FL_BASE3,
1299 .num_ports = 8,
1300 .base_baud = 115200,
1301 .uart_offset = 8,
1302 },
1303
1304 /*
1305 * Entries following this are board-specific.
1306 */
1307
1308 /*
1309 * Panacom - IOMEM
1310 */
1311 [pbn_panacom] = {
1312 .flags = FL_BASE2,
1313 .num_ports = 2,
1314 .base_baud = 921600,
1315 .uart_offset = 0x400,
1316 .reg_shift = 7,
1317 },
1318 [pbn_panacom2] = {
1319 .flags = FL_BASE2|FL_BASE_BARS,
1320 .num_ports = 2,
1321 .base_baud = 921600,
1322 .uart_offset = 0x400,
1323 .reg_shift = 7,
1324 },
1325 [pbn_panacom4] = {
1326 .flags = FL_BASE2|FL_BASE_BARS,
1327 .num_ports = 4,
1328 .base_baud = 921600,
1329 .uart_offset = 0x400,
1330 .reg_shift = 7,
1331 },
1332
1333 /* I think this entry is broken - the first_offset looks wrong --rmk */
1334 [pbn_plx_romulus] = {
1335 .flags = FL_BASE2,
1336 .num_ports = 4,
1337 .base_baud = 921600,
1338 .uart_offset = 8 << 2,
1339 .reg_shift = 2,
1340 .first_offset = 0x03,
1341 },
1342
1343 /*
1344 * This board uses the size of PCI Base region 0 to
1345 * signal now many ports are available
1346 */
1347 [pbn_oxsemi] = {
1348 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1349 .num_ports = 32,
1350 .base_baud = 115200,
1351 .uart_offset = 8,
1352 },
1353
1354 /*
1355 * EKF addition for i960 Boards form EKF with serial port.
1356 * Max 256 ports.
1357 */
1358 [pbn_intel_i960] = {
1359 .flags = FL_BASE0,
1360 .num_ports = 32,
1361 .base_baud = 921600,
1362 .uart_offset = 8 << 2,
1363 .reg_shift = 2,
1364 .first_offset = 0x10000,
1365 },
1366 [pbn_sgi_ioc3] = {
1367 .flags = FL_BASE0|FL_NOIRQ,
1368 .num_ports = 1,
1369 .base_baud = 458333,
1370 .uart_offset = 8,
1371 .reg_shift = 0,
1372 .first_offset = 0x20178,
1373 },
1374
1375 /*
1376 * NEC Vrc-5074 (Nile 4) builtin UART.
1377 */
1378 [pbn_nec_nile4] = {
1379 .flags = FL_BASE0,
1380 .num_ports = 1,
1381 .base_baud = 520833,
1382 .uart_offset = 8 << 3,
1383 .reg_shift = 3,
1384 .first_offset = 0x300,
1385 },
1386
1387 /*
1388 * Computone - uses IOMEM.
1389 */
1390 [pbn_computone_4] = {
1391 .flags = FL_BASE0,
1392 .num_ports = 4,
1393 .base_baud = 921600,
1394 .uart_offset = 0x40,
1395 .reg_shift = 2,
1396 .first_offset = 0x200,
1397 },
1398 [pbn_computone_6] = {
1399 .flags = FL_BASE0,
1400 .num_ports = 6,
1401 .base_baud = 921600,
1402 .uart_offset = 0x40,
1403 .reg_shift = 2,
1404 .first_offset = 0x200,
1405 },
1406 [pbn_computone_8] = {
1407 .flags = FL_BASE0,
1408 .num_ports = 8,
1409 .base_baud = 921600,
1410 .uart_offset = 0x40,
1411 .reg_shift = 2,
1412 .first_offset = 0x200,
1413 },
1414 [pbn_sbsxrsio] = {
1415 .flags = FL_BASE0,
1416 .num_ports = 8,
1417 .base_baud = 460800,
1418 .uart_offset = 256,
1419 .reg_shift = 4,
1420 },
1421 /*
1422 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1423 * Only basic 16550A support.
1424 * XR17C15[24] are not tested, but they should work.
1425 */
1426 [pbn_exar_XR17C152] = {
1427 .flags = FL_BASE0,
1428 .num_ports = 2,
1429 .base_baud = 921600,
1430 .uart_offset = 0x200,
1431 },
1432 [pbn_exar_XR17C154] = {
1433 .flags = FL_BASE0,
1434 .num_ports = 4,
1435 .base_baud = 921600,
1436 .uart_offset = 0x200,
1437 },
1438 [pbn_exar_XR17C158] = {
1439 .flags = FL_BASE0,
1440 .num_ports = 8,
1441 .base_baud = 921600,
1442 .uart_offset = 0x200,
1443 },
1444 };
1445
1446 /*
1447 * Given a complete unknown PCI device, try to use some heuristics to
1448 * guess what the configuration might be, based on the pitiful PCI
1449 * serial specs. Returns 0 on success, 1 on failure.
1450 */
1451 static int __devinit
1452 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1453 {
1454 int num_iomem, num_port, first_port = -1, i;
1455
1456 /*
1457 * If it is not a communications device or the programming
1458 * interface is greater than 6, give up.
1459 *
1460 * (Should we try to make guesses for multiport serial devices
1461 * later?)
1462 */
1463 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1464 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1465 (dev->class & 0xff) > 6)
1466 return -ENODEV;
1467
1468 num_iomem = num_port = 0;
1469 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1470 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1471 num_port++;
1472 if (first_port == -1)
1473 first_port = i;
1474 }
1475 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1476 num_iomem++;
1477 }
1478
1479 /*
1480 * If there is 1 or 0 iomem regions, and exactly one port,
1481 * use it. We guess the number of ports based on the IO
1482 * region size.
1483 */
1484 if (num_iomem <= 1 && num_port == 1) {
1485 board->flags = first_port;
1486 board->num_ports = pci_resource_len(dev, first_port) / 8;
1487 return 0;
1488 }
1489
1490 /*
1491 * Now guess if we've got a board which indexes by BARs.
1492 * Each IO BAR should be 8 bytes, and they should follow
1493 * consecutively.
1494 */
1495 first_port = -1;
1496 num_port = 0;
1497 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1498 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1499 pci_resource_len(dev, i) == 8 &&
1500 (first_port == -1 || (first_port + num_port) == i)) {
1501 num_port++;
1502 if (first_port == -1)
1503 first_port = i;
1504 }
1505 }
1506
1507 if (num_port > 1) {
1508 board->flags = first_port | FL_BASE_BARS;
1509 board->num_ports = num_port;
1510 return 0;
1511 }
1512
1513 return -ENODEV;
1514 }
1515
1516 static inline int
1517 serial_pci_matches(struct pciserial_board *board,
1518 struct pciserial_board *guessed)
1519 {
1520 return
1521 board->num_ports == guessed->num_ports &&
1522 board->base_baud == guessed->base_baud &&
1523 board->uart_offset == guessed->uart_offset &&
1524 board->reg_shift == guessed->reg_shift &&
1525 board->first_offset == guessed->first_offset;
1526 }
1527
1528 /*
1529 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1530 * to the arrangement of serial ports on a PCI card.
1531 */
1532 static int __devinit
1533 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1534 {
1535 struct uart_port serial_port;
1536 struct serial_private *priv;
1537 struct pciserial_board *board, tmp;
1538 struct pci_serial_quirk *quirk;
1539 int rc, nr_ports, i;
1540
1541 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1542 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1543 ent->driver_data);
1544 return -EINVAL;
1545 }
1546
1547 board = &pci_boards[ent->driver_data];
1548
1549 rc = pci_enable_device(dev);
1550 if (rc)
1551 return rc;
1552
1553 if (ent->driver_data == pbn_default) {
1554 /*
1555 * Use a copy of the pci_board entry for this;
1556 * avoid changing entries in the table.
1557 */
1558 memcpy(&tmp, board, sizeof(struct pciserial_board));
1559 board = &tmp;
1560
1561 /*
1562 * We matched one of our class entries. Try to
1563 * determine the parameters of this board.
1564 */
1565 rc = serial_pci_guess_board(dev, board);
1566 if (rc)
1567 goto disable;
1568 } else {
1569 /*
1570 * We matched an explicit entry. If we are able to
1571 * detect this boards settings with our heuristic,
1572 * then we no longer need this entry.
1573 */
1574 memcpy(&tmp, &pci_boards[pbn_default],
1575 sizeof(struct pciserial_board));
1576 rc = serial_pci_guess_board(dev, &tmp);
1577 if (rc == 0 && serial_pci_matches(board, &tmp))
1578 moan_device("Redundant entry in serial pci_table.",
1579 dev);
1580 }
1581
1582 nr_ports = board->num_ports;
1583
1584 /*
1585 * Find an init and setup quirks.
1586 */
1587 quirk = find_quirk(dev);
1588
1589 /*
1590 * Run the new-style initialization function.
1591 * The initialization function returns:
1592 * <0 - error
1593 * 0 - use board->num_ports
1594 * >0 - number of ports
1595 */
1596 if (quirk->init) {
1597 rc = quirk->init(dev);
1598 if (rc < 0)
1599 goto disable;
1600 if (rc)
1601 nr_ports = rc;
1602 }
1603
1604 priv = kmalloc(sizeof(struct serial_private) +
1605 sizeof(unsigned int) * nr_ports,
1606 GFP_KERNEL);
1607 if (!priv) {
1608 rc = -ENOMEM;
1609 goto deinit;
1610 }
1611
1612 memset(priv, 0, sizeof(struct serial_private) +
1613 sizeof(unsigned int) * nr_ports);
1614
1615 priv->quirk = quirk;
1616 pci_set_drvdata(dev, priv);
1617
1618 memset(&serial_port, 0, sizeof(struct uart_port));
1619 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1620 serial_port.uartclk = board->base_baud * 16;
1621 serial_port.irq = get_pci_irq(dev, board);
1622 serial_port.dev = &dev->dev;
1623
1624 for (i = 0; i < nr_ports; i++) {
1625 if (quirk->setup(dev, board, &serial_port, i))
1626 break;
1627
1628 #ifdef SERIAL_DEBUG_PCI
1629 printk("Setup PCI port: port %x, irq %d, type %d\n",
1630 serial_port.iobase, serial_port.irq, serial_port.iotype);
1631 #endif
1632
1633 priv->line[i] = serial8250_register_port(&serial_port);
1634 if (priv->line[i] < 0) {
1635 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1636 break;
1637 }
1638 }
1639
1640 priv->nr = i;
1641
1642 return 0;
1643
1644 deinit:
1645 if (quirk->exit)
1646 quirk->exit(dev);
1647 disable:
1648 pci_disable_device(dev);
1649 return rc;
1650 }
1651
1652 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1653 {
1654 struct serial_private *priv = pci_get_drvdata(dev);
1655 struct pci_serial_quirk *quirk;
1656 int i;
1657
1658 pci_set_drvdata(dev, NULL);
1659
1660 for (i = 0; i < priv->nr; i++)
1661 serial8250_unregister_port(priv->line[i]);
1662
1663 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1664 if (priv->remapped_bar[i])
1665 iounmap(priv->remapped_bar[i]);
1666 priv->remapped_bar[i] = NULL;
1667 }
1668
1669 /*
1670 * Find the exit quirks.
1671 */
1672 quirk = find_quirk(dev);
1673 if (quirk->exit)
1674 quirk->exit(dev);
1675
1676 pci_disable_device(dev);
1677
1678 kfree(priv);
1679 }
1680
1681 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1682 {
1683 struct serial_private *priv = pci_get_drvdata(dev);
1684
1685 if (priv) {
1686 int i;
1687
1688 for (i = 0; i < priv->nr; i++)
1689 serial8250_suspend_port(priv->line[i]);
1690 }
1691 pci_save_state(dev);
1692 pci_set_power_state(dev, pci_choose_state(dev, state));
1693 return 0;
1694 }
1695
1696 static int pciserial_resume_one(struct pci_dev *dev)
1697 {
1698 struct serial_private *priv = pci_get_drvdata(dev);
1699
1700 pci_set_power_state(dev, PCI_D0);
1701 pci_restore_state(dev);
1702
1703 if (priv) {
1704 int i;
1705
1706 /*
1707 * The device may have been disabled. Re-enable it.
1708 */
1709 pci_enable_device(dev);
1710
1711 /*
1712 * Ensure that the board is correctly configured.
1713 */
1714 if (priv->quirk->init)
1715 priv->quirk->init(dev);
1716
1717 for (i = 0; i < priv->nr; i++)
1718 serial8250_resume_port(priv->line[i]);
1719 }
1720 return 0;
1721 }
1722
1723 static struct pci_device_id serial_pci_tbl[] = {
1724 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1725 PCI_SUBVENDOR_ID_CONNECT_TECH,
1726 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1727 pbn_b1_8_1382400 },
1728 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1729 PCI_SUBVENDOR_ID_CONNECT_TECH,
1730 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1731 pbn_b1_4_1382400 },
1732 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1733 PCI_SUBVENDOR_ID_CONNECT_TECH,
1734 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1735 pbn_b1_2_1382400 },
1736 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1737 PCI_SUBVENDOR_ID_CONNECT_TECH,
1738 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1739 pbn_b1_8_1382400 },
1740 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1741 PCI_SUBVENDOR_ID_CONNECT_TECH,
1742 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1743 pbn_b1_4_1382400 },
1744 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1745 PCI_SUBVENDOR_ID_CONNECT_TECH,
1746 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1747 pbn_b1_2_1382400 },
1748 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1749 PCI_SUBVENDOR_ID_CONNECT_TECH,
1750 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1751 pbn_b1_8_921600 },
1752 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1753 PCI_SUBVENDOR_ID_CONNECT_TECH,
1754 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1755 pbn_b1_8_921600 },
1756 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1757 PCI_SUBVENDOR_ID_CONNECT_TECH,
1758 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1759 pbn_b1_4_921600 },
1760 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1761 PCI_SUBVENDOR_ID_CONNECT_TECH,
1762 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1763 pbn_b1_4_921600 },
1764 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1765 PCI_SUBVENDOR_ID_CONNECT_TECH,
1766 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1767 pbn_b1_2_921600 },
1768 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1769 PCI_SUBVENDOR_ID_CONNECT_TECH,
1770 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1771 pbn_b1_8_921600 },
1772 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1773 PCI_SUBVENDOR_ID_CONNECT_TECH,
1774 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1775 pbn_b1_8_921600 },
1776 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1777 PCI_SUBVENDOR_ID_CONNECT_TECH,
1778 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1779 pbn_b1_4_921600 },
1780
1781 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1783 pbn_b2_bt_1_115200 },
1784 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1786 pbn_b2_bt_2_115200 },
1787 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1789 pbn_b2_bt_4_115200 },
1790 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1792 pbn_b2_bt_2_115200 },
1793 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1795 pbn_b2_bt_4_115200 },
1796 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1798 pbn_b2_8_115200 },
1799 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1801 pbn_b2_8_115200 },
1802
1803 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1805 pbn_b2_bt_2_115200 },
1806 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1808 pbn_b2_bt_2_921600 },
1809 /*
1810 * VScom SPCOM800, from sl@s.pl
1811 */
1812 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1814 pbn_b2_8_921600 },
1815 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1817 pbn_b2_4_921600 },
1818 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1819 PCI_SUBVENDOR_ID_KEYSPAN,
1820 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1821 pbn_panacom },
1822 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1824 pbn_panacom4 },
1825 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1827 pbn_panacom2 },
1828 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1829 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1830 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1831 pbn_b2_4_460800 },
1832 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1833 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1834 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1835 pbn_b2_8_460800 },
1836 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1837 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1838 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1839 pbn_b2_16_460800 },
1840 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1841 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1842 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1843 pbn_b2_16_460800 },
1844 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1845 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1846 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1847 pbn_b2_4_460800 },
1848 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1849 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1850 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1851 pbn_b2_8_460800 },
1852 /*
1853 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1854 * (Exoray@isys.ca)
1855 */
1856 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1857 0x10b5, 0x106a, 0, 0,
1858 pbn_plx_romulus },
1859 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1861 pbn_b1_4_115200 },
1862 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1863 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1864 pbn_b1_2_115200 },
1865 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1867 pbn_b1_8_115200 },
1868 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1870 pbn_b1_8_115200 },
1871 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1872 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1873 pbn_b0_4_921600 },
1874 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1875 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
1876 pbn_b0_4_1152000 },
1877 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1879 pbn_b0_4_115200 },
1880 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1882 pbn_b0_bt_2_921600 },
1883
1884 /*
1885 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1886 * from skokodyn@yahoo.com
1887 */
1888 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1889 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1890 pbn_sbsxrsio },
1891 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1892 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1893 pbn_sbsxrsio },
1894 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1895 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1896 pbn_sbsxrsio },
1897 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1898 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1899 pbn_sbsxrsio },
1900
1901 /*
1902 * Digitan DS560-558, from jimd@esoft.com
1903 */
1904 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1906 pbn_b1_1_115200 },
1907
1908 /*
1909 * Titan Electronic cards
1910 * The 400L and 800L have a custom setup quirk.
1911 */
1912 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1914 pbn_b0_1_921600 },
1915 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1917 pbn_b0_2_921600 },
1918 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1920 pbn_b0_4_921600 },
1921 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1923 pbn_b0_4_921600 },
1924 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1926 pbn_b1_1_921600 },
1927 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1929 pbn_b1_bt_2_921600 },
1930 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1932 pbn_b0_bt_4_921600 },
1933 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1935 pbn_b0_bt_8_921600 },
1936
1937 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1939 pbn_b2_1_460800 },
1940 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
1941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1942 pbn_b2_1_460800 },
1943 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
1944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1945 pbn_b2_1_460800 },
1946 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
1947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1948 pbn_b2_bt_2_921600 },
1949 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
1950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1951 pbn_b2_bt_2_921600 },
1952 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
1953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1954 pbn_b2_bt_2_921600 },
1955 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
1956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1957 pbn_b2_bt_4_921600 },
1958 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
1959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1960 pbn_b2_bt_4_921600 },
1961 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
1962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1963 pbn_b2_bt_4_921600 },
1964 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
1965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1966 pbn_b0_1_921600 },
1967 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
1968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1969 pbn_b0_1_921600 },
1970 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
1971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1972 pbn_b0_1_921600 },
1973 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
1974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1975 pbn_b0_bt_2_921600 },
1976 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
1977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1978 pbn_b0_bt_2_921600 },
1979 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
1980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1981 pbn_b0_bt_2_921600 },
1982 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
1983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1984 pbn_b0_bt_4_921600 },
1985 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
1986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1987 pbn_b0_bt_4_921600 },
1988 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
1989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1990 pbn_b0_bt_4_921600 },
1991
1992 /*
1993 * Computone devices submitted by Doug McNash dmcnash@computone.com
1994 */
1995 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
1996 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
1997 0, 0, pbn_computone_4 },
1998 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
1999 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2000 0, 0, pbn_computone_8 },
2001 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2002 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2003 0, 0, pbn_computone_6 },
2004
2005 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2007 pbn_oxsemi },
2008 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2009 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2010 pbn_b0_bt_1_921600 },
2011
2012 /*
2013 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2014 */
2015 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2017 pbn_b0_bt_8_115200 },
2018 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2020 pbn_b0_bt_8_115200 },
2021
2022 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2024 pbn_b0_bt_2_115200 },
2025 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2027 pbn_b0_bt_2_115200 },
2028 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2030 pbn_b0_bt_2_115200 },
2031 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2032 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2033 pbn_b0_bt_4_460800 },
2034 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2035 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2036 pbn_b0_bt_4_460800 },
2037 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2038 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2039 pbn_b0_bt_2_460800 },
2040 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2041 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2042 pbn_b0_bt_2_460800 },
2043 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2045 pbn_b0_bt_2_460800 },
2046 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2047 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2048 pbn_b0_bt_1_115200 },
2049 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2051 pbn_b0_bt_1_460800 },
2052
2053 /*
2054 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2055 */
2056 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2058 pbn_b1_1_1382400 },
2059
2060 /*
2061 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2062 */
2063 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2065 pbn_b1_1_1382400 },
2066
2067 /*
2068 * RAStel 2 port modem, gerg@moreton.com.au
2069 */
2070 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2072 pbn_b2_bt_2_115200 },
2073
2074 /*
2075 * EKF addition for i960 Boards form EKF with serial port
2076 */
2077 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2078 0xE4BF, PCI_ANY_ID, 0, 0,
2079 pbn_intel_i960 },
2080
2081 /*
2082 * Xircom Cardbus/Ethernet combos
2083 */
2084 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2086 pbn_b0_1_115200 },
2087 /*
2088 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2089 */
2090 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2092 pbn_b0_1_115200 },
2093
2094 /*
2095 * Untested PCI modems, sent in from various folks...
2096 */
2097
2098 /*
2099 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2100 */
2101 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2102 0x1048, 0x1500, 0, 0,
2103 pbn_b1_1_115200 },
2104
2105 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2106 0xFF00, 0, 0, 0,
2107 pbn_sgi_ioc3 },
2108
2109 /*
2110 * HP Diva card
2111 */
2112 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2113 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2114 pbn_b1_1_115200 },
2115 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2117 pbn_b0_5_115200 },
2118 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2120 pbn_b2_1_115200 },
2121
2122 /*
2123 * NEC Vrc-5074 (Nile 4) builtin UART.
2124 */
2125 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2127 pbn_nec_nile4 },
2128
2129 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2131 pbn_b3_4_115200 },
2132 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2134 pbn_b3_8_115200 },
2135
2136 /*
2137 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2138 */
2139 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2140 PCI_ANY_ID, PCI_ANY_ID,
2141 0,
2142 0, pbn_exar_XR17C152 },
2143 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2144 PCI_ANY_ID, PCI_ANY_ID,
2145 0,
2146 0, pbn_exar_XR17C154 },
2147 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2148 PCI_ANY_ID, PCI_ANY_ID,
2149 0,
2150 0, pbn_exar_XR17C158 },
2151
2152 /*
2153 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2154 */
2155 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2157 pbn_b0_1_115200 },
2158
2159 /*
2160 * These entries match devices with class COMMUNICATION_SERIAL,
2161 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2162 */
2163 { PCI_ANY_ID, PCI_ANY_ID,
2164 PCI_ANY_ID, PCI_ANY_ID,
2165 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2166 0xffff00, pbn_default },
2167 { PCI_ANY_ID, PCI_ANY_ID,
2168 PCI_ANY_ID, PCI_ANY_ID,
2169 PCI_CLASS_COMMUNICATION_MODEM << 8,
2170 0xffff00, pbn_default },
2171 { PCI_ANY_ID, PCI_ANY_ID,
2172 PCI_ANY_ID, PCI_ANY_ID,
2173 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2174 0xffff00, pbn_default },
2175 { 0, }
2176 };
2177
2178 static struct pci_driver serial_pci_driver = {
2179 .name = "serial",
2180 .probe = pciserial_init_one,
2181 .remove = __devexit_p(pciserial_remove_one),
2182 .suspend = pciserial_suspend_one,
2183 .resume = pciserial_resume_one,
2184 .id_table = serial_pci_tbl,
2185 };
2186
2187 static int __init serial8250_pci_init(void)
2188 {
2189 return pci_register_driver(&serial_pci_driver);
2190 }
2191
2192 static void __exit serial8250_pci_exit(void)
2193 {
2194 pci_unregister_driver(&serial_pci_driver);
2195 }
2196
2197 module_init(serial8250_pci_init);
2198 module_exit(serial8250_pci_exit);
2199
2200 MODULE_LICENSE("GPL");
2201 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2202 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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