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drm/radeon/kms: fix typo in r600 cs checker
[deliverable/linux.git] / drivers / serial / bfin_5xx.c
1 /*
2 * Blackfin On-Chip Serial Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12 #define SUPPORT_SYSRQ
13 #endif
14
15 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/gfp.h>
18 #include <linux/io.h>
19 #include <linux/init.h>
20 #include <linux/console.h>
21 #include <linux/sysrq.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/serial_core.h>
26 #include <linux/dma-mapping.h>
27
28 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
29 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
30 #include <linux/kgdb.h>
31 #include <asm/irq_regs.h>
32 #endif
33
34 #include <asm/gpio.h>
35 #include <mach/bfin_serial_5xx.h>
36
37 #include <asm/dma.h>
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 #include <asm/cacheflush.h>
41
42 #ifdef CONFIG_SERIAL_BFIN_MODULE
43 # undef CONFIG_EARLY_PRINTK
44 #endif
45
46 #ifdef CONFIG_SERIAL_BFIN_MODULE
47 # undef CONFIG_EARLY_PRINTK
48 #endif
49
50 /* UART name and device definitions */
51 #define BFIN_SERIAL_NAME "ttyBF"
52 #define BFIN_SERIAL_MAJOR 204
53 #define BFIN_SERIAL_MINOR 64
54
55 static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
56 static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource);
57
58 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
59 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
60
61 # ifndef CONFIG_SERIAL_BFIN_PIO
62 # error KGDB only support UART in PIO mode.
63 # endif
64
65 static int kgdboc_port_line;
66 static int kgdboc_break_enabled;
67 #endif
68 /*
69 * Setup for console. Argument comes from the menuconfig
70 */
71 #define DMA_RX_XCOUNT 512
72 #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
73
74 #define DMA_RX_FLUSH_JIFFIES (HZ / 50)
75
76 #ifdef CONFIG_SERIAL_BFIN_DMA
77 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
78 #else
79 static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
80 #endif
81
82 static void bfin_serial_reset_irda(struct uart_port *port);
83
84 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
85 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
86 static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
87 {
88 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
89 if (uart->cts_pin < 0)
90 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
91
92 /* CTS PIN is negative assertive. */
93 if (UART_GET_CTS(uart))
94 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
95 else
96 return TIOCM_DSR | TIOCM_CAR;
97 }
98
99 static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
100 {
101 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
102 if (uart->rts_pin < 0)
103 return;
104
105 /* RTS PIN is negative assertive. */
106 if (mctrl & TIOCM_RTS)
107 UART_ENABLE_RTS(uart);
108 else
109 UART_DISABLE_RTS(uart);
110 }
111
112 /*
113 * Handle any change of modem status signal.
114 */
115 static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
116 {
117 struct bfin_serial_port *uart = dev_id;
118 unsigned int status;
119
120 status = bfin_serial_get_mctrl(&uart->port);
121 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
122 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
123 uart->scts = 1;
124 UART_CLEAR_SCTS(uart);
125 UART_CLEAR_IER(uart, EDSSI);
126 #endif
127
128 return IRQ_HANDLED;
129 }
130 #else
131 static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
132 {
133 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
134 }
135
136 static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
137 {
138 }
139 #endif
140
141 /*
142 * interrupts are disabled on entry
143 */
144 static void bfin_serial_stop_tx(struct uart_port *port)
145 {
146 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
147 #ifdef CONFIG_SERIAL_BFIN_DMA
148 struct circ_buf *xmit = &uart->port.state->xmit;
149 #endif
150
151 while (!(UART_GET_LSR(uart) & TEMT))
152 cpu_relax();
153
154 #ifdef CONFIG_SERIAL_BFIN_DMA
155 disable_dma(uart->tx_dma_channel);
156 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
157 uart->port.icount.tx += uart->tx_count;
158 uart->tx_count = 0;
159 uart->tx_done = 1;
160 #else
161 #ifdef CONFIG_BF54x
162 /* Clear TFI bit */
163 UART_PUT_LSR(uart, TFI);
164 #endif
165 UART_CLEAR_IER(uart, ETBEI);
166 #endif
167 }
168
169 /*
170 * port is locked and interrupts are disabled
171 */
172 static void bfin_serial_start_tx(struct uart_port *port)
173 {
174 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
175 struct tty_struct *tty = uart->port.state->port.tty;
176
177 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
178 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
179 uart->scts = 0;
180 uart_handle_cts_change(&uart->port, uart->scts);
181 }
182 #endif
183
184 /*
185 * To avoid losting RX interrupt, we reset IR function
186 * before sending data.
187 */
188 if (tty->termios->c_line == N_IRDA)
189 bfin_serial_reset_irda(port);
190
191 #ifdef CONFIG_SERIAL_BFIN_DMA
192 if (uart->tx_done)
193 bfin_serial_dma_tx_chars(uart);
194 #else
195 UART_SET_IER(uart, ETBEI);
196 bfin_serial_tx_chars(uart);
197 #endif
198 }
199
200 /*
201 * Interrupts are enabled
202 */
203 static void bfin_serial_stop_rx(struct uart_port *port)
204 {
205 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
206
207 UART_CLEAR_IER(uart, ERBFI);
208 }
209
210 /*
211 * Set the modem control timer to fire immediately.
212 */
213 static void bfin_serial_enable_ms(struct uart_port *port)
214 {
215 }
216
217
218 #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
219 # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
220 # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
221 #else
222 # define UART_GET_ANOMALY_THRESHOLD(uart) 0
223 # define UART_SET_ANOMALY_THRESHOLD(uart, v)
224 #endif
225
226 #ifdef CONFIG_SERIAL_BFIN_PIO
227 static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
228 {
229 struct tty_struct *tty = NULL;
230 unsigned int status, ch, flg;
231 static struct timeval anomaly_start = { .tv_sec = 0 };
232
233 status = UART_GET_LSR(uart);
234 UART_CLEAR_LSR(uart);
235
236 ch = UART_GET_CHAR(uart);
237 uart->port.icount.rx++;
238
239 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
240 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
241 if (kgdb_connected && kgdboc_port_line == uart->port.line
242 && kgdboc_break_enabled)
243 if (ch == 0x3) {/* Ctrl + C */
244 kgdb_breakpoint();
245 return;
246 }
247
248 if (!uart->port.state || !uart->port.state->port.tty)
249 return;
250 #endif
251 tty = uart->port.state->port.tty;
252
253 if (ANOMALY_05000363) {
254 /* The BF533 (and BF561) family of processors have a nice anomaly
255 * where they continuously generate characters for a "single" break.
256 * We have to basically ignore this flood until the "next" valid
257 * character comes across. Due to the nature of the flood, it is
258 * not possible to reliably catch bytes that are sent too quickly
259 * after this break. So application code talking to the Blackfin
260 * which sends a break signal must allow at least 1.5 character
261 * times after the end of the break for things to stabilize. This
262 * timeout was picked as it must absolutely be larger than 1
263 * character time +/- some percent. So 1.5 sounds good. All other
264 * Blackfin families operate properly. Woo.
265 */
266 if (anomaly_start.tv_sec) {
267 struct timeval curr;
268 suseconds_t usecs;
269
270 if ((~ch & (~ch + 1)) & 0xff)
271 goto known_good_char;
272
273 do_gettimeofday(&curr);
274 if (curr.tv_sec - anomaly_start.tv_sec > 1)
275 goto known_good_char;
276
277 usecs = 0;
278 if (curr.tv_sec != anomaly_start.tv_sec)
279 usecs += USEC_PER_SEC;
280 usecs += curr.tv_usec - anomaly_start.tv_usec;
281
282 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
283 goto known_good_char;
284
285 if (ch)
286 anomaly_start.tv_sec = 0;
287 else
288 anomaly_start = curr;
289
290 return;
291
292 known_good_char:
293 status &= ~BI;
294 anomaly_start.tv_sec = 0;
295 }
296 }
297
298 if (status & BI) {
299 if (ANOMALY_05000363)
300 if (bfin_revid() < 5)
301 do_gettimeofday(&anomaly_start);
302 uart->port.icount.brk++;
303 if (uart_handle_break(&uart->port))
304 goto ignore_char;
305 status &= ~(PE | FE);
306 }
307 if (status & PE)
308 uart->port.icount.parity++;
309 if (status & OE)
310 uart->port.icount.overrun++;
311 if (status & FE)
312 uart->port.icount.frame++;
313
314 status &= uart->port.read_status_mask;
315
316 if (status & BI)
317 flg = TTY_BREAK;
318 else if (status & PE)
319 flg = TTY_PARITY;
320 else if (status & FE)
321 flg = TTY_FRAME;
322 else
323 flg = TTY_NORMAL;
324
325 if (uart_handle_sysrq_char(&uart->port, ch))
326 goto ignore_char;
327
328 uart_insert_char(&uart->port, status, OE, ch, flg);
329
330 ignore_char:
331 tty_flip_buffer_push(tty);
332 }
333
334 static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
335 {
336 struct circ_buf *xmit = &uart->port.state->xmit;
337
338 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
339 #ifdef CONFIG_BF54x
340 /* Clear TFI bit */
341 UART_PUT_LSR(uart, TFI);
342 #endif
343 /* Anomaly notes:
344 * 05000215 - we always clear ETBEI within last UART TX
345 * interrupt to end a string. It is always set
346 * when start a new tx.
347 */
348 UART_CLEAR_IER(uart, ETBEI);
349 return;
350 }
351
352 if (uart->port.x_char) {
353 UART_PUT_CHAR(uart, uart->port.x_char);
354 uart->port.icount.tx++;
355 uart->port.x_char = 0;
356 }
357
358 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
359 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
360 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
361 uart->port.icount.tx++;
362 }
363
364 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
365 uart_write_wakeup(&uart->port);
366 }
367
368 static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
369 {
370 struct bfin_serial_port *uart = dev_id;
371
372 spin_lock(&uart->port.lock);
373 while (UART_GET_LSR(uart) & DR)
374 bfin_serial_rx_chars(uart);
375 spin_unlock(&uart->port.lock);
376
377 return IRQ_HANDLED;
378 }
379
380 static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
381 {
382 struct bfin_serial_port *uart = dev_id;
383
384 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
385 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
386 uart->scts = 0;
387 uart_handle_cts_change(&uart->port, uart->scts);
388 }
389 #endif
390 spin_lock(&uart->port.lock);
391 if (UART_GET_LSR(uart) & THRE)
392 bfin_serial_tx_chars(uart);
393 spin_unlock(&uart->port.lock);
394
395 return IRQ_HANDLED;
396 }
397 #endif
398
399 #ifdef CONFIG_SERIAL_BFIN_DMA
400 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
401 {
402 struct circ_buf *xmit = &uart->port.state->xmit;
403
404 uart->tx_done = 0;
405
406 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
407 uart->tx_count = 0;
408 uart->tx_done = 1;
409 return;
410 }
411
412 if (uart->port.x_char) {
413 UART_PUT_CHAR(uart, uart->port.x_char);
414 uart->port.icount.tx++;
415 uart->port.x_char = 0;
416 }
417
418 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
419 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
420 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
421 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
422 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
423 set_dma_config(uart->tx_dma_channel,
424 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
425 INTR_ON_BUF,
426 DIMENSION_LINEAR,
427 DATA_SIZE_8,
428 DMA_SYNC_RESTART));
429 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
430 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
431 set_dma_x_modify(uart->tx_dma_channel, 1);
432 SSYNC();
433 enable_dma(uart->tx_dma_channel);
434
435 UART_SET_IER(uart, ETBEI);
436 }
437
438 static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
439 {
440 struct tty_struct *tty = uart->port.state->port.tty;
441 int i, flg, status;
442
443 status = UART_GET_LSR(uart);
444 UART_CLEAR_LSR(uart);
445
446 uart->port.icount.rx +=
447 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
448 UART_XMIT_SIZE);
449
450 if (status & BI) {
451 uart->port.icount.brk++;
452 if (uart_handle_break(&uart->port))
453 goto dma_ignore_char;
454 status &= ~(PE | FE);
455 }
456 if (status & PE)
457 uart->port.icount.parity++;
458 if (status & OE)
459 uart->port.icount.overrun++;
460 if (status & FE)
461 uart->port.icount.frame++;
462
463 status &= uart->port.read_status_mask;
464
465 if (status & BI)
466 flg = TTY_BREAK;
467 else if (status & PE)
468 flg = TTY_PARITY;
469 else if (status & FE)
470 flg = TTY_FRAME;
471 else
472 flg = TTY_NORMAL;
473
474 for (i = uart->rx_dma_buf.tail; ; i++) {
475 if (i >= UART_XMIT_SIZE)
476 i = 0;
477 if (i == uart->rx_dma_buf.head)
478 break;
479 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
480 uart_insert_char(&uart->port, status, OE,
481 uart->rx_dma_buf.buf[i], flg);
482 }
483
484 dma_ignore_char:
485 tty_flip_buffer_push(tty);
486 }
487
488 void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
489 {
490 int x_pos, pos;
491
492 dma_disable_irq(uart->tx_dma_channel);
493 dma_disable_irq(uart->rx_dma_channel);
494 spin_lock_bh(&uart->port.lock);
495
496 /* 2D DMA RX buffer ring is used. Because curr_y_count and
497 * curr_x_count can't be read as an atomic operation,
498 * curr_y_count should be read before curr_x_count. When
499 * curr_x_count is read, curr_y_count may already indicate
500 * next buffer line. But, the position calculated here is
501 * still indicate the old line. The wrong position data may
502 * be smaller than current buffer tail, which cause garbages
503 * are received if it is not prohibit.
504 */
505 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
506 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
507 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
508 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
509 uart->rx_dma_nrows = 0;
510 x_pos = DMA_RX_XCOUNT - x_pos;
511 if (x_pos == DMA_RX_XCOUNT)
512 x_pos = 0;
513
514 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
515 /* Ignore receiving data if new position is in the same line of
516 * current buffer tail and small.
517 */
518 if (pos > uart->rx_dma_buf.tail ||
519 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
520 uart->rx_dma_buf.head = pos;
521 bfin_serial_dma_rx_chars(uart);
522 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
523 }
524
525 spin_unlock_bh(&uart->port.lock);
526 dma_enable_irq(uart->tx_dma_channel);
527 dma_enable_irq(uart->rx_dma_channel);
528
529 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
530 }
531
532 static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
533 {
534 struct bfin_serial_port *uart = dev_id;
535 struct circ_buf *xmit = &uart->port.state->xmit;
536
537 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
538 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
539 uart->scts = 0;
540 uart_handle_cts_change(&uart->port, uart->scts);
541 }
542 #endif
543
544 spin_lock(&uart->port.lock);
545 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
546 disable_dma(uart->tx_dma_channel);
547 clear_dma_irqstat(uart->tx_dma_channel);
548 /* Anomaly notes:
549 * 05000215 - we always clear ETBEI within last UART TX
550 * interrupt to end a string. It is always set
551 * when start a new tx.
552 */
553 UART_CLEAR_IER(uart, ETBEI);
554 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
555 uart->port.icount.tx += uart->tx_count;
556
557 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
558 uart_write_wakeup(&uart->port);
559
560 bfin_serial_dma_tx_chars(uart);
561 }
562
563 spin_unlock(&uart->port.lock);
564 return IRQ_HANDLED;
565 }
566
567 static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
568 {
569 struct bfin_serial_port *uart = dev_id;
570 unsigned short irqstat;
571 int x_pos, pos;
572
573 spin_lock(&uart->port.lock);
574 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
575 clear_dma_irqstat(uart->rx_dma_channel);
576
577 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
578 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
579 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
580 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
581 uart->rx_dma_nrows = 0;
582
583 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
584 if (pos > uart->rx_dma_buf.tail ||
585 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
586 uart->rx_dma_buf.head = pos;
587 bfin_serial_dma_rx_chars(uart);
588 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
589 }
590
591 spin_unlock(&uart->port.lock);
592
593 return IRQ_HANDLED;
594 }
595 #endif
596
597 /*
598 * Return TIOCSER_TEMT when transmitter is not busy.
599 */
600 static unsigned int bfin_serial_tx_empty(struct uart_port *port)
601 {
602 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
603 unsigned short lsr;
604
605 lsr = UART_GET_LSR(uart);
606 if (lsr & TEMT)
607 return TIOCSER_TEMT;
608 else
609 return 0;
610 }
611
612 static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
613 {
614 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
615 u16 lcr = UART_GET_LCR(uart);
616 if (break_state)
617 lcr |= SB;
618 else
619 lcr &= ~SB;
620 UART_PUT_LCR(uart, lcr);
621 SSYNC();
622 }
623
624 static int bfin_serial_startup(struct uart_port *port)
625 {
626 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
627
628 #ifdef CONFIG_SERIAL_BFIN_DMA
629 dma_addr_t dma_handle;
630
631 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
632 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
633 return -EBUSY;
634 }
635
636 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
637 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
638 free_dma(uart->rx_dma_channel);
639 return -EBUSY;
640 }
641
642 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
643 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
644
645 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
646 uart->rx_dma_buf.head = 0;
647 uart->rx_dma_buf.tail = 0;
648 uart->rx_dma_nrows = 0;
649
650 set_dma_config(uart->rx_dma_channel,
651 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
652 INTR_ON_ROW, DIMENSION_2D,
653 DATA_SIZE_8,
654 DMA_SYNC_RESTART));
655 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
656 set_dma_x_modify(uart->rx_dma_channel, 1);
657 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
658 set_dma_y_modify(uart->rx_dma_channel, 1);
659 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
660 enable_dma(uart->rx_dma_channel);
661
662 uart->rx_dma_timer.data = (unsigned long)(uart);
663 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
664 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
665 add_timer(&(uart->rx_dma_timer));
666 #else
667 # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
668 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
669 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
670 kgdboc_break_enabled = 0;
671 else {
672 # endif
673 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
674 "BFIN_UART_RX", uart)) {
675 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
676 return -EBUSY;
677 }
678
679 if (request_irq
680 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
681 "BFIN_UART_TX", uart)) {
682 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
683 free_irq(uart->port.irq, uart);
684 return -EBUSY;
685 }
686
687 # ifdef CONFIG_BF54x
688 {
689 /*
690 * UART2 and UART3 on BF548 share interrupt PINs and DMA
691 * controllers with SPORT2 and SPORT3. UART rx and tx
692 * interrupts are generated in PIO mode only when configure
693 * their peripheral mapping registers properly, which means
694 * request corresponding DMA channels in PIO mode as well.
695 */
696 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
697
698 switch (uart->port.irq) {
699 case IRQ_UART3_RX:
700 uart_dma_ch_rx = CH_UART3_RX;
701 uart_dma_ch_tx = CH_UART3_TX;
702 break;
703 case IRQ_UART2_RX:
704 uart_dma_ch_rx = CH_UART2_RX;
705 uart_dma_ch_tx = CH_UART2_TX;
706 break;
707 default:
708 uart_dma_ch_rx = uart_dma_ch_tx = 0;
709 break;
710 };
711
712 if (uart_dma_ch_rx &&
713 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
714 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
715 free_irq(uart->port.irq, uart);
716 free_irq(uart->port.irq + 1, uart);
717 return -EBUSY;
718 }
719 if (uart_dma_ch_tx &&
720 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
721 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
722 free_dma(uart_dma_ch_rx);
723 free_irq(uart->port.irq, uart);
724 free_irq(uart->port.irq + 1, uart);
725 return -EBUSY;
726 }
727 }
728 # endif
729 # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
730 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
731 }
732 # endif
733 #endif
734
735 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
736 if (uart->cts_pin >= 0) {
737 if (request_irq(gpio_to_irq(uart->cts_pin),
738 bfin_serial_mctrl_cts_int,
739 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
740 IRQF_DISABLED, "BFIN_UART_CTS", uart)) {
741 uart->cts_pin = -1;
742 pr_info("Unable to attach BlackFin UART CTS interrupt. So, disable it.\n");
743 }
744 }
745 if (uart->rts_pin >= 0) {
746 gpio_request(uart->rts_pin, DRIVER_NAME);
747 gpio_direction_output(uart->rts_pin, 0);
748 }
749 #endif
750 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
751 if (request_irq(uart->status_irq,
752 bfin_serial_mctrl_cts_int,
753 IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
754 pr_info("Unable to attach BlackFin UART Modem Status interrupt.\n");
755 }
756
757 /* CTS RTS PINs are negative assertive. */
758 UART_PUT_MCR(uart, ACTS);
759 UART_SET_IER(uart, EDSSI);
760 #endif
761
762 UART_SET_IER(uart, ERBFI);
763 return 0;
764 }
765
766 static void bfin_serial_shutdown(struct uart_port *port)
767 {
768 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
769
770 #ifdef CONFIG_SERIAL_BFIN_DMA
771 disable_dma(uart->tx_dma_channel);
772 free_dma(uart->tx_dma_channel);
773 disable_dma(uart->rx_dma_channel);
774 free_dma(uart->rx_dma_channel);
775 del_timer(&(uart->rx_dma_timer));
776 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
777 #else
778 #ifdef CONFIG_BF54x
779 switch (uart->port.irq) {
780 case IRQ_UART3_RX:
781 free_dma(CH_UART3_RX);
782 free_dma(CH_UART3_TX);
783 break;
784 case IRQ_UART2_RX:
785 free_dma(CH_UART2_RX);
786 free_dma(CH_UART2_TX);
787 break;
788 default:
789 break;
790 };
791 #endif
792 free_irq(uart->port.irq, uart);
793 free_irq(uart->port.irq+1, uart);
794 #endif
795
796 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
797 if (uart->cts_pin >= 0)
798 free_irq(gpio_to_irq(uart->cts_pin), uart);
799 if (uart->rts_pin >= 0)
800 gpio_free(uart->rts_pin);
801 #endif
802 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
803 if (UART_GET_IER(uart) & EDSSI)
804 free_irq(uart->status_irq, uart);
805 #endif
806 }
807
808 static void
809 bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
810 struct ktermios *old)
811 {
812 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
813 unsigned long flags;
814 unsigned int baud, quot;
815 unsigned short val, ier, lcr = 0;
816
817 switch (termios->c_cflag & CSIZE) {
818 case CS8:
819 lcr = WLS(8);
820 break;
821 case CS7:
822 lcr = WLS(7);
823 break;
824 case CS6:
825 lcr = WLS(6);
826 break;
827 case CS5:
828 lcr = WLS(5);
829 break;
830 default:
831 printk(KERN_ERR "%s: word lengh not supported\n",
832 __func__);
833 }
834
835 /* Anomaly notes:
836 * 05000231 - STOP bit is always set to 1 whatever the user is set.
837 */
838 if (termios->c_cflag & CSTOPB) {
839 if (ANOMALY_05000231)
840 printk(KERN_WARNING "STOP bits other than 1 is not "
841 "supported in case of anomaly 05000231.\n");
842 else
843 lcr |= STB;
844 }
845 if (termios->c_cflag & PARENB)
846 lcr |= PEN;
847 if (!(termios->c_cflag & PARODD))
848 lcr |= EPS;
849 if (termios->c_cflag & CMSPAR)
850 lcr |= STP;
851
852 spin_lock_irqsave(&uart->port.lock, flags);
853
854 port->read_status_mask = OE;
855 if (termios->c_iflag & INPCK)
856 port->read_status_mask |= (FE | PE);
857 if (termios->c_iflag & (BRKINT | PARMRK))
858 port->read_status_mask |= BI;
859
860 /*
861 * Characters to ignore
862 */
863 port->ignore_status_mask = 0;
864 if (termios->c_iflag & IGNPAR)
865 port->ignore_status_mask |= FE | PE;
866 if (termios->c_iflag & IGNBRK) {
867 port->ignore_status_mask |= BI;
868 /*
869 * If we're ignoring parity and break indicators,
870 * ignore overruns too (for real raw support).
871 */
872 if (termios->c_iflag & IGNPAR)
873 port->ignore_status_mask |= OE;
874 }
875
876 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
877 quot = uart_get_divisor(port, baud);
878
879 /* If discipline is not IRDA, apply ANOMALY_05000230 */
880 if (termios->c_line != N_IRDA)
881 quot -= ANOMALY_05000230;
882
883 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
884
885 /* Disable UART */
886 ier = UART_GET_IER(uart);
887 UART_DISABLE_INTS(uart);
888
889 /* Set DLAB in LCR to Access DLL and DLH */
890 UART_SET_DLAB(uart);
891
892 UART_PUT_DLL(uart, quot & 0xFF);
893 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
894 SSYNC();
895
896 /* Clear DLAB in LCR to Access THR RBR IER */
897 UART_CLEAR_DLAB(uart);
898
899 UART_PUT_LCR(uart, lcr);
900
901 /* Enable UART */
902 UART_ENABLE_INTS(uart, ier);
903
904 val = UART_GET_GCTL(uart);
905 val |= UCEN;
906 UART_PUT_GCTL(uart, val);
907
908 /* Port speed changed, update the per-port timeout. */
909 uart_update_timeout(port, termios->c_cflag, baud);
910
911 spin_unlock_irqrestore(&uart->port.lock, flags);
912 }
913
914 static const char *bfin_serial_type(struct uart_port *port)
915 {
916 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
917
918 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
919 }
920
921 /*
922 * Release the memory region(s) being used by 'port'.
923 */
924 static void bfin_serial_release_port(struct uart_port *port)
925 {
926 }
927
928 /*
929 * Request the memory region(s) being used by 'port'.
930 */
931 static int bfin_serial_request_port(struct uart_port *port)
932 {
933 return 0;
934 }
935
936 /*
937 * Configure/autoconfigure the port.
938 */
939 static void bfin_serial_config_port(struct uart_port *port, int flags)
940 {
941 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
942
943 if (flags & UART_CONFIG_TYPE &&
944 bfin_serial_request_port(&uart->port) == 0)
945 uart->port.type = PORT_BFIN;
946 }
947
948 /*
949 * Verify the new serial_struct (for TIOCSSERIAL).
950 * The only change we allow are to the flags and type, and
951 * even then only between PORT_BFIN and PORT_UNKNOWN
952 */
953 static int
954 bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
955 {
956 return 0;
957 }
958
959 /*
960 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
961 * In other cases, disable IrDA function.
962 */
963 static void bfin_serial_set_ldisc(struct uart_port *port, int ld)
964 {
965 int line = port->line;
966 unsigned short val;
967
968 switch (ld) {
969 case N_IRDA:
970 val = UART_GET_GCTL(&bfin_serial_ports[line]);
971 val |= (IREN | RPOLC);
972 UART_PUT_GCTL(&bfin_serial_ports[line], val);
973 break;
974 default:
975 val = UART_GET_GCTL(&bfin_serial_ports[line]);
976 val &= ~(IREN | RPOLC);
977 UART_PUT_GCTL(&bfin_serial_ports[line], val);
978 }
979 }
980
981 static void bfin_serial_reset_irda(struct uart_port *port)
982 {
983 int line = port->line;
984 unsigned short val;
985
986 val = UART_GET_GCTL(&bfin_serial_ports[line]);
987 val &= ~(IREN | RPOLC);
988 UART_PUT_GCTL(&bfin_serial_ports[line], val);
989 SSYNC();
990 val |= (IREN | RPOLC);
991 UART_PUT_GCTL(&bfin_serial_ports[line], val);
992 SSYNC();
993 }
994
995 #ifdef CONFIG_CONSOLE_POLL
996 /* Anomaly notes:
997 * 05000099 - Because we only use THRE in poll_put and DR in poll_get,
998 * losing other bits of UART_LSR is not a problem here.
999 */
1000 static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
1001 {
1002 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1003
1004 while (!(UART_GET_LSR(uart) & THRE))
1005 cpu_relax();
1006
1007 UART_CLEAR_DLAB(uart);
1008 UART_PUT_CHAR(uart, (unsigned char)chr);
1009 }
1010
1011 static int bfin_serial_poll_get_char(struct uart_port *port)
1012 {
1013 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1014 unsigned char chr;
1015
1016 while (!(UART_GET_LSR(uart) & DR))
1017 cpu_relax();
1018
1019 UART_CLEAR_DLAB(uart);
1020 chr = UART_GET_CHAR(uart);
1021
1022 return chr;
1023 }
1024 #endif
1025
1026 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1027 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1028 static void bfin_kgdboc_port_shutdown(struct uart_port *port)
1029 {
1030 if (kgdboc_break_enabled) {
1031 kgdboc_break_enabled = 0;
1032 bfin_serial_shutdown(port);
1033 }
1034 }
1035
1036 static int bfin_kgdboc_port_startup(struct uart_port *port)
1037 {
1038 kgdboc_port_line = port->line;
1039 kgdboc_break_enabled = !bfin_serial_startup(port);
1040 return 0;
1041 }
1042 #endif
1043
1044 static struct uart_ops bfin_serial_pops = {
1045 .tx_empty = bfin_serial_tx_empty,
1046 .set_mctrl = bfin_serial_set_mctrl,
1047 .get_mctrl = bfin_serial_get_mctrl,
1048 .stop_tx = bfin_serial_stop_tx,
1049 .start_tx = bfin_serial_start_tx,
1050 .stop_rx = bfin_serial_stop_rx,
1051 .enable_ms = bfin_serial_enable_ms,
1052 .break_ctl = bfin_serial_break_ctl,
1053 .startup = bfin_serial_startup,
1054 .shutdown = bfin_serial_shutdown,
1055 .set_termios = bfin_serial_set_termios,
1056 .set_ldisc = bfin_serial_set_ldisc,
1057 .type = bfin_serial_type,
1058 .release_port = bfin_serial_release_port,
1059 .request_port = bfin_serial_request_port,
1060 .config_port = bfin_serial_config_port,
1061 .verify_port = bfin_serial_verify_port,
1062 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1063 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1064 .kgdboc_port_startup = bfin_kgdboc_port_startup,
1065 .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown,
1066 #endif
1067 #ifdef CONFIG_CONSOLE_POLL
1068 .poll_put_char = bfin_serial_poll_put_char,
1069 .poll_get_char = bfin_serial_poll_get_char,
1070 #endif
1071 };
1072
1073 static void __init bfin_serial_hw_init(void)
1074 {
1075 #ifdef CONFIG_SERIAL_BFIN_UART0
1076 peripheral_request(P_UART0_TX, DRIVER_NAME);
1077 peripheral_request(P_UART0_RX, DRIVER_NAME);
1078 #endif
1079
1080 #ifdef CONFIG_SERIAL_BFIN_UART1
1081 peripheral_request(P_UART1_TX, DRIVER_NAME);
1082 peripheral_request(P_UART1_RX, DRIVER_NAME);
1083
1084 # if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x)
1085 peripheral_request(P_UART1_RTS, DRIVER_NAME);
1086 peripheral_request(P_UART1_CTS, DRIVER_NAME);
1087 # endif
1088 #endif
1089
1090 #ifdef CONFIG_SERIAL_BFIN_UART2
1091 peripheral_request(P_UART2_TX, DRIVER_NAME);
1092 peripheral_request(P_UART2_RX, DRIVER_NAME);
1093 #endif
1094
1095 #ifdef CONFIG_SERIAL_BFIN_UART3
1096 peripheral_request(P_UART3_TX, DRIVER_NAME);
1097 peripheral_request(P_UART3_RX, DRIVER_NAME);
1098
1099 # if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x)
1100 peripheral_request(P_UART3_RTS, DRIVER_NAME);
1101 peripheral_request(P_UART3_CTS, DRIVER_NAME);
1102 # endif
1103 #endif
1104 }
1105
1106 static void __init bfin_serial_init_ports(void)
1107 {
1108 static int first = 1;
1109 int i;
1110
1111 if (!first)
1112 return;
1113 first = 0;
1114
1115 bfin_serial_hw_init();
1116
1117 for (i = 0; i < nr_active_ports; i++) {
1118 spin_lock_init(&bfin_serial_ports[i].port.lock);
1119 bfin_serial_ports[i].port.uartclk = get_sclk();
1120 bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE;
1121 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
1122 bfin_serial_ports[i].port.line = i;
1123 bfin_serial_ports[i].port.iotype = UPIO_MEM;
1124 bfin_serial_ports[i].port.membase =
1125 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
1126 bfin_serial_ports[i].port.mapbase =
1127 bfin_serial_resource[i].uart_base_addr;
1128 bfin_serial_ports[i].port.irq =
1129 bfin_serial_resource[i].uart_irq;
1130 bfin_serial_ports[i].status_irq =
1131 bfin_serial_resource[i].uart_status_irq;
1132 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
1133 #ifdef CONFIG_SERIAL_BFIN_DMA
1134 bfin_serial_ports[i].tx_done = 1;
1135 bfin_serial_ports[i].tx_count = 0;
1136 bfin_serial_ports[i].tx_dma_channel =
1137 bfin_serial_resource[i].uart_tx_dma_channel;
1138 bfin_serial_ports[i].rx_dma_channel =
1139 bfin_serial_resource[i].uart_rx_dma_channel;
1140 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
1141 #endif
1142 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1143 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1144 bfin_serial_ports[i].cts_pin =
1145 bfin_serial_resource[i].uart_cts_pin;
1146 bfin_serial_ports[i].rts_pin =
1147 bfin_serial_resource[i].uart_rts_pin;
1148 #endif
1149 }
1150 }
1151
1152 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1153 /*
1154 * If the port was already initialised (eg, by a boot loader),
1155 * try to determine the current setup.
1156 */
1157 static void __init
1158 bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1159 int *parity, int *bits)
1160 {
1161 unsigned short status;
1162
1163 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1164 if (status == (ERBFI | ETBEI)) {
1165 /* ok, the port was enabled */
1166 u16 lcr, dlh, dll;
1167
1168 lcr = UART_GET_LCR(uart);
1169
1170 *parity = 'n';
1171 if (lcr & PEN) {
1172 if (lcr & EPS)
1173 *parity = 'e';
1174 else
1175 *parity = 'o';
1176 }
1177 switch (lcr & 0x03) {
1178 case 0: *bits = 5; break;
1179 case 1: *bits = 6; break;
1180 case 2: *bits = 7; break;
1181 case 3: *bits = 8; break;
1182 }
1183 /* Set DLAB in LCR to Access DLL and DLH */
1184 UART_SET_DLAB(uart);
1185
1186 dll = UART_GET_DLL(uart);
1187 dlh = UART_GET_DLH(uart);
1188
1189 /* Clear DLAB in LCR to Access THR RBR IER */
1190 UART_CLEAR_DLAB(uart);
1191
1192 *baud = get_sclk() / (16*(dll | dlh << 8));
1193 }
1194 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
1195 }
1196
1197 static struct uart_driver bfin_serial_reg;
1198
1199 static int __init
1200 bfin_serial_console_setup(struct console *co, char *options)
1201 {
1202 struct bfin_serial_port *uart;
1203 int baud = 57600;
1204 int bits = 8;
1205 int parity = 'n';
1206 # if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1207 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1208 int flow = 'r';
1209 # else
1210 int flow = 'n';
1211 # endif
1212
1213 /*
1214 * Check whether an invalid uart number has been specified, and
1215 * if so, search for the first available port that does have
1216 * console support.
1217 */
1218 if (co->index == -1 || co->index >= nr_active_ports)
1219 co->index = 0;
1220 uart = &bfin_serial_ports[co->index];
1221
1222 if (options)
1223 uart_parse_options(options, &baud, &parity, &bits, &flow);
1224 else
1225 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1226
1227 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
1228 }
1229 #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1230 defined (CONFIG_EARLY_PRINTK) */
1231
1232 #ifdef CONFIG_SERIAL_BFIN_CONSOLE
1233 static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1234 {
1235 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1236 while (!(UART_GET_LSR(uart) & THRE))
1237 barrier();
1238 UART_PUT_CHAR(uart, ch);
1239 SSYNC();
1240 }
1241
1242 /*
1243 * Interrupts are disabled on entering
1244 */
1245 static void
1246 bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1247 {
1248 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1249 unsigned long flags;
1250
1251 spin_lock_irqsave(&uart->port.lock, flags);
1252 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1253 spin_unlock_irqrestore(&uart->port.lock, flags);
1254
1255 }
1256
1257 static struct console bfin_serial_console = {
1258 .name = BFIN_SERIAL_NAME,
1259 .write = bfin_serial_console_write,
1260 .device = uart_console_device,
1261 .setup = bfin_serial_console_setup,
1262 .flags = CON_PRINTBUFFER,
1263 .index = -1,
1264 .data = &bfin_serial_reg,
1265 };
1266
1267 static int __init bfin_serial_rs_console_init(void)
1268 {
1269 bfin_serial_init_ports();
1270 register_console(&bfin_serial_console);
1271
1272 return 0;
1273 }
1274 console_initcall(bfin_serial_rs_console_init);
1275
1276 #define BFIN_SERIAL_CONSOLE &bfin_serial_console
1277 #else
1278 #define BFIN_SERIAL_CONSOLE NULL
1279 #endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1280
1281
1282 #ifdef CONFIG_EARLY_PRINTK
1283 static __init void early_serial_putc(struct uart_port *port, int ch)
1284 {
1285 unsigned timeout = 0xffff;
1286 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1287
1288 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1289 cpu_relax();
1290 UART_PUT_CHAR(uart, ch);
1291 }
1292
1293 static __init void early_serial_write(struct console *con, const char *s,
1294 unsigned int n)
1295 {
1296 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1297 unsigned int i;
1298
1299 for (i = 0; i < n; i++, s++) {
1300 if (*s == '\n')
1301 early_serial_putc(&uart->port, '\r');
1302 early_serial_putc(&uart->port, *s);
1303 }
1304 }
1305
1306 /*
1307 * This should have a .setup or .early_setup in it, but then things get called
1308 * without the command line options, and the baud rate gets messed up - so
1309 * don't let the common infrastructure play with things. (see calls to setup
1310 * & earlysetup in ./kernel/printk.c:register_console()
1311 */
1312 static struct __initdata console bfin_early_serial_console = {
1313 .name = "early_BFuart",
1314 .write = early_serial_write,
1315 .device = uart_console_device,
1316 .flags = CON_PRINTBUFFER,
1317 .index = -1,
1318 .data = &bfin_serial_reg,
1319 };
1320
1321 struct console __init *bfin_earlyserial_init(unsigned int port,
1322 unsigned int cflag)
1323 {
1324 struct bfin_serial_port *uart;
1325 struct ktermios t;
1326
1327 #ifdef CONFIG_SERIAL_BFIN_CONSOLE
1328 /*
1329 * If we are using early serial, don't let the normal console rewind
1330 * log buffer, since that causes things to be printed multiple times
1331 */
1332 bfin_serial_console.flags &= ~CON_PRINTBUFFER;
1333 #endif
1334
1335 if (port == -1 || port >= nr_active_ports)
1336 port = 0;
1337 bfin_serial_init_ports();
1338 bfin_early_serial_console.index = port;
1339 uart = &bfin_serial_ports[port];
1340 t.c_cflag = cflag;
1341 t.c_iflag = 0;
1342 t.c_oflag = 0;
1343 t.c_lflag = ICANON;
1344 t.c_line = port;
1345 bfin_serial_set_termios(&uart->port, &t, &t);
1346 return &bfin_early_serial_console;
1347 }
1348
1349 #endif /* CONFIG_EARLY_PRINTK */
1350
1351 static struct uart_driver bfin_serial_reg = {
1352 .owner = THIS_MODULE,
1353 .driver_name = "bfin-uart",
1354 .dev_name = BFIN_SERIAL_NAME,
1355 .major = BFIN_SERIAL_MAJOR,
1356 .minor = BFIN_SERIAL_MINOR,
1357 .nr = BFIN_UART_NR_PORTS,
1358 .cons = BFIN_SERIAL_CONSOLE,
1359 };
1360
1361 static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1362 {
1363 int i;
1364
1365 for (i = 0; i < nr_active_ports; i++) {
1366 if (bfin_serial_ports[i].port.dev != &dev->dev)
1367 continue;
1368 uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1369 }
1370
1371 return 0;
1372 }
1373
1374 static int bfin_serial_resume(struct platform_device *dev)
1375 {
1376 int i;
1377
1378 for (i = 0; i < nr_active_ports; i++) {
1379 if (bfin_serial_ports[i].port.dev != &dev->dev)
1380 continue;
1381 uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1382 }
1383
1384 return 0;
1385 }
1386
1387 static int bfin_serial_probe(struct platform_device *dev)
1388 {
1389 struct resource *res = dev->resource;
1390 int i;
1391
1392 for (i = 0; i < dev->num_resources; i++, res++)
1393 if (res->flags & IORESOURCE_MEM)
1394 break;
1395
1396 if (i < dev->num_resources) {
1397 for (i = 0; i < nr_active_ports; i++, res++) {
1398 if (bfin_serial_ports[i].port.mapbase != res->start)
1399 continue;
1400 bfin_serial_ports[i].port.dev = &dev->dev;
1401 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1402 }
1403 }
1404
1405 return 0;
1406 }
1407
1408 static int bfin_serial_remove(struct platform_device *dev)
1409 {
1410 int i;
1411
1412 for (i = 0; i < nr_active_ports; i++) {
1413 if (bfin_serial_ports[i].port.dev != &dev->dev)
1414 continue;
1415 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1416 bfin_serial_ports[i].port.dev = NULL;
1417 #if defined(CONFIG_SERIAL_BFIN_CTSRTS)
1418 gpio_free(bfin_serial_ports[i].cts_pin);
1419 gpio_free(bfin_serial_ports[i].rts_pin);
1420 #endif
1421 }
1422
1423 return 0;
1424 }
1425
1426 static struct platform_driver bfin_serial_driver = {
1427 .probe = bfin_serial_probe,
1428 .remove = bfin_serial_remove,
1429 .suspend = bfin_serial_suspend,
1430 .resume = bfin_serial_resume,
1431 .driver = {
1432 .name = "bfin-uart",
1433 .owner = THIS_MODULE,
1434 },
1435 };
1436
1437 static int __init bfin_serial_init(void)
1438 {
1439 int ret;
1440
1441 pr_info("Serial: Blackfin serial driver\n");
1442
1443 bfin_serial_init_ports();
1444
1445 ret = uart_register_driver(&bfin_serial_reg);
1446 if (ret == 0) {
1447 ret = platform_driver_register(&bfin_serial_driver);
1448 if (ret) {
1449 pr_debug("uart register failed\n");
1450 uart_unregister_driver(&bfin_serial_reg);
1451 }
1452 }
1453 return ret;
1454 }
1455
1456 static void __exit bfin_serial_exit(void)
1457 {
1458 platform_driver_unregister(&bfin_serial_driver);
1459 uart_unregister_driver(&bfin_serial_reg);
1460 }
1461
1462
1463 module_init(bfin_serial_init);
1464 module_exit(bfin_serial_exit);
1465
1466 MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1467 MODULE_DESCRIPTION("Blackfin generic serial port driver");
1468 MODULE_LICENSE("GPL");
1469 MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
1470 MODULE_ALIAS("platform:bfin-uart");
Linux kernel - Deliverables
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