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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[deliverable/linux.git] / drivers / serial / bfin_5xx.c
1 /*
2 * Blackfin On-Chip Serial Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12 #define SUPPORT_SYSRQ
13 #endif
14
15 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/io.h>
18 #include <linux/init.h>
19 #include <linux/console.h>
20 #include <linux/sysrq.h>
21 #include <linux/platform_device.h>
22 #include <linux/tty.h>
23 #include <linux/tty_flip.h>
24 #include <linux/serial_core.h>
25
26 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
27 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
28 #include <linux/kgdb.h>
29 #include <asm/irq_regs.h>
30 #endif
31
32 #include <asm/gpio.h>
33 #include <mach/bfin_serial_5xx.h>
34
35 #ifdef CONFIG_SERIAL_BFIN_DMA
36 #include <linux/dma-mapping.h>
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/cacheflush.h>
40 #endif
41
42 #ifdef CONFIG_SERIAL_BFIN_MODULE
43 # undef CONFIG_EARLY_PRINTK
44 #endif
45
46 #ifdef CONFIG_SERIAL_BFIN_MODULE
47 # undef CONFIG_EARLY_PRINTK
48 #endif
49
50 /* UART name and device definitions */
51 #define BFIN_SERIAL_NAME "ttyBF"
52 #define BFIN_SERIAL_MAJOR 204
53 #define BFIN_SERIAL_MINOR 64
54
55 static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
56 static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource);
57
58 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
59 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
60
61 # ifndef CONFIG_SERIAL_BFIN_PIO
62 # error KGDB only support UART in PIO mode.
63 # endif
64
65 static int kgdboc_port_line;
66 static int kgdboc_break_enabled;
67 #endif
68 /*
69 * Setup for console. Argument comes from the menuconfig
70 */
71 #define DMA_RX_XCOUNT 512
72 #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
73
74 #define DMA_RX_FLUSH_JIFFIES (HZ / 50)
75
76 #ifdef CONFIG_SERIAL_BFIN_DMA
77 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
78 #else
79 static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
80 #endif
81
82 static void bfin_serial_reset_irda(struct uart_port *port);
83
84 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
85 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
86 static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
87 {
88 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
89 if (uart->cts_pin < 0)
90 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
91
92 /* CTS PIN is negative assertive. */
93 if (UART_GET_CTS(uart))
94 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
95 else
96 return TIOCM_DSR | TIOCM_CAR;
97 }
98
99 static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
100 {
101 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
102 if (uart->rts_pin < 0)
103 return;
104
105 /* RTS PIN is negative assertive. */
106 if (mctrl & TIOCM_RTS)
107 UART_ENABLE_RTS(uart);
108 else
109 UART_DISABLE_RTS(uart);
110 }
111
112 /*
113 * Handle any change of modem status signal.
114 */
115 static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
116 {
117 struct bfin_serial_port *uart = dev_id;
118 unsigned int status;
119
120 status = bfin_serial_get_mctrl(&uart->port);
121 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
122 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
123 uart->scts = 1;
124 UART_CLEAR_SCTS(uart);
125 UART_CLEAR_IER(uart, EDSSI);
126 #endif
127
128 return IRQ_HANDLED;
129 }
130 #else
131 static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
132 {
133 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
134 }
135
136 static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
137 {
138 }
139 #endif
140
141 /*
142 * interrupts are disabled on entry
143 */
144 static void bfin_serial_stop_tx(struct uart_port *port)
145 {
146 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
147 #ifdef CONFIG_SERIAL_BFIN_DMA
148 struct circ_buf *xmit = &uart->port.state->xmit;
149 #endif
150
151 while (!(UART_GET_LSR(uart) & TEMT))
152 cpu_relax();
153
154 #ifdef CONFIG_SERIAL_BFIN_DMA
155 disable_dma(uart->tx_dma_channel);
156 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
157 uart->port.icount.tx += uart->tx_count;
158 uart->tx_count = 0;
159 uart->tx_done = 1;
160 #else
161 #ifdef CONFIG_BF54x
162 /* Clear TFI bit */
163 UART_PUT_LSR(uart, TFI);
164 #endif
165 UART_CLEAR_IER(uart, ETBEI);
166 #endif
167 }
168
169 /*
170 * port is locked and interrupts are disabled
171 */
172 static void bfin_serial_start_tx(struct uart_port *port)
173 {
174 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
175 struct tty_struct *tty = uart->port.state->port.tty;
176
177 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
178 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
179 uart->scts = 0;
180 uart_handle_cts_change(&uart->port, uart->scts);
181 }
182 #endif
183
184 /*
185 * To avoid losting RX interrupt, we reset IR function
186 * before sending data.
187 */
188 if (tty->termios->c_line == N_IRDA)
189 bfin_serial_reset_irda(port);
190
191 #ifdef CONFIG_SERIAL_BFIN_DMA
192 if (uart->tx_done)
193 bfin_serial_dma_tx_chars(uart);
194 #else
195 UART_SET_IER(uart, ETBEI);
196 bfin_serial_tx_chars(uart);
197 #endif
198 }
199
200 /*
201 * Interrupts are enabled
202 */
203 static void bfin_serial_stop_rx(struct uart_port *port)
204 {
205 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
206
207 UART_CLEAR_IER(uart, ERBFI);
208 }
209
210 /*
211 * Set the modem control timer to fire immediately.
212 */
213 static void bfin_serial_enable_ms(struct uart_port *port)
214 {
215 }
216
217
218 #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
219 # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
220 # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
221 #else
222 # define UART_GET_ANOMALY_THRESHOLD(uart) 0
223 # define UART_SET_ANOMALY_THRESHOLD(uart, v)
224 #endif
225
226 #ifdef CONFIG_SERIAL_BFIN_PIO
227 static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
228 {
229 struct tty_struct *tty = NULL;
230 unsigned int status, ch, flg;
231 static struct timeval anomaly_start = { .tv_sec = 0 };
232
233 status = UART_GET_LSR(uart);
234 UART_CLEAR_LSR(uart);
235
236 ch = UART_GET_CHAR(uart);
237 uart->port.icount.rx++;
238
239 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
240 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
241 if (kgdb_connected && kgdboc_port_line == uart->port.line
242 && kgdboc_break_enabled)
243 if (ch == 0x3) {/* Ctrl + C */
244 kgdb_breakpoint();
245 return;
246 }
247
248 if (!uart->port.state || !uart->port.state->port.tty)
249 return;
250 #endif
251 tty = uart->port.state->port.tty;
252
253 if (ANOMALY_05000363) {
254 /* The BF533 (and BF561) family of processors have a nice anomaly
255 * where they continuously generate characters for a "single" break.
256 * We have to basically ignore this flood until the "next" valid
257 * character comes across. Due to the nature of the flood, it is
258 * not possible to reliably catch bytes that are sent too quickly
259 * after this break. So application code talking to the Blackfin
260 * which sends a break signal must allow at least 1.5 character
261 * times after the end of the break for things to stabilize. This
262 * timeout was picked as it must absolutely be larger than 1
263 * character time +/- some percent. So 1.5 sounds good. All other
264 * Blackfin families operate properly. Woo.
265 */
266 if (anomaly_start.tv_sec) {
267 struct timeval curr;
268 suseconds_t usecs;
269
270 if ((~ch & (~ch + 1)) & 0xff)
271 goto known_good_char;
272
273 do_gettimeofday(&curr);
274 if (curr.tv_sec - anomaly_start.tv_sec > 1)
275 goto known_good_char;
276
277 usecs = 0;
278 if (curr.tv_sec != anomaly_start.tv_sec)
279 usecs += USEC_PER_SEC;
280 usecs += curr.tv_usec - anomaly_start.tv_usec;
281
282 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
283 goto known_good_char;
284
285 if (ch)
286 anomaly_start.tv_sec = 0;
287 else
288 anomaly_start = curr;
289
290 return;
291
292 known_good_char:
293 status &= ~BI;
294 anomaly_start.tv_sec = 0;
295 }
296 }
297
298 if (status & BI) {
299 if (ANOMALY_05000363)
300 if (bfin_revid() < 5)
301 do_gettimeofday(&anomaly_start);
302 uart->port.icount.brk++;
303 if (uart_handle_break(&uart->port))
304 goto ignore_char;
305 status &= ~(PE | FE);
306 }
307 if (status & PE)
308 uart->port.icount.parity++;
309 if (status & OE)
310 uart->port.icount.overrun++;
311 if (status & FE)
312 uart->port.icount.frame++;
313
314 status &= uart->port.read_status_mask;
315
316 if (status & BI)
317 flg = TTY_BREAK;
318 else if (status & PE)
319 flg = TTY_PARITY;
320 else if (status & FE)
321 flg = TTY_FRAME;
322 else
323 flg = TTY_NORMAL;
324
325 if (uart_handle_sysrq_char(&uart->port, ch))
326 goto ignore_char;
327
328 uart_insert_char(&uart->port, status, OE, ch, flg);
329
330 ignore_char:
331 tty_flip_buffer_push(tty);
332 }
333
334 static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
335 {
336 struct circ_buf *xmit = &uart->port.state->xmit;
337
338 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
339 #ifdef CONFIG_BF54x
340 /* Clear TFI bit */
341 UART_PUT_LSR(uart, TFI);
342 #endif
343 /* Anomaly notes:
344 * 05000215 - we always clear ETBEI within last UART TX
345 * interrupt to end a string. It is always set
346 * when start a new tx.
347 */
348 UART_CLEAR_IER(uart, ETBEI);
349 return;
350 }
351
352 if (uart->port.x_char) {
353 UART_PUT_CHAR(uart, uart->port.x_char);
354 uart->port.icount.tx++;
355 uart->port.x_char = 0;
356 }
357
358 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
359 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
360 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
361 uart->port.icount.tx++;
362 SSYNC();
363 }
364
365 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
366 uart_write_wakeup(&uart->port);
367 }
368
369 static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
370 {
371 struct bfin_serial_port *uart = dev_id;
372
373 spin_lock(&uart->port.lock);
374 while (UART_GET_LSR(uart) & DR)
375 bfin_serial_rx_chars(uart);
376 spin_unlock(&uart->port.lock);
377
378 return IRQ_HANDLED;
379 }
380
381 static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
382 {
383 struct bfin_serial_port *uart = dev_id;
384
385 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
386 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
387 uart->scts = 0;
388 uart_handle_cts_change(&uart->port, uart->scts);
389 }
390 #endif
391 spin_lock(&uart->port.lock);
392 if (UART_GET_LSR(uart) & THRE)
393 bfin_serial_tx_chars(uart);
394 spin_unlock(&uart->port.lock);
395
396 return IRQ_HANDLED;
397 }
398 #endif
399
400 #ifdef CONFIG_SERIAL_BFIN_DMA
401 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
402 {
403 struct circ_buf *xmit = &uart->port.state->xmit;
404
405 uart->tx_done = 0;
406
407 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
408 uart->tx_count = 0;
409 uart->tx_done = 1;
410 return;
411 }
412
413 if (uart->port.x_char) {
414 UART_PUT_CHAR(uart, uart->port.x_char);
415 uart->port.icount.tx++;
416 uart->port.x_char = 0;
417 }
418
419 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
420 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
421 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
422 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
423 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
424 set_dma_config(uart->tx_dma_channel,
425 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
426 INTR_ON_BUF,
427 DIMENSION_LINEAR,
428 DATA_SIZE_8,
429 DMA_SYNC_RESTART));
430 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
431 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
432 set_dma_x_modify(uart->tx_dma_channel, 1);
433 SSYNC();
434 enable_dma(uart->tx_dma_channel);
435
436 UART_SET_IER(uart, ETBEI);
437 }
438
439 static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
440 {
441 struct tty_struct *tty = uart->port.state->port.tty;
442 int i, flg, status;
443
444 status = UART_GET_LSR(uart);
445 UART_CLEAR_LSR(uart);
446
447 uart->port.icount.rx +=
448 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
449 UART_XMIT_SIZE);
450
451 if (status & BI) {
452 uart->port.icount.brk++;
453 if (uart_handle_break(&uart->port))
454 goto dma_ignore_char;
455 status &= ~(PE | FE);
456 }
457 if (status & PE)
458 uart->port.icount.parity++;
459 if (status & OE)
460 uart->port.icount.overrun++;
461 if (status & FE)
462 uart->port.icount.frame++;
463
464 status &= uart->port.read_status_mask;
465
466 if (status & BI)
467 flg = TTY_BREAK;
468 else if (status & PE)
469 flg = TTY_PARITY;
470 else if (status & FE)
471 flg = TTY_FRAME;
472 else
473 flg = TTY_NORMAL;
474
475 for (i = uart->rx_dma_buf.tail; ; i++) {
476 if (i >= UART_XMIT_SIZE)
477 i = 0;
478 if (i == uart->rx_dma_buf.head)
479 break;
480 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
481 uart_insert_char(&uart->port, status, OE,
482 uart->rx_dma_buf.buf[i], flg);
483 }
484
485 dma_ignore_char:
486 tty_flip_buffer_push(tty);
487 }
488
489 void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
490 {
491 int x_pos, pos;
492
493 dma_disable_irq(uart->tx_dma_channel);
494 dma_disable_irq(uart->rx_dma_channel);
495 spin_lock_bh(&uart->port.lock);
496
497 /* 2D DMA RX buffer ring is used. Because curr_y_count and
498 * curr_x_count can't be read as an atomic operation,
499 * curr_y_count should be read before curr_x_count. When
500 * curr_x_count is read, curr_y_count may already indicate
501 * next buffer line. But, the position calculated here is
502 * still indicate the old line. The wrong position data may
503 * be smaller than current buffer tail, which cause garbages
504 * are received if it is not prohibit.
505 */
506 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
507 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
508 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
509 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
510 uart->rx_dma_nrows = 0;
511 x_pos = DMA_RX_XCOUNT - x_pos;
512 if (x_pos == DMA_RX_XCOUNT)
513 x_pos = 0;
514
515 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
516 /* Ignore receiving data if new position is in the same line of
517 * current buffer tail and small.
518 */
519 if (pos > uart->rx_dma_buf.tail ||
520 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
521 uart->rx_dma_buf.head = pos;
522 bfin_serial_dma_rx_chars(uart);
523 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
524 }
525
526 spin_unlock_bh(&uart->port.lock);
527 dma_enable_irq(uart->tx_dma_channel);
528 dma_enable_irq(uart->rx_dma_channel);
529
530 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
531 }
532
533 static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
534 {
535 struct bfin_serial_port *uart = dev_id;
536 struct circ_buf *xmit = &uart->port.state->xmit;
537
538 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
539 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
540 uart->scts = 0;
541 uart_handle_cts_change(&uart->port, uart->scts);
542 }
543 #endif
544
545 spin_lock(&uart->port.lock);
546 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
547 disable_dma(uart->tx_dma_channel);
548 clear_dma_irqstat(uart->tx_dma_channel);
549 /* Anomaly notes:
550 * 05000215 - we always clear ETBEI within last UART TX
551 * interrupt to end a string. It is always set
552 * when start a new tx.
553 */
554 UART_CLEAR_IER(uart, ETBEI);
555 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
556 uart->port.icount.tx += uart->tx_count;
557
558 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
559 uart_write_wakeup(&uart->port);
560
561 bfin_serial_dma_tx_chars(uart);
562 }
563
564 spin_unlock(&uart->port.lock);
565 return IRQ_HANDLED;
566 }
567
568 static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
569 {
570 struct bfin_serial_port *uart = dev_id;
571 unsigned short irqstat;
572 int x_pos, pos;
573
574 spin_lock(&uart->port.lock);
575 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
576 clear_dma_irqstat(uart->rx_dma_channel);
577
578 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
579 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
580 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
581 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
582 uart->rx_dma_nrows = 0;
583
584 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
585 if (pos > uart->rx_dma_buf.tail ||
586 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
587 uart->rx_dma_buf.head = pos;
588 bfin_serial_dma_rx_chars(uart);
589 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
590 }
591
592 spin_unlock(&uart->port.lock);
593
594 return IRQ_HANDLED;
595 }
596 #endif
597
598 /*
599 * Return TIOCSER_TEMT when transmitter is not busy.
600 */
601 static unsigned int bfin_serial_tx_empty(struct uart_port *port)
602 {
603 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
604 unsigned short lsr;
605
606 lsr = UART_GET_LSR(uart);
607 if (lsr & TEMT)
608 return TIOCSER_TEMT;
609 else
610 return 0;
611 }
612
613 static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
614 {
615 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
616 u16 lcr = UART_GET_LCR(uart);
617 if (break_state)
618 lcr |= SB;
619 else
620 lcr &= ~SB;
621 UART_PUT_LCR(uart, lcr);
622 SSYNC();
623 }
624
625 static int bfin_serial_startup(struct uart_port *port)
626 {
627 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
628
629 #ifdef CONFIG_SERIAL_BFIN_DMA
630 dma_addr_t dma_handle;
631
632 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
633 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
634 return -EBUSY;
635 }
636
637 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
638 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
639 free_dma(uart->rx_dma_channel);
640 return -EBUSY;
641 }
642
643 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
644 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
645
646 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
647 uart->rx_dma_buf.head = 0;
648 uart->rx_dma_buf.tail = 0;
649 uart->rx_dma_nrows = 0;
650
651 set_dma_config(uart->rx_dma_channel,
652 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
653 INTR_ON_ROW, DIMENSION_2D,
654 DATA_SIZE_8,
655 DMA_SYNC_RESTART));
656 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
657 set_dma_x_modify(uart->rx_dma_channel, 1);
658 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
659 set_dma_y_modify(uart->rx_dma_channel, 1);
660 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
661 enable_dma(uart->rx_dma_channel);
662
663 uart->rx_dma_timer.data = (unsigned long)(uart);
664 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
665 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
666 add_timer(&(uart->rx_dma_timer));
667 #else
668 # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
669 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
670 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
671 kgdboc_break_enabled = 0;
672 else {
673 # endif
674 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
675 "BFIN_UART_RX", uart)) {
676 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
677 return -EBUSY;
678 }
679
680 if (request_irq
681 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
682 "BFIN_UART_TX", uart)) {
683 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
684 free_irq(uart->port.irq, uart);
685 return -EBUSY;
686 }
687
688 # ifdef CONFIG_BF54x
689 {
690 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
691
692 switch (uart->port.irq) {
693 case IRQ_UART3_RX:
694 uart_dma_ch_rx = CH_UART3_RX;
695 uart_dma_ch_tx = CH_UART3_TX;
696 break;
697 case IRQ_UART2_RX:
698 uart_dma_ch_rx = CH_UART2_RX;
699 uart_dma_ch_tx = CH_UART2_TX;
700 break;
701 default:
702 uart_dma_ch_rx = uart_dma_ch_tx = 0;
703 break;
704 };
705
706 if (uart_dma_ch_rx &&
707 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
708 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
709 free_irq(uart->port.irq, uart);
710 free_irq(uart->port.irq + 1, uart);
711 return -EBUSY;
712 }
713 if (uart_dma_ch_tx &&
714 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
715 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
716 free_dma(uart_dma_ch_rx);
717 free_irq(uart->port.irq, uart);
718 free_irq(uart->port.irq + 1, uart);
719 return -EBUSY;
720 }
721 }
722 # endif
723 # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
724 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
725 }
726 # endif
727 #endif
728
729 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
730 if (uart->cts_pin >= 0) {
731 if (request_irq(gpio_to_irq(uart->cts_pin),
732 bfin_serial_mctrl_cts_int,
733 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
734 IRQF_DISABLED, "BFIN_UART_CTS", uart)) {
735 uart->cts_pin = -1;
736 pr_info("Unable to attach BlackFin UART CTS interrupt.\
737 So, disable it.\n");
738 }
739 }
740 if (uart->rts_pin >= 0) {
741 gpio_request(uart->rts_pin, DRIVER_NAME);
742 gpio_direction_output(uart->rts_pin, 0);
743 }
744 #endif
745 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
746 if (request_irq(uart->status_irq,
747 bfin_serial_mctrl_cts_int,
748 IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
749 pr_info("Unable to attach BlackFin UART Modem \
750 Status interrupt.\n");
751 }
752
753 /* CTS RTS PINs are negative assertive. */
754 UART_PUT_MCR(uart, ACTS);
755 UART_SET_IER(uart, EDSSI);
756 #endif
757
758 UART_SET_IER(uart, ERBFI);
759 return 0;
760 }
761
762 static void bfin_serial_shutdown(struct uart_port *port)
763 {
764 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
765
766 #ifdef CONFIG_SERIAL_BFIN_DMA
767 disable_dma(uart->tx_dma_channel);
768 free_dma(uart->tx_dma_channel);
769 disable_dma(uart->rx_dma_channel);
770 free_dma(uart->rx_dma_channel);
771 del_timer(&(uart->rx_dma_timer));
772 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
773 #else
774 #ifdef CONFIG_BF54x
775 switch (uart->port.irq) {
776 case IRQ_UART3_RX:
777 free_dma(CH_UART3_RX);
778 free_dma(CH_UART3_TX);
779 break;
780 case IRQ_UART2_RX:
781 free_dma(CH_UART2_RX);
782 free_dma(CH_UART2_TX);
783 break;
784 default:
785 break;
786 };
787 #endif
788 free_irq(uart->port.irq, uart);
789 free_irq(uart->port.irq+1, uart);
790 #endif
791
792 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
793 if (uart->cts_pin >= 0)
794 free_irq(gpio_to_irq(uart->cts_pin), uart);
795 if (uart->rts_pin >= 0)
796 gpio_free(uart->rts_pin);
797 #endif
798 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
799 if (UART_GET_IER(uart) && EDSSI)
800 free_irq(uart->status_irq, uart);
801 #endif
802 }
803
804 static void
805 bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
806 struct ktermios *old)
807 {
808 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
809 unsigned long flags;
810 unsigned int baud, quot;
811 unsigned short val, ier, lcr = 0;
812
813 switch (termios->c_cflag & CSIZE) {
814 case CS8:
815 lcr = WLS(8);
816 break;
817 case CS7:
818 lcr = WLS(7);
819 break;
820 case CS6:
821 lcr = WLS(6);
822 break;
823 case CS5:
824 lcr = WLS(5);
825 break;
826 default:
827 printk(KERN_ERR "%s: word lengh not supported\n",
828 __func__);
829 }
830
831 /* Anomaly notes:
832 * 05000231 - STOP bit is always set to 1 whatever the user is set.
833 */
834 if (termios->c_cflag & CSTOPB) {
835 if (ANOMALY_05000231)
836 printk(KERN_WARNING "STOP bits other than 1 is not "
837 "supported in case of anomaly 05000231.\n");
838 else
839 lcr |= STB;
840 }
841 if (termios->c_cflag & PARENB)
842 lcr |= PEN;
843 if (!(termios->c_cflag & PARODD))
844 lcr |= EPS;
845 if (termios->c_cflag & CMSPAR)
846 lcr |= STP;
847
848 port->read_status_mask = OE;
849 if (termios->c_iflag & INPCK)
850 port->read_status_mask |= (FE | PE);
851 if (termios->c_iflag & (BRKINT | PARMRK))
852 port->read_status_mask |= BI;
853
854 /*
855 * Characters to ignore
856 */
857 port->ignore_status_mask = 0;
858 if (termios->c_iflag & IGNPAR)
859 port->ignore_status_mask |= FE | PE;
860 if (termios->c_iflag & IGNBRK) {
861 port->ignore_status_mask |= BI;
862 /*
863 * If we're ignoring parity and break indicators,
864 * ignore overruns too (for real raw support).
865 */
866 if (termios->c_iflag & IGNPAR)
867 port->ignore_status_mask |= OE;
868 }
869
870 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
871 quot = uart_get_divisor(port, baud) - ANOMALY_05000230;
872 spin_lock_irqsave(&uart->port.lock, flags);
873
874 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
875
876 /* Disable UART */
877 ier = UART_GET_IER(uart);
878 UART_DISABLE_INTS(uart);
879
880 /* Set DLAB in LCR to Access DLL and DLH */
881 UART_SET_DLAB(uart);
882
883 UART_PUT_DLL(uart, quot & 0xFF);
884 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
885 SSYNC();
886
887 /* Clear DLAB in LCR to Access THR RBR IER */
888 UART_CLEAR_DLAB(uart);
889
890 UART_PUT_LCR(uart, lcr);
891
892 /* Enable UART */
893 UART_ENABLE_INTS(uart, ier);
894
895 val = UART_GET_GCTL(uart);
896 val |= UCEN;
897 UART_PUT_GCTL(uart, val);
898
899 /* Port speed changed, update the per-port timeout. */
900 uart_update_timeout(port, termios->c_cflag, baud);
901
902 spin_unlock_irqrestore(&uart->port.lock, flags);
903 }
904
905 static const char *bfin_serial_type(struct uart_port *port)
906 {
907 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
908
909 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
910 }
911
912 /*
913 * Release the memory region(s) being used by 'port'.
914 */
915 static void bfin_serial_release_port(struct uart_port *port)
916 {
917 }
918
919 /*
920 * Request the memory region(s) being used by 'port'.
921 */
922 static int bfin_serial_request_port(struct uart_port *port)
923 {
924 return 0;
925 }
926
927 /*
928 * Configure/autoconfigure the port.
929 */
930 static void bfin_serial_config_port(struct uart_port *port, int flags)
931 {
932 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
933
934 if (flags & UART_CONFIG_TYPE &&
935 bfin_serial_request_port(&uart->port) == 0)
936 uart->port.type = PORT_BFIN;
937 }
938
939 /*
940 * Verify the new serial_struct (for TIOCSSERIAL).
941 * The only change we allow are to the flags and type, and
942 * even then only between PORT_BFIN and PORT_UNKNOWN
943 */
944 static int
945 bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
946 {
947 return 0;
948 }
949
950 /*
951 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
952 * In other cases, disable IrDA function.
953 */
954 static void bfin_serial_set_ldisc(struct uart_port *port)
955 {
956 int line = port->line;
957 unsigned short val;
958
959 if (line >= port->state->port.tty->driver->num)
960 return;
961
962 switch (port->state->port.tty->termios->c_line) {
963 case N_IRDA:
964 val = UART_GET_GCTL(&bfin_serial_ports[line]);
965 val |= (IREN | RPOLC);
966 UART_PUT_GCTL(&bfin_serial_ports[line], val);
967 break;
968 default:
969 val = UART_GET_GCTL(&bfin_serial_ports[line]);
970 val &= ~(IREN | RPOLC);
971 UART_PUT_GCTL(&bfin_serial_ports[line], val);
972 }
973 }
974
975 static void bfin_serial_reset_irda(struct uart_port *port)
976 {
977 int line = port->line;
978 unsigned short val;
979
980 val = UART_GET_GCTL(&bfin_serial_ports[line]);
981 val &= ~(IREN | RPOLC);
982 UART_PUT_GCTL(&bfin_serial_ports[line], val);
983 SSYNC();
984 val |= (IREN | RPOLC);
985 UART_PUT_GCTL(&bfin_serial_ports[line], val);
986 SSYNC();
987 }
988
989 #ifdef CONFIG_CONSOLE_POLL
990 /* Anomaly notes:
991 * 05000099 - Because we only use THRE in poll_put and DR in poll_get,
992 * losing other bits of UART_LSR is not a problem here.
993 */
994 static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
995 {
996 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
997
998 while (!(UART_GET_LSR(uart) & THRE))
999 cpu_relax();
1000
1001 UART_CLEAR_DLAB(uart);
1002 UART_PUT_CHAR(uart, (unsigned char)chr);
1003 }
1004
1005 static int bfin_serial_poll_get_char(struct uart_port *port)
1006 {
1007 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1008 unsigned char chr;
1009
1010 while (!(UART_GET_LSR(uart) & DR))
1011 cpu_relax();
1012
1013 UART_CLEAR_DLAB(uart);
1014 chr = UART_GET_CHAR(uart);
1015
1016 return chr;
1017 }
1018 #endif
1019
1020 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1021 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1022 static void bfin_kgdboc_port_shutdown(struct uart_port *port)
1023 {
1024 if (kgdboc_break_enabled) {
1025 kgdboc_break_enabled = 0;
1026 bfin_serial_shutdown(port);
1027 }
1028 }
1029
1030 static int bfin_kgdboc_port_startup(struct uart_port *port)
1031 {
1032 kgdboc_port_line = port->line;
1033 kgdboc_break_enabled = !bfin_serial_startup(port);
1034 return 0;
1035 }
1036 #endif
1037
1038 static struct uart_ops bfin_serial_pops = {
1039 .tx_empty = bfin_serial_tx_empty,
1040 .set_mctrl = bfin_serial_set_mctrl,
1041 .get_mctrl = bfin_serial_get_mctrl,
1042 .stop_tx = bfin_serial_stop_tx,
1043 .start_tx = bfin_serial_start_tx,
1044 .stop_rx = bfin_serial_stop_rx,
1045 .enable_ms = bfin_serial_enable_ms,
1046 .break_ctl = bfin_serial_break_ctl,
1047 .startup = bfin_serial_startup,
1048 .shutdown = bfin_serial_shutdown,
1049 .set_termios = bfin_serial_set_termios,
1050 .set_ldisc = bfin_serial_set_ldisc,
1051 .type = bfin_serial_type,
1052 .release_port = bfin_serial_release_port,
1053 .request_port = bfin_serial_request_port,
1054 .config_port = bfin_serial_config_port,
1055 .verify_port = bfin_serial_verify_port,
1056 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1057 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1058 .kgdboc_port_startup = bfin_kgdboc_port_startup,
1059 .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown,
1060 #endif
1061 #ifdef CONFIG_CONSOLE_POLL
1062 .poll_put_char = bfin_serial_poll_put_char,
1063 .poll_get_char = bfin_serial_poll_get_char,
1064 #endif
1065 };
1066
1067 static void __init bfin_serial_hw_init(void)
1068 {
1069 #ifdef CONFIG_SERIAL_BFIN_UART0
1070 peripheral_request(P_UART0_TX, DRIVER_NAME);
1071 peripheral_request(P_UART0_RX, DRIVER_NAME);
1072 #endif
1073
1074 #ifdef CONFIG_SERIAL_BFIN_UART1
1075 peripheral_request(P_UART1_TX, DRIVER_NAME);
1076 peripheral_request(P_UART1_RX, DRIVER_NAME);
1077
1078 # if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x)
1079 peripheral_request(P_UART1_RTS, DRIVER_NAME);
1080 peripheral_request(P_UART1_CTS, DRIVER_NAME);
1081 # endif
1082 #endif
1083
1084 #ifdef CONFIG_SERIAL_BFIN_UART2
1085 peripheral_request(P_UART2_TX, DRIVER_NAME);
1086 peripheral_request(P_UART2_RX, DRIVER_NAME);
1087 #endif
1088
1089 #ifdef CONFIG_SERIAL_BFIN_UART3
1090 peripheral_request(P_UART3_TX, DRIVER_NAME);
1091 peripheral_request(P_UART3_RX, DRIVER_NAME);
1092
1093 # if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x)
1094 peripheral_request(P_UART3_RTS, DRIVER_NAME);
1095 peripheral_request(P_UART3_CTS, DRIVER_NAME);
1096 # endif
1097 #endif
1098 }
1099
1100 static void __init bfin_serial_init_ports(void)
1101 {
1102 static int first = 1;
1103 int i;
1104
1105 if (!first)
1106 return;
1107 first = 0;
1108
1109 bfin_serial_hw_init();
1110
1111 for (i = 0; i < nr_active_ports; i++) {
1112 spin_lock_init(&bfin_serial_ports[i].port.lock);
1113 bfin_serial_ports[i].port.uartclk = get_sclk();
1114 bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE;
1115 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
1116 bfin_serial_ports[i].port.line = i;
1117 bfin_serial_ports[i].port.iotype = UPIO_MEM;
1118 bfin_serial_ports[i].port.membase =
1119 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
1120 bfin_serial_ports[i].port.mapbase =
1121 bfin_serial_resource[i].uart_base_addr;
1122 bfin_serial_ports[i].port.irq =
1123 bfin_serial_resource[i].uart_irq;
1124 bfin_serial_ports[i].status_irq =
1125 bfin_serial_resource[i].uart_status_irq;
1126 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
1127 #ifdef CONFIG_SERIAL_BFIN_DMA
1128 bfin_serial_ports[i].tx_done = 1;
1129 bfin_serial_ports[i].tx_count = 0;
1130 bfin_serial_ports[i].tx_dma_channel =
1131 bfin_serial_resource[i].uart_tx_dma_channel;
1132 bfin_serial_ports[i].rx_dma_channel =
1133 bfin_serial_resource[i].uart_rx_dma_channel;
1134 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
1135 #endif
1136 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1137 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1138 bfin_serial_ports[i].cts_pin =
1139 bfin_serial_resource[i].uart_cts_pin;
1140 bfin_serial_ports[i].rts_pin =
1141 bfin_serial_resource[i].uart_rts_pin;
1142 #endif
1143 }
1144 }
1145
1146 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1147 /*
1148 * If the port was already initialised (eg, by a boot loader),
1149 * try to determine the current setup.
1150 */
1151 static void __init
1152 bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1153 int *parity, int *bits)
1154 {
1155 unsigned short status;
1156
1157 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1158 if (status == (ERBFI | ETBEI)) {
1159 /* ok, the port was enabled */
1160 u16 lcr, dlh, dll;
1161
1162 lcr = UART_GET_LCR(uart);
1163
1164 *parity = 'n';
1165 if (lcr & PEN) {
1166 if (lcr & EPS)
1167 *parity = 'e';
1168 else
1169 *parity = 'o';
1170 }
1171 switch (lcr & 0x03) {
1172 case 0: *bits = 5; break;
1173 case 1: *bits = 6; break;
1174 case 2: *bits = 7; break;
1175 case 3: *bits = 8; break;
1176 }
1177 /* Set DLAB in LCR to Access DLL and DLH */
1178 UART_SET_DLAB(uart);
1179
1180 dll = UART_GET_DLL(uart);
1181 dlh = UART_GET_DLH(uart);
1182
1183 /* Clear DLAB in LCR to Access THR RBR IER */
1184 UART_CLEAR_DLAB(uart);
1185
1186 *baud = get_sclk() / (16*(dll | dlh << 8));
1187 }
1188 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
1189 }
1190
1191 static struct uart_driver bfin_serial_reg;
1192
1193 static int __init
1194 bfin_serial_console_setup(struct console *co, char *options)
1195 {
1196 struct bfin_serial_port *uart;
1197 int baud = 57600;
1198 int bits = 8;
1199 int parity = 'n';
1200 # if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1201 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1202 int flow = 'r';
1203 # else
1204 int flow = 'n';
1205 # endif
1206
1207 /*
1208 * Check whether an invalid uart number has been specified, and
1209 * if so, search for the first available port that does have
1210 * console support.
1211 */
1212 if (co->index == -1 || co->index >= nr_active_ports)
1213 co->index = 0;
1214 uart = &bfin_serial_ports[co->index];
1215
1216 if (options)
1217 uart_parse_options(options, &baud, &parity, &bits, &flow);
1218 else
1219 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1220
1221 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
1222 }
1223 #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1224 defined (CONFIG_EARLY_PRINTK) */
1225
1226 #ifdef CONFIG_SERIAL_BFIN_CONSOLE
1227 static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1228 {
1229 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1230 while (!(UART_GET_LSR(uart) & THRE))
1231 barrier();
1232 UART_PUT_CHAR(uart, ch);
1233 SSYNC();
1234 }
1235
1236 /*
1237 * Interrupts are disabled on entering
1238 */
1239 static void
1240 bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1241 {
1242 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1243 unsigned long flags;
1244
1245 spin_lock_irqsave(&uart->port.lock, flags);
1246 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1247 spin_unlock_irqrestore(&uart->port.lock, flags);
1248
1249 }
1250
1251 static struct console bfin_serial_console = {
1252 .name = BFIN_SERIAL_NAME,
1253 .write = bfin_serial_console_write,
1254 .device = uart_console_device,
1255 .setup = bfin_serial_console_setup,
1256 .flags = CON_PRINTBUFFER,
1257 .index = -1,
1258 .data = &bfin_serial_reg,
1259 };
1260
1261 static int __init bfin_serial_rs_console_init(void)
1262 {
1263 bfin_serial_init_ports();
1264 register_console(&bfin_serial_console);
1265
1266 return 0;
1267 }
1268 console_initcall(bfin_serial_rs_console_init);
1269
1270 #define BFIN_SERIAL_CONSOLE &bfin_serial_console
1271 #else
1272 #define BFIN_SERIAL_CONSOLE NULL
1273 #endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1274
1275
1276 #ifdef CONFIG_EARLY_PRINTK
1277 static __init void early_serial_putc(struct uart_port *port, int ch)
1278 {
1279 unsigned timeout = 0xffff;
1280 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1281
1282 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1283 cpu_relax();
1284 UART_PUT_CHAR(uart, ch);
1285 }
1286
1287 static __init void early_serial_write(struct console *con, const char *s,
1288 unsigned int n)
1289 {
1290 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1291 unsigned int i;
1292
1293 for (i = 0; i < n; i++, s++) {
1294 if (*s == '\n')
1295 early_serial_putc(&uart->port, '\r');
1296 early_serial_putc(&uart->port, *s);
1297 }
1298 }
1299
1300 /*
1301 * This should have a .setup or .early_setup in it, but then things get called
1302 * without the command line options, and the baud rate gets messed up - so
1303 * don't let the common infrastructure play with things. (see calls to setup
1304 * & earlysetup in ./kernel/printk.c:register_console()
1305 */
1306 static struct __initdata console bfin_early_serial_console = {
1307 .name = "early_BFuart",
1308 .write = early_serial_write,
1309 .device = uart_console_device,
1310 .flags = CON_PRINTBUFFER,
1311 .index = -1,
1312 .data = &bfin_serial_reg,
1313 };
1314
1315 struct console __init *bfin_earlyserial_init(unsigned int port,
1316 unsigned int cflag)
1317 {
1318 struct bfin_serial_port *uart;
1319 struct ktermios t;
1320
1321 if (port == -1 || port >= nr_active_ports)
1322 port = 0;
1323 bfin_serial_init_ports();
1324 bfin_early_serial_console.index = port;
1325 uart = &bfin_serial_ports[port];
1326 t.c_cflag = cflag;
1327 t.c_iflag = 0;
1328 t.c_oflag = 0;
1329 t.c_lflag = ICANON;
1330 t.c_line = port;
1331 bfin_serial_set_termios(&uart->port, &t, &t);
1332 return &bfin_early_serial_console;
1333 }
1334
1335 #endif /* CONFIG_EARLY_PRINTK */
1336
1337 static struct uart_driver bfin_serial_reg = {
1338 .owner = THIS_MODULE,
1339 .driver_name = "bfin-uart",
1340 .dev_name = BFIN_SERIAL_NAME,
1341 .major = BFIN_SERIAL_MAJOR,
1342 .minor = BFIN_SERIAL_MINOR,
1343 .nr = BFIN_UART_NR_PORTS,
1344 .cons = BFIN_SERIAL_CONSOLE,
1345 };
1346
1347 static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1348 {
1349 int i;
1350
1351 for (i = 0; i < nr_active_ports; i++) {
1352 if (bfin_serial_ports[i].port.dev != &dev->dev)
1353 continue;
1354 uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1355 }
1356
1357 return 0;
1358 }
1359
1360 static int bfin_serial_resume(struct platform_device *dev)
1361 {
1362 int i;
1363
1364 for (i = 0; i < nr_active_ports; i++) {
1365 if (bfin_serial_ports[i].port.dev != &dev->dev)
1366 continue;
1367 uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1368 }
1369
1370 return 0;
1371 }
1372
1373 static int bfin_serial_probe(struct platform_device *dev)
1374 {
1375 struct resource *res = dev->resource;
1376 int i;
1377
1378 for (i = 0; i < dev->num_resources; i++, res++)
1379 if (res->flags & IORESOURCE_MEM)
1380 break;
1381
1382 if (i < dev->num_resources) {
1383 for (i = 0; i < nr_active_ports; i++, res++) {
1384 if (bfin_serial_ports[i].port.mapbase != res->start)
1385 continue;
1386 bfin_serial_ports[i].port.dev = &dev->dev;
1387 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1388 }
1389 }
1390
1391 return 0;
1392 }
1393
1394 static int bfin_serial_remove(struct platform_device *dev)
1395 {
1396 int i;
1397
1398 for (i = 0; i < nr_active_ports; i++) {
1399 if (bfin_serial_ports[i].port.dev != &dev->dev)
1400 continue;
1401 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1402 bfin_serial_ports[i].port.dev = NULL;
1403 #if defined(CONFIG_SERIAL_BFIN_CTSRTS)
1404 gpio_free(bfin_serial_ports[i].cts_pin);
1405 gpio_free(bfin_serial_ports[i].rts_pin);
1406 #endif
1407 }
1408
1409 return 0;
1410 }
1411
1412 static struct platform_driver bfin_serial_driver = {
1413 .probe = bfin_serial_probe,
1414 .remove = bfin_serial_remove,
1415 .suspend = bfin_serial_suspend,
1416 .resume = bfin_serial_resume,
1417 .driver = {
1418 .name = "bfin-uart",
1419 .owner = THIS_MODULE,
1420 },
1421 };
1422
1423 static int __init bfin_serial_init(void)
1424 {
1425 int ret;
1426
1427 pr_info("Serial: Blackfin serial driver\n");
1428
1429 bfin_serial_init_ports();
1430
1431 ret = uart_register_driver(&bfin_serial_reg);
1432 if (ret == 0) {
1433 ret = platform_driver_register(&bfin_serial_driver);
1434 if (ret) {
1435 pr_debug("uart register failed\n");
1436 uart_unregister_driver(&bfin_serial_reg);
1437 }
1438 }
1439 return ret;
1440 }
1441
1442 static void __exit bfin_serial_exit(void)
1443 {
1444 platform_driver_unregister(&bfin_serial_driver);
1445 uart_unregister_driver(&bfin_serial_reg);
1446 }
1447
1448
1449 module_init(bfin_serial_init);
1450 module_exit(bfin_serial_exit);
1451
1452 MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1453 MODULE_DESCRIPTION("Blackfin generic serial port driver");
1454 MODULE_LICENSE("GPL");
1455 MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
1456 MODULE_ALIAS("platform:bfin-uart");
Linux kernel - Deliverables
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