2 * mfd.c: driver for High Speed UART device of Intel Medfield platform
4 * Refer pxa.c, 8250.c and some other drivers in drivers/serial/
6 * (C) Copyright 2010 Intel Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; version 2
15 * 1. DMA channel allocation: 0/1 channel are assigned to port 0,
16 * 2/3 chan to port 1, 4/5 chan to port 3. Even number chans
17 * are used for RX, odd chans for TX
19 * 2. In A0 stepping, UART will not support TX half empty flag
21 * 3. The RI/DSR/DCD/DTR are not pinned out, DCD & DSR are always
22 * asserted, only when the HW is reset the DDCD and DDSR will
26 #include <linux/module.h>
27 #include <linux/init.h>
28 #include <linux/console.h>
29 #include <linux/sysrq.h>
30 #include <linux/serial_reg.h>
31 #include <linux/circ_buf.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/tty.h>
35 #include <linux/tty_flip.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial_mfd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/pci.h>
41 #include <linux/debugfs.h>
43 #define MFD_HSU_A0_STEPPING 1
45 #define HSU_DMA_BUF_SIZE 2048
47 #define chan_readl(chan, offset) readl(chan->reg + offset)
48 #define chan_writel(chan, offset, val) writel(val, chan->reg + offset)
50 #define mfd_readl(obj, offset) readl(obj->reg + offset)
51 #define mfd_writel(obj, offset, val) writel(val, obj->reg + offset)
53 #define HSU_DMA_TIMEOUT_CHECK_FREQ (HZ/10)
55 struct hsu_dma_buffer
{
64 enum dma_data_direction dirt
;
65 struct uart_hsu_port
*uport
;
67 struct timer_list rx_timer
; /* only needed by RX channel */
70 struct uart_hsu_port
{
71 struct uart_port port
;
75 unsigned int lsr_break_flag
;
80 struct hsu_dma_chan
*txc
;
81 struct hsu_dma_chan
*rxc
;
82 struct hsu_dma_buffer txbuf
;
83 struct hsu_dma_buffer rxbuf
;
84 int use_dma
; /* flag for DMA/PIO */
89 /* Top level data structure of HSU */
96 struct uart_hsu_port port
[3];
97 struct hsu_dma_chan chans
[10];
99 struct dentry
*debugfs
;
102 static inline unsigned int serial_in(struct uart_hsu_port
*up
, int offset
)
106 if (offset
> UART_MSR
) {
108 val
= readl(up
->port
.membase
+ offset
);
110 val
= (unsigned int)readb(up
->port
.membase
+ offset
);
115 static inline void serial_out(struct uart_hsu_port
*up
, int offset
, int value
)
117 if (offset
> UART_MSR
) {
119 writel(value
, up
->port
.membase
+ offset
);
121 unsigned char val
= value
& 0xff;
122 writeb(val
, up
->port
.membase
+ offset
);
126 #ifdef CONFIG_DEBUG_FS
128 #define HSU_REGS_BUFSIZE 1024
130 static int hsu_show_regs_open(struct inode
*inode
, struct file
*file
)
132 file
->private_data
= inode
->i_private
;
136 static ssize_t
port_show_regs(struct file
*file
, char __user
*user_buf
,
137 size_t count
, loff_t
*ppos
)
139 struct uart_hsu_port
*up
= file
->private_data
;
144 buf
= kzalloc(HSU_REGS_BUFSIZE
, GFP_KERNEL
);
148 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
149 "MFD HSU port[%d] regs:\n", up
->index
);
151 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
152 "=================================\n");
153 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
154 "IER: \t\t0x%08x\n", serial_in(up
, UART_IER
));
155 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
156 "IIR: \t\t0x%08x\n", serial_in(up
, UART_IIR
));
157 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
158 "LCR: \t\t0x%08x\n", serial_in(up
, UART_LCR
));
159 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
160 "MCR: \t\t0x%08x\n", serial_in(up
, UART_MCR
));
161 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
162 "LSR: \t\t0x%08x\n", serial_in(up
, UART_LSR
));
163 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
164 "MSR: \t\t0x%08x\n", serial_in(up
, UART_MSR
));
165 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
166 "FOR: \t\t0x%08x\n", serial_in(up
, UART_FOR
));
167 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
168 "PS: \t\t0x%08x\n", serial_in(up
, UART_PS
));
169 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
170 "MUL: \t\t0x%08x\n", serial_in(up
, UART_MUL
));
171 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
172 "DIV: \t\t0x%08x\n", serial_in(up
, UART_DIV
));
174 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
179 static ssize_t
dma_show_regs(struct file
*file
, char __user
*user_buf
,
180 size_t count
, loff_t
*ppos
)
182 struct hsu_dma_chan
*chan
= file
->private_data
;
187 buf
= kzalloc(HSU_REGS_BUFSIZE
, GFP_KERNEL
);
191 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
192 "MFD HSU DMA channel [%d] regs:\n", chan
->id
);
194 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
195 "=================================\n");
196 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
197 "CR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_CR
));
198 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
199 "DCR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_DCR
));
200 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
201 "BSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_BSR
));
202 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
203 "MOTSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_MOTSR
));
204 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
205 "D0SAR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D0SAR
));
206 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
207 "D0TSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D0TSR
));
208 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
209 "D0SAR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D1SAR
));
210 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
211 "D0TSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D1TSR
));
212 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
213 "D0SAR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D2SAR
));
214 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
215 "D0TSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D2TSR
));
216 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
217 "D0SAR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D3SAR
));
218 len
+= snprintf(buf
+ len
, HSU_REGS_BUFSIZE
- len
,
219 "D0TSR: \t\t0x%08x\n", chan_readl(chan
, HSU_CH_D3TSR
));
221 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
226 static const struct file_operations port_regs_ops
= {
227 .owner
= THIS_MODULE
,
228 .open
= hsu_show_regs_open
,
229 .read
= port_show_regs
,
230 .llseek
= default_llseek
,
233 static const struct file_operations dma_regs_ops
= {
234 .owner
= THIS_MODULE
,
235 .open
= hsu_show_regs_open
,
236 .read
= dma_show_regs
,
237 .llseek
= default_llseek
,
240 static int hsu_debugfs_init(struct hsu_port
*hsu
)
245 hsu
->debugfs
= debugfs_create_dir("hsu", NULL
);
249 for (i
= 0; i
< 3; i
++) {
250 snprintf(name
, sizeof(name
), "port_%d_regs", i
);
251 debugfs_create_file(name
, S_IFREG
| S_IRUGO
,
252 hsu
->debugfs
, (void *)(&hsu
->port
[i
]), &port_regs_ops
);
255 for (i
= 0; i
< 6; i
++) {
256 snprintf(name
, sizeof(name
), "dma_chan_%d_regs", i
);
257 debugfs_create_file(name
, S_IFREG
| S_IRUGO
,
258 hsu
->debugfs
, (void *)&hsu
->chans
[i
], &dma_regs_ops
);
264 static void hsu_debugfs_remove(struct hsu_port
*hsu
)
267 debugfs_remove_recursive(hsu
->debugfs
);
271 static inline int hsu_debugfs_init(struct hsu_port
*hsu
)
276 static inline void hsu_debugfs_remove(struct hsu_port
*hsu
)
279 #endif /* CONFIG_DEBUG_FS */
281 static void serial_hsu_enable_ms(struct uart_port
*port
)
283 struct uart_hsu_port
*up
=
284 container_of(port
, struct uart_hsu_port
, port
);
286 up
->ier
|= UART_IER_MSI
;
287 serial_out(up
, UART_IER
, up
->ier
);
290 void hsu_dma_tx(struct uart_hsu_port
*up
)
292 struct circ_buf
*xmit
= &up
->port
.state
->xmit
;
293 struct hsu_dma_buffer
*dbuf
= &up
->txbuf
;
296 /* test_and_set_bit may be better, but anyway it's in lock protected mode */
300 /* Update the circ buf info */
301 xmit
->tail
+= dbuf
->ofs
;
302 xmit
->tail
&= UART_XMIT_SIZE
- 1;
304 up
->port
.icount
.tx
+= dbuf
->ofs
;
307 /* Disable the channel */
308 chan_writel(up
->txc
, HSU_CH_CR
, 0x0);
310 if (!uart_circ_empty(xmit
) && !uart_tx_stopped(&up
->port
)) {
311 dma_sync_single_for_device(up
->port
.dev
,
316 count
= CIRC_CNT_TO_END(xmit
->head
, xmit
->tail
, UART_XMIT_SIZE
);
319 /* Reprogram the channel */
320 chan_writel(up
->txc
, HSU_CH_D0SAR
, dbuf
->dma_addr
+ xmit
->tail
);
321 chan_writel(up
->txc
, HSU_CH_D0TSR
, count
);
323 /* Reenable the channel */
324 chan_writel(up
->txc
, HSU_CH_DCR
, 0x1
329 chan_writel(up
->txc
, HSU_CH_CR
, 0x1);
332 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
333 uart_write_wakeup(&up
->port
);
336 /* The buffer is already cache coherent */
337 void hsu_dma_start_rx_chan(struct hsu_dma_chan
*rxc
, struct hsu_dma_buffer
*dbuf
)
341 chan_writel(rxc
, HSU_CH_BSR
, 32);
342 chan_writel(rxc
, HSU_CH_MOTSR
, 4);
344 chan_writel(rxc
, HSU_CH_D0SAR
, dbuf
->dma_addr
);
345 chan_writel(rxc
, HSU_CH_D0TSR
, dbuf
->dma_size
);
346 chan_writel(rxc
, HSU_CH_DCR
, 0x1 | (0x1 << 8)
348 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
350 chan_writel(rxc
, HSU_CH_CR
, 0x3);
352 mod_timer(&rxc
->rx_timer
, jiffies
+ HSU_DMA_TIMEOUT_CHECK_FREQ
);
355 /* Protected by spin_lock_irqsave(port->lock) */
356 static void serial_hsu_start_tx(struct uart_port
*port
)
358 struct uart_hsu_port
*up
=
359 container_of(port
, struct uart_hsu_port
, port
);
363 } else if (!(up
->ier
& UART_IER_THRI
)) {
364 up
->ier
|= UART_IER_THRI
;
365 serial_out(up
, UART_IER
, up
->ier
);
369 static void serial_hsu_stop_tx(struct uart_port
*port
)
371 struct uart_hsu_port
*up
=
372 container_of(port
, struct uart_hsu_port
, port
);
373 struct hsu_dma_chan
*txc
= up
->txc
;
376 chan_writel(txc
, HSU_CH_CR
, 0x0);
377 else if (up
->ier
& UART_IER_THRI
) {
378 up
->ier
&= ~UART_IER_THRI
;
379 serial_out(up
, UART_IER
, up
->ier
);
383 /* This is always called in spinlock protected mode, so
384 * modify timeout timer is safe here */
385 void hsu_dma_rx(struct uart_hsu_port
*up
, u32 int_sts
)
387 struct hsu_dma_buffer
*dbuf
= &up
->rxbuf
;
388 struct hsu_dma_chan
*chan
= up
->rxc
;
389 struct uart_port
*port
= &up
->port
;
390 struct tty_struct
*tty
= port
->state
->port
.tty
;
397 * First need to know how many is already transferred,
398 * then check if its a timeout DMA irq, and return
399 * the trail bytes out, push them up and reenable the
403 /* Timeout IRQ, need wait some time, see Errata 2 */
407 /* Stop the channel */
408 chan_writel(chan
, HSU_CH_CR
, 0x0);
410 count
= chan_readl(chan
, HSU_CH_D0SAR
) - dbuf
->dma_addr
;
412 /* Restart the channel before we leave */
413 chan_writel(chan
, HSU_CH_CR
, 0x3);
416 del_timer(&chan
->rx_timer
);
418 dma_sync_single_for_cpu(port
->dev
, dbuf
->dma_addr
,
419 dbuf
->dma_size
, DMA_FROM_DEVICE
);
422 * Head will only wrap around when we recycle
423 * the DMA buffer, and when that happens, we
424 * explicitly set tail to 0. So head will
425 * always be greater than tail.
427 tty_insert_flip_string(tty
, dbuf
->buf
, count
);
428 port
->icount
.rx
+= count
;
430 dma_sync_single_for_device(up
->port
.dev
, dbuf
->dma_addr
,
431 dbuf
->dma_size
, DMA_FROM_DEVICE
);
433 /* Reprogram the channel */
434 chan_writel(chan
, HSU_CH_D0SAR
, dbuf
->dma_addr
);
435 chan_writel(chan
, HSU_CH_D0TSR
, dbuf
->dma_size
);
436 chan_writel(chan
, HSU_CH_DCR
, 0x1
439 | (0x1 << 24) /* timeout bit, see HSU Errata 1 */
441 tty_flip_buffer_push(tty
);
443 chan_writel(chan
, HSU_CH_CR
, 0x3);
444 chan
->rx_timer
.expires
= jiffies
+ HSU_DMA_TIMEOUT_CHECK_FREQ
;
445 add_timer(&chan
->rx_timer
);
449 static void serial_hsu_stop_rx(struct uart_port
*port
)
451 struct uart_hsu_port
*up
=
452 container_of(port
, struct uart_hsu_port
, port
);
453 struct hsu_dma_chan
*chan
= up
->rxc
;
456 chan_writel(chan
, HSU_CH_CR
, 0x2);
458 up
->ier
&= ~UART_IER_RLSI
;
459 up
->port
.read_status_mask
&= ~UART_LSR_DR
;
460 serial_out(up
, UART_IER
, up
->ier
);
464 static inline void receive_chars(struct uart_hsu_port
*up
, int *status
)
466 struct tty_struct
*tty
= up
->port
.state
->port
.tty
;
467 unsigned int ch
, flag
;
468 unsigned int max_count
= 256;
474 ch
= serial_in(up
, UART_RX
);
476 up
->port
.icount
.rx
++;
478 if (unlikely(*status
& (UART_LSR_BI
| UART_LSR_PE
|
479 UART_LSR_FE
| UART_LSR_OE
))) {
481 dev_warn(up
->dev
, "We really rush into ERR/BI case"
482 "status = 0x%02x", *status
);
483 /* For statistics only */
484 if (*status
& UART_LSR_BI
) {
485 *status
&= ~(UART_LSR_FE
| UART_LSR_PE
);
486 up
->port
.icount
.brk
++;
488 * We do the SysRQ and SAK checking
489 * here because otherwise the break
490 * may get masked by ignore_status_mask
491 * or read_status_mask.
493 if (uart_handle_break(&up
->port
))
495 } else if (*status
& UART_LSR_PE
)
496 up
->port
.icount
.parity
++;
497 else if (*status
& UART_LSR_FE
)
498 up
->port
.icount
.frame
++;
499 if (*status
& UART_LSR_OE
)
500 up
->port
.icount
.overrun
++;
502 /* Mask off conditions which should be ignored. */
503 *status
&= up
->port
.read_status_mask
;
505 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
507 up
->port
.cons
->index
== up
->port
.line
) {
508 /* Recover the break flag from console xmit */
509 *status
|= up
->lsr_break_flag
;
510 up
->lsr_break_flag
= 0;
513 if (*status
& UART_LSR_BI
) {
515 } else if (*status
& UART_LSR_PE
)
517 else if (*status
& UART_LSR_FE
)
521 if (uart_handle_sysrq_char(&up
->port
, ch
))
524 uart_insert_char(&up
->port
, *status
, UART_LSR_OE
, ch
, flag
);
526 *status
= serial_in(up
, UART_LSR
);
527 } while ((*status
& UART_LSR_DR
) && max_count
--);
528 tty_flip_buffer_push(tty
);
531 static void transmit_chars(struct uart_hsu_port
*up
)
533 struct circ_buf
*xmit
= &up
->port
.state
->xmit
;
536 if (up
->port
.x_char
) {
537 serial_out(up
, UART_TX
, up
->port
.x_char
);
538 up
->port
.icount
.tx
++;
542 if (uart_circ_empty(xmit
) || uart_tx_stopped(&up
->port
)) {
543 serial_hsu_stop_tx(&up
->port
);
547 #ifndef MFD_HSU_A0_STEPPING
548 count
= up
->port
.fifosize
/ 2;
551 * A0 only supports fully empty IRQ, and the first char written
552 * into it won't clear the EMPT bit, so we may need be cautious
553 * by useing a shorter buffer
555 count
= up
->port
.fifosize
- 4;
558 serial_out(up
, UART_TX
, xmit
->buf
[xmit
->tail
]);
559 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
561 up
->port
.icount
.tx
++;
562 if (uart_circ_empty(xmit
))
564 } while (--count
> 0);
566 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
567 uart_write_wakeup(&up
->port
);
569 if (uart_circ_empty(xmit
))
570 serial_hsu_stop_tx(&up
->port
);
573 static inline void check_modem_status(struct uart_hsu_port
*up
)
577 status
= serial_in(up
, UART_MSR
);
579 if ((status
& UART_MSR_ANY_DELTA
) == 0)
582 if (status
& UART_MSR_TERI
)
583 up
->port
.icount
.rng
++;
584 if (status
& UART_MSR_DDSR
)
585 up
->port
.icount
.dsr
++;
586 /* We may only get DDCD when HW init and reset */
587 if (status
& UART_MSR_DDCD
)
588 uart_handle_dcd_change(&up
->port
, status
& UART_MSR_DCD
);
589 /* Will start/stop_tx accordingly */
590 if (status
& UART_MSR_DCTS
)
591 uart_handle_cts_change(&up
->port
, status
& UART_MSR_CTS
);
593 wake_up_interruptible(&up
->port
.state
->port
.delta_msr_wait
);
597 * This handles the interrupt from one port.
599 static irqreturn_t
port_irq(int irq
, void *dev_id
)
601 struct uart_hsu_port
*up
= dev_id
;
602 unsigned int iir
, lsr
;
605 if (unlikely(!up
->running
))
608 spin_lock_irqsave(&up
->port
.lock
, flags
);
610 lsr
= serial_in(up
, UART_LSR
);
611 if (unlikely(lsr
& (UART_LSR_BI
| UART_LSR_PE
|
612 UART_LSR_FE
| UART_LSR_OE
)))
614 "Got lsr irq while using DMA, lsr = 0x%2x\n",
616 check_modem_status(up
);
617 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
621 iir
= serial_in(up
, UART_IIR
);
622 if (iir
& UART_IIR_NO_INT
) {
623 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
627 lsr
= serial_in(up
, UART_LSR
);
628 if (lsr
& UART_LSR_DR
)
629 receive_chars(up
, &lsr
);
630 check_modem_status(up
);
632 /* lsr will be renewed during the receive_chars */
633 if (lsr
& UART_LSR_THRE
)
636 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
640 static inline void dma_chan_irq(struct hsu_dma_chan
*chan
)
642 struct uart_hsu_port
*up
= chan
->uport
;
646 spin_lock_irqsave(&up
->port
.lock
, flags
);
648 if (!up
->use_dma
|| !up
->running
)
652 * No matter what situation, need read clear the IRQ status
653 * There is a bug, see Errata 5, HSD 2900918
655 int_sts
= chan_readl(chan
, HSU_CH_SR
);
658 if (chan
->dirt
== DMA_FROM_DEVICE
)
659 hsu_dma_rx(up
, int_sts
);
662 if (chan
->dirt
== DMA_TO_DEVICE
) {
663 chan_writel(chan
, HSU_CH_CR
, 0x0);
669 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
673 static irqreturn_t
dma_irq(int irq
, void *dev_id
)
675 struct hsu_port
*hsu
= dev_id
;
678 int_sts
= mfd_readl(hsu
, HSU_GBL_DMAISR
);
680 /* Currently we only have 6 channels may be used */
681 for (i
= 0; i
< 6; i
++) {
683 dma_chan_irq(&hsu
->chans
[i
]);
690 static unsigned int serial_hsu_tx_empty(struct uart_port
*port
)
692 struct uart_hsu_port
*up
=
693 container_of(port
, struct uart_hsu_port
, port
);
697 spin_lock_irqsave(&up
->port
.lock
, flags
);
698 ret
= serial_in(up
, UART_LSR
) & UART_LSR_TEMT
? TIOCSER_TEMT
: 0;
699 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
704 static unsigned int serial_hsu_get_mctrl(struct uart_port
*port
)
706 struct uart_hsu_port
*up
=
707 container_of(port
, struct uart_hsu_port
, port
);
708 unsigned char status
;
711 status
= serial_in(up
, UART_MSR
);
714 if (status
& UART_MSR_DCD
)
716 if (status
& UART_MSR_RI
)
718 if (status
& UART_MSR_DSR
)
720 if (status
& UART_MSR_CTS
)
725 static void serial_hsu_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
727 struct uart_hsu_port
*up
=
728 container_of(port
, struct uart_hsu_port
, port
);
729 unsigned char mcr
= 0;
731 if (mctrl
& TIOCM_RTS
)
733 if (mctrl
& TIOCM_DTR
)
735 if (mctrl
& TIOCM_OUT1
)
736 mcr
|= UART_MCR_OUT1
;
737 if (mctrl
& TIOCM_OUT2
)
738 mcr
|= UART_MCR_OUT2
;
739 if (mctrl
& TIOCM_LOOP
)
740 mcr
|= UART_MCR_LOOP
;
744 serial_out(up
, UART_MCR
, mcr
);
747 static void serial_hsu_break_ctl(struct uart_port
*port
, int break_state
)
749 struct uart_hsu_port
*up
=
750 container_of(port
, struct uart_hsu_port
, port
);
753 spin_lock_irqsave(&up
->port
.lock
, flags
);
754 if (break_state
== -1)
755 up
->lcr
|= UART_LCR_SBC
;
757 up
->lcr
&= ~UART_LCR_SBC
;
758 serial_out(up
, UART_LCR
, up
->lcr
);
759 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
763 * What special to do:
764 * 1. chose the 64B fifo mode
765 * 2. make sure not to select half empty mode for A0 stepping
766 * 3. start dma or pio depends on configuration
767 * 4. we only allocate dma memory when needed
769 static int serial_hsu_startup(struct uart_port
*port
)
771 struct uart_hsu_port
*up
=
772 container_of(port
, struct uart_hsu_port
, port
);
776 * Clear the FIFO buffers and disable them.
777 * (they will be reenabled in set_termios())
779 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
);
780 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
781 UART_FCR_CLEAR_RCVR
| UART_FCR_CLEAR_XMIT
);
782 serial_out(up
, UART_FCR
, 0);
784 /* Clear the interrupt registers. */
785 (void) serial_in(up
, UART_LSR
);
786 (void) serial_in(up
, UART_RX
);
787 (void) serial_in(up
, UART_IIR
);
788 (void) serial_in(up
, UART_MSR
);
790 /* Now, initialize the UART, default is 8n1 */
791 serial_out(up
, UART_LCR
, UART_LCR_WLEN8
);
793 spin_lock_irqsave(&up
->port
.lock
, flags
);
795 up
->port
.mctrl
|= TIOCM_OUT2
;
796 serial_hsu_set_mctrl(&up
->port
, up
->port
.mctrl
);
799 * Finally, enable interrupts. Note: Modem status interrupts
800 * are set via set_termios(), which will be occurring imminently
801 * anyway, so we don't enable them here.
804 up
->ier
= UART_IER_RLSI
| UART_IER_RDI
| UART_IER_RTOIE
;
807 serial_out(up
, UART_IER
, up
->ier
);
809 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
813 struct hsu_dma_buffer
*dbuf
;
814 struct circ_buf
*xmit
= &port
->state
->xmit
;
818 /* First allocate the RX buffer */
820 dbuf
->buf
= kzalloc(HSU_DMA_BUF_SIZE
, GFP_KERNEL
);
825 dbuf
->dma_addr
= dma_map_single(port
->dev
,
829 dbuf
->dma_size
= HSU_DMA_BUF_SIZE
;
831 /* Start the RX channel right now */
832 hsu_dma_start_rx_chan(up
->rxc
, dbuf
);
834 /* Next init the TX DMA */
836 dbuf
->buf
= xmit
->buf
;
837 dbuf
->dma_addr
= dma_map_single(port
->dev
,
841 dbuf
->dma_size
= UART_XMIT_SIZE
;
843 /* This should not be changed all around */
844 chan_writel(up
->txc
, HSU_CH_BSR
, 32);
845 chan_writel(up
->txc
, HSU_CH_MOTSR
, 4);
850 /* And clear the interrupt registers again for luck. */
851 (void) serial_in(up
, UART_LSR
);
852 (void) serial_in(up
, UART_RX
);
853 (void) serial_in(up
, UART_IIR
);
854 (void) serial_in(up
, UART_MSR
);
860 static void serial_hsu_shutdown(struct uart_port
*port
)
862 struct uart_hsu_port
*up
=
863 container_of(port
, struct uart_hsu_port
, port
);
866 del_timer_sync(&up
->rxc
->rx_timer
);
868 /* Disable interrupts from this port */
870 serial_out(up
, UART_IER
, 0);
873 spin_lock_irqsave(&up
->port
.lock
, flags
);
874 up
->port
.mctrl
&= ~TIOCM_OUT2
;
875 serial_hsu_set_mctrl(&up
->port
, up
->port
.mctrl
);
876 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
878 /* Disable break condition and FIFOs */
879 serial_out(up
, UART_LCR
, serial_in(up
, UART_LCR
) & ~UART_LCR_SBC
);
880 serial_out(up
, UART_FCR
, UART_FCR_ENABLE_FIFO
|
881 UART_FCR_CLEAR_RCVR
|
882 UART_FCR_CLEAR_XMIT
);
883 serial_out(up
, UART_FCR
, 0);
887 serial_hsu_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
888 struct ktermios
*old
)
890 struct uart_hsu_port
*up
=
891 container_of(port
, struct uart_hsu_port
, port
);
892 struct tty_struct
*tty
= port
->state
->port
.tty
;
893 unsigned char cval
, fcr
= 0;
895 unsigned int baud
, quot
;
899 switch (termios
->c_cflag
& CSIZE
) {
901 cval
= UART_LCR_WLEN5
;
904 cval
= UART_LCR_WLEN6
;
907 cval
= UART_LCR_WLEN7
;
911 cval
= UART_LCR_WLEN8
;
915 /* CMSPAR isn't supported by this driver */
917 tty
->termios
->c_cflag
&= ~CMSPAR
;
919 if (termios
->c_cflag
& CSTOPB
)
920 cval
|= UART_LCR_STOP
;
921 if (termios
->c_cflag
& PARENB
)
922 cval
|= UART_LCR_PARITY
;
923 if (!(termios
->c_cflag
& PARODD
))
924 cval
|= UART_LCR_EPAR
;
927 * For those basic low baud rate we can get the direct
928 * scalar from 2746800, like 115200 = 2746800/24, for those
929 * higher baud rate, we have to handle them case by case,
930 * but DIV reg is never touched as its default value 0x3d09
932 baud
= uart_get_baud_rate(port
, termios
, old
, 0, 4000000);
933 quot
= uart_get_divisor(port
, baud
);
960 if ((up
->port
.uartclk
/ quot
) < (2400 * 16))
961 fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_HSU_64_1B
;
962 else if ((up
->port
.uartclk
/ quot
) < (230400 * 16))
963 fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_HSU_64_16B
;
965 fcr
= UART_FCR_ENABLE_FIFO
| UART_FCR_HSU_64_32B
;
967 fcr
|= UART_FCR_HSU_64B_FIFO
;
968 #ifdef MFD_HSU_A0_STEPPING
969 /* A0 doesn't support half empty IRQ */
970 fcr
|= UART_FCR_FULL_EMPT_TXI
;
974 * Ok, we're now changing the port state. Do it with
975 * interrupts disabled.
977 spin_lock_irqsave(&up
->port
.lock
, flags
);
979 /* Update the per-port timeout */
980 uart_update_timeout(port
, termios
->c_cflag
, baud
);
982 up
->port
.read_status_mask
= UART_LSR_OE
| UART_LSR_THRE
| UART_LSR_DR
;
983 if (termios
->c_iflag
& INPCK
)
984 up
->port
.read_status_mask
|= UART_LSR_FE
| UART_LSR_PE
;
985 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
986 up
->port
.read_status_mask
|= UART_LSR_BI
;
988 /* Characters to ignore */
989 up
->port
.ignore_status_mask
= 0;
990 if (termios
->c_iflag
& IGNPAR
)
991 up
->port
.ignore_status_mask
|= UART_LSR_PE
| UART_LSR_FE
;
992 if (termios
->c_iflag
& IGNBRK
) {
993 up
->port
.ignore_status_mask
|= UART_LSR_BI
;
995 * If we're ignoring parity and break indicators,
996 * ignore overruns too (for real raw support).
998 if (termios
->c_iflag
& IGNPAR
)
999 up
->port
.ignore_status_mask
|= UART_LSR_OE
;
1002 /* Ignore all characters if CREAD is not set */
1003 if ((termios
->c_cflag
& CREAD
) == 0)
1004 up
->port
.ignore_status_mask
|= UART_LSR_DR
;
1007 * CTS flow control flag and modem status interrupts, disable
1010 up
->ier
&= ~UART_IER_MSI
;
1011 if (UART_ENABLE_MS(&up
->port
, termios
->c_cflag
))
1012 up
->ier
|= UART_IER_MSI
;
1014 serial_out(up
, UART_IER
, up
->ier
);
1016 if (termios
->c_cflag
& CRTSCTS
)
1017 up
->mcr
|= UART_MCR_AFE
| UART_MCR_RTS
;
1019 up
->mcr
&= ~UART_MCR_AFE
;
1021 serial_out(up
, UART_LCR
, cval
| UART_LCR_DLAB
); /* set DLAB */
1022 serial_out(up
, UART_DLL
, quot
& 0xff); /* LS of divisor */
1023 serial_out(up
, UART_DLM
, quot
>> 8); /* MS of divisor */
1024 serial_out(up
, UART_LCR
, cval
); /* reset DLAB */
1025 serial_out(up
, UART_MUL
, mul
); /* set MUL */
1026 serial_out(up
, UART_PS
, ps
); /* set PS */
1027 up
->lcr
= cval
; /* Save LCR */
1028 serial_hsu_set_mctrl(&up
->port
, up
->port
.mctrl
);
1029 serial_out(up
, UART_FCR
, fcr
);
1030 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
1034 serial_hsu_pm(struct uart_port
*port
, unsigned int state
,
1035 unsigned int oldstate
)
1039 static void serial_hsu_release_port(struct uart_port
*port
)
1043 static int serial_hsu_request_port(struct uart_port
*port
)
1048 static void serial_hsu_config_port(struct uart_port
*port
, int flags
)
1050 struct uart_hsu_port
*up
=
1051 container_of(port
, struct uart_hsu_port
, port
);
1052 up
->port
.type
= PORT_MFD
;
1056 serial_hsu_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1058 /* We don't want the core code to modify any port params */
1063 serial_hsu_type(struct uart_port
*port
)
1065 struct uart_hsu_port
*up
=
1066 container_of(port
, struct uart_hsu_port
, port
);
1070 /* Mainly for uart console use */
1071 static struct uart_hsu_port
*serial_hsu_ports
[3];
1072 static struct uart_driver serial_hsu_reg
;
1074 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1076 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1078 /* Wait for transmitter & holding register to empty */
1079 static inline void wait_for_xmitr(struct uart_hsu_port
*up
)
1081 unsigned int status
, tmout
= 1000;
1083 /* Wait up to 1ms for the character to be sent. */
1085 status
= serial_in(up
, UART_LSR
);
1087 if (status
& UART_LSR_BI
)
1088 up
->lsr_break_flag
= UART_LSR_BI
;
1093 } while (!(status
& BOTH_EMPTY
));
1095 /* Wait up to 1s for flow control if necessary */
1096 if (up
->port
.flags
& UPF_CONS_FLOW
) {
1099 ((serial_in(up
, UART_MSR
) & UART_MSR_CTS
) == 0))
1104 static void serial_hsu_console_putchar(struct uart_port
*port
, int ch
)
1106 struct uart_hsu_port
*up
=
1107 container_of(port
, struct uart_hsu_port
, port
);
1110 serial_out(up
, UART_TX
, ch
);
1114 * Print a string to the serial port trying not to disturb
1115 * any possible real use of the port...
1117 * The console_lock must be held when we get here.
1120 serial_hsu_console_write(struct console
*co
, const char *s
, unsigned int count
)
1122 struct uart_hsu_port
*up
= serial_hsu_ports
[co
->index
];
1123 unsigned long flags
;
1127 local_irq_save(flags
);
1130 else if (oops_in_progress
) {
1131 locked
= spin_trylock(&up
->port
.lock
);
1133 spin_lock(&up
->port
.lock
);
1135 /* First save the IER then disable the interrupts */
1136 ier
= serial_in(up
, UART_IER
);
1137 serial_out(up
, UART_IER
, 0);
1139 uart_console_write(&up
->port
, s
, count
, serial_hsu_console_putchar
);
1142 * Finally, wait for transmitter to become empty
1143 * and restore the IER
1146 serial_out(up
, UART_IER
, ier
);
1149 spin_unlock(&up
->port
.lock
);
1150 local_irq_restore(flags
);
1153 static struct console serial_hsu_console
;
1156 serial_hsu_console_setup(struct console
*co
, char *options
)
1158 struct uart_hsu_port
*up
;
1165 if (co
->index
== -1 || co
->index
>= serial_hsu_reg
.nr
)
1167 up
= serial_hsu_ports
[co
->index
];
1172 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1174 ret
= uart_set_options(&up
->port
, co
, baud
, parity
, bits
, flow
);
1179 static struct console serial_hsu_console
= {
1181 .write
= serial_hsu_console_write
,
1182 .device
= uart_console_device
,
1183 .setup
= serial_hsu_console_setup
,
1184 .flags
= CON_PRINTBUFFER
,
1186 .data
= &serial_hsu_reg
,
1190 struct uart_ops serial_hsu_pops
= {
1191 .tx_empty
= serial_hsu_tx_empty
,
1192 .set_mctrl
= serial_hsu_set_mctrl
,
1193 .get_mctrl
= serial_hsu_get_mctrl
,
1194 .stop_tx
= serial_hsu_stop_tx
,
1195 .start_tx
= serial_hsu_start_tx
,
1196 .stop_rx
= serial_hsu_stop_rx
,
1197 .enable_ms
= serial_hsu_enable_ms
,
1198 .break_ctl
= serial_hsu_break_ctl
,
1199 .startup
= serial_hsu_startup
,
1200 .shutdown
= serial_hsu_shutdown
,
1201 .set_termios
= serial_hsu_set_termios
,
1202 .pm
= serial_hsu_pm
,
1203 .type
= serial_hsu_type
,
1204 .release_port
= serial_hsu_release_port
,
1205 .request_port
= serial_hsu_request_port
,
1206 .config_port
= serial_hsu_config_port
,
1207 .verify_port
= serial_hsu_verify_port
,
1210 static struct uart_driver serial_hsu_reg
= {
1211 .owner
= THIS_MODULE
,
1212 .driver_name
= "MFD serial",
1213 .dev_name
= "ttyMFD",
1220 static int serial_hsu_suspend(struct pci_dev
*pdev
, pm_message_t state
)
1222 void *priv
= pci_get_drvdata(pdev
);
1223 struct uart_hsu_port
*up
;
1225 /* Make sure this is not the internal dma controller */
1226 if (priv
&& (pdev
->device
!= 0x081E)) {
1228 uart_suspend_port(&serial_hsu_reg
, &up
->port
);
1231 pci_save_state(pdev
);
1232 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
1236 static int serial_hsu_resume(struct pci_dev
*pdev
)
1238 void *priv
= pci_get_drvdata(pdev
);
1239 struct uart_hsu_port
*up
;
1242 pci_set_power_state(pdev
, PCI_D0
);
1243 pci_restore_state(pdev
);
1245 ret
= pci_enable_device(pdev
);
1247 dev_warn(&pdev
->dev
,
1248 "HSU: can't re-enable device, try to continue\n");
1250 if (priv
&& (pdev
->device
!= 0x081E)) {
1252 uart_resume_port(&serial_hsu_reg
, &up
->port
);
1257 #define serial_hsu_suspend NULL
1258 #define serial_hsu_resume NULL
1261 /* temp global pointer before we settle down on using one or four PCI dev */
1262 static struct hsu_port
*phsu
;
1264 static int serial_hsu_probe(struct pci_dev
*pdev
,
1265 const struct pci_device_id
*ent
)
1267 struct uart_hsu_port
*uport
;
1270 printk(KERN_INFO
"HSU: found PCI Serial controller(ID: %04x:%04x)\n",
1271 pdev
->vendor
, pdev
->device
);
1273 switch (pdev
->device
) {
1284 /* internal DMA controller */
1288 dev_err(&pdev
->dev
, "HSU: out of index!");
1292 ret
= pci_enable_device(pdev
);
1297 /* DMA controller */
1298 ret
= request_irq(pdev
->irq
, dma_irq
, 0, "hsu_dma", phsu
);
1300 dev_err(&pdev
->dev
, "can not get IRQ\n");
1303 pci_set_drvdata(pdev
, phsu
);
1306 uport
= &phsu
->port
[index
];
1307 uport
->port
.irq
= pdev
->irq
;
1308 uport
->port
.dev
= &pdev
->dev
;
1309 uport
->dev
= &pdev
->dev
;
1311 ret
= request_irq(pdev
->irq
, port_irq
, 0, uport
->name
, uport
);
1313 dev_err(&pdev
->dev
, "can not get IRQ\n");
1316 uart_add_one_port(&serial_hsu_reg
, &uport
->port
);
1318 #ifdef CONFIG_SERIAL_MFD_HSU_CONSOLE
1320 register_console(&serial_hsu_console
);
1321 uport
->port
.cons
= &serial_hsu_console
;
1324 pci_set_drvdata(pdev
, uport
);
1330 pci_disable_device(pdev
);
1334 static void hsu_dma_rx_timeout(unsigned long data
)
1336 struct hsu_dma_chan
*chan
= (void *)data
;
1337 struct uart_hsu_port
*up
= chan
->uport
;
1338 struct hsu_dma_buffer
*dbuf
= &up
->rxbuf
;
1340 unsigned long flags
;
1342 spin_lock_irqsave(&up
->port
.lock
, flags
);
1344 count
= chan_readl(chan
, HSU_CH_D0SAR
) - dbuf
->dma_addr
;
1347 mod_timer(&chan
->rx_timer
, jiffies
+ HSU_DMA_TIMEOUT_CHECK_FREQ
);
1353 spin_unlock_irqrestore(&up
->port
.lock
, flags
);
1356 static void hsu_global_init(void)
1358 struct hsu_port
*hsu
;
1359 struct uart_hsu_port
*uport
;
1360 struct hsu_dma_chan
*dchan
;
1363 hsu
= kzalloc(sizeof(struct hsu_port
), GFP_KERNEL
);
1367 /* Get basic io resource and map it */
1368 hsu
->paddr
= 0xffa28000;
1369 hsu
->iolen
= 0x1000;
1371 if (!(request_mem_region(hsu
->paddr
, hsu
->iolen
, "HSU global")))
1372 pr_warning("HSU: error in request mem region\n");
1374 hsu
->reg
= ioremap_nocache((unsigned long)hsu
->paddr
, hsu
->iolen
);
1376 pr_err("HSU: error in ioremap\n");
1378 goto err_free_region
;
1381 /* Initialise the 3 UART ports */
1383 for (i
= 0; i
< 3; i
++) {
1384 uport
->port
.type
= PORT_MFD
;
1385 uport
->port
.iotype
= UPIO_MEM
;
1386 uport
->port
.mapbase
= (resource_size_t
)hsu
->paddr
1387 + HSU_PORT_REG_OFFSET
1388 + i
* HSU_PORT_REG_LENGTH
;
1389 uport
->port
.membase
= hsu
->reg
+ HSU_PORT_REG_OFFSET
1390 + i
* HSU_PORT_REG_LENGTH
;
1392 sprintf(uport
->name
, "hsu_port%d", i
);
1393 uport
->port
.fifosize
= 64;
1394 uport
->port
.ops
= &serial_hsu_pops
;
1395 uport
->port
.line
= i
;
1396 uport
->port
.flags
= UPF_IOREMAP
;
1397 /* set the scalable maxim support rate to 2746800 bps */
1398 uport
->port
.uartclk
= 115200 * 24 * 16;
1401 uport
->txc
= &hsu
->chans
[i
* 2];
1402 uport
->rxc
= &hsu
->chans
[i
* 2 + 1];
1404 serial_hsu_ports
[i
] = uport
;
1409 /* Initialise 6 dma channels */
1411 for (i
= 0; i
< 6; i
++) {
1413 dchan
->dirt
= (i
& 0x1) ? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
1414 dchan
->uport
= &hsu
->port
[i
/2];
1415 dchan
->reg
= hsu
->reg
+ HSU_DMA_CHANS_REG_OFFSET
+
1416 i
* HSU_DMA_CHANS_REG_LENGTH
;
1418 /* Work around for RX */
1419 if (dchan
->dirt
== DMA_FROM_DEVICE
) {
1420 init_timer(&dchan
->rx_timer
);
1421 dchan
->rx_timer
.function
= hsu_dma_rx_timeout
;
1422 dchan
->rx_timer
.data
= (unsigned long)dchan
;
1429 hsu_debugfs_init(hsu
);
1433 release_mem_region(hsu
->paddr
, hsu
->iolen
);
1438 static void serial_hsu_remove(struct pci_dev
*pdev
)
1440 struct hsu_port
*hsu
;
1443 hsu
= pci_get_drvdata(pdev
);
1447 for (i
= 0; i
< 3; i
++)
1448 uart_remove_one_port(&serial_hsu_reg
, &hsu
->port
[i
].port
);
1450 pci_set_drvdata(pdev
, NULL
);
1451 free_irq(hsu
->irq
, hsu
);
1452 pci_disable_device(pdev
);
1455 /* First 3 are UART ports, and the 4th is the DMA */
1456 static const struct pci_device_id pci_ids
[] __devinitdata
= {
1457 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081B) },
1458 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081C) },
1459 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081D) },
1460 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, 0x081E) },
1464 static struct pci_driver hsu_pci_driver
= {
1465 .name
= "HSU serial",
1466 .id_table
= pci_ids
,
1467 .probe
= serial_hsu_probe
,
1468 .remove
= __devexit_p(serial_hsu_remove
),
1469 .suspend
= serial_hsu_suspend
,
1470 .resume
= serial_hsu_resume
,
1473 static int __init
hsu_pci_init(void)
1479 ret
= uart_register_driver(&serial_hsu_reg
);
1483 return pci_register_driver(&hsu_pci_driver
);
1486 static void __exit
hsu_pci_exit(void)
1488 pci_unregister_driver(&hsu_pci_driver
);
1489 uart_unregister_driver(&serial_hsu_reg
);
1491 hsu_debugfs_remove(phsu
);
1496 module_init(hsu_pci_init
);
1497 module_exit(hsu_pci_exit
);
1499 MODULE_LICENSE("GPL v2");
1500 MODULE_ALIAS("platform:medfield-hsu");