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Create platform_device.h to contain all the platform device details.
[deliverable/linux.git] / drivers / serial / s3c2410.c
1 /*
2 * linux/drivers/serial/s3c2410.c
3 *
4 * Driver for onboard UARTs on the Samsung S3C24XX
5 *
6 * Based on drivers/char/serial.c and drivers/char/21285.c
7 *
8 * Ben Dooks, (c) 2003-2005 Simtec Electronics
9 * http://www.simtec.co.uk/products/SWLINUX/
10 *
11 * Changelog:
12 *
13 * 22-Jul-2004 BJD Finished off device rewrite
14 *
15 * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
16 * problems with baud rate and loss of IR settings. Update
17 * to add configuration via platform_device structure
18 *
19 * 28-Sep-2004 BJD Re-write for the following items
20 * - S3C2410 and S3C2440 serial support
21 * - Power Management support
22 * - Fix console via IrDA devices
23 * - SysReq (Herbert Pötzl)
24 * - Break character handling (Herbert Pötzl)
25 * - spin-lock initialisation (Dimitry Andric)
26 * - added clock control
27 * - updated init code to use platform_device info
28 *
29 * 06-Mar-2005 BJD Add s3c2440 fclk clock source
30 *
31 * 09-Mar-2005 BJD Add s3c2400 support
32 *
33 * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
34 */
35
36 /* Note on 2440 fclk clock source handling
37 *
38 * Whilst it is possible to use the fclk as clock source, the method
39 * of properly switching too/from this is currently un-implemented, so
40 * whichever way is configured at startup is the one that will be used.
41 */
42
43 /* Hote on 2410 error handling
44 *
45 * The s3c2410 manual has a love/hate affair with the contents of the
46 * UERSTAT register in the UART blocks, and keeps marking some of the
47 * error bits as reserved. Having checked with the s3c2410x01,
48 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
49 * feature from the latter versions of the manual.
50 *
51 * If it becomes aparrent that latter versions of the 2410 remove these
52 * bits, then action will have to be taken to differentiate the versions
53 * and change the policy on BREAK
54 *
55 * BJD, 04-Nov-2004
56 */
57
58 #include <linux/config.h>
59
60 #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
61 #define SUPPORT_SYSRQ
62 #endif
63
64 #include <linux/module.h>
65 #include <linux/ioport.h>
66 #include <linux/platform_device.h>
67 #include <linux/init.h>
68 #include <linux/sysrq.h>
69 #include <linux/console.h>
70 #include <linux/tty.h>
71 #include <linux/tty_flip.h>
72 #include <linux/serial_core.h>
73 #include <linux/serial.h>
74 #include <linux/delay.h>
75
76 #include <asm/io.h>
77 #include <asm/irq.h>
78
79 #include <asm/hardware.h>
80 #include <asm/hardware/clock.h>
81
82 #include <asm/arch/regs-serial.h>
83 #include <asm/arch/regs-gpio.h>
84
85 /* structures */
86
87 struct s3c24xx_uart_info {
88 char *name;
89 unsigned int type;
90 unsigned int fifosize;
91 unsigned long rx_fifomask;
92 unsigned long rx_fifoshift;
93 unsigned long rx_fifofull;
94 unsigned long tx_fifomask;
95 unsigned long tx_fifoshift;
96 unsigned long tx_fifofull;
97
98 /* clock source control */
99
100 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
101 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
102
103 /* uart controls */
104 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
105 };
106
107 struct s3c24xx_uart_port {
108 unsigned char rx_claimed;
109 unsigned char tx_claimed;
110
111 struct s3c24xx_uart_info *info;
112 struct s3c24xx_uart_clksrc *clksrc;
113 struct clk *clk;
114 struct clk *baudclk;
115 struct uart_port port;
116 };
117
118
119 /* configuration defines */
120
121 #if 0
122 #if 1
123 /* send debug to the low-level output routines */
124
125 extern void printascii(const char *);
126
127 static void
128 s3c24xx_serial_dbg(const char *fmt, ...)
129 {
130 va_list va;
131 char buff[256];
132
133 va_start(va, fmt);
134 vsprintf(buff, fmt, va);
135 va_end(va);
136
137 printascii(buff);
138 }
139
140 #define dbg(x...) s3c24xx_serial_dbg(x)
141
142 #else
143 #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
144 #endif
145 #else /* no debug */
146 #define dbg(x...) do {} while(0)
147 #endif
148
149 /* UART name and device definitions */
150
151 #define S3C24XX_SERIAL_NAME "ttySAC"
152 #define S3C24XX_SERIAL_DEVFS "tts/"
153 #define S3C24XX_SERIAL_MAJOR 204
154 #define S3C24XX_SERIAL_MINOR 64
155
156
157 /* conversion functions */
158
159 #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
160 #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
161
162 /* we can support 3 uarts, but not always use them */
163
164 #define NR_PORTS (3)
165
166 /* port irq numbers */
167
168 #define TX_IRQ(port) ((port)->irq + 1)
169 #define RX_IRQ(port) ((port)->irq)
170
171 /* register access controls */
172
173 #define portaddr(port, reg) ((port)->membase + (reg))
174
175 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
176 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
177
178 #define wr_regb(port, reg, val) \
179 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
180
181 #define wr_regl(port, reg, val) \
182 do { __raw_writel(val, portaddr(port, reg)); } while(0)
183
184 /* macros to change one thing to another */
185
186 #define tx_enabled(port) ((port)->unused[0])
187 #define rx_enabled(port) ((port)->unused[1])
188
189 /* flag to ignore all characters comming in */
190 #define RXSTAT_DUMMY_READ (0x10000000)
191
192 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
193 {
194 return container_of(port, struct s3c24xx_uart_port, port);
195 }
196
197 /* translate a port to the device name */
198
199 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
200 {
201 return to_platform_device(port->dev)->name;
202 }
203
204 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
205 {
206 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
207 }
208
209 static void s3c24xx_serial_rx_enable(struct uart_port *port)
210 {
211 unsigned long flags;
212 unsigned int ucon, ufcon;
213 int count = 10000;
214
215 spin_lock_irqsave(&port->lock, flags);
216
217 while (--count && !s3c24xx_serial_txempty_nofifo(port))
218 udelay(100);
219
220 ufcon = rd_regl(port, S3C2410_UFCON);
221 ufcon |= S3C2410_UFCON_RESETRX;
222 wr_regl(port, S3C2410_UFCON, ufcon);
223
224 ucon = rd_regl(port, S3C2410_UCON);
225 ucon |= S3C2410_UCON_RXIRQMODE;
226 wr_regl(port, S3C2410_UCON, ucon);
227
228 rx_enabled(port) = 1;
229 spin_unlock_irqrestore(&port->lock, flags);
230 }
231
232 static void s3c24xx_serial_rx_disable(struct uart_port *port)
233 {
234 unsigned long flags;
235 unsigned int ucon;
236
237 spin_lock_irqsave(&port->lock, flags);
238
239 ucon = rd_regl(port, S3C2410_UCON);
240 ucon &= ~S3C2410_UCON_RXIRQMODE;
241 wr_regl(port, S3C2410_UCON, ucon);
242
243 rx_enabled(port) = 0;
244 spin_unlock_irqrestore(&port->lock, flags);
245 }
246
247 static void s3c24xx_serial_stop_tx(struct uart_port *port)
248 {
249 if (tx_enabled(port)) {
250 disable_irq(TX_IRQ(port));
251 tx_enabled(port) = 0;
252 if (port->flags & UPF_CONS_FLOW)
253 s3c24xx_serial_rx_enable(port);
254 }
255 }
256
257 static void s3c24xx_serial_start_tx(struct uart_port *port)
258 {
259 if (!tx_enabled(port)) {
260 if (port->flags & UPF_CONS_FLOW)
261 s3c24xx_serial_rx_disable(port);
262
263 enable_irq(TX_IRQ(port));
264 tx_enabled(port) = 1;
265 }
266 }
267
268
269 static void s3c24xx_serial_stop_rx(struct uart_port *port)
270 {
271 if (rx_enabled(port)) {
272 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
273 disable_irq(RX_IRQ(port));
274 rx_enabled(port) = 0;
275 }
276 }
277
278 static void s3c24xx_serial_enable_ms(struct uart_port *port)
279 {
280 }
281
282 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
283 {
284 return to_ourport(port)->info;
285 }
286
287 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
288 {
289 if (port->dev == NULL)
290 return NULL;
291
292 return (struct s3c2410_uartcfg *)port->dev->platform_data;
293 }
294
295 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
296 unsigned long ufstat)
297 {
298 struct s3c24xx_uart_info *info = ourport->info;
299
300 if (ufstat & info->rx_fifofull)
301 return info->fifosize;
302
303 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
304 }
305
306
307 /* ? - where has parity gone?? */
308 #define S3C2410_UERSTAT_PARITY (0x1000)
309
310 static irqreturn_t
311 s3c24xx_serial_rx_chars(int irq, void *dev_id, struct pt_regs *regs)
312 {
313 struct s3c24xx_uart_port *ourport = dev_id;
314 struct uart_port *port = &ourport->port;
315 struct tty_struct *tty = port->info->tty;
316 unsigned int ufcon, ch, flag, ufstat, uerstat;
317 int max_count = 64;
318
319 while (max_count-- > 0) {
320 ufcon = rd_regl(port, S3C2410_UFCON);
321 ufstat = rd_regl(port, S3C2410_UFSTAT);
322
323 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
324 break;
325
326 if (tty->flip.count >= TTY_FLIPBUF_SIZE) {
327 if (tty->low_latency)
328 tty_flip_buffer_push(tty);
329
330 /*
331 * If this failed then we will throw away the
332 * bytes but must do so to clear interrupts
333 */
334 }
335
336 uerstat = rd_regl(port, S3C2410_UERSTAT);
337 ch = rd_regb(port, S3C2410_URXH);
338
339 if (port->flags & UPF_CONS_FLOW) {
340 int txe = s3c24xx_serial_txempty_nofifo(port);
341
342 if (rx_enabled(port)) {
343 if (!txe) {
344 rx_enabled(port) = 0;
345 continue;
346 }
347 } else {
348 if (txe) {
349 ufcon |= S3C2410_UFCON_RESETRX;
350 wr_regl(port, S3C2410_UFCON, ufcon);
351 rx_enabled(port) = 1;
352 goto out;
353 }
354 continue;
355 }
356 }
357
358 /* insert the character into the buffer */
359
360 flag = TTY_NORMAL;
361 port->icount.rx++;
362
363 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
364 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
365 ch, uerstat);
366
367 /* check for break */
368 if (uerstat & S3C2410_UERSTAT_BREAK) {
369 dbg("break!\n");
370 port->icount.brk++;
371 if (uart_handle_break(port))
372 goto ignore_char;
373 }
374
375 if (uerstat & S3C2410_UERSTAT_FRAME)
376 port->icount.frame++;
377 if (uerstat & S3C2410_UERSTAT_OVERRUN)
378 port->icount.overrun++;
379
380 uerstat &= port->read_status_mask;
381
382 if (uerstat & S3C2410_UERSTAT_BREAK)
383 flag = TTY_BREAK;
384 else if (uerstat & S3C2410_UERSTAT_PARITY)
385 flag = TTY_PARITY;
386 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
387 flag = TTY_FRAME;
388 }
389
390 if (uart_handle_sysrq_char(port, ch, regs))
391 goto ignore_char;
392
393 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag);
394
395 ignore_char:
396 continue;
397 }
398 tty_flip_buffer_push(tty);
399
400 out:
401 return IRQ_HANDLED;
402 }
403
404 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id, struct pt_regs *regs)
405 {
406 struct s3c24xx_uart_port *ourport = id;
407 struct uart_port *port = &ourport->port;
408 struct circ_buf *xmit = &port->info->xmit;
409 int count = 256;
410
411 if (port->x_char) {
412 wr_regb(port, S3C2410_UTXH, port->x_char);
413 port->icount.tx++;
414 port->x_char = 0;
415 goto out;
416 }
417
418 /* if there isnt anything more to transmit, or the uart is now
419 * stopped, disable the uart and exit
420 */
421
422 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
423 s3c24xx_serial_stop_tx(port);
424 goto out;
425 }
426
427 /* try and drain the buffer... */
428
429 while (!uart_circ_empty(xmit) && count-- > 0) {
430 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
431 break;
432
433 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
434 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
435 port->icount.tx++;
436 }
437
438 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
439 uart_write_wakeup(port);
440
441 if (uart_circ_empty(xmit))
442 s3c24xx_serial_stop_tx(port);
443
444 out:
445 return IRQ_HANDLED;
446 }
447
448 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
449 {
450 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
451 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
452 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
453
454 if (ufcon & S3C2410_UFCON_FIFOMODE) {
455 if ((ufstat & info->tx_fifomask) != 0 ||
456 (ufstat & info->tx_fifofull))
457 return 0;
458
459 return 1;
460 }
461
462 return s3c24xx_serial_txempty_nofifo(port);
463 }
464
465 /* no modem control lines */
466 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
467 {
468 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
469
470 if (umstat & S3C2410_UMSTAT_CTS)
471 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
472 else
473 return TIOCM_CAR | TIOCM_DSR;
474 }
475
476 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
477 {
478 /* todo - possibly remove AFC and do manual CTS */
479 }
480
481 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
482 {
483 unsigned long flags;
484 unsigned int ucon;
485
486 spin_lock_irqsave(&port->lock, flags);
487
488 ucon = rd_regl(port, S3C2410_UCON);
489
490 if (break_state)
491 ucon |= S3C2410_UCON_SBREAK;
492 else
493 ucon &= ~S3C2410_UCON_SBREAK;
494
495 wr_regl(port, S3C2410_UCON, ucon);
496
497 spin_unlock_irqrestore(&port->lock, flags);
498 }
499
500 static void s3c24xx_serial_shutdown(struct uart_port *port)
501 {
502 struct s3c24xx_uart_port *ourport = to_ourport(port);
503
504 if (ourport->tx_claimed) {
505 free_irq(TX_IRQ(port), ourport);
506 tx_enabled(port) = 0;
507 ourport->tx_claimed = 0;
508 }
509
510 if (ourport->rx_claimed) {
511 free_irq(RX_IRQ(port), ourport);
512 ourport->rx_claimed = 0;
513 rx_enabled(port) = 0;
514 }
515 }
516
517
518 static int s3c24xx_serial_startup(struct uart_port *port)
519 {
520 struct s3c24xx_uart_port *ourport = to_ourport(port);
521 int ret;
522
523 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
524 port->mapbase, port->membase);
525
526 rx_enabled(port) = 1;
527
528 ret = request_irq(RX_IRQ(port),
529 s3c24xx_serial_rx_chars, 0,
530 s3c24xx_serial_portname(port), ourport);
531
532 if (ret != 0) {
533 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
534 return ret;
535 }
536
537 ourport->rx_claimed = 1;
538
539 dbg("requesting tx irq...\n");
540
541 tx_enabled(port) = 1;
542
543 ret = request_irq(TX_IRQ(port),
544 s3c24xx_serial_tx_chars, 0,
545 s3c24xx_serial_portname(port), ourport);
546
547 if (ret) {
548 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
549 goto err;
550 }
551
552 ourport->tx_claimed = 1;
553
554 dbg("s3c24xx_serial_startup ok\n");
555
556 /* the port reset code should have done the correct
557 * register setup for the port controls */
558
559 return ret;
560
561 err:
562 s3c24xx_serial_shutdown(port);
563 return ret;
564 }
565
566 /* power power management control */
567
568 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
569 unsigned int old)
570 {
571 struct s3c24xx_uart_port *ourport = to_ourport(port);
572
573 switch (level) {
574 case 3:
575 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
576 clk_disable(ourport->baudclk);
577
578 clk_disable(ourport->clk);
579 break;
580
581 case 0:
582 clk_enable(ourport->clk);
583
584 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
585 clk_enable(ourport->baudclk);
586
587 break;
588 default:
589 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
590 }
591 }
592
593 /* baud rate calculation
594 *
595 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
596 * of different sources, including the peripheral clock ("pclk") and an
597 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
598 * with a programmable extra divisor.
599 *
600 * The following code goes through the clock sources, and calculates the
601 * baud clocks (and the resultant actual baud rates) and then tries to
602 * pick the closest one and select that.
603 *
604 */
605
606
607 #define MAX_CLKS (8)
608
609 static struct s3c24xx_uart_clksrc tmp_clksrc = {
610 .name = "pclk",
611 .min_baud = 0,
612 .max_baud = 0,
613 .divisor = 1,
614 };
615
616 static inline int
617 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
618 {
619 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
620
621 return (info->get_clksrc)(port, c);
622 }
623
624 static inline int
625 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
626 {
627 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
628
629 return (info->set_clksrc)(port, c);
630 }
631
632 struct baud_calc {
633 struct s3c24xx_uart_clksrc *clksrc;
634 unsigned int calc;
635 unsigned int quot;
636 struct clk *src;
637 };
638
639 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
640 struct uart_port *port,
641 struct s3c24xx_uart_clksrc *clksrc,
642 unsigned int baud)
643 {
644 unsigned long rate;
645
646 calc->src = clk_get(port->dev, clksrc->name);
647 if (calc->src == NULL || IS_ERR(calc->src))
648 return 0;
649
650 rate = clk_get_rate(calc->src);
651 rate /= clksrc->divisor;
652
653 calc->clksrc = clksrc;
654 calc->quot = (rate + (8 * baud)) / (16 * baud);
655 calc->calc = (rate / (calc->quot * 16));
656
657 calc->quot--;
658 return 1;
659 }
660
661 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
662 struct s3c24xx_uart_clksrc **clksrc,
663 struct clk **clk,
664 unsigned int baud)
665 {
666 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
667 struct s3c24xx_uart_clksrc *clkp;
668 struct baud_calc res[MAX_CLKS];
669 struct baud_calc *resptr, *best, *sptr;
670 int i;
671
672 clkp = cfg->clocks;
673 best = NULL;
674
675 if (cfg->clocks_size < 2) {
676 if (cfg->clocks_size == 0)
677 clkp = &tmp_clksrc;
678
679 /* check to see if we're sourcing fclk, and if so we're
680 * going to have to update the clock source
681 */
682
683 if (strcmp(clkp->name, "fclk") == 0) {
684 struct s3c24xx_uart_clksrc src;
685
686 s3c24xx_serial_getsource(port, &src);
687
688 /* check that the port already using fclk, and if
689 * not, then re-select fclk
690 */
691
692 if (strcmp(src.name, clkp->name) == 0) {
693 s3c24xx_serial_setsource(port, clkp);
694 s3c24xx_serial_getsource(port, &src);
695 }
696
697 clkp->divisor = src.divisor;
698 }
699
700 s3c24xx_serial_calcbaud(res, port, clkp, baud);
701 best = res;
702 resptr = best + 1;
703 } else {
704 resptr = res;
705
706 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
707 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
708 resptr++;
709 }
710 }
711
712 /* ok, we now need to select the best clock we found */
713
714 if (!best) {
715 unsigned int deviation = (1<<30)|((1<<30)-1);
716 int calc_deviation;
717
718 for (sptr = res; sptr < resptr; sptr++) {
719 printk(KERN_DEBUG
720 "found clk %p (%s) quot %d, calc %d\n",
721 sptr->clksrc, sptr->clksrc->name,
722 sptr->quot, sptr->calc);
723
724 calc_deviation = baud - sptr->calc;
725 if (calc_deviation < 0)
726 calc_deviation = -calc_deviation;
727
728 if (calc_deviation < deviation) {
729 best = sptr;
730 deviation = calc_deviation;
731 }
732 }
733
734 printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
735 }
736
737 printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
738 best->clksrc, best->clksrc->name, best->quot, best->calc);
739
740 /* store results to pass back */
741
742 *clksrc = best->clksrc;
743 *clk = best->src;
744
745 return best->quot;
746 }
747
748 static void s3c24xx_serial_set_termios(struct uart_port *port,
749 struct termios *termios,
750 struct termios *old)
751 {
752 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
753 struct s3c24xx_uart_port *ourport = to_ourport(port);
754 struct s3c24xx_uart_clksrc *clksrc = NULL;
755 struct clk *clk = NULL;
756 unsigned long flags;
757 unsigned int baud, quot;
758 unsigned int ulcon;
759 unsigned int umcon;
760
761 /*
762 * We don't support modem control lines.
763 */
764 termios->c_cflag &= ~(HUPCL | CMSPAR);
765 termios->c_cflag |= CLOCAL;
766
767 /*
768 * Ask the core to calculate the divisor for us.
769 */
770
771 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
772
773 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
774 quot = port->custom_divisor;
775 else
776 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
777
778 /* check to see if we need to change clock source */
779
780 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
781 s3c24xx_serial_setsource(port, clksrc);
782
783 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
784 clk_disable(ourport->baudclk);
785 clk_unuse(ourport->baudclk);
786 ourport->baudclk = NULL;
787 }
788
789 clk_use(clk);
790 clk_enable(clk);
791
792 ourport->clksrc = clksrc;
793 ourport->baudclk = clk;
794 }
795
796 switch (termios->c_cflag & CSIZE) {
797 case CS5:
798 dbg("config: 5bits/char\n");
799 ulcon = S3C2410_LCON_CS5;
800 break;
801 case CS6:
802 dbg("config: 6bits/char\n");
803 ulcon = S3C2410_LCON_CS6;
804 break;
805 case CS7:
806 dbg("config: 7bits/char\n");
807 ulcon = S3C2410_LCON_CS7;
808 break;
809 case CS8:
810 default:
811 dbg("config: 8bits/char\n");
812 ulcon = S3C2410_LCON_CS8;
813 break;
814 }
815
816 /* preserve original lcon IR settings */
817 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
818
819 if (termios->c_cflag & CSTOPB)
820 ulcon |= S3C2410_LCON_STOPB;
821
822 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
823
824 if (termios->c_cflag & PARENB) {
825 if (termios->c_cflag & PARODD)
826 ulcon |= S3C2410_LCON_PODD;
827 else
828 ulcon |= S3C2410_LCON_PEVEN;
829 } else {
830 ulcon |= S3C2410_LCON_PNONE;
831 }
832
833 spin_lock_irqsave(&port->lock, flags);
834
835 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
836
837 wr_regl(port, S3C2410_ULCON, ulcon);
838 wr_regl(port, S3C2410_UBRDIV, quot);
839 wr_regl(port, S3C2410_UMCON, umcon);
840
841 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
842 rd_regl(port, S3C2410_ULCON),
843 rd_regl(port, S3C2410_UCON),
844 rd_regl(port, S3C2410_UFCON));
845
846 /*
847 * Update the per-port timeout.
848 */
849 uart_update_timeout(port, termios->c_cflag, baud);
850
851 /*
852 * Which character status flags are we interested in?
853 */
854 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
855 if (termios->c_iflag & INPCK)
856 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
857
858 /*
859 * Which character status flags should we ignore?
860 */
861 port->ignore_status_mask = 0;
862 if (termios->c_iflag & IGNPAR)
863 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
864 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
865 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
866
867 /*
868 * Ignore all characters if CREAD is not set.
869 */
870 if ((termios->c_cflag & CREAD) == 0)
871 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
872
873 spin_unlock_irqrestore(&port->lock, flags);
874 }
875
876 static const char *s3c24xx_serial_type(struct uart_port *port)
877 {
878 switch (port->type) {
879 case PORT_S3C2410:
880 return "S3C2410";
881 case PORT_S3C2440:
882 return "S3C2440";
883 default:
884 return NULL;
885 }
886 }
887
888 #define MAP_SIZE (0x100)
889
890 static void s3c24xx_serial_release_port(struct uart_port *port)
891 {
892 release_mem_region(port->mapbase, MAP_SIZE);
893 }
894
895 static int s3c24xx_serial_request_port(struct uart_port *port)
896 {
897 const char *name = s3c24xx_serial_portname(port);
898 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
899 }
900
901 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
902 {
903 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
904
905 if (flags & UART_CONFIG_TYPE &&
906 s3c24xx_serial_request_port(port) == 0)
907 port->type = info->type;
908 }
909
910 /*
911 * verify the new serial_struct (for TIOCSSERIAL).
912 */
913 static int
914 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
915 {
916 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
917
918 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
919 return -EINVAL;
920
921 return 0;
922 }
923
924
925 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
926
927 static struct console s3c24xx_serial_console;
928
929 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
930 #else
931 #define S3C24XX_SERIAL_CONSOLE NULL
932 #endif
933
934 static struct uart_ops s3c24xx_serial_ops = {
935 .pm = s3c24xx_serial_pm,
936 .tx_empty = s3c24xx_serial_tx_empty,
937 .get_mctrl = s3c24xx_serial_get_mctrl,
938 .set_mctrl = s3c24xx_serial_set_mctrl,
939 .stop_tx = s3c24xx_serial_stop_tx,
940 .start_tx = s3c24xx_serial_start_tx,
941 .stop_rx = s3c24xx_serial_stop_rx,
942 .enable_ms = s3c24xx_serial_enable_ms,
943 .break_ctl = s3c24xx_serial_break_ctl,
944 .startup = s3c24xx_serial_startup,
945 .shutdown = s3c24xx_serial_shutdown,
946 .set_termios = s3c24xx_serial_set_termios,
947 .type = s3c24xx_serial_type,
948 .release_port = s3c24xx_serial_release_port,
949 .request_port = s3c24xx_serial_request_port,
950 .config_port = s3c24xx_serial_config_port,
951 .verify_port = s3c24xx_serial_verify_port,
952 };
953
954
955 static struct uart_driver s3c24xx_uart_drv = {
956 .owner = THIS_MODULE,
957 .dev_name = "s3c2410_serial",
958 .nr = 3,
959 .cons = S3C24XX_SERIAL_CONSOLE,
960 .driver_name = S3C24XX_SERIAL_NAME,
961 .devfs_name = S3C24XX_SERIAL_DEVFS,
962 .major = S3C24XX_SERIAL_MAJOR,
963 .minor = S3C24XX_SERIAL_MINOR,
964 };
965
966 static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
967 [0] = {
968 .port = {
969 .lock = SPIN_LOCK_UNLOCKED,
970 .iotype = UPIO_MEM,
971 .irq = IRQ_S3CUART_RX0,
972 .uartclk = 0,
973 .fifosize = 16,
974 .ops = &s3c24xx_serial_ops,
975 .flags = UPF_BOOT_AUTOCONF,
976 .line = 0,
977 }
978 },
979 [1] = {
980 .port = {
981 .lock = SPIN_LOCK_UNLOCKED,
982 .iotype = UPIO_MEM,
983 .irq = IRQ_S3CUART_RX1,
984 .uartclk = 0,
985 .fifosize = 16,
986 .ops = &s3c24xx_serial_ops,
987 .flags = UPF_BOOT_AUTOCONF,
988 .line = 1,
989 }
990 },
991 #if NR_PORTS > 2
992
993 [2] = {
994 .port = {
995 .lock = SPIN_LOCK_UNLOCKED,
996 .iotype = UPIO_MEM,
997 .irq = IRQ_S3CUART_RX2,
998 .uartclk = 0,
999 .fifosize = 16,
1000 .ops = &s3c24xx_serial_ops,
1001 .flags = UPF_BOOT_AUTOCONF,
1002 .line = 2,
1003 }
1004 }
1005 #endif
1006 };
1007
1008 /* s3c24xx_serial_resetport
1009 *
1010 * wrapper to call the specific reset for this port (reset the fifos
1011 * and the settings)
1012 */
1013
1014 static inline int s3c24xx_serial_resetport(struct uart_port * port,
1015 struct s3c2410_uartcfg *cfg)
1016 {
1017 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1018
1019 return (info->reset_port)(port, cfg);
1020 }
1021
1022 /* s3c24xx_serial_init_port
1023 *
1024 * initialise a single serial port from the platform device given
1025 */
1026
1027 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1028 struct s3c24xx_uart_info *info,
1029 struct platform_device *platdev)
1030 {
1031 struct uart_port *port = &ourport->port;
1032 struct s3c2410_uartcfg *cfg;
1033 struct resource *res;
1034
1035 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1036
1037 if (platdev == NULL)
1038 return -ENODEV;
1039
1040 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1041
1042 if (port->mapbase != 0)
1043 return 0;
1044
1045 if (cfg->hwport > 3)
1046 return -EINVAL;
1047
1048 /* setup info for port */
1049 port->dev = &platdev->dev;
1050 ourport->info = info;
1051
1052 /* copy the info in from provided structure */
1053 ourport->port.fifosize = info->fifosize;
1054
1055 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1056
1057 port->uartclk = 1;
1058
1059 if (cfg->uart_flags & UPF_CONS_FLOW) {
1060 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1061 port->flags |= UPF_CONS_FLOW;
1062 }
1063
1064 /* sort our the physical and virtual addresses for each UART */
1065
1066 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1067 if (res == NULL) {
1068 printk(KERN_ERR "failed to find memory resource for uart\n");
1069 return -EINVAL;
1070 }
1071
1072 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1073
1074 port->mapbase = res->start;
1075 port->membase = S3C24XX_VA_UART + (res->start - S3C2410_PA_UART);
1076 port->irq = platform_get_irq(platdev, 0);
1077
1078 ourport->clk = clk_get(&platdev->dev, "uart");
1079
1080 if (ourport->clk != NULL && !IS_ERR(ourport->clk))
1081 clk_use(ourport->clk);
1082
1083 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1084 port->mapbase, port->membase, port->irq, port->uartclk);
1085
1086 /* reset the fifos (and setup the uart) */
1087 s3c24xx_serial_resetport(port, cfg);
1088 return 0;
1089 }
1090
1091 /* Device driver serial port probe */
1092
1093 static int probe_index = 0;
1094
1095 static int s3c24xx_serial_probe(struct device *_dev,
1096 struct s3c24xx_uart_info *info)
1097 {
1098 struct s3c24xx_uart_port *ourport;
1099 struct platform_device *dev = to_platform_device(_dev);
1100 int ret;
1101
1102 dbg("s3c24xx_serial_probe(%p, %p) %d\n", _dev, info, probe_index);
1103
1104 ourport = &s3c24xx_serial_ports[probe_index];
1105 probe_index++;
1106
1107 dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
1108
1109 ret = s3c24xx_serial_init_port(ourport, info, dev);
1110 if (ret < 0)
1111 goto probe_err;
1112
1113 dbg("%s: adding port\n", __FUNCTION__);
1114 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1115 dev_set_drvdata(_dev, &ourport->port);
1116
1117 return 0;
1118
1119 probe_err:
1120 return ret;
1121 }
1122
1123 static int s3c24xx_serial_remove(struct device *_dev)
1124 {
1125 struct uart_port *port = s3c24xx_dev_to_port(_dev);
1126
1127 if (port)
1128 uart_remove_one_port(&s3c24xx_uart_drv, port);
1129
1130 return 0;
1131 }
1132
1133 /* UART power management code */
1134
1135 #ifdef CONFIG_PM
1136
1137 static int s3c24xx_serial_suspend(struct device *dev, pm_message_t state)
1138 {
1139 struct uart_port *port = s3c24xx_dev_to_port(dev);
1140
1141 if (port)
1142 uart_suspend_port(&s3c24xx_uart_drv, port);
1143
1144 return 0;
1145 }
1146
1147 static int s3c24xx_serial_resume(struct device *dev)
1148 {
1149 struct uart_port *port = s3c24xx_dev_to_port(dev);
1150 struct s3c24xx_uart_port *ourport = to_ourport(port);
1151
1152 if (port) {
1153 clk_enable(ourport->clk);
1154 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1155 clk_disable(ourport->clk);
1156
1157 uart_resume_port(&s3c24xx_uart_drv, port);
1158 }
1159
1160 return 0;
1161 }
1162
1163 #else
1164 #define s3c24xx_serial_suspend NULL
1165 #define s3c24xx_serial_resume NULL
1166 #endif
1167
1168 static int s3c24xx_serial_init(struct device_driver *drv,
1169 struct s3c24xx_uart_info *info)
1170 {
1171 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1172 return driver_register(drv);
1173 }
1174
1175
1176 /* now comes the code to initialise either the s3c2410 or s3c2440 serial
1177 * port information
1178 */
1179
1180 /* cpu specific variations on the serial port support */
1181
1182 #ifdef CONFIG_CPU_S3C2400
1183
1184 static int s3c2400_serial_getsource(struct uart_port *port,
1185 struct s3c24xx_uart_clksrc *clk)
1186 {
1187 clk->divisor = 1;
1188 clk->name = "pclk";
1189
1190 return 0;
1191 }
1192
1193 static int s3c2400_serial_setsource(struct uart_port *port,
1194 struct s3c24xx_uart_clksrc *clk)
1195 {
1196 return 0;
1197 }
1198
1199 static int s3c2400_serial_resetport(struct uart_port *port,
1200 struct s3c2410_uartcfg *cfg)
1201 {
1202 dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
1203 port, port->mapbase, cfg);
1204
1205 wr_regl(port, S3C2410_UCON, cfg->ucon);
1206 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1207
1208 /* reset both fifos */
1209
1210 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1211 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1212
1213 return 0;
1214 }
1215
1216 static struct s3c24xx_uart_info s3c2400_uart_inf = {
1217 .name = "Samsung S3C2400 UART",
1218 .type = PORT_S3C2400,
1219 .fifosize = 16,
1220 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1221 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1222 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1223 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1224 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1225 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1226 .get_clksrc = s3c2400_serial_getsource,
1227 .set_clksrc = s3c2400_serial_setsource,
1228 .reset_port = s3c2400_serial_resetport,
1229 };
1230
1231 static int s3c2400_serial_probe(struct device *dev)
1232 {
1233 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
1234 }
1235
1236 static struct device_driver s3c2400_serial_drv = {
1237 .name = "s3c2400-uart",
1238 .owner = THIS_MODULE,
1239 .bus = &platform_bus_type,
1240 .probe = s3c2400_serial_probe,
1241 .remove = s3c24xx_serial_remove,
1242 .suspend = s3c24xx_serial_suspend,
1243 .resume = s3c24xx_serial_resume,
1244 };
1245
1246 static inline int s3c2400_serial_init(void)
1247 {
1248 return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
1249 }
1250
1251 static inline void s3c2400_serial_exit(void)
1252 {
1253 driver_unregister(&s3c2400_serial_drv);
1254 }
1255
1256 #define s3c2400_uart_inf_at &s3c2400_uart_inf
1257 #else
1258
1259 static inline int s3c2400_serial_init(void)
1260 {
1261 return 0;
1262 }
1263
1264 static inline void s3c2400_serial_exit(void)
1265 {
1266 }
1267
1268 #define s3c2400_uart_inf_at NULL
1269
1270 #endif /* CONFIG_CPU_S3C2400 */
1271
1272 /* S3C2410 support */
1273
1274 #ifdef CONFIG_CPU_S3C2410
1275
1276 static int s3c2410_serial_setsource(struct uart_port *port,
1277 struct s3c24xx_uart_clksrc *clk)
1278 {
1279 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1280
1281 if (strcmp(clk->name, "uclk") == 0)
1282 ucon |= S3C2410_UCON_UCLK;
1283 else
1284 ucon &= ~S3C2410_UCON_UCLK;
1285
1286 wr_regl(port, S3C2410_UCON, ucon);
1287 return 0;
1288 }
1289
1290 static int s3c2410_serial_getsource(struct uart_port *port,
1291 struct s3c24xx_uart_clksrc *clk)
1292 {
1293 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1294
1295 clk->divisor = 1;
1296 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1297
1298 return 0;
1299 }
1300
1301 static int s3c2410_serial_resetport(struct uart_port *port,
1302 struct s3c2410_uartcfg *cfg)
1303 {
1304 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
1305 port, port->mapbase, cfg);
1306
1307 wr_regl(port, S3C2410_UCON, cfg->ucon);
1308 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1309
1310 /* reset both fifos */
1311
1312 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1313 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1314
1315 return 0;
1316 }
1317
1318 static struct s3c24xx_uart_info s3c2410_uart_inf = {
1319 .name = "Samsung S3C2410 UART",
1320 .type = PORT_S3C2410,
1321 .fifosize = 16,
1322 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1323 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1324 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1325 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1326 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1327 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1328 .get_clksrc = s3c2410_serial_getsource,
1329 .set_clksrc = s3c2410_serial_setsource,
1330 .reset_port = s3c2410_serial_resetport,
1331 };
1332
1333 /* device management */
1334
1335 static int s3c2410_serial_probe(struct device *dev)
1336 {
1337 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1338 }
1339
1340 static struct device_driver s3c2410_serial_drv = {
1341 .name = "s3c2410-uart",
1342 .owner = THIS_MODULE,
1343 .bus = &platform_bus_type,
1344 .probe = s3c2410_serial_probe,
1345 .remove = s3c24xx_serial_remove,
1346 .suspend = s3c24xx_serial_suspend,
1347 .resume = s3c24xx_serial_resume,
1348 };
1349
1350 static inline int s3c2410_serial_init(void)
1351 {
1352 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1353 }
1354
1355 static inline void s3c2410_serial_exit(void)
1356 {
1357 driver_unregister(&s3c2410_serial_drv);
1358 }
1359
1360 #define s3c2410_uart_inf_at &s3c2410_uart_inf
1361 #else
1362
1363 static inline int s3c2410_serial_init(void)
1364 {
1365 return 0;
1366 }
1367
1368 static inline void s3c2410_serial_exit(void)
1369 {
1370 }
1371
1372 #define s3c2410_uart_inf_at NULL
1373
1374 #endif /* CONFIG_CPU_S3C2410 */
1375
1376 #ifdef CONFIG_CPU_S3C2440
1377
1378 static int s3c2440_serial_setsource(struct uart_port *port,
1379 struct s3c24xx_uart_clksrc *clk)
1380 {
1381 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1382
1383 // todo - proper fclk<>nonfclk switch //
1384
1385 ucon &= ~S3C2440_UCON_CLKMASK;
1386
1387 if (strcmp(clk->name, "uclk") == 0)
1388 ucon |= S3C2440_UCON_UCLK;
1389 else if (strcmp(clk->name, "pclk") == 0)
1390 ucon |= S3C2440_UCON_PCLK;
1391 else if (strcmp(clk->name, "fclk") == 0)
1392 ucon |= S3C2440_UCON_FCLK;
1393 else {
1394 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1395 return -EINVAL;
1396 }
1397
1398 wr_regl(port, S3C2410_UCON, ucon);
1399 return 0;
1400 }
1401
1402
1403 static int s3c2440_serial_getsource(struct uart_port *port,
1404 struct s3c24xx_uart_clksrc *clk)
1405 {
1406 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1407 unsigned long ucon0, ucon1, ucon2;
1408
1409 switch (ucon & S3C2440_UCON_CLKMASK) {
1410 case S3C2440_UCON_UCLK:
1411 clk->divisor = 1;
1412 clk->name = "uclk";
1413 break;
1414
1415 case S3C2440_UCON_PCLK:
1416 case S3C2440_UCON_PCLK2:
1417 clk->divisor = 1;
1418 clk->name = "pclk";
1419 break;
1420
1421 case S3C2440_UCON_FCLK:
1422 /* the fun of calculating the uart divisors on
1423 * the s3c2440 */
1424
1425 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
1426 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
1427 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
1428
1429 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
1430
1431 ucon0 &= S3C2440_UCON0_DIVMASK;
1432 ucon1 &= S3C2440_UCON1_DIVMASK;
1433 ucon2 &= S3C2440_UCON2_DIVMASK;
1434
1435 if (ucon0 != 0) {
1436 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
1437 clk->divisor += 6;
1438 } else if (ucon1 != 0) {
1439 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
1440 clk->divisor += 21;
1441 } else if (ucon2 != 0) {
1442 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
1443 clk->divisor += 36;
1444 } else {
1445 /* manual calims 44, seems to be 9 */
1446 clk->divisor = 9;
1447 }
1448
1449 clk->name = "fclk";
1450 break;
1451 }
1452
1453 return 0;
1454 }
1455
1456 static int s3c2440_serial_resetport(struct uart_port *port,
1457 struct s3c2410_uartcfg *cfg)
1458 {
1459 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1460
1461 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
1462 port, port->mapbase, cfg);
1463
1464 /* ensure we don't change the clock settings... */
1465
1466 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
1467
1468 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1469 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1470
1471 /* reset both fifos */
1472
1473 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1474 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1475
1476 return 0;
1477 }
1478
1479 static struct s3c24xx_uart_info s3c2440_uart_inf = {
1480 .name = "Samsung S3C2440 UART",
1481 .type = PORT_S3C2440,
1482 .fifosize = 64,
1483 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1484 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1485 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1486 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1487 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1488 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1489 .get_clksrc = s3c2440_serial_getsource,
1490 .set_clksrc = s3c2440_serial_setsource,
1491 .reset_port = s3c2440_serial_resetport,
1492 };
1493
1494 /* device management */
1495
1496 static int s3c2440_serial_probe(struct device *dev)
1497 {
1498 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1499 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1500 }
1501
1502 static struct device_driver s3c2440_serial_drv = {
1503 .name = "s3c2440-uart",
1504 .owner = THIS_MODULE,
1505 .bus = &platform_bus_type,
1506 .probe = s3c2440_serial_probe,
1507 .remove = s3c24xx_serial_remove,
1508 .suspend = s3c24xx_serial_suspend,
1509 .resume = s3c24xx_serial_resume,
1510 };
1511
1512
1513 static inline int s3c2440_serial_init(void)
1514 {
1515 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1516 }
1517
1518 static inline void s3c2440_serial_exit(void)
1519 {
1520 driver_unregister(&s3c2440_serial_drv);
1521 }
1522
1523 #define s3c2440_uart_inf_at &s3c2440_uart_inf
1524 #else
1525
1526 static inline int s3c2440_serial_init(void)
1527 {
1528 return 0;
1529 }
1530
1531 static inline void s3c2440_serial_exit(void)
1532 {
1533 }
1534
1535 #define s3c2440_uart_inf_at NULL
1536 #endif /* CONFIG_CPU_S3C2440 */
1537
1538 /* module initialisation code */
1539
1540 static int __init s3c24xx_serial_modinit(void)
1541 {
1542 int ret;
1543
1544 ret = uart_register_driver(&s3c24xx_uart_drv);
1545 if (ret < 0) {
1546 printk(KERN_ERR "failed to register UART driver\n");
1547 return -1;
1548 }
1549
1550 s3c2400_serial_init();
1551 s3c2410_serial_init();
1552 s3c2440_serial_init();
1553
1554 return 0;
1555 }
1556
1557 static void __exit s3c24xx_serial_modexit(void)
1558 {
1559 s3c2400_serial_exit();
1560 s3c2410_serial_exit();
1561 s3c2440_serial_exit();
1562
1563 uart_unregister_driver(&s3c24xx_uart_drv);
1564 }
1565
1566
1567 module_init(s3c24xx_serial_modinit);
1568 module_exit(s3c24xx_serial_modexit);
1569
1570 /* Console code */
1571
1572 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1573
1574 static struct uart_port *cons_uart;
1575
1576 static int
1577 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1578 {
1579 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1580 unsigned long ufstat, utrstat;
1581
1582 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1583 /* fifo mode - check ammount of data in fifo registers... */
1584
1585 ufstat = rd_regl(port, S3C2410_UFSTAT);
1586 return (ufstat & info->tx_fifofull) ? 0 : 1;
1587 }
1588
1589 /* in non-fifo mode, we go and use the tx buffer empty */
1590
1591 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1592 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1593 }
1594
1595 static void
1596 s3c24xx_serial_console_write(struct console *co, const char *s,
1597 unsigned int count)
1598 {
1599 int i;
1600 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1601
1602 for (i = 0; i < count; i++) {
1603 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1604 barrier();
1605
1606 wr_regb(cons_uart, S3C2410_UTXH, s[i]);
1607
1608 if (s[i] == '\n') {
1609 while (!s3c24xx_serial_console_txrdy(cons_uart, ufcon))
1610 barrier();
1611
1612 wr_regb(cons_uart, S3C2410_UTXH, '\r');
1613 }
1614 }
1615 }
1616
1617 static void __init
1618 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1619 int *parity, int *bits)
1620 {
1621 struct s3c24xx_uart_clksrc clksrc;
1622 struct clk *clk;
1623 unsigned int ulcon;
1624 unsigned int ucon;
1625 unsigned int ubrdiv;
1626 unsigned long rate;
1627
1628 ulcon = rd_regl(port, S3C2410_ULCON);
1629 ucon = rd_regl(port, S3C2410_UCON);
1630 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1631
1632 dbg("s3c24xx_serial_get_options: port=%p\n"
1633 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1634 port, ulcon, ucon, ubrdiv);
1635
1636 if ((ucon & 0xf) != 0) {
1637 /* consider the serial port configured if the tx/rx mode set */
1638
1639 switch (ulcon & S3C2410_LCON_CSMASK) {
1640 case S3C2410_LCON_CS5:
1641 *bits = 5;
1642 break;
1643 case S3C2410_LCON_CS6:
1644 *bits = 6;
1645 break;
1646 case S3C2410_LCON_CS7:
1647 *bits = 7;
1648 break;
1649 default:
1650 case S3C2410_LCON_CS8:
1651 *bits = 8;
1652 break;
1653 }
1654
1655 switch (ulcon & S3C2410_LCON_PMASK) {
1656 case S3C2410_LCON_PEVEN:
1657 *parity = 'e';
1658 break;
1659
1660 case S3C2410_LCON_PODD:
1661 *parity = 'o';
1662 break;
1663
1664 case S3C2410_LCON_PNONE:
1665 default:
1666 *parity = 'n';
1667 }
1668
1669 /* now calculate the baud rate */
1670
1671 s3c24xx_serial_getsource(port, &clksrc);
1672
1673 clk = clk_get(port->dev, clksrc.name);
1674 if (!IS_ERR(clk) && clk != NULL)
1675 rate = clk_get_rate(clk) / clksrc.divisor;
1676 else
1677 rate = 1;
1678
1679
1680 *baud = rate / ( 16 * (ubrdiv + 1));
1681 dbg("calculated baud %d\n", *baud);
1682 }
1683
1684 }
1685
1686 /* s3c24xx_serial_init_ports
1687 *
1688 * initialise the serial ports from the machine provided initialisation
1689 * data.
1690 */
1691
1692 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1693 {
1694 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1695 struct platform_device **platdev_ptr;
1696 int i;
1697
1698 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1699
1700 platdev_ptr = s3c24xx_uart_devs;
1701
1702 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1703 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1704 }
1705
1706 return 0;
1707 }
1708
1709 static int __init
1710 s3c24xx_serial_console_setup(struct console *co, char *options)
1711 {
1712 struct uart_port *port;
1713 int baud = 9600;
1714 int bits = 8;
1715 int parity = 'n';
1716 int flow = 'n';
1717
1718 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1719 co, co->index, options);
1720
1721 /* is this a valid port */
1722
1723 if (co->index == -1 || co->index >= NR_PORTS)
1724 co->index = 0;
1725
1726 port = &s3c24xx_serial_ports[co->index].port;
1727
1728 /* is the port configured? */
1729
1730 if (port->mapbase == 0x0) {
1731 co->index = 0;
1732 port = &s3c24xx_serial_ports[co->index].port;
1733 }
1734
1735 cons_uart = port;
1736
1737 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1738
1739 /*
1740 * Check whether an invalid uart number has been specified, and
1741 * if so, search for the first available port that does have
1742 * console support.
1743 */
1744 if (options)
1745 uart_parse_options(options, &baud, &parity, &bits, &flow);
1746 else
1747 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1748
1749 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1750
1751 return uart_set_options(port, co, baud, parity, bits, flow);
1752 }
1753
1754 /* s3c24xx_serial_initconsole
1755 *
1756 * initialise the console from one of the uart drivers
1757 */
1758
1759 static struct console s3c24xx_serial_console =
1760 {
1761 .name = S3C24XX_SERIAL_NAME,
1762 .device = uart_console_device,
1763 .flags = CON_PRINTBUFFER,
1764 .index = -1,
1765 .write = s3c24xx_serial_console_write,
1766 .setup = s3c24xx_serial_console_setup
1767 };
1768
1769 static int s3c24xx_serial_initconsole(void)
1770 {
1771 struct s3c24xx_uart_info *info;
1772 struct platform_device *dev = s3c24xx_uart_devs[0];
1773
1774 dbg("s3c24xx_serial_initconsole\n");
1775
1776 /* select driver based on the cpu */
1777
1778 if (dev == NULL) {
1779 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1780 return 0;
1781 }
1782
1783 if (strcmp(dev->name, "s3c2400-uart") == 0) {
1784 info = s3c2400_uart_inf_at;
1785 } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
1786 info = s3c2410_uart_inf_at;
1787 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1788 info = s3c2440_uart_inf_at;
1789 } else {
1790 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1791 return 0;
1792 }
1793
1794 if (info == NULL) {
1795 printk(KERN_ERR "s3c24xx: no driver for console\n");
1796 return 0;
1797 }
1798
1799 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1800 s3c24xx_serial_init_ports(info);
1801
1802 register_console(&s3c24xx_serial_console);
1803 return 0;
1804 }
1805
1806 console_initcall(s3c24xx_serial_initconsole);
1807
1808 #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1809
1810 MODULE_LICENSE("GPL");
1811 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1812 MODULE_DESCRIPTION("Samsung S3C2410/S3C2440 Serial port driver");
Linux kernel - Deliverables
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