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[deliverable/linux.git] / drivers / serial / sh-sci.c
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002 - 2006 Paul Mundt
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20
21 #undef DEBUG
22
23 #include <linux/module.h>
24 #include <linux/errno.h>
25 #include <linux/timer.h>
26 #include <linux/interrupt.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/serial.h>
30 #include <linux/major.h>
31 #include <linux/string.h>
32 #include <linux/sysrq.h>
33 #include <linux/ioport.h>
34 #include <linux/mm.h>
35 #include <linux/init.h>
36 #include <linux/delay.h>
37 #include <linux/console.h>
38 #include <linux/platform_device.h>
39
40 #ifdef CONFIG_CPU_FREQ
41 #include <linux/notifier.h>
42 #include <linux/cpufreq.h>
43 #endif
44
45 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
46 #include <asm/clock.h>
47 #include <asm/sh_bios.h>
48 #include <asm/kgdb.h>
49 #endif
50
51 #include <asm/sci.h>
52
53 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
54 #define SUPPORT_SYSRQ
55 #endif
56
57 #include "sh-sci.h"
58
59 struct sci_port {
60 struct uart_port port;
61
62 /* Port type */
63 unsigned int type;
64
65 /* Port IRQs: ERI, RXI, TXI, BRI (optional) */
66 unsigned int irqs[SCIx_NR_IRQS];
67
68 /* Port pin configuration */
69 void (*init_pins)(struct uart_port *port,
70 unsigned int cflag);
71
72 /* Port enable callback */
73 void (*enable)(struct uart_port *port);
74
75 /* Port disable callback */
76 void (*disable)(struct uart_port *port);
77
78 /* Break timer */
79 struct timer_list break_timer;
80 int break_flag;
81 };
82
83 #ifdef CONFIG_SH_KGDB
84 static struct sci_port *kgdb_sci_port;
85 #endif
86
87 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
88 static struct sci_port *serial_console_port;
89 #endif
90
91 /* Function prototypes */
92 static void sci_stop_tx(struct uart_port *port);
93
94 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
95
96 static struct sci_port sci_ports[SCI_NPORTS];
97 static struct uart_driver sci_uart_driver;
98
99 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \
100 defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
101 static inline void handle_error(struct uart_port *port)
102 {
103 /* Clear error flags */
104 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
105 }
106
107 static int get_char(struct uart_port *port)
108 {
109 unsigned long flags;
110 unsigned short status;
111 int c;
112
113 spin_lock_irqsave(&port->lock, flags);
114 do {
115 status = sci_in(port, SCxSR);
116 if (status & SCxSR_ERRORS(port)) {
117 handle_error(port);
118 continue;
119 }
120 } while (!(status & SCxSR_RDxF(port)));
121 c = sci_in(port, SCxRDR);
122 sci_in(port, SCxSR); /* Dummy read */
123 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
124 spin_unlock_irqrestore(&port->lock, flags);
125
126 return c;
127 }
128 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
129
130 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB)
131 static void put_char(struct uart_port *port, char c)
132 {
133 unsigned long flags;
134 unsigned short status;
135
136 spin_lock_irqsave(&port->lock, flags);
137
138 do {
139 status = sci_in(port, SCxSR);
140 } while (!(status & SCxSR_TDxE(port)));
141
142 sci_out(port, SCxTDR, c);
143 sci_in(port, SCxSR); /* Dummy read */
144 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
145
146 spin_unlock_irqrestore(&port->lock, flags);
147 }
148 #endif
149
150 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
151 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
152 {
153 struct uart_port *port = &sci_port->port;
154 const unsigned char *p = buffer;
155 int i;
156
157 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
158 int checksum;
159 int usegdb=0;
160
161 #ifdef CONFIG_SH_STANDARD_BIOS
162 /* This call only does a trap the first time it is
163 * called, and so is safe to do here unconditionally
164 */
165 usegdb |= sh_bios_in_gdb_mode();
166 #endif
167 #ifdef CONFIG_SH_KGDB
168 usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port));
169 #endif
170
171 if (usegdb) {
172 /* $<packet info>#<checksum>. */
173 do {
174 unsigned char c;
175 put_char(port, '$');
176 put_char(port, 'O'); /* 'O'utput to console */
177 checksum = 'O';
178
179 for (i=0; i<count; i++) { /* Don't use run length encoding */
180 int h, l;
181
182 c = *p++;
183 h = highhex(c);
184 l = lowhex(c);
185 put_char(port, h);
186 put_char(port, l);
187 checksum += h + l;
188 }
189 put_char(port, '#');
190 put_char(port, highhex(checksum));
191 put_char(port, lowhex(checksum));
192 } while (get_char(port) != '+');
193 } else
194 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
195 for (i=0; i<count; i++) {
196 if (*p == 10)
197 put_char(port, '\r');
198 put_char(port, *p++);
199 }
200 }
201 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
202
203 #ifdef CONFIG_SH_KGDB
204 static int kgdb_sci_getchar(void)
205 {
206 int c;
207
208 /* Keep trying to read a character, this could be neater */
209 while ((c = get_char(kgdb_sci_port)) < 0)
210 cpu_relax();
211
212 return c;
213 }
214
215 static inline void kgdb_sci_putchar(int c)
216 {
217 put_char(kgdb_sci_port, c);
218 }
219 #endif /* CONFIG_SH_KGDB */
220
221 #if defined(__H8300S__)
222 enum { sci_disable, sci_enable };
223
224 static void h8300_sci_config(struct uart_port* port, unsigned int ctrl)
225 {
226 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
227 int ch = (port->mapbase - SMR0) >> 3;
228 unsigned char mask = 1 << (ch+1);
229
230 if (ctrl == sci_disable) {
231 *mstpcrl |= mask;
232 } else {
233 *mstpcrl &= ~mask;
234 }
235 }
236
237 static inline void h8300_sci_enable(struct uart_port *port)
238 {
239 h8300_sci_config(port, sci_enable);
240 }
241
242 static inline void h8300_sci_disable(struct uart_port *port)
243 {
244 h8300_sci_config(port, sci_disable);
245 }
246 #endif
247
248 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \
249 defined(__H8300H__) || defined(__H8300S__)
250 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
251 {
252 int ch = (port->mapbase - SMR0) >> 3;
253
254 /* set DDR regs */
255 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
256 h8300_sci_pins[ch].rx,
257 H8300_GPIO_INPUT);
258 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
259 h8300_sci_pins[ch].tx,
260 H8300_GPIO_OUTPUT);
261
262 /* tx mark output*/
263 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
264 }
265 #else
266 #define sci_init_pins_sci NULL
267 #endif
268
269 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
270 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
271 {
272 unsigned int fcr_val = 0;
273
274 if (cflag & CRTSCTS)
275 fcr_val |= SCFCR_MCE;
276
277 sci_out(port, SCFCR, fcr_val);
278 }
279 #else
280 #define sci_init_pins_irda NULL
281 #endif
282
283 #ifdef SCI_ONLY
284 #define sci_init_pins_scif NULL
285 #endif
286
287 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
288 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
289 /* SH7300 doesn't use RTS/CTS */
290 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
291 {
292 sci_out(port, SCFCR, 0);
293 }
294 #elif defined(CONFIG_CPU_SH3)
295 /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
296 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
297 {
298 unsigned int fcr_val = 0;
299 unsigned short data;
300
301 /* We need to set SCPCR to enable RTS/CTS */
302 data = ctrl_inw(SCPCR);
303 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
304 ctrl_outw(data & 0x0fcf, SCPCR);
305
306 if (cflag & CRTSCTS)
307 fcr_val |= SCFCR_MCE;
308 else {
309 /* We need to set SCPCR to enable RTS/CTS */
310 data = ctrl_inw(SCPCR);
311 /* Clear out SCP7MD1,0, SCP4MD1,0,
312 Set SCP6MD1,0 = {01} (output) */
313 ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
314
315 data = ctrl_inb(SCPDR);
316 /* Set /RTS2 (bit6) = 0 */
317 ctrl_outb(data & 0xbf, SCPDR);
318 }
319
320 sci_out(port, SCFCR, fcr_val);
321 }
322 #else
323 /* For SH7750 */
324 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
325 {
326 unsigned int fcr_val = 0;
327
328 if (cflag & CRTSCTS) {
329 fcr_val |= SCFCR_MCE;
330 } else {
331 #ifdef CONFIG_CPU_SUBTYPE_SH7343
332 /* Nothing */
333 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
334 ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
335 #else
336 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
337 #endif
338 }
339 sci_out(port, SCFCR, fcr_val);
340 }
341 #endif
342
343 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || defined(CONFIG_CPU_SUBTYPE_SH7780)
344 static inline int scif_txroom(struct uart_port *port)
345 {
346 return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0x7f);
347 }
348
349 static inline int scif_rxroom(struct uart_port *port)
350 {
351 return sci_in(port, SCRFDR) & 0x7f;
352 }
353 #else
354 static inline int scif_txroom(struct uart_port *port)
355 {
356 return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
357 }
358
359 static inline int scif_rxroom(struct uart_port *port)
360 {
361 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
362 }
363 #endif
364 #endif /* SCIF_ONLY || SCI_AND_SCIF */
365
366 static inline int sci_txroom(struct uart_port *port)
367 {
368 return ((sci_in(port, SCxSR) & SCI_TDRE) != 0);
369 }
370
371 static inline int sci_rxroom(struct uart_port *port)
372 {
373 return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0);
374 }
375
376 /* ********************************************************************** *
377 * the interrupt related routines *
378 * ********************************************************************** */
379
380 static void sci_transmit_chars(struct uart_port *port)
381 {
382 struct circ_buf *xmit = &port->info->xmit;
383 unsigned int stopped = uart_tx_stopped(port);
384 unsigned short status;
385 unsigned short ctrl;
386 int count;
387
388 status = sci_in(port, SCxSR);
389 if (!(status & SCxSR_TDxE(port))) {
390 ctrl = sci_in(port, SCSCR);
391 if (uart_circ_empty(xmit)) {
392 ctrl &= ~SCI_CTRL_FLAGS_TIE;
393 } else {
394 ctrl |= SCI_CTRL_FLAGS_TIE;
395 }
396 sci_out(port, SCSCR, ctrl);
397 return;
398 }
399
400 #ifndef SCI_ONLY
401 if (port->type == PORT_SCIF)
402 count = scif_txroom(port);
403 else
404 #endif
405 count = sci_txroom(port);
406
407 do {
408 unsigned char c;
409
410 if (port->x_char) {
411 c = port->x_char;
412 port->x_char = 0;
413 } else if (!uart_circ_empty(xmit) && !stopped) {
414 c = xmit->buf[xmit->tail];
415 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
416 } else {
417 break;
418 }
419
420 sci_out(port, SCxTDR, c);
421
422 port->icount.tx++;
423 } while (--count > 0);
424
425 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
426
427 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
428 uart_write_wakeup(port);
429 if (uart_circ_empty(xmit)) {
430 sci_stop_tx(port);
431 } else {
432 ctrl = sci_in(port, SCSCR);
433
434 #if !defined(SCI_ONLY)
435 if (port->type == PORT_SCIF) {
436 sci_in(port, SCxSR); /* Dummy read */
437 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
438 }
439 #endif
440
441 ctrl |= SCI_CTRL_FLAGS_TIE;
442 sci_out(port, SCSCR, ctrl);
443 }
444 }
445
446 /* On SH3, SCIF may read end-of-break as a space->mark char */
447 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
448
449 static inline void sci_receive_chars(struct uart_port *port)
450 {
451 struct sci_port *sci_port = (struct sci_port *)port;
452 struct tty_struct *tty = port->info->tty;
453 int i, count, copied = 0;
454 unsigned short status;
455 unsigned char flag;
456
457 status = sci_in(port, SCxSR);
458 if (!(status & SCxSR_RDxF(port)))
459 return;
460
461 while (1) {
462 #if !defined(SCI_ONLY)
463 if (port->type == PORT_SCIF)
464 count = scif_rxroom(port);
465 else
466 #endif
467 count = sci_rxroom(port);
468
469 /* Don't copy more bytes than there is room for in the buffer */
470 count = tty_buffer_request_room(tty, count);
471
472 /* If for any reason we can't copy more data, we're done! */
473 if (count == 0)
474 break;
475
476 if (port->type == PORT_SCI) {
477 char c = sci_in(port, SCxRDR);
478 if (uart_handle_sysrq_char(port, c) || sci_port->break_flag)
479 count = 0;
480 else {
481 tty_insert_flip_char(tty, c, TTY_NORMAL);
482 }
483 } else {
484 for (i=0; i<count; i++) {
485 char c = sci_in(port, SCxRDR);
486 status = sci_in(port, SCxSR);
487 #if defined(CONFIG_CPU_SH3)
488 /* Skip "chars" during break */
489 if (sci_port->break_flag) {
490 if ((c == 0) &&
491 (status & SCxSR_FER(port))) {
492 count--; i--;
493 continue;
494 }
495
496 /* Nonzero => end-of-break */
497 pr_debug("scif: debounce<%02x>\n", c);
498 sci_port->break_flag = 0;
499
500 if (STEPFN(c)) {
501 count--; i--;
502 continue;
503 }
504 }
505 #endif /* CONFIG_CPU_SH3 */
506 if (uart_handle_sysrq_char(port, c)) {
507 count--; i--;
508 continue;
509 }
510
511 /* Store data and status */
512 if (status&SCxSR_FER(port)) {
513 flag = TTY_FRAME;
514 pr_debug("sci: frame error\n");
515 } else if (status&SCxSR_PER(port)) {
516 flag = TTY_PARITY;
517 pr_debug("sci: parity error\n");
518 } else
519 flag = TTY_NORMAL;
520 tty_insert_flip_char(tty, c, flag);
521 }
522 }
523
524 sci_in(port, SCxSR); /* dummy read */
525 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
526
527 copied += count;
528 port->icount.rx += count;
529 }
530
531 if (copied) {
532 /* Tell the rest of the system the news. New characters! */
533 tty_flip_buffer_push(tty);
534 } else {
535 sci_in(port, SCxSR); /* dummy read */
536 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
537 }
538 }
539
540 #define SCI_BREAK_JIFFIES (HZ/20)
541 /* The sci generates interrupts during the break,
542 * 1 per millisecond or so during the break period, for 9600 baud.
543 * So dont bother disabling interrupts.
544 * But dont want more than 1 break event.
545 * Use a kernel timer to periodically poll the rx line until
546 * the break is finished.
547 */
548 static void sci_schedule_break_timer(struct sci_port *port)
549 {
550 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
551 add_timer(&port->break_timer);
552 }
553 /* Ensure that two consecutive samples find the break over. */
554 static void sci_break_timer(unsigned long data)
555 {
556 struct sci_port *port = (struct sci_port *)data;
557
558 if (sci_rxd_in(&port->port) == 0) {
559 port->break_flag = 1;
560 sci_schedule_break_timer(port);
561 } else if (port->break_flag == 1) {
562 /* break is over. */
563 port->break_flag = 2;
564 sci_schedule_break_timer(port);
565 } else
566 port->break_flag = 0;
567 }
568
569 static inline int sci_handle_errors(struct uart_port *port)
570 {
571 int copied = 0;
572 unsigned short status = sci_in(port, SCxSR);
573 struct tty_struct *tty = port->info->tty;
574
575 if (status & SCxSR_ORER(port)) {
576 /* overrun error */
577 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
578 copied++;
579 pr_debug("sci: overrun error\n");
580 }
581
582 if (status & SCxSR_FER(port)) {
583 if (sci_rxd_in(port) == 0) {
584 /* Notify of BREAK */
585 struct sci_port *sci_port = (struct sci_port *)port;
586
587 if (!sci_port->break_flag) {
588 sci_port->break_flag = 1;
589 sci_schedule_break_timer(sci_port);
590
591 /* Do sysrq handling. */
592 if (uart_handle_break(port))
593 return 0;
594 pr_debug("sci: BREAK detected\n");
595 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
596 copied++;
597 }
598 } else {
599 /* frame error */
600 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
601 copied++;
602 pr_debug("sci: frame error\n");
603 }
604 }
605
606 if (status & SCxSR_PER(port)) {
607 /* parity error */
608 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
609 copied++;
610 pr_debug("sci: parity error\n");
611 }
612
613 if (copied)
614 tty_flip_buffer_push(tty);
615
616 return copied;
617 }
618
619 static inline int sci_handle_breaks(struct uart_port *port)
620 {
621 int copied = 0;
622 unsigned short status = sci_in(port, SCxSR);
623 struct tty_struct *tty = port->info->tty;
624 struct sci_port *s = &sci_ports[port->line];
625
626 if (!s->break_flag && status & SCxSR_BRK(port)) {
627 #if defined(CONFIG_CPU_SH3)
628 /* Debounce break */
629 s->break_flag = 1;
630 #endif
631 /* Notify of BREAK */
632 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
633 copied++;
634 pr_debug("sci: BREAK detected\n");
635 }
636
637 #if defined(SCIF_ORER)
638 /* XXX: Handle SCIF overrun error */
639 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
640 sci_out(port, SCLSR, 0);
641 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
642 copied++;
643 pr_debug("sci: overrun error\n");
644 }
645 }
646 #endif
647
648 if (copied)
649 tty_flip_buffer_push(tty);
650
651 return copied;
652 }
653
654 static irqreturn_t sci_rx_interrupt(int irq, void *port)
655 {
656 /* I think sci_receive_chars has to be called irrespective
657 * of whether the I_IXOFF is set, otherwise, how is the interrupt
658 * to be disabled?
659 */
660 sci_receive_chars(port);
661
662 return IRQ_HANDLED;
663 }
664
665 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
666 {
667 struct uart_port *port = ptr;
668
669 spin_lock_irq(&port->lock);
670 sci_transmit_chars(port);
671 spin_unlock_irq(&port->lock);
672
673 return IRQ_HANDLED;
674 }
675
676 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
677 {
678 struct uart_port *port = ptr;
679
680 /* Handle errors */
681 if (port->type == PORT_SCI) {
682 if (sci_handle_errors(port)) {
683 /* discard character in rx buffer */
684 sci_in(port, SCxSR);
685 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
686 }
687 } else {
688 #if defined(SCIF_ORER)
689 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
690 struct tty_struct *tty = port->info->tty;
691
692 sci_out(port, SCLSR, 0);
693 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
694 tty_flip_buffer_push(tty);
695 pr_debug("scif: overrun error\n");
696 }
697 #endif
698 sci_rx_interrupt(irq, ptr);
699 }
700
701 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
702
703 /* Kick the transmission */
704 sci_tx_interrupt(irq, ptr);
705
706 return IRQ_HANDLED;
707 }
708
709 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
710 {
711 struct uart_port *port = ptr;
712
713 /* Handle BREAKs */
714 sci_handle_breaks(port);
715
716 #ifdef CONFIG_SH_KGDB
717 /* Break into the debugger if a break is detected */
718 BREAKPOINT();
719 #endif
720
721 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
722
723 return IRQ_HANDLED;
724 }
725
726 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
727 {
728 unsigned short ssr_status, scr_status;
729 struct uart_port *port = ptr;
730
731 ssr_status = sci_in(port,SCxSR);
732 scr_status = sci_in(port,SCSCR);
733
734 /* Tx Interrupt */
735 if ((ssr_status & 0x0020) && (scr_status & 0x0080))
736 sci_tx_interrupt(irq, ptr);
737 /* Rx Interrupt */
738 if ((ssr_status & 0x0002) && (scr_status & 0x0040))
739 sci_rx_interrupt(irq, ptr);
740 /* Error Interrupt */
741 if ((ssr_status & 0x0080) && (scr_status & 0x0400))
742 sci_er_interrupt(irq, ptr);
743 /* Break Interrupt */
744 if ((ssr_status & 0x0010) && (scr_status & 0x0200))
745 sci_br_interrupt(irq, ptr);
746
747 return IRQ_HANDLED;
748 }
749
750 #ifdef CONFIG_CPU_FREQ
751 /*
752 * Here we define a transistion notifier so that we can update all of our
753 * ports' baud rate when the peripheral clock changes.
754 */
755 static int sci_notifier(struct notifier_block *self,
756 unsigned long phase, void *p)
757 {
758 struct cpufreq_freqs *freqs = p;
759 int i;
760
761 if ((phase == CPUFREQ_POSTCHANGE) ||
762 (phase == CPUFREQ_RESUMECHANGE)){
763 for (i = 0; i < SCI_NPORTS; i++) {
764 struct uart_port *port = &sci_ports[i].port;
765 struct clk *clk;
766
767 /*
768 * Update the uartclk per-port if frequency has
769 * changed, since it will no longer necessarily be
770 * consistent with the old frequency.
771 *
772 * Really we want to be able to do something like
773 * uart_change_speed() or something along those lines
774 * here to implicitly reset the per-port baud rate..
775 *
776 * Clean this up later..
777 */
778 clk = clk_get(NULL, "module_clk");
779 port->uartclk = clk_get_rate(clk) * 16;
780 clk_put(clk);
781 }
782
783 printk(KERN_INFO "%s: got a postchange notification "
784 "for cpu %d (old %d, new %d)\n",
785 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
786 }
787
788 return NOTIFY_OK;
789 }
790
791 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
792 #endif /* CONFIG_CPU_FREQ */
793
794 static int sci_request_irq(struct sci_port *port)
795 {
796 int i;
797 irqreturn_t (*handlers[4])(int irq, void *ptr) = {
798 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
799 sci_br_interrupt,
800 };
801 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
802 "SCI Transmit Data Empty", "SCI Break" };
803
804 if (port->irqs[0] == port->irqs[1]) {
805 if (!port->irqs[0]) {
806 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
807 return -ENODEV;
808 }
809
810 if (request_irq(port->irqs[0], sci_mpxed_interrupt,
811 IRQF_DISABLED, "sci", port)) {
812 printk(KERN_ERR "sci: Cannot allocate irq.\n");
813 return -ENODEV;
814 }
815 } else {
816 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
817 if (!port->irqs[i])
818 continue;
819 if (request_irq(port->irqs[i], handlers[i],
820 IRQF_DISABLED, desc[i], port)) {
821 printk(KERN_ERR "sci: Cannot allocate irq.\n");
822 return -ENODEV;
823 }
824 }
825 }
826
827 return 0;
828 }
829
830 static void sci_free_irq(struct sci_port *port)
831 {
832 int i;
833
834 if (port->irqs[0] == port->irqs[1]) {
835 if (!port->irqs[0])
836 printk("sci: sci_free_irq error\n");
837 else
838 free_irq(port->irqs[0], port);
839 } else {
840 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
841 if (!port->irqs[i])
842 continue;
843
844 free_irq(port->irqs[i], port);
845 }
846 }
847 }
848
849 static unsigned int sci_tx_empty(struct uart_port *port)
850 {
851 /* Can't detect */
852 return TIOCSER_TEMT;
853 }
854
855 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
856 {
857 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
858 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
859 /* If you have signals for DTR and DCD, please implement here. */
860 }
861
862 static unsigned int sci_get_mctrl(struct uart_port *port)
863 {
864 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
865 and CTS/RTS */
866
867 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
868 }
869
870 static void sci_start_tx(struct uart_port *port)
871 {
872 unsigned short ctrl;
873
874 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
875 ctrl = sci_in(port, SCSCR);
876 ctrl |= SCI_CTRL_FLAGS_TIE;
877 sci_out(port, SCSCR, ctrl);
878 }
879
880 static void sci_stop_tx(struct uart_port *port)
881 {
882 unsigned short ctrl;
883
884 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
885 ctrl = sci_in(port, SCSCR);
886 ctrl &= ~SCI_CTRL_FLAGS_TIE;
887 sci_out(port, SCSCR, ctrl);
888 }
889
890 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
891 {
892 unsigned short ctrl;
893
894 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
895 ctrl = sci_in(port, SCSCR);
896 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
897 sci_out(port, SCSCR, ctrl);
898 }
899
900 static void sci_stop_rx(struct uart_port *port)
901 {
902 unsigned short ctrl;
903
904 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
905 ctrl = sci_in(port, SCSCR);
906 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
907 sci_out(port, SCSCR, ctrl);
908 }
909
910 static void sci_enable_ms(struct uart_port *port)
911 {
912 /* Nothing here yet .. */
913 }
914
915 static void sci_break_ctl(struct uart_port *port, int break_state)
916 {
917 /* Nothing here yet .. */
918 }
919
920 static int sci_startup(struct uart_port *port)
921 {
922 struct sci_port *s = &sci_ports[port->line];
923
924 if (s->enable)
925 s->enable(port);
926
927 sci_request_irq(s);
928 sci_start_tx(port);
929 sci_start_rx(port, 1);
930
931 return 0;
932 }
933
934 static void sci_shutdown(struct uart_port *port)
935 {
936 struct sci_port *s = &sci_ports[port->line];
937
938 sci_stop_rx(port);
939 sci_stop_tx(port);
940 sci_free_irq(s);
941
942 if (s->disable)
943 s->disable(port);
944 }
945
946 static void sci_set_termios(struct uart_port *port, struct termios *termios,
947 struct termios *old)
948 {
949 struct sci_port *s = &sci_ports[port->line];
950 unsigned int status, baud, smr_val;
951 unsigned long flags;
952 int t;
953
954 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
955
956 switch (baud) {
957 case 0:
958 t = -1;
959 break;
960 default:
961 {
962 #if defined(CONFIG_SUPERH) && !defined(CONFIG_SUPERH64)
963 struct clk *clk = clk_get(NULL, "module_clk");
964 t = SCBRR_VALUE(baud, clk_get_rate(clk));
965 clk_put(clk);
966 #else
967 t = SCBRR_VALUE(baud);
968 #endif
969 }
970 break;
971 }
972
973 spin_lock_irqsave(&port->lock, flags);
974
975 do {
976 status = sci_in(port, SCxSR);
977 } while (!(status & SCxSR_TEND(port)));
978
979 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
980
981 #if !defined(SCI_ONLY)
982 if (port->type == PORT_SCIF)
983 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
984 #endif
985
986 smr_val = sci_in(port, SCSMR) & 3;
987 if ((termios->c_cflag & CSIZE) == CS7)
988 smr_val |= 0x40;
989 if (termios->c_cflag & PARENB)
990 smr_val |= 0x20;
991 if (termios->c_cflag & PARODD)
992 smr_val |= 0x30;
993 if (termios->c_cflag & CSTOPB)
994 smr_val |= 0x08;
995
996 uart_update_timeout(port, termios->c_cflag, baud);
997
998 sci_out(port, SCSMR, smr_val);
999
1000 if (t > 0) {
1001 if(t >= 256) {
1002 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1003 t >>= 2;
1004 } else {
1005 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1006 }
1007 sci_out(port, SCBRR, t);
1008 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1009 }
1010
1011 if (likely(s->init_pins))
1012 s->init_pins(port, termios->c_cflag);
1013
1014 sci_out(port, SCSCR, SCSCR_INIT(port));
1015
1016 if ((termios->c_cflag & CREAD) != 0)
1017 sci_start_rx(port,0);
1018
1019 spin_unlock_irqrestore(&port->lock, flags);
1020 }
1021
1022 static const char *sci_type(struct uart_port *port)
1023 {
1024 switch (port->type) {
1025 case PORT_SCI: return "sci";
1026 case PORT_SCIF: return "scif";
1027 case PORT_IRDA: return "irda";
1028 }
1029
1030 return 0;
1031 }
1032
1033 static void sci_release_port(struct uart_port *port)
1034 {
1035 /* Nothing here yet .. */
1036 }
1037
1038 static int sci_request_port(struct uart_port *port)
1039 {
1040 /* Nothing here yet .. */
1041 return 0;
1042 }
1043
1044 static void sci_config_port(struct uart_port *port, int flags)
1045 {
1046 struct sci_port *s = &sci_ports[port->line];
1047
1048 port->type = s->type;
1049
1050 switch (port->type) {
1051 case PORT_SCI:
1052 s->init_pins = sci_init_pins_sci;
1053 break;
1054 case PORT_SCIF:
1055 s->init_pins = sci_init_pins_scif;
1056 break;
1057 case PORT_IRDA:
1058 s->init_pins = sci_init_pins_irda;
1059 break;
1060 }
1061
1062 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1063 if (port->mapbase == 0)
1064 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1065
1066 port->membase = (void __iomem *)port->mapbase;
1067 #endif
1068 }
1069
1070 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1071 {
1072 struct sci_port *s = &sci_ports[port->line];
1073
1074 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1075 return -EINVAL;
1076 if (ser->baud_base < 2400)
1077 /* No paper tape reader for Mitch.. */
1078 return -EINVAL;
1079
1080 return 0;
1081 }
1082
1083 static struct uart_ops sci_uart_ops = {
1084 .tx_empty = sci_tx_empty,
1085 .set_mctrl = sci_set_mctrl,
1086 .get_mctrl = sci_get_mctrl,
1087 .start_tx = sci_start_tx,
1088 .stop_tx = sci_stop_tx,
1089 .stop_rx = sci_stop_rx,
1090 .enable_ms = sci_enable_ms,
1091 .break_ctl = sci_break_ctl,
1092 .startup = sci_startup,
1093 .shutdown = sci_shutdown,
1094 .set_termios = sci_set_termios,
1095 .type = sci_type,
1096 .release_port = sci_release_port,
1097 .request_port = sci_request_port,
1098 .config_port = sci_config_port,
1099 .verify_port = sci_verify_port,
1100 };
1101
1102 static void __init sci_init_ports(void)
1103 {
1104 static int first = 1;
1105 int i;
1106
1107 if (!first)
1108 return;
1109
1110 first = 0;
1111
1112 for (i = 0; i < SCI_NPORTS; i++) {
1113 sci_ports[i].port.ops = &sci_uart_ops;
1114 sci_ports[i].port.iotype = UPIO_MEM;
1115 sci_ports[i].port.line = i;
1116 sci_ports[i].port.fifosize = 1;
1117
1118 #if defined(__H8300H__) || defined(__H8300S__)
1119 #ifdef __H8300S__
1120 sci_ports[i].enable = h8300_sci_enable;
1121 sci_ports[i].disable = h8300_sci_disable;
1122 #endif
1123 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK;
1124 #elif defined(CONFIG_SUPERH64)
1125 sci_ports[i].port.uartclk = current_cpu_data.module_clock * 16;
1126 #else
1127 /*
1128 * XXX: We should use a proper SCI/SCIF clock
1129 */
1130 {
1131 struct clk *clk = clk_get(NULL, "module_clk");
1132 sci_ports[i].port.uartclk = clk_get_rate(clk) * 16;
1133 clk_put(clk);
1134 }
1135 #endif
1136
1137 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i];
1138 sci_ports[i].break_timer.function = sci_break_timer;
1139
1140 init_timer(&sci_ports[i].break_timer);
1141 }
1142 }
1143
1144 int __init early_sci_setup(struct uart_port *port)
1145 {
1146 if (unlikely(port->line > SCI_NPORTS))
1147 return -ENODEV;
1148
1149 sci_init_ports();
1150
1151 sci_ports[port->line].port.membase = port->membase;
1152 sci_ports[port->line].port.mapbase = port->mapbase;
1153 sci_ports[port->line].port.type = port->type;
1154
1155 return 0;
1156 }
1157
1158 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1159 /*
1160 * Print a string to the serial port trying not to disturb
1161 * any possible real use of the port...
1162 */
1163 static void serial_console_write(struct console *co, const char *s,
1164 unsigned count)
1165 {
1166 put_string(serial_console_port, s, count);
1167 }
1168
1169 static int __init serial_console_setup(struct console *co, char *options)
1170 {
1171 struct uart_port *port;
1172 int baud = 115200;
1173 int bits = 8;
1174 int parity = 'n';
1175 int flow = 'n';
1176 int ret;
1177
1178 /*
1179 * Check whether an invalid uart number has been specified, and
1180 * if so, search for the first available port that does have
1181 * console support.
1182 */
1183 if (co->index >= SCI_NPORTS)
1184 co->index = 0;
1185
1186 serial_console_port = &sci_ports[co->index];
1187 port = &serial_console_port->port;
1188
1189 /*
1190 * Also need to check port->type, we don't actually have any
1191 * UPIO_PORT ports, but uart_report_port() handily misreports
1192 * it anyways if we don't have a port available by the time this is
1193 * called.
1194 */
1195 if (!port->type)
1196 return -ENODEV;
1197 if (!port->membase || !port->mapbase)
1198 return -ENODEV;
1199
1200 spin_lock_init(&port->lock);
1201
1202 port->type = serial_console_port->type;
1203
1204 if (port->flags & UPF_IOREMAP)
1205 sci_config_port(port, 0);
1206
1207 if (serial_console_port->enable)
1208 serial_console_port->enable(port);
1209
1210 if (options)
1211 uart_parse_options(options, &baud, &parity, &bits, &flow);
1212
1213 ret = uart_set_options(port, co, baud, parity, bits, flow);
1214 #if defined(__H8300H__) || defined(__H8300S__)
1215 /* disable rx interrupt */
1216 if (ret == 0)
1217 sci_stop_rx(port);
1218 #endif
1219 return ret;
1220 }
1221
1222 static struct console serial_console = {
1223 .name = "ttySC",
1224 .device = uart_console_device,
1225 .write = serial_console_write,
1226 .setup = serial_console_setup,
1227 .flags = CON_PRINTBUFFER,
1228 .index = -1,
1229 .data = &sci_uart_driver,
1230 };
1231
1232 static int __init sci_console_init(void)
1233 {
1234 sci_init_ports();
1235 register_console(&serial_console);
1236 return 0;
1237 }
1238 console_initcall(sci_console_init);
1239 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1240
1241 #ifdef CONFIG_SH_KGDB
1242 /*
1243 * FIXME: Most of this can go away.. at the moment, we rely on
1244 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1245 * most of that can easily be done here instead.
1246 *
1247 * For the time being, just accept the values that were parsed earlier..
1248 */
1249 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1250 int *parity, int *bits)
1251 {
1252 *baud = kgdb_baud;
1253 *parity = tolower(kgdb_parity);
1254 *bits = kgdb_bits - '0';
1255 }
1256
1257 /*
1258 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1259 * care of the early-on initialization for kgdb, regardless of whether we
1260 * actually use kgdb as a console or not.
1261 *
1262 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1263 */
1264 int __init kgdb_console_setup(struct console *co, char *options)
1265 {
1266 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1267 int baud = 38400;
1268 int bits = 8;
1269 int parity = 'n';
1270 int flow = 'n';
1271
1272 spin_lock_init(&port->lock);
1273
1274 if (co->index != kgdb_portnum)
1275 co->index = kgdb_portnum;
1276
1277 if (options)
1278 uart_parse_options(options, &baud, &parity, &bits, &flow);
1279 else
1280 kgdb_console_get_options(port, &baud, &parity, &bits);
1281
1282 kgdb_getchar = kgdb_sci_getchar;
1283 kgdb_putchar = kgdb_sci_putchar;
1284
1285 return uart_set_options(port, co, baud, parity, bits, flow);
1286 }
1287 #endif /* CONFIG_SH_KGDB */
1288
1289 #ifdef CONFIG_SH_KGDB_CONSOLE
1290 static struct console kgdb_console = {
1291 .name = "ttySC",
1292 .write = kgdb_console_write,
1293 .setup = kgdb_console_setup,
1294 .flags = CON_PRINTBUFFER | CON_ENABLED,
1295 .index = -1,
1296 .data = &sci_uart_driver,
1297 };
1298
1299 /* Register the KGDB console so we get messages (d'oh!) */
1300 static int __init kgdb_console_init(void)
1301 {
1302 sci_init_ports();
1303 register_console(&kgdb_console);
1304 return 0;
1305 }
1306 console_initcall(kgdb_console_init);
1307 #endif /* CONFIG_SH_KGDB_CONSOLE */
1308
1309 #if defined(CONFIG_SH_KGDB_CONSOLE)
1310 #define SCI_CONSOLE &kgdb_console
1311 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1312 #define SCI_CONSOLE &serial_console
1313 #else
1314 #define SCI_CONSOLE 0
1315 #endif
1316
1317 static char banner[] __initdata =
1318 KERN_INFO "SuperH SCI(F) driver initialized\n";
1319
1320 static struct uart_driver sci_uart_driver = {
1321 .owner = THIS_MODULE,
1322 .driver_name = "sci",
1323 .dev_name = "ttySC",
1324 .major = SCI_MAJOR,
1325 .minor = SCI_MINOR_START,
1326 .nr = SCI_NPORTS,
1327 .cons = SCI_CONSOLE,
1328 };
1329
1330 /*
1331 * Register a set of serial devices attached to a platform device. The
1332 * list is terminated with a zero flags entry, which means we expect
1333 * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need
1334 * remapping (such as sh64) should also set UPF_IOREMAP.
1335 */
1336 static int __devinit sci_probe(struct platform_device *dev)
1337 {
1338 struct plat_sci_port *p = dev->dev.platform_data;
1339 int i;
1340
1341 for (i = 0; p && p->flags != 0 && i < SCI_NPORTS; p++, i++) {
1342 struct sci_port *sciport = &sci_ports[i];
1343
1344 sciport->port.mapbase = p->mapbase;
1345
1346 /*
1347 * For the simple (and majority of) cases where we don't need
1348 * to do any remapping, just cast the cookie directly.
1349 */
1350 if (p->mapbase && !p->membase && !(p->flags & UPF_IOREMAP))
1351 p->membase = (void __iomem *)p->mapbase;
1352
1353 sciport->port.membase = p->membase;
1354
1355 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1356 sciport->port.flags = p->flags;
1357 sciport->port.dev = &dev->dev;
1358
1359 sciport->type = sciport->port.type = p->type;
1360
1361 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1362
1363 uart_add_one_port(&sci_uart_driver, &sciport->port);
1364 }
1365
1366 #ifdef CONFIG_CPU_FREQ
1367 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1368 dev_info(&dev->dev, "sci: CPU frequency notifier registered\n");
1369 #endif
1370
1371 #ifdef CONFIG_SH_STANDARD_BIOS
1372 sh_bios_gdb_detach();
1373 #endif
1374
1375 return 0;
1376 }
1377
1378 static int __devexit sci_remove(struct platform_device *dev)
1379 {
1380 int i;
1381
1382 for (i = 0; i < SCI_NPORTS; i++)
1383 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1384
1385 return 0;
1386 }
1387
1388 static int sci_suspend(struct platform_device *dev, pm_message_t state)
1389 {
1390 int i;
1391
1392 for (i = 0; i < SCI_NPORTS; i++) {
1393 struct sci_port *p = &sci_ports[i];
1394
1395 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1396 uart_suspend_port(&sci_uart_driver, &p->port);
1397 }
1398
1399 return 0;
1400 }
1401
1402 static int sci_resume(struct platform_device *dev)
1403 {
1404 int i;
1405
1406 for (i = 0; i < SCI_NPORTS; i++) {
1407 struct sci_port *p = &sci_ports[i];
1408
1409 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev)
1410 uart_resume_port(&sci_uart_driver, &p->port);
1411 }
1412
1413 return 0;
1414 }
1415
1416 static struct platform_driver sci_driver = {
1417 .probe = sci_probe,
1418 .remove = __devexit_p(sci_remove),
1419 .suspend = sci_suspend,
1420 .resume = sci_resume,
1421 .driver = {
1422 .name = "sh-sci",
1423 .owner = THIS_MODULE,
1424 },
1425 };
1426
1427 static int __init sci_init(void)
1428 {
1429 int ret;
1430
1431 printk(banner);
1432
1433 sci_init_ports();
1434
1435 ret = uart_register_driver(&sci_uart_driver);
1436 if (likely(ret == 0)) {
1437 ret = platform_driver_register(&sci_driver);
1438 if (unlikely(ret))
1439 uart_unregister_driver(&sci_uart_driver);
1440 }
1441
1442 return ret;
1443 }
1444
1445 static void __exit sci_exit(void)
1446 {
1447 platform_driver_unregister(&sci_driver);
1448 uart_unregister_driver(&sci_uart_driver);
1449 }
1450
1451 module_init(sci_init);
1452 module_exit(sci_exit);
1453
1454 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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