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[PATCH] TTY layer buffering revamp
[deliverable/linux.git] / drivers / serial / sh-sci.c
1 /*
2 * drivers/serial/sh-sci.c
3 *
4 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 *
6 * Copyright (C) 2002, 2003, 2004 Paul Mundt
7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20
21 #undef DEBUG
22
23 #include <linux/config.h>
24 #include <linux/module.h>
25 #include <linux/errno.h>
26 #include <linux/signal.h>
27 #include <linux/sched.h>
28 #include <linux/timer.h>
29 #include <linux/interrupt.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial.h>
33 #include <linux/major.h>
34 #include <linux/string.h>
35 #include <linux/sysrq.h>
36 #include <linux/fcntl.h>
37 #include <linux/ptrace.h>
38 #include <linux/ioport.h>
39 #include <linux/mm.h>
40 #include <linux/slab.h>
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/console.h>
44 #include <linux/bitops.h>
45
46 #ifdef CONFIG_CPU_FREQ
47 #include <linux/notifier.h>
48 #include <linux/cpufreq.h>
49 #endif
50
51 #include <asm/system.h>
52 #include <asm/io.h>
53 #include <asm/irq.h>
54 #include <asm/uaccess.h>
55
56 #include <linux/generic_serial.h>
57
58 #ifdef CONFIG_SH_STANDARD_BIOS
59 #include <asm/sh_bios.h>
60 #endif
61
62 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
63 #define SUPPORT_SYSRQ
64 #endif
65
66 #include "sh-sci.h"
67
68 #ifdef CONFIG_SH_KGDB
69 #include <asm/kgdb.h>
70
71 static int kgdb_get_char(struct sci_port *port);
72 static void kgdb_put_char(struct sci_port *port, char c);
73 static void kgdb_handle_error(struct sci_port *port);
74 static struct sci_port *kgdb_sci_port;
75 #endif /* CONFIG_SH_KGDB */
76
77 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
78 static struct sci_port *serial_console_port = 0;
79 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
80
81 /* Function prototypes */
82 static void sci_stop_tx(struct uart_port *port);
83 static void sci_start_tx(struct uart_port *port);
84 static void sci_start_rx(struct uart_port *port, unsigned int tty_start);
85 static void sci_stop_rx(struct uart_port *port);
86 static int sci_request_irq(struct sci_port *port);
87 static void sci_free_irq(struct sci_port *port);
88
89 static struct sci_port sci_ports[SCI_NPORTS];
90 static struct uart_driver sci_uart_driver;
91
92 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
93
94 static void handle_error(struct uart_port *port)
95 { /* Clear error flags */
96 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
97 }
98
99 static int get_char(struct uart_port *port)
100 {
101 unsigned long flags;
102 unsigned short status;
103 int c;
104
105 local_irq_save(flags);
106 do {
107 status = sci_in(port, SCxSR);
108 if (status & SCxSR_ERRORS(port)) {
109 handle_error(port);
110 continue;
111 }
112 } while (!(status & SCxSR_RDxF(port)));
113 c = sci_in(port, SCxRDR);
114 sci_in(port, SCxSR); /* Dummy read */
115 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
116 local_irq_restore(flags);
117
118 return c;
119 }
120
121 /* Taken from sh-stub.c of GDB 4.18 */
122 static const char hexchars[] = "0123456789abcdef";
123
124 static __inline__ char highhex(int x)
125 {
126 return hexchars[(x >> 4) & 0xf];
127 }
128
129 static __inline__ char lowhex(int x)
130 {
131 return hexchars[x & 0xf];
132 }
133
134 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
135
136 /*
137 * Send the packet in buffer. The host gets one chance to read it.
138 * This routine does not wait for a positive acknowledge.
139 */
140
141 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
142 static void put_char(struct uart_port *port, char c)
143 {
144 unsigned long flags;
145 unsigned short status;
146
147 local_irq_save(flags);
148
149 do {
150 status = sci_in(port, SCxSR);
151 } while (!(status & SCxSR_TDxE(port)));
152
153 sci_out(port, SCxTDR, c);
154 sci_in(port, SCxSR); /* Dummy read */
155 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
156
157 local_irq_restore(flags);
158 }
159
160 static void put_string(struct sci_port *sci_port, const char *buffer, int count)
161 {
162 struct uart_port *port = &sci_port->port;
163 const unsigned char *p = buffer;
164 int i;
165
166 #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB)
167 int checksum;
168 int usegdb=0;
169
170 #ifdef CONFIG_SH_STANDARD_BIOS
171 /* This call only does a trap the first time it is
172 * called, and so is safe to do here unconditionally
173 */
174 usegdb |= sh_bios_in_gdb_mode();
175 #endif
176 #ifdef CONFIG_SH_KGDB
177 usegdb |= (kgdb_in_gdb_mode && (port == kgdb_sci_port));
178 #endif
179
180 if (usegdb) {
181 /* $<packet info>#<checksum>. */
182 do {
183 unsigned char c;
184 put_char(port, '$');
185 put_char(port, 'O'); /* 'O'utput to console */
186 checksum = 'O';
187
188 for (i=0; i<count; i++) { /* Don't use run length encoding */
189 int h, l;
190
191 c = *p++;
192 h = highhex(c);
193 l = lowhex(c);
194 put_char(port, h);
195 put_char(port, l);
196 checksum += h + l;
197 }
198 put_char(port, '#');
199 put_char(port, highhex(checksum));
200 put_char(port, lowhex(checksum));
201 } while (get_char(port) != '+');
202 } else
203 #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */
204 for (i=0; i<count; i++) {
205 if (*p == 10)
206 put_char(port, '\r');
207 put_char(port, *p++);
208 }
209 }
210 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
211
212
213 #ifdef CONFIG_SH_KGDB
214
215 /* Is the SCI ready, ie is there a char waiting? */
216 static int kgdb_is_char_ready(struct sci_port *port)
217 {
218 unsigned short status = sci_in(port, SCxSR);
219
220 if (status & (SCxSR_ERRORS(port) | SCxSR_BRK(port)))
221 kgdb_handle_error(port);
222
223 return (status & SCxSR_RDxF(port));
224 }
225
226 /* Write a char */
227 static void kgdb_put_char(struct sci_port *port, char c)
228 {
229 unsigned short status;
230
231 do
232 status = sci_in(port, SCxSR);
233 while (!(status & SCxSR_TDxE(port)));
234
235 sci_out(port, SCxTDR, c);
236 sci_in(port, SCxSR); /* Dummy read */
237 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
238 }
239
240 /* Get a char if there is one, else ret -1 */
241 static int kgdb_get_char(struct sci_port *port)
242 {
243 int c;
244
245 if (kgdb_is_char_ready(port) == 0)
246 c = -1;
247 else {
248 c = sci_in(port, SCxRDR);
249 sci_in(port, SCxSR); /* Dummy read */
250 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
251 }
252
253 return c;
254 }
255
256 /* Called from kgdbstub.c to get a character, i.e. is blocking */
257 static int kgdb_sci_getchar(void)
258 {
259 volatile int c;
260
261 /* Keep trying to read a character, this could be neater */
262 while ((c = kgdb_get_char(kgdb_sci_port)) < 0);
263
264 return c;
265 }
266
267 /* Called from kgdbstub.c to put a character, just a wrapper */
268 static void kgdb_sci_putchar(int c)
269 {
270
271 kgdb_put_char(kgdb_sci_port, c);
272 }
273
274 /* Clear any errors on the SCI */
275 static void kgdb_handle_error(struct sci_port *port)
276 {
277 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); /* Clear error flags */
278 }
279
280 /* Breakpoint if there's a break sent on the serial port */
281 static void kgdb_break_interrupt(int irq, void *ptr, struct pt_regs *regs)
282 {
283 struct sci_port *port = ptr;
284 unsigned short status = sci_in(port, SCxSR);
285
286 if (status & SCxSR_BRK(port)) {
287
288 /* Break into the debugger if a break is detected */
289 BREAKPOINT();
290
291 /* Clear */
292 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
293 }
294 }
295
296 #endif /* CONFIG_SH_KGDB */
297
298 #if defined(__H8300S__)
299 enum { sci_disable, sci_enable };
300
301 static void h8300_sci_enable(struct uart_port* port, unsigned int ctrl)
302 {
303 volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL;
304 int ch = (port->mapbase - SMR0) >> 3;
305 unsigned char mask = 1 << (ch+1);
306
307 if (ctrl == sci_disable) {
308 *mstpcrl |= mask;
309 } else {
310 *mstpcrl &= ~mask;
311 }
312 }
313 #endif
314
315 #if defined(SCI_ONLY) || defined(SCI_AND_SCIF)
316 #if defined(__H8300H__) || defined(__H8300S__)
317 static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag)
318 {
319 int ch = (port->mapbase - SMR0) >> 3;
320
321 /* set DDR regs */
322 H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].rx,H8300_GPIO_INPUT);
323 H8300_GPIO_DDR(h8300_sci_pins[ch].port,h8300_sci_pins[ch].tx,H8300_GPIO_OUTPUT);
324 /* tx mark output*/
325 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
326 }
327 #else
328 static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
329 {
330 }
331 #endif
332 #endif
333
334 #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF)
335 #if defined(CONFIG_CPU_SH3)
336 /* For SH7705, SH7707, SH7709, SH7709A, SH7729, SH7300*/
337 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
338 {
339 unsigned int fcr_val = 0;
340 #if !defined(CONFIG_CPU_SUBTYPE_SH7300) /* SH7300 doesn't use RTS/CTS */
341 {
342 unsigned short data;
343
344 /* We need to set SCPCR to enable RTS/CTS */
345 data = ctrl_inw(SCPCR);
346 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
347 ctrl_outw(data&0x0fcf, SCPCR);
348 }
349 if (cflag & CRTSCTS)
350 fcr_val |= SCFCR_MCE;
351 else {
352 unsigned short data;
353
354 /* We need to set SCPCR to enable RTS/CTS */
355 data = ctrl_inw(SCPCR);
356 /* Clear out SCP7MD1,0, SCP4MD1,0,
357 Set SCP6MD1,0 = {01} (output) */
358 ctrl_outw((data&0x0fcf)|0x1000, SCPCR);
359
360 data = ctrl_inb(SCPDR);
361 /* Set /RTS2 (bit6) = 0 */
362 ctrl_outb(data&0xbf, SCPDR);
363 }
364 #endif
365 sci_out(port, SCFCR, fcr_val);
366 }
367
368 static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
369 {
370 unsigned int fcr_val = 0;
371
372 if (cflag & CRTSCTS)
373 fcr_val |= SCFCR_MCE;
374
375 sci_out(port, SCFCR, fcr_val);
376 }
377
378 #else
379
380 /* For SH7750 */
381 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
382 {
383 unsigned int fcr_val = 0;
384
385 if (cflag & CRTSCTS) {
386 fcr_val |= SCFCR_MCE;
387 } else {
388 ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
389 }
390 sci_out(port, SCFCR, fcr_val);
391 }
392
393 #endif
394 #endif /* SCIF_ONLY || SCI_AND_SCIF */
395
396 /* ********************************************************************** *
397 * the interrupt related routines *
398 * ********************************************************************** */
399
400 static void sci_transmit_chars(struct uart_port *port)
401 {
402 struct circ_buf *xmit = &port->info->xmit;
403 unsigned int stopped = uart_tx_stopped(port);
404 unsigned long flags;
405 unsigned short status;
406 unsigned short ctrl;
407 int count, txroom;
408
409 status = sci_in(port, SCxSR);
410 if (!(status & SCxSR_TDxE(port))) {
411 local_irq_save(flags);
412 ctrl = sci_in(port, SCSCR);
413 if (uart_circ_empty(xmit)) {
414 ctrl &= ~SCI_CTRL_FLAGS_TIE;
415 } else {
416 ctrl |= SCI_CTRL_FLAGS_TIE;
417 }
418 sci_out(port, SCSCR, ctrl);
419 local_irq_restore(flags);
420 return;
421 }
422
423 #if !defined(SCI_ONLY)
424 if (port->type == PORT_SCIF) {
425 txroom = SCIF_TXROOM_MAX - (sci_in(port, SCFDR)>>8);
426 } else {
427 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
428 }
429 #else
430 txroom = (sci_in(port, SCxSR) & SCI_TDRE)?1:0;
431 #endif
432
433 count = txroom;
434
435 do {
436 unsigned char c;
437
438 if (port->x_char) {
439 c = port->x_char;
440 port->x_char = 0;
441 } else if (!uart_circ_empty(xmit) && !stopped) {
442 c = xmit->buf[xmit->tail];
443 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
444 } else {
445 break;
446 }
447
448 sci_out(port, SCxTDR, c);
449
450 port->icount.tx++;
451 } while (--count > 0);
452
453 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
454
455 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
456 uart_write_wakeup(port);
457 if (uart_circ_empty(xmit)) {
458 sci_stop_tx(port);
459 } else {
460 local_irq_save(flags);
461 ctrl = sci_in(port, SCSCR);
462
463 #if !defined(SCI_ONLY)
464 if (port->type == PORT_SCIF) {
465 sci_in(port, SCxSR); /* Dummy read */
466 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
467 }
468 #endif
469
470 ctrl |= SCI_CTRL_FLAGS_TIE;
471 sci_out(port, SCSCR, ctrl);
472 local_irq_restore(flags);
473 }
474 }
475
476 /* On SH3, SCIF may read end-of-break as a space->mark char */
477 #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); })
478
479 static inline void sci_receive_chars(struct uart_port *port,
480 struct pt_regs *regs)
481 {
482 struct tty_struct *tty = port->info->tty;
483 int i, count, copied = 0;
484 unsigned short status;
485 unsigned char flag;
486
487 status = sci_in(port, SCxSR);
488 if (!(status & SCxSR_RDxF(port)))
489 return;
490
491 while (1) {
492 #if !defined(SCI_ONLY)
493 if (port->type == PORT_SCIF) {
494 count = sci_in(port, SCFDR)&SCIF_RFDC_MASK ;
495 } else {
496 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
497 }
498 #else
499 count = (sci_in(port, SCxSR)&SCxSR_RDxF(port))?1:0;
500 #endif
501
502 /* Don't copy more bytes than there is room for in the buffer */
503 count = tty_buffer_request_room(tty, count);
504
505 /* If for any reason we can't copy more data, we're done! */
506 if (count == 0)
507 break;
508
509 if (port->type == PORT_SCI) {
510 char c = sci_in(port, SCxRDR);
511 if(((struct sci_port *)port)->break_flag
512 || uart_handle_sysrq_char(port, c, regs)) {
513 count = 0;
514 } else {
515 tty_insert_flip_char(tty, c, TTY_NORMAL);
516 }
517 } else {
518 for (i=0; i<count; i++) {
519 char c = sci_in(port, SCxRDR);
520 status = sci_in(port, SCxSR);
521 #if defined(CONFIG_CPU_SH3)
522 /* Skip "chars" during break */
523 if (((struct sci_port *)port)->break_flag) {
524 if ((c == 0) &&
525 (status & SCxSR_FER(port))) {
526 count--; i--;
527 continue;
528 }
529 /* Nonzero => end-of-break */
530 pr_debug("scif: debounce<%02x>\n", c);
531 ((struct sci_port *)port)->break_flag = 0;
532 if (STEPFN(c)) {
533 count--; i--;
534 continue;
535 }
536 }
537 #endif /* CONFIG_CPU_SH3 */
538 if (uart_handle_sysrq_char(port, c, regs)) {
539 count--; i--;
540 continue;
541 }
542
543 /* Store data and status */
544 if (status&SCxSR_FER(port)) {
545 flag = TTY_FRAME;
546 pr_debug("sci: frame error\n");
547 } else if (status&SCxSR_PER(port)) {
548 flag = TTY_PARITY;
549 pr_debug("sci: parity error\n");
550 } else
551 flag = TTY_NORMAL;
552 tty_insert_flip_char(tty, c, flag);
553 }
554 }
555
556 sci_in(port, SCxSR); /* dummy read */
557 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
558
559 copied += count;
560 port->icount.rx += count;
561 }
562
563 if (copied) {
564 /* Tell the rest of the system the news. New characters! */
565 tty_flip_buffer_push(tty);
566 } else {
567 sci_in(port, SCxSR); /* dummy read */
568 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
569 }
570 }
571
572 #define SCI_BREAK_JIFFIES (HZ/20)
573 /* The sci generates interrupts during the break,
574 * 1 per millisecond or so during the break period, for 9600 baud.
575 * So dont bother disabling interrupts.
576 * But dont want more than 1 break event.
577 * Use a kernel timer to periodically poll the rx line until
578 * the break is finished.
579 */
580 static void sci_schedule_break_timer(struct sci_port *port)
581 {
582 port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES;
583 add_timer(&port->break_timer);
584 }
585 /* Ensure that two consecutive samples find the break over. */
586 static void sci_break_timer(unsigned long data)
587 {
588 struct sci_port * port = (struct sci_port *)data;
589 if(sci_rxd_in(&port->port) == 0) {
590 port->break_flag = 1;
591 sci_schedule_break_timer(port);
592 } else if(port->break_flag == 1){
593 /* break is over. */
594 port->break_flag = 2;
595 sci_schedule_break_timer(port);
596 } else port->break_flag = 0;
597 }
598
599 static inline int sci_handle_errors(struct uart_port *port)
600 {
601 int copied = 0;
602 unsigned short status = sci_in(port, SCxSR);
603 struct tty_struct *tty = port->info->tty;
604
605 if (status&SCxSR_ORER(port)) {
606 /* overrun error */
607 if(tty_insert_flip_char(tty, 0, TTY_OVERRUN))
608 copied++;
609 pr_debug("sci: overrun error\n");
610 }
611
612 if (status&SCxSR_FER(port)) {
613 if (sci_rxd_in(port) == 0) {
614 /* Notify of BREAK */
615 struct sci_port * sci_port = (struct sci_port *)port;
616 if(!sci_port->break_flag) {
617 sci_port->break_flag = 1;
618 sci_schedule_break_timer((struct sci_port *)port);
619 /* Do sysrq handling. */
620 if(uart_handle_break(port))
621 return 0;
622 pr_debug("sci: BREAK detected\n");
623 if(tty_insert_flip_char(tty, 0, TTY_BREAK))
624 copied++;
625 }
626 }
627 else {
628 /* frame error */
629 if(tty_insert_flip_char(tty, 0, TTY_FRAME))
630 copied++;
631 pr_debug("sci: frame error\n");
632 }
633 }
634
635 if (status&SCxSR_PER(port)) {
636 if(tty_insert_flip_char(tty, 0, TTY_PARITY))
637 copied++;
638 /* parity error */
639 pr_debug("sci: parity error\n");
640 }
641
642 if (copied)
643 tty_flip_buffer_push(tty);
644
645 return copied;
646 }
647
648 static inline int sci_handle_breaks(struct uart_port *port)
649 {
650 int copied = 0;
651 unsigned short status = sci_in(port, SCxSR);
652 struct tty_struct *tty = port->info->tty;
653 struct sci_port *s = &sci_ports[port->line];
654
655 if (!s->break_flag && status & SCxSR_BRK(port))
656 #if defined(CONFIG_CPU_SH3)
657 /* Debounce break */
658 s->break_flag = 1;
659 #endif
660 /* Notify of BREAK */
661 if(tty_insert_flip_char(tty, 0, TTY_BREAK))
662 copied++;
663 pr_debug("sci: BREAK detected\n");
664 }
665
666 #if defined(SCIF_ORER)
667 /* XXX: Handle SCIF overrun error */
668 if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) {
669 sci_out(port, SCLSR, 0);
670 if(tty_insert_flip_char(tty, 0, TTY_OVERRUN)) {
671 copied++;
672 pr_debug("sci: overrun error\n");
673 }
674 }
675 #endif
676
677 if (copied)
678 tty_flip_buffer_push(tty);
679 return copied;
680 }
681
682 static irqreturn_t sci_rx_interrupt(int irq, void *ptr, struct pt_regs *regs)
683 {
684 struct uart_port *port = ptr;
685
686 /* I think sci_receive_chars has to be called irrespective
687 * of whether the I_IXOFF is set, otherwise, how is the interrupt
688 * to be disabled?
689 */
690 sci_receive_chars(port, regs);
691
692 return IRQ_HANDLED;
693 }
694
695 static irqreturn_t sci_tx_interrupt(int irq, void *ptr, struct pt_regs *regs)
696 {
697 struct uart_port *port = ptr;
698
699 sci_transmit_chars(port);
700
701 return IRQ_HANDLED;
702 }
703
704 static irqreturn_t sci_er_interrupt(int irq, void *ptr, struct pt_regs *regs)
705 {
706 struct uart_port *port = ptr;
707
708 /* Handle errors */
709 if (port->type == PORT_SCI) {
710 if (sci_handle_errors(port)) {
711 /* discard character in rx buffer */
712 sci_in(port, SCxSR);
713 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
714 }
715 } else {
716 #if defined(SCIF_ORER)
717 if((sci_in(port, SCLSR) & SCIF_ORER) != 0) {
718 struct tty_struct *tty = port->info->tty;
719
720 sci_out(port, SCLSR, 0);
721 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
722 tty_flip_buffer_push(tty);
723 pr_debug("scif: overrun error\n");
724 }
725 #endif
726 sci_rx_interrupt(irq, ptr, regs);
727 }
728
729 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
730
731 /* Kick the transmission */
732 sci_tx_interrupt(irq, ptr, regs);
733
734 return IRQ_HANDLED;
735 }
736
737 static irqreturn_t sci_br_interrupt(int irq, void *ptr, struct pt_regs *regs)
738 {
739 struct uart_port *port = ptr;
740
741 /* Handle BREAKs */
742 sci_handle_breaks(port);
743 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
744
745 return IRQ_HANDLED;
746 }
747
748 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr, struct pt_regs *regs)
749 {
750 unsigned short ssr_status, scr_status;
751 struct uart_port *port = ptr;
752
753 ssr_status = sci_in(port,SCxSR);
754 scr_status = sci_in(port,SCSCR);
755
756 /* Tx Interrupt */
757 if ((ssr_status&0x0020) && (scr_status&0x0080))
758 sci_tx_interrupt(irq, ptr, regs);
759 /* Rx Interrupt */
760 if ((ssr_status&0x0002) && (scr_status&0x0040))
761 sci_rx_interrupt(irq, ptr, regs);
762 /* Error Interrupt */
763 if ((ssr_status&0x0080) && (scr_status&0x0400))
764 sci_er_interrupt(irq, ptr, regs);
765 /* Break Interrupt */
766 if ((ssr_status&0x0010) && (scr_status&0x0200))
767 sci_br_interrupt(irq, ptr, regs);
768
769 return IRQ_HANDLED;
770 }
771
772 #ifdef CONFIG_CPU_FREQ
773 /*
774 * Here we define a transistion notifier so that we can update all of our
775 * ports' baud rate when the peripheral clock changes.
776 */
777 static int sci_notifier(struct notifier_block *self, unsigned long phase, void *p)
778 {
779 struct cpufreq_freqs *freqs = p;
780 int i;
781
782 if ((phase == CPUFREQ_POSTCHANGE) ||
783 (phase == CPUFREQ_RESUMECHANGE)){
784 for (i = 0; i < SCI_NPORTS; i++) {
785 struct uart_port *port = &sci_ports[i].port;
786
787 /*
788 * Update the uartclk per-port if frequency has
789 * changed, since it will no longer necessarily be
790 * consistent with the old frequency.
791 *
792 * Really we want to be able to do something like
793 * uart_change_speed() or something along those lines
794 * here to implicitly reset the per-port baud rate..
795 *
796 * Clean this up later..
797 */
798 port->uartclk = current_cpu_data.module_clock * 16;
799 }
800
801 printk("%s: got a postchange notification for cpu %d (old %d, new %d)\n",
802 __FUNCTION__, freqs->cpu, freqs->old, freqs->new);
803 }
804
805 return NOTIFY_OK;
806 }
807
808 static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 };
809 #endif /* CONFIG_CPU_FREQ */
810
811 static int sci_request_irq(struct sci_port *port)
812 {
813 int i;
814 irqreturn_t (*handlers[4])(int irq, void *ptr, struct pt_regs *regs) = {
815 sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt,
816 sci_br_interrupt,
817 };
818 const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full",
819 "SCI Transmit Data Empty", "SCI Break" };
820
821 if (port->irqs[0] == port->irqs[1]) {
822 if (!port->irqs[0]) {
823 printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n");
824 return -ENODEV;
825 }
826 if (request_irq(port->irqs[0], sci_mpxed_interrupt, SA_INTERRUPT,
827 "sci", port)) {
828 printk(KERN_ERR "sci: Cannot allocate irq.\n");
829 return -ENODEV;
830 }
831 } else {
832 for (i = 0; i < ARRAY_SIZE(handlers); i++) {
833 if (!port->irqs[i])
834 continue;
835 if (request_irq(port->irqs[i], handlers[i], SA_INTERRUPT,
836 desc[i], port)) {
837 printk(KERN_ERR "sci: Cannot allocate irq.\n");
838 return -ENODEV;
839 }
840 }
841 }
842
843 return 0;
844 }
845
846 static void sci_free_irq(struct sci_port *port)
847 {
848 int i;
849
850 if (port->irqs[0] == port->irqs[1]) {
851 if (!port->irqs[0])
852 printk("sci: sci_free_irq error\n");
853 else
854 free_irq(port->irqs[0], port);
855 } else {
856 for (i = 0; i < ARRAY_SIZE(port->irqs); i++) {
857 if (!port->irqs[i])
858 continue;
859
860 free_irq(port->irqs[i], port);
861 }
862 }
863 }
864
865 static unsigned int sci_tx_empty(struct uart_port *port)
866 {
867 /* Can't detect */
868 return TIOCSER_TEMT;
869 }
870
871 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
872 {
873 /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */
874 /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */
875 /* If you have signals for DTR and DCD, please implement here. */
876 }
877
878 static unsigned int sci_get_mctrl(struct uart_port *port)
879 {
880 /* This routine is used for geting signals of: DTR, DCD, DSR, RI,
881 and CTS/RTS */
882
883 return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
884 }
885
886 static void sci_start_tx(struct uart_port *port)
887 {
888 struct sci_port *s = &sci_ports[port->line];
889
890 disable_irq(s->irqs[SCIx_TXI_IRQ]);
891 sci_transmit_chars(port);
892 enable_irq(s->irqs[SCIx_TXI_IRQ]);
893 }
894
895 static void sci_stop_tx(struct uart_port *port)
896 {
897 unsigned long flags;
898 unsigned short ctrl;
899
900 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
901 local_irq_save(flags);
902 ctrl = sci_in(port, SCSCR);
903 ctrl &= ~SCI_CTRL_FLAGS_TIE;
904 sci_out(port, SCSCR, ctrl);
905 local_irq_restore(flags);
906 }
907
908 static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
909 {
910 unsigned long flags;
911 unsigned short ctrl;
912
913 /* Set RIE (Receive Interrupt Enable) bit in SCSCR */
914 local_irq_save(flags);
915 ctrl = sci_in(port, SCSCR);
916 ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
917 sci_out(port, SCSCR, ctrl);
918 local_irq_restore(flags);
919 }
920
921 static void sci_stop_rx(struct uart_port *port)
922 {
923 unsigned long flags;
924 unsigned short ctrl;
925
926 /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */
927 local_irq_save(flags);
928 ctrl = sci_in(port, SCSCR);
929 ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE);
930 sci_out(port, SCSCR, ctrl);
931 local_irq_restore(flags);
932 }
933
934 static void sci_enable_ms(struct uart_port *port)
935 {
936 /* Nothing here yet .. */
937 }
938
939 static void sci_break_ctl(struct uart_port *port, int break_state)
940 {
941 /* Nothing here yet .. */
942 }
943
944 static int sci_startup(struct uart_port *port)
945 {
946 struct sci_port *s = &sci_ports[port->line];
947
948 #if defined(__H8300S__)
949 h8300_sci_enable(port, sci_enable);
950 #endif
951
952 sci_request_irq(s);
953 sci_start_tx(port);
954 sci_start_rx(port, 1);
955
956 return 0;
957 }
958
959 static void sci_shutdown(struct uart_port *port)
960 {
961 struct sci_port *s = &sci_ports[port->line];
962
963 sci_stop_rx(port);
964 sci_stop_tx(port);
965 sci_free_irq(s);
966
967 #if defined(__H8300S__)
968 h8300_sci_enable(port, sci_disable);
969 #endif
970 }
971
972 static void sci_set_termios(struct uart_port *port, struct termios *termios,
973 struct termios *old)
974 {
975 struct sci_port *s = &sci_ports[port->line];
976 unsigned int status, baud, smr_val;
977 unsigned long flags;
978 int t;
979
980 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
981
982 spin_lock_irqsave(&port->lock, flags);
983
984 do {
985 status = sci_in(port, SCxSR);
986 } while (!(status & SCxSR_TEND(port)));
987
988 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
989
990 #if !defined(SCI_ONLY)
991 if (port->type == PORT_SCIF) {
992 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
993 }
994 #endif
995
996 smr_val = sci_in(port, SCSMR) & 3;
997 if ((termios->c_cflag & CSIZE) == CS7)
998 smr_val |= 0x40;
999 if (termios->c_cflag & PARENB)
1000 smr_val |= 0x20;
1001 if (termios->c_cflag & PARODD)
1002 smr_val |= 0x30;
1003 if (termios->c_cflag & CSTOPB)
1004 smr_val |= 0x08;
1005
1006 uart_update_timeout(port, termios->c_cflag, baud);
1007
1008 sci_out(port, SCSMR, smr_val);
1009
1010 switch (baud) {
1011 case 0: t = -1; break;
1012 case 2400: t = BPS_2400; break;
1013 case 4800: t = BPS_4800; break;
1014 case 9600: t = BPS_9600; break;
1015 case 19200: t = BPS_19200; break;
1016 case 38400: t = BPS_38400; break;
1017 case 57600: t = BPS_57600; break;
1018 case 115200: t = BPS_115200; break;
1019 default: t = SCBRR_VALUE(baud); break;
1020 }
1021
1022 if (t > 0) {
1023 if(t >= 256) {
1024 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1025 t >>= 2;
1026 } else {
1027 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
1028 }
1029 sci_out(port, SCBRR, t);
1030 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1031 }
1032
1033 s->init_pins(port, termios->c_cflag);
1034 sci_out(port, SCSCR, SCSCR_INIT(port));
1035
1036 if ((termios->c_cflag & CREAD) != 0)
1037 sci_start_rx(port,0);
1038
1039 spin_unlock_irqrestore(&port->lock, flags);
1040 }
1041
1042 static const char *sci_type(struct uart_port *port)
1043 {
1044 switch (port->type) {
1045 case PORT_SCI: return "sci";
1046 case PORT_SCIF: return "scif";
1047 case PORT_IRDA: return "irda";
1048 }
1049
1050 return 0;
1051 }
1052
1053 static void sci_release_port(struct uart_port *port)
1054 {
1055 /* Nothing here yet .. */
1056 }
1057
1058 static int sci_request_port(struct uart_port *port)
1059 {
1060 /* Nothing here yet .. */
1061 return 0;
1062 }
1063
1064 static void sci_config_port(struct uart_port *port, int flags)
1065 {
1066 struct sci_port *s = &sci_ports[port->line];
1067
1068 port->type = s->type;
1069
1070 #if defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1071 if (port->mapbase == 0)
1072 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
1073
1074 port->membase = (void *)port->mapbase;
1075 #endif
1076 }
1077
1078 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1079 {
1080 struct sci_port *s = &sci_ports[port->line];
1081
1082 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS)
1083 return -EINVAL;
1084 if (ser->baud_base < 2400)
1085 /* No paper tape reader for Mitch.. */
1086 return -EINVAL;
1087
1088 return 0;
1089 }
1090
1091 static struct uart_ops sci_uart_ops = {
1092 .tx_empty = sci_tx_empty,
1093 .set_mctrl = sci_set_mctrl,
1094 .get_mctrl = sci_get_mctrl,
1095 .start_tx = sci_start_tx,
1096 .stop_tx = sci_stop_tx,
1097 .stop_rx = sci_stop_rx,
1098 .enable_ms = sci_enable_ms,
1099 .break_ctl = sci_break_ctl,
1100 .startup = sci_startup,
1101 .shutdown = sci_shutdown,
1102 .set_termios = sci_set_termios,
1103 .type = sci_type,
1104 .release_port = sci_release_port,
1105 .request_port = sci_request_port,
1106 .config_port = sci_config_port,
1107 .verify_port = sci_verify_port,
1108 };
1109
1110 static struct sci_port sci_ports[SCI_NPORTS] = {
1111 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
1112 {
1113 .port = {
1114 .membase = (void *)0xfffffe80,
1115 .mapbase = 0xfffffe80,
1116 .iotype = SERIAL_IO_MEM,
1117 .irq = 25,
1118 .ops = &sci_uart_ops,
1119 .flags = ASYNC_BOOT_AUTOCONF,
1120 .line = 0,
1121 },
1122 .type = PORT_SCI,
1123 .irqs = SCI_IRQS,
1124 .init_pins = sci_init_pins_sci,
1125 },
1126 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
1127 {
1128 .port = {
1129 .membase = (void *)SCIF0,
1130 .mapbase = SCIF0,
1131 .iotype = SERIAL_IO_MEM,
1132 .irq = 55,
1133 .ops = &sci_uart_ops,
1134 .flags = ASYNC_BOOT_AUTOCONF,
1135 .line = 0,
1136 },
1137 .type = PORT_SCIF,
1138 .irqs = SH3_IRDA_IRQS,
1139 .init_pins = sci_init_pins_scif,
1140 },
1141 {
1142 .port = {
1143 .membase = (void *)SCIF2,
1144 .mapbase = SCIF2,
1145 .iotype = SERIAL_IO_MEM,
1146 .irq = 59,
1147 .ops = &sci_uart_ops,
1148 .flags = ASYNC_BOOT_AUTOCONF,
1149 .line = 1,
1150 },
1151 .type = PORT_SCIF,
1152 .irqs = SH3_SCIF_IRQS,
1153 .init_pins = sci_init_pins_scif,
1154 }
1155 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
1156 {
1157 .port = {
1158 .membase = (void *)0xfffffe80,
1159 .mapbase = 0xfffffe80,
1160 .iotype = SERIAL_IO_MEM,
1161 .irq = 25,
1162 .ops = &sci_uart_ops,
1163 .flags = ASYNC_BOOT_AUTOCONF,
1164 .line = 0,
1165 },
1166 .type = PORT_SCI,
1167 .irqs = SCI_IRQS,
1168 .init_pins = sci_init_pins_sci,
1169 },
1170 {
1171 .port = {
1172 .membase = (void *)0xa4000150,
1173 .mapbase = 0xa4000150,
1174 .iotype = SERIAL_IO_MEM,
1175 .irq = 59,
1176 .ops = &sci_uart_ops,
1177 .flags = ASYNC_BOOT_AUTOCONF,
1178 .line = 1,
1179 },
1180 .type = PORT_SCIF,
1181 .irqs = SH3_SCIF_IRQS,
1182 .init_pins = sci_init_pins_scif,
1183 },
1184 {
1185 .port = {
1186 .membase = (void *)0xa4000140,
1187 .mapbase = 0xa4000140,
1188 .iotype = SERIAL_IO_MEM,
1189 .irq = 55,
1190 .ops = &sci_uart_ops,
1191 .flags = ASYNC_BOOT_AUTOCONF,
1192 .line = 2,
1193 },
1194 .type = PORT_IRDA,
1195 .irqs = SH3_IRDA_IRQS,
1196 .init_pins = sci_init_pins_irda,
1197 }
1198 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
1199 {
1200 .port = {
1201 .membase = (void *)0xA4430000,
1202 .mapbase = 0xA4430000,
1203 .iotype = SERIAL_IO_MEM,
1204 .irq = 25,
1205 .ops = &sci_uart_ops,
1206 .flags = ASYNC_BOOT_AUTOCONF,
1207 .line = 0,
1208 },
1209 .type = PORT_SCIF,
1210 .irqs = SH7300_SCIF0_IRQS,
1211 .init_pins = sci_init_pins_scif,
1212 },
1213 #elif defined(CONFIG_CPU_SUBTYPE_SH73180)
1214 {
1215 .port = {
1216 .membase = (void *)0xffe00000,
1217 .mapbase = 0xffe00000,
1218 .iotype = SERIAL_IO_MEM,
1219 .irq = 25,
1220 .ops = &sci_uart_ops,
1221 .flags = ASYNC_BOOT_AUTOCONF,
1222 .line = 0,
1223 },
1224 .type = PORT_SCIF,
1225 .irqs = SH73180_SCIF_IRQS,
1226 .init_pins = sci_init_pins_scif,
1227 },
1228 #elif defined(CONFIG_SH_RTS7751R2D)
1229 {
1230 .port = {
1231 .membase = (void *)0xffe80000,
1232 .mapbase = 0xffe80000,
1233 .iotype = SERIAL_IO_MEM,
1234 .irq = 43,
1235 .ops = &sci_uart_ops,
1236 .flags = ASYNC_BOOT_AUTOCONF,
1237 .line = 0,
1238 },
1239 .type = PORT_SCIF,
1240 .irqs = SH4_SCIF_IRQS,
1241 .init_pins = sci_init_pins_scif,
1242 },
1243 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
1244 {
1245 .port = {
1246 .membase = (void *)0xffe00000,
1247 .mapbase = 0xffe00000,
1248 .iotype = SERIAL_IO_MEM,
1249 .irq = 25,
1250 .ops = &sci_uart_ops,
1251 .flags = ASYNC_BOOT_AUTOCONF,
1252 .line = 0,
1253 },
1254 .type = PORT_SCI,
1255 .irqs = SCI_IRQS,
1256 .init_pins = sci_init_pins_sci,
1257 },
1258 {
1259 .port = {
1260 .membase = (void *)0xffe80000,
1261 .mapbase = 0xffe80000,
1262 .iotype = SERIAL_IO_MEM,
1263 .irq = 43,
1264 .ops = &sci_uart_ops,
1265 .flags = ASYNC_BOOT_AUTOCONF,
1266 .line = 1,
1267 },
1268 .type = PORT_SCIF,
1269 .irqs = SH4_SCIF_IRQS,
1270 .init_pins = sci_init_pins_scif,
1271 },
1272 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
1273 {
1274 .port = {
1275 .membase = (void *)0xfe600000,
1276 .mapbase = 0xfe600000,
1277 .iotype = SERIAL_IO_MEM,
1278 .irq = 55,
1279 .ops = &sci_uart_ops,
1280 .flags = ASYNC_BOOT_AUTOCONF,
1281 .line = 0,
1282 },
1283 .type = PORT_SCIF,
1284 .irqs = SH7760_SCIF0_IRQS,
1285 .init_pins = sci_init_pins_scif,
1286 },
1287 {
1288 .port = {
1289 .membase = (void *)0xfe610000,
1290 .mapbase = 0xfe610000,
1291 .iotype = SERIAL_IO_MEM,
1292 .irq = 75,
1293 .ops = &sci_uart_ops,
1294 .flags = ASYNC_BOOT_AUTOCONF,
1295 .line = 1,
1296 },
1297 .type = PORT_SCIF,
1298 .irqs = SH7760_SCIF1_IRQS,
1299 .init_pins = sci_init_pins_scif,
1300 },
1301 {
1302 .port = {
1303 .membase = (void *)0xfe620000,
1304 .mapbase = 0xfe620000,
1305 .iotype = SERIAL_IO_MEM,
1306 .irq = 79,
1307 .ops = &sci_uart_ops,
1308 .flags = ASYNC_BOOT_AUTOCONF,
1309 .line = 2,
1310 },
1311 .type = PORT_SCIF,
1312 .irqs = SH7760_SCIF2_IRQS,
1313 .init_pins = sci_init_pins_scif,
1314 },
1315 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1316 {
1317 .port = {
1318 .membase = (void *)0xffe80000,
1319 .mapbase = 0xffe80000,
1320 .iotype = SERIAL_IO_MEM,
1321 .irq = 43,
1322 .ops = &sci_uart_ops,
1323 .flags = ASYNC_BOOT_AUTOCONF,
1324 .line = 0,
1325 },
1326 .type = PORT_SCIF,
1327 .irqs = SH4_SCIF_IRQS,
1328 .init_pins = sci_init_pins_scif,
1329 },
1330 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
1331 {
1332 .port = {
1333 .membase = (void *)0xffe00000,
1334 .mapbase = 0xffe00000,
1335 .iotype = SERIAL_IO_MEM,
1336 .irq = 26,
1337 .ops = &sci_uart_ops,
1338 .flags = ASYNC_BOOT_AUTOCONF,
1339 .line = 0,
1340 },
1341 .type = PORT_SCIF,
1342 .irqs = STB1_SCIF1_IRQS,
1343 .init_pins = sci_init_pins_scif,
1344 },
1345 {
1346 .port = {
1347 .membase = (void *)0xffe80000,
1348 .mapbase = 0xffe80000,
1349 .iotype = SERIAL_IO_MEM,
1350 .irq = 43,
1351 .ops = &sci_uart_ops,
1352 .flags = ASYNC_BOOT_AUTOCONF,
1353 .line = 1,
1354 },
1355 .type = PORT_SCIF,
1356 .irqs = SH4_SCIF_IRQS,
1357 .init_pins = sci_init_pins_scif,
1358 },
1359 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1360 {
1361 .port = {
1362 .iotype = SERIAL_IO_MEM,
1363 .irq = 42,
1364 .ops = &sci_uart_ops,
1365 .flags = ASYNC_BOOT_AUTOCONF,
1366 .line = 0,
1367 },
1368 .type = PORT_SCIF,
1369 .irqs = SH5_SCIF_IRQS,
1370 .init_pins = sci_init_pins_scif,
1371 },
1372 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1373 {
1374 .port = {
1375 .membase = (void *)0x00ffffb0,
1376 .mapbase = 0x00ffffb0,
1377 .iotype = SERIAL_IO_MEM,
1378 .irq = 54,
1379 .ops = &sci_uart_ops,
1380 .flags = ASYNC_BOOT_AUTOCONF,
1381 .line = 0,
1382 },
1383 .type = PORT_SCI,
1384 .irqs = H8300H_SCI_IRQS0,
1385 .init_pins = sci_init_pins_sci,
1386 },
1387 {
1388 .port = {
1389 .membase = (void *)0x00ffffb8,
1390 .mapbase = 0x00ffffb8,
1391 .iotype = SERIAL_IO_MEM,
1392 .irq = 58,
1393 .ops = &sci_uart_ops,
1394 .flags = ASYNC_BOOT_AUTOCONF,
1395 .line = 1,
1396 },
1397 .type = PORT_SCI,
1398 .irqs = H8300H_SCI_IRQS1,
1399 .init_pins = sci_init_pins_sci,
1400 },
1401 {
1402 .port = {
1403 .membase = (void *)0x00ffffc0,
1404 .mapbase = 0x00ffffc0,
1405 .iotype = SERIAL_IO_MEM,
1406 .irq = 62,
1407 .ops = &sci_uart_ops,
1408 .flags = ASYNC_BOOT_AUTOCONF,
1409 .line = 2,
1410 },
1411 .type = PORT_SCI,
1412 .irqs = H8300H_SCI_IRQS2,
1413 .init_pins = sci_init_pins_sci,
1414 },
1415 #elif defined(CONFIG_H8S2678)
1416 {
1417 .port = {
1418 .membase = (void *)0x00ffff78,
1419 .mapbase = 0x00ffff78,
1420 .iotype = SERIAL_IO_MEM,
1421 .irq = 90,
1422 .ops = &sci_uart_ops,
1423 .flags = ASYNC_BOOT_AUTOCONF,
1424 .line = 0,
1425 },
1426 .type = PORT_SCI,
1427 .irqs = H8S_SCI_IRQS0,
1428 .init_pins = sci_init_pins_sci,
1429 },
1430 {
1431 .port = {
1432 .membase = (void *)0x00ffff80,
1433 .mapbase = 0x00ffff80,
1434 .iotype = SERIAL_IO_MEM,
1435 .irq = 94,
1436 .ops = &sci_uart_ops,
1437 .flags = ASYNC_BOOT_AUTOCONF,
1438 .line = 1,
1439 },
1440 .type = PORT_SCI,
1441 .irqs = H8S_SCI_IRQS1,
1442 .init_pins = sci_init_pins_sci,
1443 },
1444 {
1445 .port = {
1446 .membase = (void *)0x00ffff88,
1447 .mapbase = 0x00ffff88,
1448 .iotype = SERIAL_IO_MEM,
1449 .irq = 98,
1450 .ops = &sci_uart_ops,
1451 .flags = ASYNC_BOOT_AUTOCONF,
1452 .line = 2,
1453 },
1454 .type = PORT_SCI,
1455 .irqs = H8S_SCI_IRQS2,
1456 .init_pins = sci_init_pins_sci,
1457 },
1458 #else
1459 #error "CPU subtype not defined"
1460 #endif
1461 };
1462
1463 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1464 /*
1465 * Print a string to the serial port trying not to disturb
1466 * any possible real use of the port...
1467 */
1468 static void serial_console_write(struct console *co, const char *s,
1469 unsigned count)
1470 {
1471 put_string(serial_console_port, s, count);
1472 }
1473
1474 static int __init serial_console_setup(struct console *co, char *options)
1475 {
1476 struct uart_port *port;
1477 int baud = 115200;
1478 int bits = 8;
1479 int parity = 'n';
1480 int flow = 'n';
1481 int ret;
1482
1483 if (co->index >= SCI_NPORTS)
1484 co->index = 0;
1485
1486 serial_console_port = &sci_ports[co->index];
1487 port = &serial_console_port->port;
1488 port->type = serial_console_port->type;
1489
1490 #ifdef CONFIG_SUPERH64
1491 /* This is especially needed on sh64 to remap the SCIF */
1492 sci_config_port(port, 0);
1493 #endif
1494
1495 /*
1496 * We need to set the initial uartclk here, since otherwise it will
1497 * only ever be setup at sci_init() time.
1498 */
1499 #if !defined(__H8300H__) && !defined(__H8300S__)
1500 port->uartclk = current_cpu_data.module_clock * 16;
1501 #else
1502 port->uartclk = CONFIG_CPU_CLOCK;
1503 #endif
1504 #if defined(__H8300S__)
1505 h8300_sci_enable(port, sci_enable);
1506 #endif
1507 if (options)
1508 uart_parse_options(options, &baud, &parity, &bits, &flow);
1509
1510 ret = uart_set_options(port, co, baud, parity, bits, flow);
1511 #if defined(__H8300H__) || defined(__H8300S__)
1512 /* disable rx interrupt */
1513 if (ret == 0)
1514 sci_stop_rx(port);
1515 #endif
1516 return ret;
1517 }
1518
1519 static struct console serial_console = {
1520 .name = "ttySC",
1521 .device = uart_console_device,
1522 .write = serial_console_write,
1523 .setup = serial_console_setup,
1524 .flags = CON_PRINTBUFFER,
1525 .index = -1,
1526 .data = &sci_uart_driver,
1527 };
1528
1529 static int __init sci_console_init(void)
1530 {
1531 register_console(&serial_console);
1532 return 0;
1533 }
1534
1535 console_initcall(sci_console_init);
1536 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1537
1538 #ifdef CONFIG_SH_KGDB
1539 /*
1540 * FIXME: Most of this can go away.. at the moment, we rely on
1541 * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though
1542 * most of that can easily be done here instead.
1543 *
1544 * For the time being, just accept the values that were parsed earlier..
1545 */
1546 static void __init kgdb_console_get_options(struct uart_port *port, int *baud,
1547 int *parity, int *bits)
1548 {
1549 *baud = kgdb_baud;
1550 *parity = tolower(kgdb_parity);
1551 *bits = kgdb_bits - '0';
1552 }
1553
1554 /*
1555 * The naming here is somewhat misleading, since kgdb_console_setup() takes
1556 * care of the early-on initialization for kgdb, regardless of whether we
1557 * actually use kgdb as a console or not.
1558 *
1559 * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense.
1560 */
1561 int __init kgdb_console_setup(struct console *co, char *options)
1562 {
1563 struct uart_port *port = &sci_ports[kgdb_portnum].port;
1564 int baud = 38400;
1565 int bits = 8;
1566 int parity = 'n';
1567 int flow = 'n';
1568
1569 if (co->index >= SCI_NPORTS || co->index != kgdb_portnum)
1570 co->index = kgdb_portnum;
1571
1572 if (options)
1573 uart_parse_options(options, &baud, &parity, &bits, &flow);
1574 else
1575 kgdb_console_get_options(port, &baud, &parity, &bits);
1576
1577 kgdb_getchar = kgdb_sci_getchar;
1578 kgdb_putchar = kgdb_sci_putchar;
1579
1580 return uart_set_options(port, co, baud, parity, bits, flow);
1581 }
1582 #endif /* CONFIG_SH_KGDB */
1583
1584 #ifdef CONFIG_SH_KGDB_CONSOLE
1585 static struct console kgdb_console = {
1586 .name = "ttySC",
1587 .write = kgdb_console_write,
1588 .setup = kgdb_console_setup,
1589 .flags = CON_PRINTBUFFER | CON_ENABLED,
1590 .index = -1,
1591 .data = &sci_uart_driver,
1592 };
1593
1594 /* Register the KGDB console so we get messages (d'oh!) */
1595 static int __init kgdb_console_init(void)
1596 {
1597 register_console(&kgdb_console);
1598 return 0;
1599 }
1600
1601 console_initcall(kgdb_console_init);
1602 #endif /* CONFIG_SH_KGDB_CONSOLE */
1603
1604 #if defined(CONFIG_SH_KGDB_CONSOLE)
1605 #define SCI_CONSOLE &kgdb_console
1606 #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1607 #define SCI_CONSOLE &serial_console
1608 #else
1609 #define SCI_CONSOLE 0
1610 #endif
1611
1612 static char banner[] __initdata =
1613 KERN_INFO "SuperH SCI(F) driver initialized\n";
1614
1615 static struct uart_driver sci_uart_driver = {
1616 .owner = THIS_MODULE,
1617 .driver_name = "sci",
1618 #ifdef CONFIG_DEVFS_FS
1619 .devfs_name = "ttsc/",
1620 #endif
1621 .dev_name = "ttySC",
1622 .major = SCI_MAJOR,
1623 .minor = SCI_MINOR_START,
1624 .nr = SCI_NPORTS,
1625 .cons = SCI_CONSOLE,
1626 };
1627
1628 static int __init sci_init(void)
1629 {
1630 int chan, ret;
1631
1632 printk("%s", banner);
1633
1634 ret = uart_register_driver(&sci_uart_driver);
1635 if (ret == 0) {
1636 for (chan = 0; chan < SCI_NPORTS; chan++) {
1637 struct sci_port *sciport = &sci_ports[chan];
1638
1639 #if !defined(__H8300H__) && !defined(__H8300S__)
1640 sciport->port.uartclk = (current_cpu_data.module_clock * 16);
1641 #else
1642 sciport->port.uartclk = CONFIG_CPU_CLOCK;
1643 #endif
1644 uart_add_one_port(&sci_uart_driver, &sciport->port);
1645 sciport->break_timer.data = (unsigned long)sciport;
1646 sciport->break_timer.function = sci_break_timer;
1647 init_timer(&sciport->break_timer);
1648 }
1649 }
1650
1651 #ifdef CONFIG_CPU_FREQ
1652 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1653 printk("sci: CPU frequency notifier registered\n");
1654 #endif
1655
1656 #ifdef CONFIG_SH_STANDARD_BIOS
1657 sh_bios_gdb_detach();
1658 #endif
1659
1660 return ret;
1661 }
1662
1663 static void __exit sci_exit(void)
1664 {
1665 int chan;
1666
1667 for (chan = 0; chan < SCI_NPORTS; chan++)
1668 uart_remove_one_port(&sci_uart_driver, &sci_ports[chan].port);
1669
1670 uart_unregister_driver(&sci_uart_driver);
1671 }
1672
1673 module_init(sci_init);
1674 module_exit(sci_exit);
1675
Linux kernel - Deliverables
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