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sh: Add SH7263 CPU support.
[deliverable/linux.git] / drivers / serial / sh-sci.h
1 /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
2 *
3 * linux/drivers/serial/sh-sci.h
4 *
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Copyright (C) 2002, 2003 Paul Mundt
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 * Removed SH7300 support (Jul 2007).
13 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Aug 2007).
14 */
15 #include <linux/serial_core.h>
16 #include <asm/io.h>
17
18 #include <asm/gpio.h>
19
20 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
21 #include <asm/regs306x.h>
22 #endif
23 #if defined(CONFIG_H8S2678)
24 #include <asm/regs267x.h>
25 #endif
26
27 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
28 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
29 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
30 defined(CONFIG_CPU_SUBTYPE_SH7709)
31 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
32 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
33 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
34 # define SCI_AND_SCIF
35 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
36 # define SCIF0 0xA4400000
37 # define SCIF2 0xA4410000
38 # define SCSMR_Ir 0xA44A0000
39 # define IRDA_SCIF SCIF0
40 # define SCPCR 0xA4000116
41 # define SCPDR 0xA4000136
42
43 /* Set the clock source,
44 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
45 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
46 */
47 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
48 # define SCIF_ONLY
49 #elif defined(CONFIG_CPU_SUBTYPE_SH7720)
50 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
51 # define SCIF_ONLY
52 #define SCIF_ORER 0x0200 /* overrun error bit */
53 #elif defined(CONFIG_SH_RTS7751R2D)
54 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
55 # define SCIF_ORER 0x0001 /* overrun error bit */
56 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
57 # define SCIF_ONLY
58 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
59 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
60 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
61 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
62 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
63 defined(CONFIG_CPU_SUBTYPE_SH7751R)
64 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
65 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
66 # define SCIF_ORER 0x0001 /* overrun error bit */
67 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
68 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
69 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
70 # define SCI_AND_SCIF
71 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
72 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
73 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
74 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
75 # define SCIF_ORER 0x0001 /* overrun error bit */
76 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
77 # define SCIF_ONLY
78 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
79 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
80 # define SCIF_ORER 0x0001 /* overrun error bit */
81 # define PACR 0xa4050100
82 # define PBCR 0xa4050102
83 # define SCSCR_INIT(port) 0x3B
84 # define SCIF_ONLY
85 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
86 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */
87 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */
88 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */
89 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */
90 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
91 # define SCIF_ONLY
92 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
93 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
94 # define SCSPTR0 SCPDR0
95 # define SCIF_ORER 0x0001 /* overrun error bit */
96 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
97 # define SCIF_ONLY
98 # define PORT_PSCR 0xA405011E
99 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
100 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
101 # define SCIF_ORER 0x0001 /* overrun error bit */
102 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
103 # define SCIF_ONLY
104 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
105 # include <asm/hardware.h>
106 # define SCIF_BASE_ADDR 0x01030000
107 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
108 # define SCIF_PTR2_OFFS 0x0000020
109 # define SCIF_LSR2_OFFS 0x0000024
110 # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
111 # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
112 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
113 # define SCIF_ONLY
114 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
115 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
116 # define SCI_ONLY
117 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
118 #elif defined(CONFIG_H8S2678)
119 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
120 # define SCI_ONLY
121 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
122 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
123 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
124 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
125 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
126 # define SCIF_ORER 0x0001 /* overrun error bit */
127 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
128 # define SCIF_ONLY
129 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
130 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
131 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
132 # define SCIF_ORER 0x0001 /* Overrun error bit */
133 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
134 # define SCIF_ONLY
135 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
136 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */
137 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
138 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */
139 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */
140 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */
141 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */
142 # define SCIF_OPER 0x0001 /* Overrun error bit */
143 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
144 # define SCIF_ONLY
145 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
146 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
147 defined(CONFIG_CPU_SUBTYPE_SH7263)
148 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
149 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
150 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
151 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
152 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
153 # define SCIF_ONLY
154 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
155 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
156 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
157 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
158 # define SCIF_ORER 0x0001 /* overrun error bit */
159 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
160 # define SCIF_ONLY
161 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
162 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */
163 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */
164 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */
165 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */
166 # define SCIF_ORER 0x0001 /* Overrun error bit */
167 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
168 # define SCIF_ONLY
169 #else
170 # error CPU subtype not defined
171 #endif
172
173 /* SCSCR */
174 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
175 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
176 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
177 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
178 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
179 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
180 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
181 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
182 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
183 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
184 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
185 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
186 defined(CONFIG_CPU_SUBTYPE_SHX3)
187 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
188 #else
189 #define SCI_CTRL_FLAGS_REIE 0
190 #endif
191 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
192 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
193 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
194 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
195
196 /* SCxSR SCI */
197 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
198 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
199 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
200 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
201 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
202 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
203 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
204 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
205
206 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
207
208 /* SCxSR SCIF */
209 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
210 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
211 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
212 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
213 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
214 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
215 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
216 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217
218 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
219 defined(CONFIG_CPU_SUBTYPE_SH7720)
220 #define SCIF_ORER 0x0200
221 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
222 #define SCIF_RFDC_MASK 0x007f
223 #define SCIF_TXROOM_MAX 64
224 #else
225 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
226 #define SCIF_RFDC_MASK 0x001f
227 #define SCIF_TXROOM_MAX 16
228 #endif
229
230 #if defined(SCI_ONLY)
231 # define SCxSR_TEND(port) SCI_TEND
232 # define SCxSR_ERRORS(port) SCI_ERRORS
233 # define SCxSR_RDxF(port) SCI_RDRF
234 # define SCxSR_TDxE(port) SCI_TDRE
235 # define SCxSR_ORER(port) SCI_ORER
236 # define SCxSR_FER(port) SCI_FER
237 # define SCxSR_PER(port) SCI_PER
238 # define SCxSR_BRK(port) 0x00
239 # define SCxSR_RDxF_CLEAR(port) 0xbc
240 # define SCxSR_ERROR_CLEAR(port) 0xc4
241 # define SCxSR_TDxE_CLEAR(port) 0x78
242 # define SCxSR_BREAK_CLEAR(port) 0xc4
243 #elif defined(SCIF_ONLY)
244 # define SCxSR_TEND(port) SCIF_TEND
245 # define SCxSR_ERRORS(port) SCIF_ERRORS
246 # define SCxSR_RDxF(port) SCIF_RDF
247 # define SCxSR_TDxE(port) SCIF_TDFE
248 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
249 # define SCxSR_ORER(port) SCIF_ORER
250 #else
251 # define SCxSR_ORER(port) 0x0000
252 #endif
253 # define SCxSR_FER(port) SCIF_FER
254 # define SCxSR_PER(port) SCIF_PER
255 # define SCxSR_BRK(port) SCIF_BRK
256 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
257 defined(CONFIG_CPU_SUBTYPE_SH7720)
258 # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
259 # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
260 # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
261 # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
262 #else
263 /* SH7705 can also use this, clearing is same between 7705 and 7709 */
264 # define SCxSR_RDxF_CLEAR(port) 0x00fc
265 # define SCxSR_ERROR_CLEAR(port) 0x0073
266 # define SCxSR_TDxE_CLEAR(port) 0x00df
267 # define SCxSR_BREAK_CLEAR(port) 0x00e3
268 #endif
269 #else
270 # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
271 # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
272 # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
273 # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
274 # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
275 # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
276 # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
277 # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
278 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
279 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
280 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
281 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
282 #endif
283
284 /* SCFCR */
285 #define SCFCR_RFRST 0x0002
286 #define SCFCR_TFRST 0x0004
287 #define SCFCR_TCRST 0x4000
288 #define SCFCR_MCE 0x0008
289
290 #define SCI_MAJOR 204
291 #define SCI_MINOR_START 8
292
293 /* Generic serial flags */
294 #define SCI_RX_THROTTLE 0x0000001
295
296 #define SCI_MAGIC 0xbabeface
297
298 /*
299 * Events are used to schedule things to happen at timer-interrupt
300 * time, instead of at rs interrupt time.
301 */
302 #define SCI_EVENT_WRITE_WAKEUP 0
303
304 #define SCI_IN(size, offset) \
305 unsigned int addr = port->mapbase + (offset); \
306 if ((size) == 8) { \
307 return ctrl_inb(addr); \
308 } else { \
309 return ctrl_inw(addr); \
310 }
311 #define SCI_OUT(size, offset, value) \
312 unsigned int addr = port->mapbase + (offset); \
313 if ((size) == 8) { \
314 ctrl_outb(value, addr); \
315 } else { \
316 ctrl_outw(value, addr); \
317 }
318
319 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
320 static inline unsigned int sci_##name##_in(struct uart_port *port) \
321 { \
322 if (port->type == PORT_SCI) { \
323 SCI_IN(sci_size, sci_offset) \
324 } else { \
325 SCI_IN(scif_size, scif_offset); \
326 } \
327 } \
328 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
329 { \
330 if (port->type == PORT_SCI) { \
331 SCI_OUT(sci_size, sci_offset, value) \
332 } else { \
333 SCI_OUT(scif_size, scif_offset, value); \
334 } \
335 }
336
337 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
338 static inline unsigned int sci_##name##_in(struct uart_port *port) \
339 { \
340 SCI_IN(scif_size, scif_offset); \
341 } \
342 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
343 { \
344 SCI_OUT(scif_size, scif_offset, value); \
345 }
346
347 #define CPU_SCI_FNS(name, sci_offset, sci_size) \
348 static inline unsigned int sci_##name##_in(struct uart_port* port) \
349 { \
350 SCI_IN(sci_size, sci_offset); \
351 } \
352 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
353 { \
354 SCI_OUT(sci_size, sci_offset, value); \
355 }
356
357 #ifdef CONFIG_CPU_SH3
358 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
359 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
360 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
361 h8_sci_offset, h8_sci_size) \
362 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
363 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
364 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
365 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
366 defined(CONFIG_CPU_SUBTYPE_SH7720)
367 #define SCIF_FNS(name, scif_offset, scif_size) \
368 CPU_SCIF_FNS(name, scif_offset, scif_size)
369 #else
370 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
371 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
372 h8_sci_offset, h8_sci_size) \
373 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
374 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
375 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
376 #endif
377 #elif defined(__H8300H__) || defined(__H8300S__)
378 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
379 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
380 h8_sci_offset, h8_sci_size) \
381 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
382 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
383 #else
384 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
385 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
386 h8_sci_offset, h8_sci_size) \
387 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
388 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
389 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
390 #endif
391
392 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
393 defined(CONFIG_CPU_SUBTYPE_SH7720)
394
395 SCIF_FNS(SCSMR, 0x00, 16)
396 SCIF_FNS(SCBRR, 0x04, 8)
397 SCIF_FNS(SCSCR, 0x08, 16)
398 SCIF_FNS(SCTDSR, 0x0c, 8)
399 SCIF_FNS(SCFER, 0x10, 16)
400 SCIF_FNS(SCxSR, 0x14, 16)
401 SCIF_FNS(SCFCR, 0x18, 16)
402 SCIF_FNS(SCFDR, 0x1c, 16)
403 SCIF_FNS(SCxTDR, 0x20, 8)
404 SCIF_FNS(SCxRDR, 0x24, 8)
405 SCIF_FNS(SCLSR, 0x24, 16)
406 #else
407 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
408 /* name off sz off sz off sz off sz off sz*/
409 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
410 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
411 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
412 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
413 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
414 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
415 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
416 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
417 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
418 defined(CONFIG_CPU_SUBTYPE_SH7785)
419 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
420 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
421 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
422 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
423 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
424 #else
425 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
426 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
427 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
428 #endif
429 #endif
430 #define sci_in(port, reg) sci_##reg##_in(port)
431 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
432
433 /* H8/300 series SCI pins assignment */
434 #if defined(__H8300H__) || defined(__H8300S__)
435 static const struct __attribute__((packed)) {
436 int port; /* GPIO port no */
437 unsigned short rx,tx; /* GPIO bit no */
438 } h8300_sci_pins[] = {
439 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
440 { /* SCI0 */
441 .port = H8300_GPIO_P9,
442 .rx = H8300_GPIO_B2,
443 .tx = H8300_GPIO_B0,
444 },
445 { /* SCI1 */
446 .port = H8300_GPIO_P9,
447 .rx = H8300_GPIO_B3,
448 .tx = H8300_GPIO_B1,
449 },
450 { /* SCI2 */
451 .port = H8300_GPIO_PB,
452 .rx = H8300_GPIO_B7,
453 .tx = H8300_GPIO_B6,
454 }
455 #elif defined(CONFIG_H8S2678)
456 { /* SCI0 */
457 .port = H8300_GPIO_P3,
458 .rx = H8300_GPIO_B2,
459 .tx = H8300_GPIO_B0,
460 },
461 { /* SCI1 */
462 .port = H8300_GPIO_P3,
463 .rx = H8300_GPIO_B3,
464 .tx = H8300_GPIO_B1,
465 },
466 { /* SCI2 */
467 .port = H8300_GPIO_P5,
468 .rx = H8300_GPIO_B1,
469 .tx = H8300_GPIO_B0,
470 }
471 #endif
472 };
473 #endif
474
475 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
476 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
477 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
478 defined(CONFIG_CPU_SUBTYPE_SH7709)
479 static inline int sci_rxd_in(struct uart_port *port)
480 {
481 if (port->mapbase == 0xfffffe80)
482 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
483 if (port->mapbase == 0xa4000150)
484 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
485 if (port->mapbase == 0xa4000140)
486 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
487 return 1;
488 }
489 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
490 static inline int sci_rxd_in(struct uart_port *port)
491 {
492 if (port->mapbase == SCIF0)
493 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
494 if (port->mapbase == SCIF2)
495 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
496 return 1;
497 }
498 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
499 static inline int sci_rxd_in(struct uart_port *port)
500 {
501 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
502 }
503 static inline void set_sh771x_scif_pfc(struct uart_port *port)
504 {
505 if (port->mapbase == 0xA4400000){
506 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
507 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
508 return;
509 }
510 if (port->mapbase == 0xA4410000){
511 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
512 return;
513 }
514 }
515 #elif defined(CONFIG_CPU_SUBTYPE_SH7720)
516 static inline int sci_rxd_in(struct uart_port *port)
517 {
518 if (port->mapbase == 0xa4430000)
519 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
520 else if (port->mapbase == 0xa4438000)
521 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
522 return 1;
523 }
524 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
525 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
526 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
527 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
528 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
529 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
530 defined(CONFIG_CPU_SUBTYPE_SH4_202)
531 static inline int sci_rxd_in(struct uart_port *port)
532 {
533 #ifndef SCIF_ONLY
534 if (port->mapbase == 0xffe00000)
535 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
536 #endif
537 #ifndef SCI_ONLY
538 if (port->mapbase == 0xffe80000)
539 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
540 #endif
541 return 1;
542 }
543 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
544 static inline int sci_rxd_in(struct uart_port *port)
545 {
546 if (port->mapbase == 0xfe600000)
547 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
548 if (port->mapbase == 0xfe610000)
549 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
550 if (port->mapbase == 0xfe620000)
551 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
552 return 1;
553 }
554 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
555 static inline int sci_rxd_in(struct uart_port *port)
556 {
557 if (port->mapbase == 0xffe00000)
558 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
559 if (port->mapbase == 0xffe10000)
560 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
561 if (port->mapbase == 0xffe20000)
562 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
563 if (port->mapbase == 0xffe30000)
564 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
565 return 1;
566 }
567 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
568 static inline int sci_rxd_in(struct uart_port *port)
569 {
570 if (port->mapbase == 0xffe00000)
571 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
572 return 1;
573 }
574 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
575 static inline int sci_rxd_in(struct uart_port *port)
576 {
577 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
578 }
579 #elif defined(__H8300H__) || defined(__H8300S__)
580 static inline int sci_rxd_in(struct uart_port *port)
581 {
582 int ch = (port->mapbase - SMR0) >> 3;
583 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
584 }
585 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
586 static inline int sci_rxd_in(struct uart_port *port)
587 {
588 if (port->mapbase == 0xff923000)
589 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
590 if (port->mapbase == 0xff924000)
591 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
592 if (port->mapbase == 0xff925000)
593 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
594 return 1;
595 }
596 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
597 static inline int sci_rxd_in(struct uart_port *port)
598 {
599 if (port->mapbase == 0xffe00000)
600 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
601 if (port->mapbase == 0xffe10000)
602 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
603 return 1;
604 }
605 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
606 static inline int sci_rxd_in(struct uart_port *port)
607 {
608 if (port->mapbase == 0xffea0000)
609 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
610 if (port->mapbase == 0xffeb0000)
611 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
612 if (port->mapbase == 0xffec0000)
613 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
614 if (port->mapbase == 0xffed0000)
615 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
616 if (port->mapbase == 0xffee0000)
617 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
618 if (port->mapbase == 0xffef0000)
619 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
620 return 1;
621 }
622 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
623 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
624 defined(CONFIG_CPU_SUBTYPE_SH7263)
625 static inline int sci_rxd_in(struct uart_port *port)
626 {
627 if (port->mapbase == 0xfffe8000)
628 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
629 if (port->mapbase == 0xfffe8800)
630 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
631 if (port->mapbase == 0xfffe9000)
632 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
633 if (port->mapbase == 0xfffe9800)
634 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
635 return 1;
636 }
637 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
638 static inline int sci_rxd_in(struct uart_port *port)
639 {
640 if (port->mapbase == 0xf8400000)
641 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
642 if (port->mapbase == 0xf8410000)
643 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
644 if (port->mapbase == 0xf8420000)
645 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
646 return 1;
647 }
648 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
649 static inline int sci_rxd_in(struct uart_port *port)
650 {
651 if (port->mapbase == 0xffc30000)
652 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
653 if (port->mapbase == 0xffc40000)
654 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
655 if (port->mapbase == 0xffc50000)
656 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
657 if (port->mapbase == 0xffc60000)
658 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
659 return 1;
660 }
661 #endif
662
663 /*
664 * Values for the BitRate Register (SCBRR)
665 *
666 * The values are actually divisors for a frequency which can
667 * be internal to the SH3 (14.7456MHz) or derived from an external
668 * clock source. This driver assumes the internal clock is used;
669 * to support using an external clock source, config options or
670 * possibly command-line options would need to be added.
671 *
672 * Also, to support speeds below 2400 (why?) the lower 2 bits of
673 * the SCSMR register would also need to be set to non-zero values.
674 *
675 * -- Greg Banks 27Feb2000
676 *
677 * Answer: The SCBRR register is only eight bits, and the value in
678 * it gets larger with lower baud rates. At around 2400 (depending on
679 * the peripherial module clock) you run out of bits. However the
680 * lower two bits of SCSMR allow the module clock to be divided down,
681 * scaling the value which is needed in SCBRR.
682 *
683 * -- Stuart Menefy - 23 May 2000
684 *
685 * I meant, why would anyone bother with bitrates below 2400.
686 *
687 * -- Greg Banks - 7Jul2000
688 *
689 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
690 * tape reader as a console!
691 *
692 * -- Mitch Davis - 15 Jul 2000
693 */
694
695 #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
696 defined(CONFIG_CPU_SUBTYPE_SH7785)
697 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
698 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
699 defined(CONFIG_CPU_SUBTYPE_SH7720)
700 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
701 #elif defined(__H8300H__) || defined(__H8300S__)
702 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
703 #elif defined(CONFIG_SUPERH64)
704 #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
705 #else /* Generic SH */
706 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
707 #endif
Linux kernel - Deliverables
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