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[SERIAL] sunsu: Convert to of_driver framework.
[deliverable/linux.git] / drivers / serial / sunsu.c
1 /* $Id: su.c,v 1.55 2002/01/08 16:00:16 davem Exp $
2 * su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998-1999 Pete Zaitcev (zaitcev@yahoo.com)
6 *
7 * This is mainly a variation of 8250.c, credits go to authors mentioned
8 * therein. In fact this driver should be merged into the generic 8250.c
9 * infrastructure perhaps using a 8250_sparc.c module.
10 *
11 * Fixed to use tty_get_baud_rate().
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Converted to new 2.5.x UART layer.
15 * David S. Miller (davem@redhat.com), 2002-Jul-29
16 */
17
18 #include <linux/config.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/sched.h>
22 #include <linux/spinlock.h>
23 #include <linux/errno.h>
24 #include <linux/tty.h>
25 #include <linux/tty_flip.h>
26 #include <linux/major.h>
27 #include <linux/string.h>
28 #include <linux/ptrace.h>
29 #include <linux/ioport.h>
30 #include <linux/circ_buf.h>
31 #include <linux/serial.h>
32 #include <linux/sysrq.h>
33 #include <linux/console.h>
34 #ifdef CONFIG_SERIO
35 #include <linux/serio.h>
36 #endif
37 #include <linux/serial_reg.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include <asm/prom.h>
44 #include <asm/of_device.h>
45
46 #if defined(CONFIG_SERIAL_SUNSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
47 #define SUPPORT_SYSRQ
48 #endif
49
50 #include <linux/serial_core.h>
51
52 #include "suncore.h"
53
54 /* We are on a NS PC87303 clocked with 24.0 MHz, which results
55 * in a UART clock of 1.8462 MHz.
56 */
57 #define SU_BASE_BAUD (1846200 / 16)
58
59 enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT };
60 static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" };
61
62 /*
63 * Here we define the default xmit fifo size used for each type of UART.
64 */
65 static const struct serial_uart_config uart_config[PORT_MAX_8250+1] = {
66 { "unknown", 1, 0 },
67 { "8250", 1, 0 },
68 { "16450", 1, 0 },
69 { "16550", 1, 0 },
70 { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
71 { "Cirrus", 1, 0 },
72 { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
73 { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
74 { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO },
75 { "Startech", 1, 0 },
76 { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO },
77 { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
78 { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
79 { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO }
80 };
81
82 struct uart_sunsu_port {
83 struct uart_port port;
84 unsigned char acr;
85 unsigned char ier;
86 unsigned short rev;
87 unsigned char lcr;
88 unsigned int lsr_break_flag;
89 unsigned int cflag;
90
91 /* Probing information. */
92 enum su_type su_type;
93 unsigned int type_probed; /* XXX Stupid */
94 unsigned long reg_size;
95
96 #ifdef CONFIG_SERIO
97 struct serio serio;
98 int serio_open;
99 #endif
100 };
101
102 static unsigned int serial_in(struct uart_sunsu_port *up, int offset)
103 {
104 offset <<= up->port.regshift;
105
106 switch (up->port.iotype) {
107 case UPIO_HUB6:
108 outb(up->port.hub6 - 1 + offset, up->port.iobase);
109 return inb(up->port.iobase + 1);
110
111 case UPIO_MEM:
112 return readb(up->port.membase + offset);
113
114 default:
115 return inb(up->port.iobase + offset);
116 }
117 }
118
119 static void serial_out(struct uart_sunsu_port *up, int offset, int value)
120 {
121 #ifndef CONFIG_SPARC64
122 /*
123 * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are
124 * connected with a gate then go to SlavIO. When IRQ4 goes tristated
125 * gate outputs a logical one. Since we use level triggered interrupts
126 * we have lockup and watchdog reset. We cannot mask IRQ because
127 * keyboard shares IRQ with us (Word has it as Bob Smelik's design).
128 * This problem is similar to what Alpha people suffer, see serial.c.
129 */
130 if (offset == UART_MCR)
131 value |= UART_MCR_OUT2;
132 #endif
133 offset <<= up->port.regshift;
134
135 switch (up->port.iotype) {
136 case UPIO_HUB6:
137 outb(up->port.hub6 - 1 + offset, up->port.iobase);
138 outb(value, up->port.iobase + 1);
139 break;
140
141 case UPIO_MEM:
142 writeb(value, up->port.membase + offset);
143 break;
144
145 default:
146 outb(value, up->port.iobase + offset);
147 }
148 }
149
150 /*
151 * We used to support using pause I/O for certain machines. We
152 * haven't supported this for a while, but just in case it's badly
153 * needed for certain old 386 machines, I've left these #define's
154 * in....
155 */
156 #define serial_inp(up, offset) serial_in(up, offset)
157 #define serial_outp(up, offset, value) serial_out(up, offset, value)
158
159
160 /*
161 * For the 16C950
162 */
163 static void serial_icr_write(struct uart_sunsu_port *up, int offset, int value)
164 {
165 serial_out(up, UART_SCR, offset);
166 serial_out(up, UART_ICR, value);
167 }
168
169 #if 0 /* Unused currently */
170 static unsigned int serial_icr_read(struct uart_sunsu_port *up, int offset)
171 {
172 unsigned int value;
173
174 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
175 serial_out(up, UART_SCR, offset);
176 value = serial_in(up, UART_ICR);
177 serial_icr_write(up, UART_ACR, up->acr);
178
179 return value;
180 }
181 #endif
182
183 #ifdef CONFIG_SERIAL_8250_RSA
184 /*
185 * Attempts to turn on the RSA FIFO. Returns zero on failure.
186 * We set the port uart clock rate if we succeed.
187 */
188 static int __enable_rsa(struct uart_sunsu_port *up)
189 {
190 unsigned char mode;
191 int result;
192
193 mode = serial_inp(up, UART_RSA_MSR);
194 result = mode & UART_RSA_MSR_FIFO;
195
196 if (!result) {
197 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
198 mode = serial_inp(up, UART_RSA_MSR);
199 result = mode & UART_RSA_MSR_FIFO;
200 }
201
202 if (result)
203 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
204
205 return result;
206 }
207
208 static void enable_rsa(struct uart_sunsu_port *up)
209 {
210 if (up->port.type == PORT_RSA) {
211 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
212 spin_lock_irq(&up->port.lock);
213 __enable_rsa(up);
214 spin_unlock_irq(&up->port.lock);
215 }
216 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
217 serial_outp(up, UART_RSA_FRR, 0);
218 }
219 }
220
221 /*
222 * Attempts to turn off the RSA FIFO. Returns zero on failure.
223 * It is unknown why interrupts were disabled in here. However,
224 * the caller is expected to preserve this behaviour by grabbing
225 * the spinlock before calling this function.
226 */
227 static void disable_rsa(struct uart_sunsu_port *up)
228 {
229 unsigned char mode;
230 int result;
231
232 if (up->port.type == PORT_RSA &&
233 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
234 spin_lock_irq(&up->port.lock);
235
236 mode = serial_inp(up, UART_RSA_MSR);
237 result = !(mode & UART_RSA_MSR_FIFO);
238
239 if (!result) {
240 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
241 mode = serial_inp(up, UART_RSA_MSR);
242 result = !(mode & UART_RSA_MSR_FIFO);
243 }
244
245 if (result)
246 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
247 spin_unlock_irq(&up->port.lock);
248 }
249 }
250 #endif /* CONFIG_SERIAL_8250_RSA */
251
252 static inline void __stop_tx(struct uart_sunsu_port *p)
253 {
254 if (p->ier & UART_IER_THRI) {
255 p->ier &= ~UART_IER_THRI;
256 serial_out(p, UART_IER, p->ier);
257 }
258 }
259
260 static void sunsu_stop_tx(struct uart_port *port)
261 {
262 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
263
264 __stop_tx(up);
265
266 /*
267 * We really want to stop the transmitter from sending.
268 */
269 if (up->port.type == PORT_16C950) {
270 up->acr |= UART_ACR_TXDIS;
271 serial_icr_write(up, UART_ACR, up->acr);
272 }
273 }
274
275 static void sunsu_start_tx(struct uart_port *port)
276 {
277 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
278
279 if (!(up->ier & UART_IER_THRI)) {
280 up->ier |= UART_IER_THRI;
281 serial_out(up, UART_IER, up->ier);
282 }
283
284 /*
285 * Re-enable the transmitter if we disabled it.
286 */
287 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
288 up->acr &= ~UART_ACR_TXDIS;
289 serial_icr_write(up, UART_ACR, up->acr);
290 }
291 }
292
293 static void sunsu_stop_rx(struct uart_port *port)
294 {
295 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
296
297 up->ier &= ~UART_IER_RLSI;
298 up->port.read_status_mask &= ~UART_LSR_DR;
299 serial_out(up, UART_IER, up->ier);
300 }
301
302 static void sunsu_enable_ms(struct uart_port *port)
303 {
304 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
305 unsigned long flags;
306
307 spin_lock_irqsave(&up->port.lock, flags);
308 up->ier |= UART_IER_MSI;
309 serial_out(up, UART_IER, up->ier);
310 spin_unlock_irqrestore(&up->port.lock, flags);
311 }
312
313 static struct tty_struct *
314 receive_chars(struct uart_sunsu_port *up, unsigned char *status, struct pt_regs *regs)
315 {
316 struct tty_struct *tty = up->port.info->tty;
317 unsigned char ch, flag;
318 int max_count = 256;
319 int saw_console_brk = 0;
320
321 do {
322 ch = serial_inp(up, UART_RX);
323 flag = TTY_NORMAL;
324 up->port.icount.rx++;
325
326 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
327 UART_LSR_FE | UART_LSR_OE))) {
328 /*
329 * For statistics only
330 */
331 if (*status & UART_LSR_BI) {
332 *status &= ~(UART_LSR_FE | UART_LSR_PE);
333 up->port.icount.brk++;
334 if (up->port.cons != NULL &&
335 up->port.line == up->port.cons->index)
336 saw_console_brk = 1;
337 /*
338 * We do the SysRQ and SAK checking
339 * here because otherwise the break
340 * may get masked by ignore_status_mask
341 * or read_status_mask.
342 */
343 if (uart_handle_break(&up->port))
344 goto ignore_char;
345 } else if (*status & UART_LSR_PE)
346 up->port.icount.parity++;
347 else if (*status & UART_LSR_FE)
348 up->port.icount.frame++;
349 if (*status & UART_LSR_OE)
350 up->port.icount.overrun++;
351
352 /*
353 * Mask off conditions which should be ingored.
354 */
355 *status &= up->port.read_status_mask;
356
357 if (up->port.cons != NULL &&
358 up->port.line == up->port.cons->index) {
359 /* Recover the break flag from console xmit */
360 *status |= up->lsr_break_flag;
361 up->lsr_break_flag = 0;
362 }
363
364 if (*status & UART_LSR_BI) {
365 flag = TTY_BREAK;
366 } else if (*status & UART_LSR_PE)
367 flag = TTY_PARITY;
368 else if (*status & UART_LSR_FE)
369 flag = TTY_FRAME;
370 }
371 if (uart_handle_sysrq_char(&up->port, ch, regs))
372 goto ignore_char;
373 if ((*status & up->port.ignore_status_mask) == 0)
374 tty_insert_flip_char(tty, ch, flag);
375 if (*status & UART_LSR_OE)
376 /*
377 * Overrun is special, since it's reported
378 * immediately, and doesn't affect the current
379 * character.
380 */
381 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
382 ignore_char:
383 *status = serial_inp(up, UART_LSR);
384 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
385
386 if (saw_console_brk)
387 sun_do_break();
388
389 return tty;
390 }
391
392 static void transmit_chars(struct uart_sunsu_port *up)
393 {
394 struct circ_buf *xmit = &up->port.info->xmit;
395 int count;
396
397 if (up->port.x_char) {
398 serial_outp(up, UART_TX, up->port.x_char);
399 up->port.icount.tx++;
400 up->port.x_char = 0;
401 return;
402 }
403 if (uart_tx_stopped(&up->port)) {
404 sunsu_stop_tx(&up->port);
405 return;
406 }
407 if (uart_circ_empty(xmit)) {
408 __stop_tx(up);
409 return;
410 }
411
412 count = up->port.fifosize;
413 do {
414 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
415 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
416 up->port.icount.tx++;
417 if (uart_circ_empty(xmit))
418 break;
419 } while (--count > 0);
420
421 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
422 uart_write_wakeup(&up->port);
423
424 if (uart_circ_empty(xmit))
425 __stop_tx(up);
426 }
427
428 static void check_modem_status(struct uart_sunsu_port *up)
429 {
430 int status;
431
432 status = serial_in(up, UART_MSR);
433
434 if ((status & UART_MSR_ANY_DELTA) == 0)
435 return;
436
437 if (status & UART_MSR_TERI)
438 up->port.icount.rng++;
439 if (status & UART_MSR_DDSR)
440 up->port.icount.dsr++;
441 if (status & UART_MSR_DDCD)
442 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
443 if (status & UART_MSR_DCTS)
444 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
445
446 wake_up_interruptible(&up->port.info->delta_msr_wait);
447 }
448
449 static irqreturn_t sunsu_serial_interrupt(int irq, void *dev_id, struct pt_regs *regs)
450 {
451 struct uart_sunsu_port *up = dev_id;
452 unsigned long flags;
453 unsigned char status;
454
455 spin_lock_irqsave(&up->port.lock, flags);
456
457 do {
458 struct tty_struct *tty;
459
460 status = serial_inp(up, UART_LSR);
461 tty = NULL;
462 if (status & UART_LSR_DR)
463 tty = receive_chars(up, &status, regs);
464 check_modem_status(up);
465 if (status & UART_LSR_THRE)
466 transmit_chars(up);
467
468 spin_unlock_irqrestore(&up->port.lock, flags);
469
470 if (tty)
471 tty_flip_buffer_push(tty);
472
473 spin_lock_irqsave(&up->port.lock, flags);
474
475 } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT));
476
477 spin_unlock_irqrestore(&up->port.lock, flags);
478
479 return IRQ_HANDLED;
480 }
481
482 /* Separate interrupt handling path for keyboard/mouse ports. */
483
484 static void
485 sunsu_change_speed(struct uart_port *port, unsigned int cflag,
486 unsigned int iflag, unsigned int quot);
487
488 static void sunsu_change_mouse_baud(struct uart_sunsu_port *up)
489 {
490 unsigned int cur_cflag = up->cflag;
491 int quot, new_baud;
492
493 up->cflag &= ~CBAUD;
494 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
495
496 quot = up->port.uartclk / (16 * new_baud);
497
498 sunsu_change_speed(&up->port, up->cflag, 0, quot);
499 }
500
501 static void receive_kbd_ms_chars(struct uart_sunsu_port *up, struct pt_regs *regs, int is_break)
502 {
503 do {
504 unsigned char ch = serial_inp(up, UART_RX);
505
506 /* Stop-A is handled by drivers/char/keyboard.c now. */
507 if (up->su_type == SU_PORT_KBD) {
508 #ifdef CONFIG_SERIO
509 serio_interrupt(&up->serio, ch, 0, regs);
510 #endif
511 } else if (up->su_type == SU_PORT_MS) {
512 int ret = suncore_mouse_baud_detection(ch, is_break);
513
514 switch (ret) {
515 case 2:
516 sunsu_change_mouse_baud(up);
517 /* fallthru */
518 case 1:
519 break;
520
521 case 0:
522 #ifdef CONFIG_SERIO
523 serio_interrupt(&up->serio, ch, 0, regs);
524 #endif
525 break;
526 };
527 }
528 } while (serial_in(up, UART_LSR) & UART_LSR_DR);
529 }
530
531 static irqreturn_t sunsu_kbd_ms_interrupt(int irq, void *dev_id, struct pt_regs *regs)
532 {
533 struct uart_sunsu_port *up = dev_id;
534
535 if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) {
536 unsigned char status = serial_inp(up, UART_LSR);
537
538 if ((status & UART_LSR_DR) || (status & UART_LSR_BI))
539 receive_kbd_ms_chars(up, regs,
540 (status & UART_LSR_BI) != 0);
541 }
542
543 return IRQ_HANDLED;
544 }
545
546 static unsigned int sunsu_tx_empty(struct uart_port *port)
547 {
548 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
549 unsigned long flags;
550 unsigned int ret;
551
552 spin_lock_irqsave(&up->port.lock, flags);
553 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
554 spin_unlock_irqrestore(&up->port.lock, flags);
555
556 return ret;
557 }
558
559 static unsigned int sunsu_get_mctrl(struct uart_port *port)
560 {
561 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
562 unsigned char status;
563 unsigned int ret;
564
565 status = serial_in(up, UART_MSR);
566
567 ret = 0;
568 if (status & UART_MSR_DCD)
569 ret |= TIOCM_CAR;
570 if (status & UART_MSR_RI)
571 ret |= TIOCM_RNG;
572 if (status & UART_MSR_DSR)
573 ret |= TIOCM_DSR;
574 if (status & UART_MSR_CTS)
575 ret |= TIOCM_CTS;
576 return ret;
577 }
578
579 static void sunsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
580 {
581 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
582 unsigned char mcr = 0;
583
584 if (mctrl & TIOCM_RTS)
585 mcr |= UART_MCR_RTS;
586 if (mctrl & TIOCM_DTR)
587 mcr |= UART_MCR_DTR;
588 if (mctrl & TIOCM_OUT1)
589 mcr |= UART_MCR_OUT1;
590 if (mctrl & TIOCM_OUT2)
591 mcr |= UART_MCR_OUT2;
592 if (mctrl & TIOCM_LOOP)
593 mcr |= UART_MCR_LOOP;
594
595 serial_out(up, UART_MCR, mcr);
596 }
597
598 static void sunsu_break_ctl(struct uart_port *port, int break_state)
599 {
600 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
601 unsigned long flags;
602
603 spin_lock_irqsave(&up->port.lock, flags);
604 if (break_state == -1)
605 up->lcr |= UART_LCR_SBC;
606 else
607 up->lcr &= ~UART_LCR_SBC;
608 serial_out(up, UART_LCR, up->lcr);
609 spin_unlock_irqrestore(&up->port.lock, flags);
610 }
611
612 static int sunsu_startup(struct uart_port *port)
613 {
614 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
615 unsigned long flags;
616 int retval;
617
618 if (up->port.type == PORT_16C950) {
619 /* Wake up and initialize UART */
620 up->acr = 0;
621 serial_outp(up, UART_LCR, 0xBF);
622 serial_outp(up, UART_EFR, UART_EFR_ECB);
623 serial_outp(up, UART_IER, 0);
624 serial_outp(up, UART_LCR, 0);
625 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
626 serial_outp(up, UART_LCR, 0xBF);
627 serial_outp(up, UART_EFR, UART_EFR_ECB);
628 serial_outp(up, UART_LCR, 0);
629 }
630
631 #ifdef CONFIG_SERIAL_8250_RSA
632 /*
633 * If this is an RSA port, see if we can kick it up to the
634 * higher speed clock.
635 */
636 enable_rsa(up);
637 #endif
638
639 /*
640 * Clear the FIFO buffers and disable them.
641 * (they will be reenabled in set_termios())
642 */
643 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) {
644 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
645 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
646 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
647 serial_outp(up, UART_FCR, 0);
648 }
649
650 /*
651 * Clear the interrupt registers.
652 */
653 (void) serial_inp(up, UART_LSR);
654 (void) serial_inp(up, UART_RX);
655 (void) serial_inp(up, UART_IIR);
656 (void) serial_inp(up, UART_MSR);
657
658 /*
659 * At this point, there's no way the LSR could still be 0xff;
660 * if it is, then bail out, because there's likely no UART
661 * here.
662 */
663 if (!(up->port.flags & UPF_BUGGY_UART) &&
664 (serial_inp(up, UART_LSR) == 0xff)) {
665 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
666 return -ENODEV;
667 }
668
669 if (up->su_type != SU_PORT_PORT) {
670 retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt,
671 SA_SHIRQ, su_typev[up->su_type], up);
672 } else {
673 retval = request_irq(up->port.irq, sunsu_serial_interrupt,
674 SA_SHIRQ, su_typev[up->su_type], up);
675 }
676 if (retval) {
677 printk("su: Cannot register IRQ %d\n", up->port.irq);
678 return retval;
679 }
680
681 /*
682 * Now, initialize the UART
683 */
684 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
685
686 spin_lock_irqsave(&up->port.lock, flags);
687
688 up->port.mctrl |= TIOCM_OUT2;
689
690 sunsu_set_mctrl(&up->port, up->port.mctrl);
691 spin_unlock_irqrestore(&up->port.lock, flags);
692
693 /*
694 * Finally, enable interrupts. Note: Modem status interrupts
695 * are set via set_termios(), which will be occurring imminently
696 * anyway, so we don't enable them here.
697 */
698 up->ier = UART_IER_RLSI | UART_IER_RDI;
699 serial_outp(up, UART_IER, up->ier);
700
701 if (up->port.flags & UPF_FOURPORT) {
702 unsigned int icp;
703 /*
704 * Enable interrupts on the AST Fourport board
705 */
706 icp = (up->port.iobase & 0xfe0) | 0x01f;
707 outb_p(0x80, icp);
708 (void) inb_p(icp);
709 }
710
711 /*
712 * And clear the interrupt registers again for luck.
713 */
714 (void) serial_inp(up, UART_LSR);
715 (void) serial_inp(up, UART_RX);
716 (void) serial_inp(up, UART_IIR);
717 (void) serial_inp(up, UART_MSR);
718
719 return 0;
720 }
721
722 static void sunsu_shutdown(struct uart_port *port)
723 {
724 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
725 unsigned long flags;
726
727 /*
728 * Disable interrupts from this port
729 */
730 up->ier = 0;
731 serial_outp(up, UART_IER, 0);
732
733 spin_lock_irqsave(&up->port.lock, flags);
734 if (up->port.flags & UPF_FOURPORT) {
735 /* reset interrupts on the AST Fourport board */
736 inb((up->port.iobase & 0xfe0) | 0x1f);
737 up->port.mctrl |= TIOCM_OUT1;
738 } else
739 up->port.mctrl &= ~TIOCM_OUT2;
740
741 sunsu_set_mctrl(&up->port, up->port.mctrl);
742 spin_unlock_irqrestore(&up->port.lock, flags);
743
744 /*
745 * Disable break condition and FIFOs
746 */
747 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
748 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
749 UART_FCR_CLEAR_RCVR |
750 UART_FCR_CLEAR_XMIT);
751 serial_outp(up, UART_FCR, 0);
752
753 #ifdef CONFIG_SERIAL_8250_RSA
754 /*
755 * Reset the RSA board back to 115kbps compat mode.
756 */
757 disable_rsa(up);
758 #endif
759
760 /*
761 * Read data port to reset things.
762 */
763 (void) serial_in(up, UART_RX);
764
765 free_irq(up->port.irq, up);
766 }
767
768 static void
769 sunsu_change_speed(struct uart_port *port, unsigned int cflag,
770 unsigned int iflag, unsigned int quot)
771 {
772 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
773 unsigned char cval, fcr = 0;
774 unsigned long flags;
775
776 switch (cflag & CSIZE) {
777 case CS5:
778 cval = 0x00;
779 break;
780 case CS6:
781 cval = 0x01;
782 break;
783 case CS7:
784 cval = 0x02;
785 break;
786 default:
787 case CS8:
788 cval = 0x03;
789 break;
790 }
791
792 if (cflag & CSTOPB)
793 cval |= 0x04;
794 if (cflag & PARENB)
795 cval |= UART_LCR_PARITY;
796 if (!(cflag & PARODD))
797 cval |= UART_LCR_EPAR;
798 #ifdef CMSPAR
799 if (cflag & CMSPAR)
800 cval |= UART_LCR_SPAR;
801 #endif
802
803 /*
804 * Work around a bug in the Oxford Semiconductor 952 rev B
805 * chip which causes it to seriously miscalculate baud rates
806 * when DLL is 0.
807 */
808 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
809 up->rev == 0x5201)
810 quot ++;
811
812 if (uart_config[up->port.type].flags & UART_USE_FIFO) {
813 if ((up->port.uartclk / quot) < (2400 * 16))
814 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
815 #ifdef CONFIG_SERIAL_8250_RSA
816 else if (up->port.type == PORT_RSA)
817 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14;
818 #endif
819 else
820 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8;
821 }
822 if (up->port.type == PORT_16750)
823 fcr |= UART_FCR7_64BYTE;
824
825 /*
826 * Ok, we're now changing the port state. Do it with
827 * interrupts disabled.
828 */
829 spin_lock_irqsave(&up->port.lock, flags);
830
831 /*
832 * Update the per-port timeout.
833 */
834 uart_update_timeout(port, cflag, (port->uartclk / (16 * quot)));
835
836 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
837 if (iflag & INPCK)
838 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
839 if (iflag & (BRKINT | PARMRK))
840 up->port.read_status_mask |= UART_LSR_BI;
841
842 /*
843 * Characteres to ignore
844 */
845 up->port.ignore_status_mask = 0;
846 if (iflag & IGNPAR)
847 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
848 if (iflag & IGNBRK) {
849 up->port.ignore_status_mask |= UART_LSR_BI;
850 /*
851 * If we're ignoring parity and break indicators,
852 * ignore overruns too (for real raw support).
853 */
854 if (iflag & IGNPAR)
855 up->port.ignore_status_mask |= UART_LSR_OE;
856 }
857
858 /*
859 * ignore all characters if CREAD is not set
860 */
861 if ((cflag & CREAD) == 0)
862 up->port.ignore_status_mask |= UART_LSR_DR;
863
864 /*
865 * CTS flow control flag and modem status interrupts
866 */
867 up->ier &= ~UART_IER_MSI;
868 if (UART_ENABLE_MS(&up->port, cflag))
869 up->ier |= UART_IER_MSI;
870
871 serial_out(up, UART_IER, up->ier);
872
873 if (uart_config[up->port.type].flags & UART_STARTECH) {
874 serial_outp(up, UART_LCR, 0xBF);
875 serial_outp(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0);
876 }
877 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
878 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
879 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
880 if (up->port.type == PORT_16750)
881 serial_outp(up, UART_FCR, fcr); /* set fcr */
882 serial_outp(up, UART_LCR, cval); /* reset DLAB */
883 up->lcr = cval; /* Save LCR */
884 if (up->port.type != PORT_16750) {
885 if (fcr & UART_FCR_ENABLE_FIFO) {
886 /* emulated UARTs (Lucent Venus 167x) need two steps */
887 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
888 }
889 serial_outp(up, UART_FCR, fcr); /* set fcr */
890 }
891
892 up->cflag = cflag;
893
894 spin_unlock_irqrestore(&up->port.lock, flags);
895 }
896
897 static void
898 sunsu_set_termios(struct uart_port *port, struct termios *termios,
899 struct termios *old)
900 {
901 unsigned int baud, quot;
902
903 /*
904 * Ask the core to calculate the divisor for us.
905 */
906 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
907 quot = uart_get_divisor(port, baud);
908
909 sunsu_change_speed(port, termios->c_cflag, termios->c_iflag, quot);
910 }
911
912 static void sunsu_release_port(struct uart_port *port)
913 {
914 }
915
916 static int sunsu_request_port(struct uart_port *port)
917 {
918 return 0;
919 }
920
921 static void sunsu_config_port(struct uart_port *port, int flags)
922 {
923 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
924
925 if (flags & UART_CONFIG_TYPE) {
926 /*
927 * We are supposed to call autoconfig here, but this requires
928 * splitting all the OBP probing crap from the UART probing.
929 * We'll do it when we kill sunsu.c altogether.
930 */
931 port->type = up->type_probed; /* XXX */
932 }
933 }
934
935 static int
936 sunsu_verify_port(struct uart_port *port, struct serial_struct *ser)
937 {
938 return -EINVAL;
939 }
940
941 static const char *
942 sunsu_type(struct uart_port *port)
943 {
944 int type = port->type;
945
946 if (type >= ARRAY_SIZE(uart_config))
947 type = 0;
948 return uart_config[type].name;
949 }
950
951 static struct uart_ops sunsu_pops = {
952 .tx_empty = sunsu_tx_empty,
953 .set_mctrl = sunsu_set_mctrl,
954 .get_mctrl = sunsu_get_mctrl,
955 .stop_tx = sunsu_stop_tx,
956 .start_tx = sunsu_start_tx,
957 .stop_rx = sunsu_stop_rx,
958 .enable_ms = sunsu_enable_ms,
959 .break_ctl = sunsu_break_ctl,
960 .startup = sunsu_startup,
961 .shutdown = sunsu_shutdown,
962 .set_termios = sunsu_set_termios,
963 .type = sunsu_type,
964 .release_port = sunsu_release_port,
965 .request_port = sunsu_request_port,
966 .config_port = sunsu_config_port,
967 .verify_port = sunsu_verify_port,
968 };
969
970 #define UART_NR 4
971
972 static struct uart_sunsu_port sunsu_ports[UART_NR];
973
974 #ifdef CONFIG_SERIO
975
976 static DEFINE_SPINLOCK(sunsu_serio_lock);
977
978 static int sunsu_serio_write(struct serio *serio, unsigned char ch)
979 {
980 struct uart_sunsu_port *up = serio->port_data;
981 unsigned long flags;
982 int lsr;
983
984 spin_lock_irqsave(&sunsu_serio_lock, flags);
985
986 do {
987 lsr = serial_in(up, UART_LSR);
988 } while (!(lsr & UART_LSR_THRE));
989
990 /* Send the character out. */
991 serial_out(up, UART_TX, ch);
992
993 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
994
995 return 0;
996 }
997
998 static int sunsu_serio_open(struct serio *serio)
999 {
1000 struct uart_sunsu_port *up = serio->port_data;
1001 unsigned long flags;
1002 int ret;
1003
1004 spin_lock_irqsave(&sunsu_serio_lock, flags);
1005 if (!up->serio_open) {
1006 up->serio_open = 1;
1007 ret = 0;
1008 } else
1009 ret = -EBUSY;
1010 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1011
1012 return ret;
1013 }
1014
1015 static void sunsu_serio_close(struct serio *serio)
1016 {
1017 struct uart_sunsu_port *up = serio->port_data;
1018 unsigned long flags;
1019
1020 spin_lock_irqsave(&sunsu_serio_lock, flags);
1021 up->serio_open = 0;
1022 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1023 }
1024
1025 #endif /* CONFIG_SERIO */
1026
1027 static void sunsu_autoconfig(struct uart_sunsu_port *up)
1028 {
1029 unsigned char status1, status2, scratch, scratch2, scratch3;
1030 unsigned char save_lcr, save_mcr;
1031 unsigned long flags;
1032
1033 if (up->su_type == SU_PORT_NONE)
1034 return;
1035
1036 up->type_probed = PORT_UNKNOWN;
1037 up->port.iotype = UPIO_MEM;
1038
1039 spin_lock_irqsave(&up->port.lock, flags);
1040
1041 if (!(up->port.flags & UPF_BUGGY_UART)) {
1042 /*
1043 * Do a simple existence test first; if we fail this, there's
1044 * no point trying anything else.
1045 *
1046 * 0x80 is used as a nonsense port to prevent against false
1047 * positives due to ISA bus float. The assumption is that
1048 * 0x80 is a non-existent port; which should be safe since
1049 * include/asm/io.h also makes this assumption.
1050 */
1051 scratch = serial_inp(up, UART_IER);
1052 serial_outp(up, UART_IER, 0);
1053 #ifdef __i386__
1054 outb(0xff, 0x080);
1055 #endif
1056 scratch2 = serial_inp(up, UART_IER);
1057 serial_outp(up, UART_IER, 0x0f);
1058 #ifdef __i386__
1059 outb(0, 0x080);
1060 #endif
1061 scratch3 = serial_inp(up, UART_IER);
1062 serial_outp(up, UART_IER, scratch);
1063 if (scratch2 != 0 || scratch3 != 0x0F)
1064 goto out; /* We failed; there's nothing here */
1065 }
1066
1067 save_mcr = serial_in(up, UART_MCR);
1068 save_lcr = serial_in(up, UART_LCR);
1069
1070 /*
1071 * Check to see if a UART is really there. Certain broken
1072 * internal modems based on the Rockwell chipset fail this
1073 * test, because they apparently don't implement the loopback
1074 * test mode. So this test is skipped on the COM 1 through
1075 * COM 4 ports. This *should* be safe, since no board
1076 * manufacturer would be stupid enough to design a board
1077 * that conflicts with COM 1-4 --- we hope!
1078 */
1079 if (!(up->port.flags & UPF_SKIP_TEST)) {
1080 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1081 status1 = serial_inp(up, UART_MSR) & 0xF0;
1082 serial_outp(up, UART_MCR, save_mcr);
1083 if (status1 != 0x90)
1084 goto out; /* We failed loopback test */
1085 }
1086 serial_outp(up, UART_LCR, 0xBF); /* set up for StarTech test */
1087 serial_outp(up, UART_EFR, 0); /* EFR is the same as FCR */
1088 serial_outp(up, UART_LCR, 0);
1089 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1090 scratch = serial_in(up, UART_IIR) >> 6;
1091 switch (scratch) {
1092 case 0:
1093 up->port.type = PORT_16450;
1094 break;
1095 case 1:
1096 up->port.type = PORT_UNKNOWN;
1097 break;
1098 case 2:
1099 up->port.type = PORT_16550;
1100 break;
1101 case 3:
1102 up->port.type = PORT_16550A;
1103 break;
1104 }
1105 if (up->port.type == PORT_16550A) {
1106 /* Check for Startech UART's */
1107 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1108 if (serial_in(up, UART_EFR) == 0) {
1109 up->port.type = PORT_16650;
1110 } else {
1111 serial_outp(up, UART_LCR, 0xBF);
1112 if (serial_in(up, UART_EFR) == 0)
1113 up->port.type = PORT_16650V2;
1114 }
1115 }
1116 if (up->port.type == PORT_16550A) {
1117 /* Check for TI 16750 */
1118 serial_outp(up, UART_LCR, save_lcr | UART_LCR_DLAB);
1119 serial_outp(up, UART_FCR,
1120 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1121 scratch = serial_in(up, UART_IIR) >> 5;
1122 if (scratch == 7) {
1123 /*
1124 * If this is a 16750, and not a cheap UART
1125 * clone, then it should only go into 64 byte
1126 * mode if the UART_FCR7_64BYTE bit was set
1127 * while UART_LCR_DLAB was latched.
1128 */
1129 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1130 serial_outp(up, UART_LCR, 0);
1131 serial_outp(up, UART_FCR,
1132 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1133 scratch = serial_in(up, UART_IIR) >> 5;
1134 if (scratch == 6)
1135 up->port.type = PORT_16750;
1136 }
1137 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1138 }
1139 serial_outp(up, UART_LCR, save_lcr);
1140 if (up->port.type == PORT_16450) {
1141 scratch = serial_in(up, UART_SCR);
1142 serial_outp(up, UART_SCR, 0xa5);
1143 status1 = serial_in(up, UART_SCR);
1144 serial_outp(up, UART_SCR, 0x5a);
1145 status2 = serial_in(up, UART_SCR);
1146 serial_outp(up, UART_SCR, scratch);
1147
1148 if ((status1 != 0xa5) || (status2 != 0x5a))
1149 up->port.type = PORT_8250;
1150 }
1151
1152 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
1153
1154 if (up->port.type == PORT_UNKNOWN)
1155 goto out;
1156 up->type_probed = up->port.type; /* XXX */
1157
1158 /*
1159 * Reset the UART.
1160 */
1161 #ifdef CONFIG_SERIAL_8250_RSA
1162 if (up->port.type == PORT_RSA)
1163 serial_outp(up, UART_RSA_FRR, 0);
1164 #endif
1165 serial_outp(up, UART_MCR, save_mcr);
1166 serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO |
1167 UART_FCR_CLEAR_RCVR |
1168 UART_FCR_CLEAR_XMIT));
1169 serial_outp(up, UART_FCR, 0);
1170 (void)serial_in(up, UART_RX);
1171 serial_outp(up, UART_IER, 0);
1172
1173 out:
1174 spin_unlock_irqrestore(&up->port.lock, flags);
1175 }
1176
1177 static struct uart_driver sunsu_reg = {
1178 .owner = THIS_MODULE,
1179 .driver_name = "serial",
1180 .dev_name = "ttyS",
1181 .major = TTY_MAJOR,
1182 };
1183
1184 static int __init sunsu_kbd_ms_init(struct uart_sunsu_port *up)
1185 {
1186 int quot, baud;
1187 #ifdef CONFIG_SERIO
1188 struct serio *serio;
1189 #endif
1190
1191 if (up->su_type == SU_PORT_KBD) {
1192 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1193 baud = 1200;
1194 } else {
1195 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1196 baud = 4800;
1197 }
1198 quot = up->port.uartclk / (16 * baud);
1199
1200 sunsu_autoconfig(up);
1201 if (up->port.type == PORT_UNKNOWN)
1202 return -ENODEV;
1203
1204 #ifdef CONFIG_SERIO
1205 serio = &up->serio;
1206 serio->port_data = up;
1207
1208 serio->id.type = SERIO_RS232;
1209 if (up->su_type == SU_PORT_KBD) {
1210 serio->id.proto = SERIO_SUNKBD;
1211 strlcpy(serio->name, "sukbd", sizeof(serio->name));
1212 } else {
1213 serio->id.proto = SERIO_SUN;
1214 serio->id.extra = 1;
1215 strlcpy(serio->name, "sums", sizeof(serio->name));
1216 }
1217 strlcpy(serio->phys,
1218 (!(up->port.line & 1) ? "su/serio0" : "su/serio1"),
1219 sizeof(serio->phys));
1220
1221 serio->write = sunsu_serio_write;
1222 serio->open = sunsu_serio_open;
1223 serio->close = sunsu_serio_close;
1224 serio->dev.parent = up->port.dev;
1225
1226 serio_register_port(serio);
1227 #endif
1228
1229 sunsu_change_speed(&up->port, up->cflag, 0, quot);
1230
1231 sunsu_startup(&up->port);
1232 return 0;
1233 }
1234
1235 /*
1236 * ------------------------------------------------------------
1237 * Serial console driver
1238 * ------------------------------------------------------------
1239 */
1240
1241 #ifdef CONFIG_SERIAL_SUNSU_CONSOLE
1242
1243 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1244
1245 /*
1246 * Wait for transmitter & holding register to empty
1247 */
1248 static __inline__ void wait_for_xmitr(struct uart_sunsu_port *up)
1249 {
1250 unsigned int status, tmout = 10000;
1251
1252 /* Wait up to 10ms for the character(s) to be sent. */
1253 do {
1254 status = serial_in(up, UART_LSR);
1255
1256 if (status & UART_LSR_BI)
1257 up->lsr_break_flag = UART_LSR_BI;
1258
1259 if (--tmout == 0)
1260 break;
1261 udelay(1);
1262 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1263
1264 /* Wait up to 1s for flow control if necessary */
1265 if (up->port.flags & UPF_CONS_FLOW) {
1266 tmout = 1000000;
1267 while (--tmout &&
1268 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1269 udelay(1);
1270 }
1271 }
1272
1273 static void sunsu_console_putchar(struct uart_port *port, int ch)
1274 {
1275 struct uart_sunsu_port *up = (struct uart_sunsu_port *)port;
1276
1277 wait_for_xmitr(up);
1278 serial_out(up, UART_TX, ch);
1279 }
1280
1281 /*
1282 * Print a string to the serial port trying not to disturb
1283 * any possible real use of the port...
1284 */
1285 static void sunsu_console_write(struct console *co, const char *s,
1286 unsigned int count)
1287 {
1288 struct uart_sunsu_port *up = &sunsu_ports[co->index];
1289 unsigned int ier;
1290
1291 /*
1292 * First save the UER then disable the interrupts
1293 */
1294 ier = serial_in(up, UART_IER);
1295 serial_out(up, UART_IER, 0);
1296
1297 uart_console_write(&up->port, s, count, sunsu_console_putchar);
1298
1299 /*
1300 * Finally, wait for transmitter to become empty
1301 * and restore the IER
1302 */
1303 wait_for_xmitr(up);
1304 serial_out(up, UART_IER, ier);
1305 }
1306
1307 /*
1308 * Setup initial baud/bits/parity. We do two things here:
1309 * - construct a cflag setting for the first su_open()
1310 * - initialize the serial port
1311 * Return non-zero if we didn't find a serial port.
1312 */
1313 static int sunsu_console_setup(struct console *co, char *options)
1314 {
1315 struct uart_port *port;
1316 int baud = 9600;
1317 int bits = 8;
1318 int parity = 'n';
1319 int flow = 'n';
1320
1321 printk("Console: ttyS%d (SU)\n",
1322 (sunsu_reg.minor - 64) + co->index);
1323
1324 /*
1325 * Check whether an invalid uart number has been specified, and
1326 * if so, search for the first available port that does have
1327 * console support.
1328 */
1329 if (co->index >= UART_NR)
1330 co->index = 0;
1331 port = &sunsu_ports[co->index].port;
1332
1333 /*
1334 * Temporary fix.
1335 */
1336 spin_lock_init(&port->lock);
1337
1338 if (options)
1339 uart_parse_options(options, &baud, &parity, &bits, &flow);
1340
1341 return uart_set_options(port, co, baud, parity, bits, flow);
1342 }
1343
1344 static struct console sunsu_cons = {
1345 .name = "ttyS",
1346 .write = sunsu_console_write,
1347 .device = uart_console_device,
1348 .setup = sunsu_console_setup,
1349 .flags = CON_PRINTBUFFER,
1350 .index = -1,
1351 .data = &sunsu_reg,
1352 };
1353
1354 /*
1355 * Register console.
1356 */
1357
1358 static inline struct console *SUNSU_CONSOLE(int num_uart)
1359 {
1360 int i;
1361
1362 if (con_is_present())
1363 return NULL;
1364
1365 for (i = 0; i < num_uart; i++) {
1366 int this_minor = sunsu_reg.minor + i;
1367
1368 if ((this_minor - 64) == (serial_console - 1))
1369 break;
1370 }
1371 if (i == num_uart)
1372 return NULL;
1373
1374 sunsu_cons.index = i;
1375
1376 return &sunsu_cons;
1377 }
1378 #else
1379 #define SUNSU_CONSOLE(num_uart) (NULL)
1380 #define sunsu_serial_console_init() do { } while (0)
1381 #endif
1382
1383 static enum su_type __devinit su_get_type(struct device_node *dp)
1384 {
1385 struct device_node *ap = of_find_node_by_path("/aliases");
1386
1387 if (ap) {
1388 char *keyb = of_get_property(ap, "keyboard", NULL);
1389 char *ms = of_get_property(ap, "mouse", NULL);
1390
1391 if (keyb) {
1392 if (dp == of_find_node_by_path(keyb))
1393 return SU_PORT_KBD;
1394 }
1395 if (ms) {
1396 if (dp == of_find_node_by_path(ms))
1397 return SU_PORT_MS;
1398 }
1399 }
1400
1401 return SU_PORT_PORT;
1402 }
1403
1404 static int __devinit su_probe(struct of_device *op, const struct of_device_id *match)
1405 {
1406 static int inst;
1407 struct device_node *dp = op->node;
1408 struct uart_sunsu_port *up;
1409 struct resource *rp;
1410 int err;
1411
1412 if (inst >= UART_NR)
1413 return -EINVAL;
1414
1415 up = &sunsu_ports[inst];
1416 up->port.line = inst;
1417
1418 spin_lock_init(&up->port.lock);
1419
1420 up->su_type = su_get_type(dp);
1421
1422 rp = &op->resource[0];
1423 up->port.mapbase = op->resource[0].start;
1424
1425 up->reg_size = (rp->end - rp->start) + 1;
1426 up->port.membase = of_ioremap(rp, 0, up->reg_size, "su");
1427 if (!up->port.membase)
1428 return -ENOMEM;
1429
1430 up->port.irq = op->irqs[0];
1431
1432 up->port.dev = &op->dev;
1433
1434 up->port.type = PORT_UNKNOWN;
1435 up->port.uartclk = (SU_BASE_BAUD * 16);
1436
1437 err = 0;
1438 if (up->su_type == SU_PORT_KBD || up->su_type == SU_PORT_MS) {
1439 err = sunsu_kbd_ms_init(up);
1440 if (err)
1441 goto out_unmap;
1442 }
1443
1444 up->port.flags |= UPF_BOOT_AUTOCONF;
1445
1446 sunsu_autoconfig(up);
1447
1448 err = -ENODEV;
1449 if (up->port.type == PORT_UNKNOWN)
1450 goto out_unmap;
1451
1452 up->port.ops = &sunsu_pops;
1453
1454 err = uart_add_one_port(&sunsu_reg, &up->port);
1455 if (err)
1456 goto out_unmap;
1457
1458 dev_set_drvdata(&op->dev, up);
1459
1460 inst++;
1461
1462 return 0;
1463
1464 out_unmap:
1465 of_iounmap(up->port.membase, up->reg_size);
1466 return err;
1467 }
1468
1469 static int __devexit su_remove(struct of_device *dev)
1470 {
1471 struct uart_sunsu_port *up = dev_get_drvdata(&dev->dev);;
1472
1473 if (up->su_type == SU_PORT_MS ||
1474 up->su_type == SU_PORT_KBD) {
1475 #ifdef CONFIG_SERIO
1476 serio_unregister_port(&up->serio);
1477 #endif
1478 } else if (up->port.type != PORT_UNKNOWN)
1479 uart_remove_one_port(&sunsu_reg, &up->port);
1480
1481 return 0;
1482 }
1483
1484 static struct of_device_id su_match[] = {
1485 {
1486 .name = "su",
1487 },
1488 {
1489 .name = "su_pnp",
1490 },
1491 {
1492 .name = "serial",
1493 .compatible = "su",
1494 },
1495 {},
1496 };
1497 MODULE_DEVICE_TABLE(of, su_match);
1498
1499 static struct of_platform_driver su_driver = {
1500 .name = "su",
1501 .match_table = su_match,
1502 .probe = su_probe,
1503 .remove = __devexit_p(su_remove),
1504 };
1505
1506 static int num_uart;
1507
1508 static int __init sunsu_init(void)
1509 {
1510 struct device_node *dp;
1511 int err;
1512
1513 num_uart = 0;
1514 for_each_node_by_name(dp, "su") {
1515 if (su_get_type(dp) == SU_PORT_PORT)
1516 num_uart++;
1517 }
1518 for_each_node_by_name(dp, "su_pnp") {
1519 if (su_get_type(dp) == SU_PORT_PORT)
1520 num_uart++;
1521 }
1522 for_each_node_by_name(dp, "serial") {
1523 if (of_device_is_compatible(dp, "su")) {
1524 if (su_get_type(dp) == SU_PORT_PORT)
1525 num_uart++;
1526 }
1527 }
1528
1529 if (num_uart) {
1530 sunsu_reg.minor = sunserial_current_minor;
1531 sunsu_reg.nr = num_uart;
1532 err = uart_register_driver(&sunsu_reg);
1533 if (err)
1534 return err;
1535 sunsu_reg.tty_driver->name_base = sunsu_reg.minor - 64;
1536 sunserial_current_minor += num_uart;
1537 sunsu_reg.cons = SUNSU_CONSOLE(num_uart);
1538 }
1539
1540 err = of_register_driver(&su_driver, &of_bus_type);
1541 if (err && num_uart)
1542 uart_unregister_driver(&sunsu_reg);
1543
1544 return err;
1545 }
1546
1547 static void __exit sunsu_exit(void)
1548 {
1549 if (num_uart)
1550 uart_unregister_driver(&sunsu_reg);
1551 }
1552
1553 module_init(sunsu_init);
1554 module_exit(sunsu_exit);
1555 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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