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Merge branch 'next/drivers' into HEAD
[deliverable/linux.git] / drivers / sh / intc / core.c
1 /*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009 - 2012 Paul Mundt
6 *
7 * Based on intc2.c and ipr.c
8 *
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
18 */
19 #define pr_fmt(fmt) "intc: " fmt
20
21 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/io.h>
24 #include <linux/slab.h>
25 #include <linux/stat.h>
26 #include <linux/interrupt.h>
27 #include <linux/sh_intc.h>
28 #include <linux/irqdomain.h>
29 #include <linux/device.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/list.h>
32 #include <linux/spinlock.h>
33 #include <linux/radix-tree.h>
34 #include <linux/export.h>
35 #include <linux/sort.h>
36 #include "internals.h"
37
38 LIST_HEAD(intc_list);
39 DEFINE_RAW_SPINLOCK(intc_big_lock);
40 static unsigned int nr_intc_controllers;
41
42 /*
43 * Default priority level
44 * - this needs to be at least 2 for 5-bit priorities on 7780
45 */
46 static unsigned int default_prio_level = 2; /* 2 - 16 */
47 static unsigned int intc_prio_level[INTC_NR_IRQS]; /* for now */
48
49 unsigned int intc_get_dfl_prio_level(void)
50 {
51 return default_prio_level;
52 }
53
54 unsigned int intc_get_prio_level(unsigned int irq)
55 {
56 return intc_prio_level[irq];
57 }
58
59 void intc_set_prio_level(unsigned int irq, unsigned int level)
60 {
61 unsigned long flags;
62
63 raw_spin_lock_irqsave(&intc_big_lock, flags);
64 intc_prio_level[irq] = level;
65 raw_spin_unlock_irqrestore(&intc_big_lock, flags);
66 }
67
68 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
69 {
70 generic_handle_irq((unsigned int)irq_get_handler_data(irq));
71 }
72
73 static void __init intc_register_irq(struct intc_desc *desc,
74 struct intc_desc_int *d,
75 intc_enum enum_id,
76 unsigned int irq)
77 {
78 struct intc_handle_int *hp;
79 struct irq_data *irq_data;
80 unsigned int data[2], primary;
81 unsigned long flags;
82
83 /*
84 * Register the IRQ position with the global IRQ map, then insert
85 * it in to the radix tree.
86 */
87 irq_reserve_irq(irq);
88
89 raw_spin_lock_irqsave(&intc_big_lock, flags);
90 radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
91 raw_spin_unlock_irqrestore(&intc_big_lock, flags);
92
93 /*
94 * Prefer single interrupt source bitmap over other combinations:
95 *
96 * 1. bitmap, single interrupt source
97 * 2. priority, single interrupt source
98 * 3. bitmap, multiple interrupt sources (groups)
99 * 4. priority, multiple interrupt sources (groups)
100 */
101 data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
102 data[1] = intc_get_prio_handle(desc, d, enum_id, 0);
103
104 primary = 0;
105 if (!data[0] && data[1])
106 primary = 1;
107
108 if (!data[0] && !data[1])
109 pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
110 irq, irq2evt(irq));
111
112 data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
113 data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);
114
115 if (!data[primary])
116 primary ^= 1;
117
118 BUG_ON(!data[primary]); /* must have primary masking method */
119
120 irq_data = irq_get_irq_data(irq);
121
122 disable_irq_nosync(irq);
123 irq_set_chip_and_handler_name(irq, &d->chip, handle_level_irq,
124 "level");
125 irq_set_chip_data(irq, (void *)data[primary]);
126
127 /*
128 * set priority level
129 */
130 intc_set_prio_level(irq, intc_get_dfl_prio_level());
131
132 /* enable secondary masking method if present */
133 if (data[!primary])
134 _intc_enable(irq_data, data[!primary]);
135
136 /* add irq to d->prio list if priority is available */
137 if (data[1]) {
138 hp = d->prio + d->nr_prio;
139 hp->irq = irq;
140 hp->handle = data[1];
141
142 if (primary) {
143 /*
144 * only secondary priority should access registers, so
145 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
146 */
147 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
148 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
149 }
150 d->nr_prio++;
151 }
152
153 /* add irq to d->sense list if sense is available */
154 data[0] = intc_get_sense_handle(desc, d, enum_id);
155 if (data[0]) {
156 (d->sense + d->nr_sense)->irq = irq;
157 (d->sense + d->nr_sense)->handle = data[0];
158 d->nr_sense++;
159 }
160
161 /* irq should be disabled by default */
162 d->chip.irq_mask(irq_data);
163
164 intc_set_ack_handle(irq, desc, d, enum_id);
165 intc_set_dist_handle(irq, desc, d, enum_id);
166
167 activate_irq(irq);
168 }
169
170 static unsigned int __init save_reg(struct intc_desc_int *d,
171 unsigned int cnt,
172 unsigned long value,
173 unsigned int smp)
174 {
175 if (value) {
176 value = intc_phys_to_virt(d, value);
177
178 d->reg[cnt] = value;
179 #ifdef CONFIG_SMP
180 d->smp[cnt] = smp;
181 #endif
182 return 1;
183 }
184
185 return 0;
186 }
187
188 int __init register_intc_controller(struct intc_desc *desc)
189 {
190 unsigned int i, k, smp;
191 struct intc_hw_desc *hw = &desc->hw;
192 struct intc_desc_int *d;
193 struct resource *res;
194
195 pr_info("Registered controller '%s' with %u IRQs\n",
196 desc->name, hw->nr_vectors);
197
198 d = kzalloc(sizeof(*d), GFP_NOWAIT);
199 if (!d)
200 goto err0;
201
202 INIT_LIST_HEAD(&d->list);
203 list_add_tail(&d->list, &intc_list);
204
205 raw_spin_lock_init(&d->lock);
206 INIT_RADIX_TREE(&d->tree, GFP_ATOMIC);
207
208 d->index = nr_intc_controllers;
209
210 if (desc->num_resources) {
211 d->nr_windows = desc->num_resources;
212 d->window = kzalloc(d->nr_windows * sizeof(*d->window),
213 GFP_NOWAIT);
214 if (!d->window)
215 goto err1;
216
217 for (k = 0; k < d->nr_windows; k++) {
218 res = desc->resource + k;
219 WARN_ON(resource_type(res) != IORESOURCE_MEM);
220 d->window[k].phys = res->start;
221 d->window[k].size = resource_size(res);
222 d->window[k].virt = ioremap_nocache(res->start,
223 resource_size(res));
224 if (!d->window[k].virt)
225 goto err2;
226 }
227 }
228
229 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
230 #ifdef CONFIG_INTC_BALANCING
231 if (d->nr_reg)
232 d->nr_reg += hw->nr_mask_regs;
233 #endif
234 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
235 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
236 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
237 d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;
238
239 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
240 if (!d->reg)
241 goto err2;
242
243 #ifdef CONFIG_SMP
244 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
245 if (!d->smp)
246 goto err3;
247 #endif
248 k = 0;
249
250 if (hw->mask_regs) {
251 for (i = 0; i < hw->nr_mask_regs; i++) {
252 smp = IS_SMP(hw->mask_regs[i]);
253 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
254 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
255 #ifdef CONFIG_INTC_BALANCING
256 k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
257 #endif
258 }
259 }
260
261 if (hw->prio_regs) {
262 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
263 GFP_NOWAIT);
264 if (!d->prio)
265 goto err4;
266
267 for (i = 0; i < hw->nr_prio_regs; i++) {
268 smp = IS_SMP(hw->prio_regs[i]);
269 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
270 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
271 }
272
273 sort(d->prio, hw->nr_prio_regs, sizeof(*d->prio),
274 intc_handle_int_cmp, NULL);
275 }
276
277 if (hw->sense_regs) {
278 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
279 GFP_NOWAIT);
280 if (!d->sense)
281 goto err5;
282
283 for (i = 0; i < hw->nr_sense_regs; i++)
284 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
285
286 sort(d->sense, hw->nr_sense_regs, sizeof(*d->sense),
287 intc_handle_int_cmp, NULL);
288 }
289
290 if (hw->subgroups)
291 for (i = 0; i < hw->nr_subgroups; i++)
292 if (hw->subgroups[i].reg)
293 k+= save_reg(d, k, hw->subgroups[i].reg, 0);
294
295 memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
296 d->chip.name = desc->name;
297
298 if (hw->ack_regs)
299 for (i = 0; i < hw->nr_ack_regs; i++)
300 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
301 else
302 d->chip.irq_mask_ack = d->chip.irq_disable;
303
304 /* disable bits matching force_disable before registering irqs */
305 if (desc->force_disable)
306 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
307
308 /* disable bits matching force_enable before registering irqs */
309 if (desc->force_enable)
310 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
311
312 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
313
314 intc_irq_domain_init(d, hw);
315
316 /* register the vectors one by one */
317 for (i = 0; i < hw->nr_vectors; i++) {
318 struct intc_vect *vect = hw->vectors + i;
319 unsigned int irq = evt2irq(vect->vect);
320 int res;
321
322 if (!vect->enum_id)
323 continue;
324
325 res = irq_create_identity_mapping(d->domain, irq);
326 if (unlikely(res)) {
327 if (res == -EEXIST) {
328 res = irq_domain_associate(d->domain, irq, irq);
329 if (unlikely(res)) {
330 pr_err("domain association failure\n");
331 continue;
332 }
333 } else {
334 pr_err("can't identity map IRQ %d\n", irq);
335 continue;
336 }
337 }
338
339 intc_irq_xlate_set(irq, vect->enum_id, d);
340 intc_register_irq(desc, d, vect->enum_id, irq);
341
342 for (k = i + 1; k < hw->nr_vectors; k++) {
343 struct intc_vect *vect2 = hw->vectors + k;
344 unsigned int irq2 = evt2irq(vect2->vect);
345
346 if (vect->enum_id != vect2->enum_id)
347 continue;
348
349 /*
350 * In the case of multi-evt handling and sparse
351 * IRQ support, each vector still needs to have
352 * its own backing irq_desc.
353 */
354 res = irq_create_identity_mapping(d->domain, irq2);
355 if (unlikely(res)) {
356 if (res == -EEXIST) {
357 res = irq_domain_associate(d->domain,
358 irq2, irq2);
359 if (unlikely(res)) {
360 pr_err("domain association "
361 "failure\n");
362 continue;
363 }
364 } else {
365 pr_err("can't identity map IRQ %d\n",
366 irq);
367 continue;
368 }
369 }
370
371 vect2->enum_id = 0;
372
373 /* redirect this interrupts to the first one */
374 irq_set_chip(irq2, &dummy_irq_chip);
375 irq_set_chained_handler(irq2, intc_redirect_irq);
376 irq_set_handler_data(irq2, (void *)irq);
377 }
378 }
379
380 intc_subgroup_init(desc, d);
381
382 /* enable bits matching force_enable after registering irqs */
383 if (desc->force_enable)
384 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
385
386 d->skip_suspend = desc->skip_syscore_suspend;
387
388 nr_intc_controllers++;
389
390 return 0;
391 err5:
392 kfree(d->prio);
393 err4:
394 #ifdef CONFIG_SMP
395 kfree(d->smp);
396 err3:
397 #endif
398 kfree(d->reg);
399 err2:
400 for (k = 0; k < d->nr_windows; k++)
401 if (d->window[k].virt)
402 iounmap(d->window[k].virt);
403
404 kfree(d->window);
405 err1:
406 kfree(d);
407 err0:
408 pr_err("unable to allocate INTC memory\n");
409
410 return -ENOMEM;
411 }
412
413 static int intc_suspend(void)
414 {
415 struct intc_desc_int *d;
416
417 list_for_each_entry(d, &intc_list, list) {
418 int irq;
419
420 if (d->skip_suspend)
421 continue;
422
423 /* enable wakeup irqs belonging to this intc controller */
424 for_each_active_irq(irq) {
425 struct irq_data *data;
426 struct irq_chip *chip;
427
428 data = irq_get_irq_data(irq);
429 chip = irq_data_get_irq_chip(data);
430 if (chip != &d->chip)
431 continue;
432 if (irqd_is_wakeup_set(data))
433 chip->irq_enable(data);
434 }
435 }
436 return 0;
437 }
438
439 static void intc_resume(void)
440 {
441 struct intc_desc_int *d;
442
443 list_for_each_entry(d, &intc_list, list) {
444 int irq;
445
446 if (d->skip_suspend)
447 continue;
448
449 for_each_active_irq(irq) {
450 struct irq_data *data;
451 struct irq_chip *chip;
452
453 data = irq_get_irq_data(irq);
454 chip = irq_data_get_irq_chip(data);
455 /*
456 * This will catch the redirect and VIRQ cases
457 * due to the dummy_irq_chip being inserted.
458 */
459 if (chip != &d->chip)
460 continue;
461 if (irqd_irq_disabled(data))
462 chip->irq_disable(data);
463 else
464 chip->irq_enable(data);
465 }
466 }
467 }
468
469 struct syscore_ops intc_syscore_ops = {
470 .suspend = intc_suspend,
471 .resume = intc_resume,
472 };
473
474 struct bus_type intc_subsys = {
475 .name = "intc",
476 .dev_name = "intc",
477 };
478
479 static ssize_t
480 show_intc_name(struct device *dev, struct device_attribute *attr, char *buf)
481 {
482 struct intc_desc_int *d;
483
484 d = container_of(dev, struct intc_desc_int, dev);
485
486 return sprintf(buf, "%s\n", d->chip.name);
487 }
488
489 static DEVICE_ATTR(name, S_IRUGO, show_intc_name, NULL);
490
491 static int __init register_intc_devs(void)
492 {
493 struct intc_desc_int *d;
494 int error;
495
496 register_syscore_ops(&intc_syscore_ops);
497
498 error = subsys_system_register(&intc_subsys, NULL);
499 if (!error) {
500 list_for_each_entry(d, &intc_list, list) {
501 d->dev.id = d->index;
502 d->dev.bus = &intc_subsys;
503 error = device_register(&d->dev);
504 if (error == 0)
505 error = device_create_file(&d->dev,
506 &dev_attr_name);
507 if (error)
508 break;
509 }
510 }
511
512 if (error)
513 pr_err("device registration error\n");
514
515 return error;
516 }
517 device_initcall(register_intc_devs);
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