projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-next-2.6
[deliverable/linux.git] / drivers / sh / intc.c
1 /*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009 Paul Mundt
6 *
7 * Based on intc2.c and ipr.c
8 *
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
18 */
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
22 #include <linux/io.h>
23 #include <linux/interrupt.h>
24 #include <linux/sh_intc.h>
25 #include <linux/sysdev.h>
26 #include <linux/list.h>
27 #include <linux/topology.h>
28 #include <linux/bitmap.h>
29
30 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
31 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
32 ((addr_e) << 16) | ((addr_d << 24)))
33
34 #define _INTC_SHIFT(h) (h & 0x1f)
35 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
36 #define _INTC_FN(h) ((h >> 9) & 0xf)
37 #define _INTC_MODE(h) ((h >> 13) & 0x7)
38 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
39 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
40
41 struct intc_handle_int {
42 unsigned int irq;
43 unsigned long handle;
44 };
45
46 struct intc_desc_int {
47 struct list_head list;
48 struct sys_device sysdev;
49 pm_message_t state;
50 unsigned long *reg;
51 #ifdef CONFIG_SMP
52 unsigned long *smp;
53 #endif
54 unsigned int nr_reg;
55 struct intc_handle_int *prio;
56 unsigned int nr_prio;
57 struct intc_handle_int *sense;
58 unsigned int nr_sense;
59 struct irq_chip chip;
60 };
61
62 static LIST_HEAD(intc_list);
63
64 /*
65 * The intc_irq_map provides a global map of bound IRQ vectors for a
66 * given platform. Allocation of IRQs are either static through the CPU
67 * vector map, or dynamic in the case of board mux vectors or MSI.
68 *
69 * As this is a central point for all IRQ controllers on the system,
70 * each of the available sources are mapped out here. This combined with
71 * sparseirq makes it quite trivial to keep the vector map tightly packed
72 * when dynamically creating IRQs, as well as tying in to otherwise
73 * unused irq_desc positions in the sparse array.
74 */
75 static DECLARE_BITMAP(intc_irq_map, NR_IRQS);
76 static DEFINE_SPINLOCK(vector_lock);
77
78 #ifdef CONFIG_SMP
79 #define IS_SMP(x) x.smp
80 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
81 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
82 #else
83 #define IS_SMP(x) 0
84 #define INTC_REG(d, x, c) (d->reg[(x)])
85 #define SMP_NR(d, x) 1
86 #endif
87
88 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
89 static unsigned long ack_handle[NR_IRQS];
90
91 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
92 {
93 struct irq_chip *chip = get_irq_chip(irq);
94 return container_of(chip, struct intc_desc_int, chip);
95 }
96
97 static inline unsigned int set_field(unsigned int value,
98 unsigned int field_value,
99 unsigned int handle)
100 {
101 unsigned int width = _INTC_WIDTH(handle);
102 unsigned int shift = _INTC_SHIFT(handle);
103
104 value &= ~(((1 << width) - 1) << shift);
105 value |= field_value << shift;
106 return value;
107 }
108
109 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
110 {
111 __raw_writeb(set_field(0, data, h), addr);
112 (void)__raw_readb(addr); /* Defeat write posting */
113 }
114
115 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
116 {
117 __raw_writew(set_field(0, data, h), addr);
118 (void)__raw_readw(addr); /* Defeat write posting */
119 }
120
121 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
122 {
123 __raw_writel(set_field(0, data, h), addr);
124 (void)__raw_readl(addr); /* Defeat write posting */
125 }
126
127 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
128 {
129 unsigned long flags;
130 local_irq_save(flags);
131 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
132 (void)__raw_readb(addr); /* Defeat write posting */
133 local_irq_restore(flags);
134 }
135
136 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
137 {
138 unsigned long flags;
139 local_irq_save(flags);
140 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
141 (void)__raw_readw(addr); /* Defeat write posting */
142 local_irq_restore(flags);
143 }
144
145 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
146 {
147 unsigned long flags;
148 local_irq_save(flags);
149 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
150 (void)__raw_readl(addr); /* Defeat write posting */
151 local_irq_restore(flags);
152 }
153
154 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
155
156 static void (*intc_reg_fns[])(unsigned long addr,
157 unsigned long h,
158 unsigned long data) = {
159 [REG_FN_WRITE_BASE + 0] = write_8,
160 [REG_FN_WRITE_BASE + 1] = write_16,
161 [REG_FN_WRITE_BASE + 3] = write_32,
162 [REG_FN_MODIFY_BASE + 0] = modify_8,
163 [REG_FN_MODIFY_BASE + 1] = modify_16,
164 [REG_FN_MODIFY_BASE + 3] = modify_32,
165 };
166
167 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
168 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
169 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
170 MODE_PRIO_REG, /* Priority value written to enable interrupt */
171 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
172 };
173
174 static void intc_mode_field(unsigned long addr,
175 unsigned long handle,
176 void (*fn)(unsigned long,
177 unsigned long,
178 unsigned long),
179 unsigned int irq)
180 {
181 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
182 }
183
184 static void intc_mode_zero(unsigned long addr,
185 unsigned long handle,
186 void (*fn)(unsigned long,
187 unsigned long,
188 unsigned long),
189 unsigned int irq)
190 {
191 fn(addr, handle, 0);
192 }
193
194 static void intc_mode_prio(unsigned long addr,
195 unsigned long handle,
196 void (*fn)(unsigned long,
197 unsigned long,
198 unsigned long),
199 unsigned int irq)
200 {
201 fn(addr, handle, intc_prio_level[irq]);
202 }
203
204 static void (*intc_enable_fns[])(unsigned long addr,
205 unsigned long handle,
206 void (*fn)(unsigned long,
207 unsigned long,
208 unsigned long),
209 unsigned int irq) = {
210 [MODE_ENABLE_REG] = intc_mode_field,
211 [MODE_MASK_REG] = intc_mode_zero,
212 [MODE_DUAL_REG] = intc_mode_field,
213 [MODE_PRIO_REG] = intc_mode_prio,
214 [MODE_PCLR_REG] = intc_mode_prio,
215 };
216
217 static void (*intc_disable_fns[])(unsigned long addr,
218 unsigned long handle,
219 void (*fn)(unsigned long,
220 unsigned long,
221 unsigned long),
222 unsigned int irq) = {
223 [MODE_ENABLE_REG] = intc_mode_zero,
224 [MODE_MASK_REG] = intc_mode_field,
225 [MODE_DUAL_REG] = intc_mode_field,
226 [MODE_PRIO_REG] = intc_mode_zero,
227 [MODE_PCLR_REG] = intc_mode_field,
228 };
229
230 static inline void _intc_enable(unsigned int irq, unsigned long handle)
231 {
232 struct intc_desc_int *d = get_intc_desc(irq);
233 unsigned long addr;
234 unsigned int cpu;
235
236 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
237 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
238 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
239 [_INTC_FN(handle)], irq);
240 }
241 }
242
243 static void intc_enable(unsigned int irq)
244 {
245 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
246 }
247
248 static void intc_disable(unsigned int irq)
249 {
250 struct intc_desc_int *d = get_intc_desc(irq);
251 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
252 unsigned long addr;
253 unsigned int cpu;
254
255 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
256 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
257 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
258 [_INTC_FN(handle)], irq);
259 }
260 }
261
262 static void (*intc_enable_noprio_fns[])(unsigned long addr,
263 unsigned long handle,
264 void (*fn)(unsigned long,
265 unsigned long,
266 unsigned long),
267 unsigned int irq) = {
268 [MODE_ENABLE_REG] = intc_mode_field,
269 [MODE_MASK_REG] = intc_mode_zero,
270 [MODE_DUAL_REG] = intc_mode_field,
271 [MODE_PRIO_REG] = intc_mode_field,
272 [MODE_PCLR_REG] = intc_mode_field,
273 };
274
275 static void intc_enable_disable(struct intc_desc_int *d,
276 unsigned long handle, int do_enable)
277 {
278 unsigned long addr;
279 unsigned int cpu;
280 void (*fn)(unsigned long, unsigned long,
281 void (*)(unsigned long, unsigned long, unsigned long),
282 unsigned int);
283
284 if (do_enable) {
285 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
286 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
287 fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
288 fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
289 }
290 } else {
291 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
292 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
293 fn = intc_disable_fns[_INTC_MODE(handle)];
294 fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
295 }
296 }
297 }
298
299 static int intc_set_wake(unsigned int irq, unsigned int on)
300 {
301 return 0; /* allow wakeup, but setup hardware in intc_suspend() */
302 }
303
304 static void intc_mask_ack(unsigned int irq)
305 {
306 struct intc_desc_int *d = get_intc_desc(irq);
307 unsigned long handle = ack_handle[irq];
308 unsigned long addr;
309
310 intc_disable(irq);
311
312 /* read register and write zero only to the assocaited bit */
313
314 if (handle) {
315 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
316 switch (_INTC_FN(handle)) {
317 case REG_FN_MODIFY_BASE + 0: /* 8bit */
318 __raw_readb(addr);
319 __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
320 break;
321 case REG_FN_MODIFY_BASE + 1: /* 16bit */
322 __raw_readw(addr);
323 __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
324 break;
325 case REG_FN_MODIFY_BASE + 3: /* 32bit */
326 __raw_readl(addr);
327 __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
328 break;
329 default:
330 BUG();
331 break;
332 }
333 }
334 }
335
336 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
337 unsigned int nr_hp,
338 unsigned int irq)
339 {
340 int i;
341
342 /* this doesn't scale well, but...
343 *
344 * this function should only be used for cerain uncommon
345 * operations such as intc_set_priority() and intc_set_sense()
346 * and in those rare cases performance doesn't matter that much.
347 * keeping the memory footprint low is more important.
348 *
349 * one rather simple way to speed this up and still keep the
350 * memory footprint down is to make sure the array is sorted
351 * and then perform a bisect to lookup the irq.
352 */
353
354 for (i = 0; i < nr_hp; i++) {
355 if ((hp + i)->irq != irq)
356 continue;
357
358 return hp + i;
359 }
360
361 return NULL;
362 }
363
364 int intc_set_priority(unsigned int irq, unsigned int prio)
365 {
366 struct intc_desc_int *d = get_intc_desc(irq);
367 struct intc_handle_int *ihp;
368
369 if (!intc_prio_level[irq] || prio <= 1)
370 return -EINVAL;
371
372 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
373 if (ihp) {
374 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
375 return -EINVAL;
376
377 intc_prio_level[irq] = prio;
378
379 /*
380 * only set secondary masking method directly
381 * primary masking method is using intc_prio_level[irq]
382 * priority level will be set during next enable()
383 */
384
385 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
386 _intc_enable(irq, ihp->handle);
387 }
388 return 0;
389 }
390
391 #define VALID(x) (x | 0x80)
392
393 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
394 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
395 [IRQ_TYPE_EDGE_RISING] = VALID(1),
396 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
397 /* SH7706, SH7707 and SH7709 do not support high level triggered */
398 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
399 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
400 !defined(CONFIG_CPU_SUBTYPE_SH7709)
401 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
402 #endif
403 };
404
405 static int intc_set_sense(unsigned int irq, unsigned int type)
406 {
407 struct intc_desc_int *d = get_intc_desc(irq);
408 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
409 struct intc_handle_int *ihp;
410 unsigned long addr;
411
412 if (!value)
413 return -EINVAL;
414
415 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
416 if (ihp) {
417 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
418 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
419 }
420 return 0;
421 }
422
423 static unsigned int __init intc_get_reg(struct intc_desc_int *d,
424 unsigned long address)
425 {
426 unsigned int k;
427
428 for (k = 0; k < d->nr_reg; k++) {
429 if (d->reg[k] == address)
430 return k;
431 }
432
433 BUG();
434 return 0;
435 }
436
437 static intc_enum __init intc_grp_id(struct intc_desc *desc,
438 intc_enum enum_id)
439 {
440 struct intc_group *g = desc->hw.groups;
441 unsigned int i, j;
442
443 for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
444 g = desc->hw.groups + i;
445
446 for (j = 0; g->enum_ids[j]; j++) {
447 if (g->enum_ids[j] != enum_id)
448 continue;
449
450 return g->enum_id;
451 }
452 }
453
454 return 0;
455 }
456
457 static unsigned int __init _intc_mask_data(struct intc_desc *desc,
458 struct intc_desc_int *d,
459 intc_enum enum_id,
460 unsigned int *reg_idx,
461 unsigned int *fld_idx)
462 {
463 struct intc_mask_reg *mr = desc->hw.mask_regs;
464 unsigned int fn, mode;
465 unsigned long reg_e, reg_d;
466
467 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
468 mr = desc->hw.mask_regs + *reg_idx;
469
470 for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
471 if (mr->enum_ids[*fld_idx] != enum_id)
472 continue;
473
474 if (mr->set_reg && mr->clr_reg) {
475 fn = REG_FN_WRITE_BASE;
476 mode = MODE_DUAL_REG;
477 reg_e = mr->clr_reg;
478 reg_d = mr->set_reg;
479 } else {
480 fn = REG_FN_MODIFY_BASE;
481 if (mr->set_reg) {
482 mode = MODE_ENABLE_REG;
483 reg_e = mr->set_reg;
484 reg_d = mr->set_reg;
485 } else {
486 mode = MODE_MASK_REG;
487 reg_e = mr->clr_reg;
488 reg_d = mr->clr_reg;
489 }
490 }
491
492 fn += (mr->reg_width >> 3) - 1;
493 return _INTC_MK(fn, mode,
494 intc_get_reg(d, reg_e),
495 intc_get_reg(d, reg_d),
496 1,
497 (mr->reg_width - 1) - *fld_idx);
498 }
499
500 *fld_idx = 0;
501 (*reg_idx)++;
502 }
503
504 return 0;
505 }
506
507 static unsigned int __init intc_mask_data(struct intc_desc *desc,
508 struct intc_desc_int *d,
509 intc_enum enum_id, int do_grps)
510 {
511 unsigned int i = 0;
512 unsigned int j = 0;
513 unsigned int ret;
514
515 ret = _intc_mask_data(desc, d, enum_id, &i, &j);
516 if (ret)
517 return ret;
518
519 if (do_grps)
520 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
521
522 return 0;
523 }
524
525 static unsigned int __init _intc_prio_data(struct intc_desc *desc,
526 struct intc_desc_int *d,
527 intc_enum enum_id,
528 unsigned int *reg_idx,
529 unsigned int *fld_idx)
530 {
531 struct intc_prio_reg *pr = desc->hw.prio_regs;
532 unsigned int fn, n, mode, bit;
533 unsigned long reg_e, reg_d;
534
535 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
536 pr = desc->hw.prio_regs + *reg_idx;
537
538 for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
539 if (pr->enum_ids[*fld_idx] != enum_id)
540 continue;
541
542 if (pr->set_reg && pr->clr_reg) {
543 fn = REG_FN_WRITE_BASE;
544 mode = MODE_PCLR_REG;
545 reg_e = pr->set_reg;
546 reg_d = pr->clr_reg;
547 } else {
548 fn = REG_FN_MODIFY_BASE;
549 mode = MODE_PRIO_REG;
550 if (!pr->set_reg)
551 BUG();
552 reg_e = pr->set_reg;
553 reg_d = pr->set_reg;
554 }
555
556 fn += (pr->reg_width >> 3) - 1;
557 n = *fld_idx + 1;
558
559 BUG_ON(n * pr->field_width > pr->reg_width);
560
561 bit = pr->reg_width - (n * pr->field_width);
562
563 return _INTC_MK(fn, mode,
564 intc_get_reg(d, reg_e),
565 intc_get_reg(d, reg_d),
566 pr->field_width, bit);
567 }
568
569 *fld_idx = 0;
570 (*reg_idx)++;
571 }
572
573 return 0;
574 }
575
576 static unsigned int __init intc_prio_data(struct intc_desc *desc,
577 struct intc_desc_int *d,
578 intc_enum enum_id, int do_grps)
579 {
580 unsigned int i = 0;
581 unsigned int j = 0;
582 unsigned int ret;
583
584 ret = _intc_prio_data(desc, d, enum_id, &i, &j);
585 if (ret)
586 return ret;
587
588 if (do_grps)
589 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
590
591 return 0;
592 }
593
594 static void __init intc_enable_disable_enum(struct intc_desc *desc,
595 struct intc_desc_int *d,
596 intc_enum enum_id, int enable)
597 {
598 unsigned int i, j, data;
599
600 /* go through and enable/disable all mask bits */
601 i = j = 0;
602 do {
603 data = _intc_mask_data(desc, d, enum_id, &i, &j);
604 if (data)
605 intc_enable_disable(d, data, enable);
606 j++;
607 } while (data);
608
609 /* go through and enable/disable all priority fields */
610 i = j = 0;
611 do {
612 data = _intc_prio_data(desc, d, enum_id, &i, &j);
613 if (data)
614 intc_enable_disable(d, data, enable);
615
616 j++;
617 } while (data);
618 }
619
620 static unsigned int __init intc_ack_data(struct intc_desc *desc,
621 struct intc_desc_int *d,
622 intc_enum enum_id)
623 {
624 struct intc_mask_reg *mr = desc->hw.ack_regs;
625 unsigned int i, j, fn, mode;
626 unsigned long reg_e, reg_d;
627
628 for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
629 mr = desc->hw.ack_regs + i;
630
631 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
632 if (mr->enum_ids[j] != enum_id)
633 continue;
634
635 fn = REG_FN_MODIFY_BASE;
636 mode = MODE_ENABLE_REG;
637 reg_e = mr->set_reg;
638 reg_d = mr->set_reg;
639
640 fn += (mr->reg_width >> 3) - 1;
641 return _INTC_MK(fn, mode,
642 intc_get_reg(d, reg_e),
643 intc_get_reg(d, reg_d),
644 1,
645 (mr->reg_width - 1) - j);
646 }
647 }
648
649 return 0;
650 }
651
652 static unsigned int __init intc_sense_data(struct intc_desc *desc,
653 struct intc_desc_int *d,
654 intc_enum enum_id)
655 {
656 struct intc_sense_reg *sr = desc->hw.sense_regs;
657 unsigned int i, j, fn, bit;
658
659 for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
660 sr = desc->hw.sense_regs + i;
661
662 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
663 if (sr->enum_ids[j] != enum_id)
664 continue;
665
666 fn = REG_FN_MODIFY_BASE;
667 fn += (sr->reg_width >> 3) - 1;
668
669 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
670
671 bit = sr->reg_width - ((j + 1) * sr->field_width);
672
673 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
674 0, sr->field_width, bit);
675 }
676 }
677
678 return 0;
679 }
680
681 static void __init intc_register_irq(struct intc_desc *desc,
682 struct intc_desc_int *d,
683 intc_enum enum_id,
684 unsigned int irq)
685 {
686 struct intc_handle_int *hp;
687 unsigned int data[2], primary;
688
689 /*
690 * Register the IRQ position with the global IRQ map
691 */
692 set_bit(irq, intc_irq_map);
693
694 /* Prefer single interrupt source bitmap over other combinations:
695 * 1. bitmap, single interrupt source
696 * 2. priority, single interrupt source
697 * 3. bitmap, multiple interrupt sources (groups)
698 * 4. priority, multiple interrupt sources (groups)
699 */
700
701 data[0] = intc_mask_data(desc, d, enum_id, 0);
702 data[1] = intc_prio_data(desc, d, enum_id, 0);
703
704 primary = 0;
705 if (!data[0] && data[1])
706 primary = 1;
707
708 if (!data[0] && !data[1])
709 pr_warning("intc: missing unique irq mask for "
710 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
711
712 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
713 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
714
715 if (!data[primary])
716 primary ^= 1;
717
718 BUG_ON(!data[primary]); /* must have primary masking method */
719
720 disable_irq_nosync(irq);
721 set_irq_chip_and_handler_name(irq, &d->chip,
722 handle_level_irq, "level");
723 set_irq_chip_data(irq, (void *)data[primary]);
724
725 /* set priority level
726 * - this needs to be at least 2 for 5-bit priorities on 7780
727 */
728 intc_prio_level[irq] = 2;
729
730 /* enable secondary masking method if present */
731 if (data[!primary])
732 _intc_enable(irq, data[!primary]);
733
734 /* add irq to d->prio list if priority is available */
735 if (data[1]) {
736 hp = d->prio + d->nr_prio;
737 hp->irq = irq;
738 hp->handle = data[1];
739
740 if (primary) {
741 /*
742 * only secondary priority should access registers, so
743 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
744 */
745
746 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
747 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
748 }
749 d->nr_prio++;
750 }
751
752 /* add irq to d->sense list if sense is available */
753 data[0] = intc_sense_data(desc, d, enum_id);
754 if (data[0]) {
755 (d->sense + d->nr_sense)->irq = irq;
756 (d->sense + d->nr_sense)->handle = data[0];
757 d->nr_sense++;
758 }
759
760 /* irq should be disabled by default */
761 d->chip.mask(irq);
762
763 if (desc->hw.ack_regs)
764 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
765 }
766
767 static unsigned int __init save_reg(struct intc_desc_int *d,
768 unsigned int cnt,
769 unsigned long value,
770 unsigned int smp)
771 {
772 if (value) {
773 d->reg[cnt] = value;
774 #ifdef CONFIG_SMP
775 d->smp[cnt] = smp;
776 #endif
777 return 1;
778 }
779
780 return 0;
781 }
782
783 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
784 {
785 generic_handle_irq((unsigned int)get_irq_data(irq));
786 }
787
788 void __init register_intc_controller(struct intc_desc *desc)
789 {
790 unsigned int i, k, smp;
791 struct intc_hw_desc *hw = &desc->hw;
792 struct intc_desc_int *d;
793
794 d = kzalloc(sizeof(*d), GFP_NOWAIT);
795
796 INIT_LIST_HEAD(&d->list);
797 list_add(&d->list, &intc_list);
798
799 d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
800 d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
801 d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
802 d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
803
804 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
805 #ifdef CONFIG_SMP
806 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
807 #endif
808 k = 0;
809
810 if (hw->mask_regs) {
811 for (i = 0; i < hw->nr_mask_regs; i++) {
812 smp = IS_SMP(hw->mask_regs[i]);
813 k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
814 k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
815 }
816 }
817
818 if (hw->prio_regs) {
819 d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
820 GFP_NOWAIT);
821
822 for (i = 0; i < hw->nr_prio_regs; i++) {
823 smp = IS_SMP(hw->prio_regs[i]);
824 k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
825 k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
826 }
827 }
828
829 if (hw->sense_regs) {
830 d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
831 GFP_NOWAIT);
832
833 for (i = 0; i < hw->nr_sense_regs; i++)
834 k += save_reg(d, k, hw->sense_regs[i].reg, 0);
835 }
836
837 d->chip.name = desc->name;
838 d->chip.mask = intc_disable;
839 d->chip.unmask = intc_enable;
840 d->chip.mask_ack = intc_disable;
841 d->chip.enable = intc_enable;
842 d->chip.disable = intc_disable;
843 d->chip.shutdown = intc_disable;
844 d->chip.set_type = intc_set_sense;
845 d->chip.set_wake = intc_set_wake;
846
847 if (hw->ack_regs) {
848 for (i = 0; i < hw->nr_ack_regs; i++)
849 k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
850
851 d->chip.mask_ack = intc_mask_ack;
852 }
853
854 /* disable bits matching force_disable before registering irqs */
855 if (desc->force_disable)
856 intc_enable_disable_enum(desc, d, desc->force_disable, 0);
857
858 /* disable bits matching force_enable before registering irqs */
859 if (desc->force_enable)
860 intc_enable_disable_enum(desc, d, desc->force_enable, 0);
861
862 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
863
864 /* register the vectors one by one */
865 for (i = 0; i < hw->nr_vectors; i++) {
866 struct intc_vect *vect = hw->vectors + i;
867 unsigned int irq = evt2irq(vect->vect);
868 struct irq_desc *irq_desc;
869
870 if (!vect->enum_id)
871 continue;
872
873 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
874 if (unlikely(!irq_desc)) {
875 pr_info("can't get irq_desc for %d\n", irq);
876 continue;
877 }
878
879 intc_register_irq(desc, d, vect->enum_id, irq);
880
881 for (k = i + 1; k < hw->nr_vectors; k++) {
882 struct intc_vect *vect2 = hw->vectors + k;
883 unsigned int irq2 = evt2irq(vect2->vect);
884
885 if (vect->enum_id != vect2->enum_id)
886 continue;
887
888 /*
889 * In the case of multi-evt handling and sparse
890 * IRQ support, each vector still needs to have
891 * its own backing irq_desc.
892 */
893 irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
894 if (unlikely(!irq_desc)) {
895 pr_info("can't get irq_desc for %d\n", irq2);
896 continue;
897 }
898
899 vect2->enum_id = 0;
900
901 /* redirect this interrupts to the first one */
902 set_irq_chip(irq2, &dummy_irq_chip);
903 set_irq_chained_handler(irq2, intc_redirect_irq);
904 set_irq_data(irq2, (void *)irq);
905 }
906 }
907
908 /* enable bits matching force_enable after registering irqs */
909 if (desc->force_enable)
910 intc_enable_disable_enum(desc, d, desc->force_enable, 1);
911 }
912
913 static int intc_suspend(struct sys_device *dev, pm_message_t state)
914 {
915 struct intc_desc_int *d;
916 struct irq_desc *desc;
917 int irq;
918
919 /* get intc controller associated with this sysdev */
920 d = container_of(dev, struct intc_desc_int, sysdev);
921
922 switch (state.event) {
923 case PM_EVENT_ON:
924 if (d->state.event != PM_EVENT_FREEZE)
925 break;
926 for_each_irq_desc(irq, desc) {
927 if (desc->handle_irq == intc_redirect_irq)
928 continue;
929 if (desc->chip != &d->chip)
930 continue;
931 if (desc->status & IRQ_DISABLED)
932 intc_disable(irq);
933 else
934 intc_enable(irq);
935 }
936 break;
937 case PM_EVENT_FREEZE:
938 /* nothing has to be done */
939 break;
940 case PM_EVENT_SUSPEND:
941 /* enable wakeup irqs belonging to this intc controller */
942 for_each_irq_desc(irq, desc) {
943 if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
944 intc_enable(irq);
945 }
946 break;
947 }
948 d->state = state;
949
950 return 0;
951 }
952
953 static int intc_resume(struct sys_device *dev)
954 {
955 return intc_suspend(dev, PMSG_ON);
956 }
957
958 static struct sysdev_class intc_sysdev_class = {
959 .name = "intc",
960 .suspend = intc_suspend,
961 .resume = intc_resume,
962 };
963
964 /* register this intc as sysdev to allow suspend/resume */
965 static int __init register_intc_sysdevs(void)
966 {
967 struct intc_desc_int *d;
968 int error;
969 int id = 0;
970
971 error = sysdev_class_register(&intc_sysdev_class);
972 if (!error) {
973 list_for_each_entry(d, &intc_list, list) {
974 d->sysdev.id = id;
975 d->sysdev.cls = &intc_sysdev_class;
976 error = sysdev_register(&d->sysdev);
977 if (error)
978 break;
979 id++;
980 }
981 }
982
983 if (error)
984 pr_warning("intc: sysdev registration error\n");
985
986 return error;
987 }
988 device_initcall(register_intc_sysdevs);
989
990 /*
991 * Dynamic IRQ allocation and deallocation
992 */
993 unsigned int create_irq_nr(unsigned int irq_want, int node)
994 {
995 unsigned int irq = 0, new;
996 unsigned long flags;
997 struct irq_desc *desc;
998
999 spin_lock_irqsave(&vector_lock, flags);
1000
1001 /*
1002 * First try the wanted IRQ
1003 */
1004 if (test_and_set_bit(irq_want, intc_irq_map) == 0) {
1005 new = irq_want;
1006 } else {
1007 /* .. then fall back to scanning. */
1008 new = find_first_zero_bit(intc_irq_map, nr_irqs);
1009 if (unlikely(new == nr_irqs))
1010 goto out_unlock;
1011
1012 __set_bit(new, intc_irq_map);
1013 }
1014
1015 desc = irq_to_desc_alloc_node(new, node);
1016 if (unlikely(!desc)) {
1017 pr_info("can't get irq_desc for %d\n", new);
1018 goto out_unlock;
1019 }
1020
1021 desc = move_irq_desc(desc, node);
1022 irq = new;
1023
1024 out_unlock:
1025 spin_unlock_irqrestore(&vector_lock, flags);
1026
1027 if (irq > 0)
1028 dynamic_irq_init(irq);
1029
1030 return irq;
1031 }
1032
1033 int create_irq(void)
1034 {
1035 int nid = cpu_to_node(smp_processor_id());
1036 int irq;
1037
1038 irq = create_irq_nr(NR_IRQS_LEGACY, nid);
1039 if (irq == 0)
1040 irq = -1;
1041
1042 return irq;
1043 }
1044
1045 void destroy_irq(unsigned int irq)
1046 {
1047 unsigned long flags;
1048
1049 dynamic_irq_cleanup(irq);
1050
1051 spin_lock_irqsave(&vector_lock, flags);
1052 __clear_bit(irq, intc_irq_map);
1053 spin_unlock_irqrestore(&vector_lock, flags);
1054 }
1055
1056 int reserve_irq_vector(unsigned int irq)
1057 {
1058 unsigned long flags;
1059 int ret = 0;
1060
1061 spin_lock_irqsave(&vector_lock, flags);
1062 if (test_and_set_bit(irq, intc_irq_map))
1063 ret = -EBUSY;
1064 spin_unlock_irqrestore(&vector_lock, flags);
1065
1066 return ret;
1067 }
1068
1069 void reserve_irq_legacy(void)
1070 {
1071 unsigned long flags;
1072 int i, j;
1073
1074 spin_lock_irqsave(&vector_lock, flags);
1075 j = find_first_bit(intc_irq_map, nr_irqs);
1076 for (i = 0; i < j; i++)
1077 __set_bit(i, intc_irq_map);
1078 spin_unlock_irqrestore(&vector_lock, flags);
1079 }
Linux kernel - Deliverables
This page took 0.098055 seconds and 5 git commands to generate.