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Merge branch 'for-rmk/samsung6' of git://git.fluff.org/bjdooks/linux into devel-stable
[deliverable/linux.git] / drivers / sh / intc.c
1 /*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 * Copyright (C) 2009 Paul Mundt
6 *
7 * Based on intc2.c and ipr.c
8 *
9 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
10 * Copyright (C) 2000 Kazumoto Kojima
11 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
12 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
13 * Copyright (C) 2005, 2006 Paul Mundt
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive
17 * for more details.
18 */
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/module.h>
22 #include <linux/io.h>
23 #include <linux/interrupt.h>
24 #include <linux/sh_intc.h>
25 #include <linux/sysdev.h>
26 #include <linux/list.h>
27 #include <linux/topology.h>
28 #include <linux/bitmap.h>
29
30 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
31 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
32 ((addr_e) << 16) | ((addr_d << 24)))
33
34 #define _INTC_SHIFT(h) (h & 0x1f)
35 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
36 #define _INTC_FN(h) ((h >> 9) & 0xf)
37 #define _INTC_MODE(h) ((h >> 13) & 0x7)
38 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
39 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
40
41 struct intc_handle_int {
42 unsigned int irq;
43 unsigned long handle;
44 };
45
46 struct intc_desc_int {
47 struct list_head list;
48 struct sys_device sysdev;
49 pm_message_t state;
50 unsigned long *reg;
51 #ifdef CONFIG_SMP
52 unsigned long *smp;
53 #endif
54 unsigned int nr_reg;
55 struct intc_handle_int *prio;
56 unsigned int nr_prio;
57 struct intc_handle_int *sense;
58 unsigned int nr_sense;
59 struct irq_chip chip;
60 };
61
62 static LIST_HEAD(intc_list);
63
64 /*
65 * The intc_irq_map provides a global map of bound IRQ vectors for a
66 * given platform. Allocation of IRQs are either static through the CPU
67 * vector map, or dynamic in the case of board mux vectors or MSI.
68 *
69 * As this is a central point for all IRQ controllers on the system,
70 * each of the available sources are mapped out here. This combined with
71 * sparseirq makes it quite trivial to keep the vector map tightly packed
72 * when dynamically creating IRQs, as well as tying in to otherwise
73 * unused irq_desc positions in the sparse array.
74 */
75 static DECLARE_BITMAP(intc_irq_map, NR_IRQS);
76 static DEFINE_SPINLOCK(vector_lock);
77
78 #ifdef CONFIG_SMP
79 #define IS_SMP(x) x.smp
80 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
81 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
82 #else
83 #define IS_SMP(x) 0
84 #define INTC_REG(d, x, c) (d->reg[(x)])
85 #define SMP_NR(d, x) 1
86 #endif
87
88 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
89 static unsigned long ack_handle[NR_IRQS];
90
91 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
92 {
93 struct irq_chip *chip = get_irq_chip(irq);
94 return container_of(chip, struct intc_desc_int, chip);
95 }
96
97 static inline unsigned int set_field(unsigned int value,
98 unsigned int field_value,
99 unsigned int handle)
100 {
101 unsigned int width = _INTC_WIDTH(handle);
102 unsigned int shift = _INTC_SHIFT(handle);
103
104 value &= ~(((1 << width) - 1) << shift);
105 value |= field_value << shift;
106 return value;
107 }
108
109 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
110 {
111 __raw_writeb(set_field(0, data, h), addr);
112 (void)__raw_readb(addr); /* Defeat write posting */
113 }
114
115 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
116 {
117 __raw_writew(set_field(0, data, h), addr);
118 (void)__raw_readw(addr); /* Defeat write posting */
119 }
120
121 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
122 {
123 __raw_writel(set_field(0, data, h), addr);
124 (void)__raw_readl(addr); /* Defeat write posting */
125 }
126
127 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
128 {
129 unsigned long flags;
130 local_irq_save(flags);
131 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
132 (void)__raw_readb(addr); /* Defeat write posting */
133 local_irq_restore(flags);
134 }
135
136 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
137 {
138 unsigned long flags;
139 local_irq_save(flags);
140 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
141 (void)__raw_readw(addr); /* Defeat write posting */
142 local_irq_restore(flags);
143 }
144
145 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
146 {
147 unsigned long flags;
148 local_irq_save(flags);
149 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
150 (void)__raw_readl(addr); /* Defeat write posting */
151 local_irq_restore(flags);
152 }
153
154 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
155
156 static void (*intc_reg_fns[])(unsigned long addr,
157 unsigned long h,
158 unsigned long data) = {
159 [REG_FN_WRITE_BASE + 0] = write_8,
160 [REG_FN_WRITE_BASE + 1] = write_16,
161 [REG_FN_WRITE_BASE + 3] = write_32,
162 [REG_FN_MODIFY_BASE + 0] = modify_8,
163 [REG_FN_MODIFY_BASE + 1] = modify_16,
164 [REG_FN_MODIFY_BASE + 3] = modify_32,
165 };
166
167 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
168 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
169 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
170 MODE_PRIO_REG, /* Priority value written to enable interrupt */
171 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
172 };
173
174 static void intc_mode_field(unsigned long addr,
175 unsigned long handle,
176 void (*fn)(unsigned long,
177 unsigned long,
178 unsigned long),
179 unsigned int irq)
180 {
181 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
182 }
183
184 static void intc_mode_zero(unsigned long addr,
185 unsigned long handle,
186 void (*fn)(unsigned long,
187 unsigned long,
188 unsigned long),
189 unsigned int irq)
190 {
191 fn(addr, handle, 0);
192 }
193
194 static void intc_mode_prio(unsigned long addr,
195 unsigned long handle,
196 void (*fn)(unsigned long,
197 unsigned long,
198 unsigned long),
199 unsigned int irq)
200 {
201 fn(addr, handle, intc_prio_level[irq]);
202 }
203
204 static void (*intc_enable_fns[])(unsigned long addr,
205 unsigned long handle,
206 void (*fn)(unsigned long,
207 unsigned long,
208 unsigned long),
209 unsigned int irq) = {
210 [MODE_ENABLE_REG] = intc_mode_field,
211 [MODE_MASK_REG] = intc_mode_zero,
212 [MODE_DUAL_REG] = intc_mode_field,
213 [MODE_PRIO_REG] = intc_mode_prio,
214 [MODE_PCLR_REG] = intc_mode_prio,
215 };
216
217 static void (*intc_disable_fns[])(unsigned long addr,
218 unsigned long handle,
219 void (*fn)(unsigned long,
220 unsigned long,
221 unsigned long),
222 unsigned int irq) = {
223 [MODE_ENABLE_REG] = intc_mode_zero,
224 [MODE_MASK_REG] = intc_mode_field,
225 [MODE_DUAL_REG] = intc_mode_field,
226 [MODE_PRIO_REG] = intc_mode_zero,
227 [MODE_PCLR_REG] = intc_mode_field,
228 };
229
230 static inline void _intc_enable(unsigned int irq, unsigned long handle)
231 {
232 struct intc_desc_int *d = get_intc_desc(irq);
233 unsigned long addr;
234 unsigned int cpu;
235
236 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
237 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
238 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
239 [_INTC_FN(handle)], irq);
240 }
241 }
242
243 static void intc_enable(unsigned int irq)
244 {
245 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
246 }
247
248 static void intc_disable(unsigned int irq)
249 {
250 struct intc_desc_int *d = get_intc_desc(irq);
251 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
252 unsigned long addr;
253 unsigned int cpu;
254
255 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
256 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
257 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
258 [_INTC_FN(handle)], irq);
259 }
260 }
261
262 static int intc_set_wake(unsigned int irq, unsigned int on)
263 {
264 return 0; /* allow wakeup, but setup hardware in intc_suspend() */
265 }
266
267 static void intc_mask_ack(unsigned int irq)
268 {
269 struct intc_desc_int *d = get_intc_desc(irq);
270 unsigned long handle = ack_handle[irq];
271 unsigned long addr;
272
273 intc_disable(irq);
274
275 /* read register and write zero only to the assocaited bit */
276
277 if (handle) {
278 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
279 switch (_INTC_FN(handle)) {
280 case REG_FN_MODIFY_BASE + 0: /* 8bit */
281 __raw_readb(addr);
282 __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
283 break;
284 case REG_FN_MODIFY_BASE + 1: /* 16bit */
285 __raw_readw(addr);
286 __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
287 break;
288 case REG_FN_MODIFY_BASE + 3: /* 32bit */
289 __raw_readl(addr);
290 __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
291 break;
292 default:
293 BUG();
294 break;
295 }
296 }
297 }
298
299 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
300 unsigned int nr_hp,
301 unsigned int irq)
302 {
303 int i;
304
305 /* this doesn't scale well, but...
306 *
307 * this function should only be used for cerain uncommon
308 * operations such as intc_set_priority() and intc_set_sense()
309 * and in those rare cases performance doesn't matter that much.
310 * keeping the memory footprint low is more important.
311 *
312 * one rather simple way to speed this up and still keep the
313 * memory footprint down is to make sure the array is sorted
314 * and then perform a bisect to lookup the irq.
315 */
316
317 for (i = 0; i < nr_hp; i++) {
318 if ((hp + i)->irq != irq)
319 continue;
320
321 return hp + i;
322 }
323
324 return NULL;
325 }
326
327 int intc_set_priority(unsigned int irq, unsigned int prio)
328 {
329 struct intc_desc_int *d = get_intc_desc(irq);
330 struct intc_handle_int *ihp;
331
332 if (!intc_prio_level[irq] || prio <= 1)
333 return -EINVAL;
334
335 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
336 if (ihp) {
337 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
338 return -EINVAL;
339
340 intc_prio_level[irq] = prio;
341
342 /*
343 * only set secondary masking method directly
344 * primary masking method is using intc_prio_level[irq]
345 * priority level will be set during next enable()
346 */
347
348 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
349 _intc_enable(irq, ihp->handle);
350 }
351 return 0;
352 }
353
354 #define VALID(x) (x | 0x80)
355
356 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
357 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
358 [IRQ_TYPE_EDGE_RISING] = VALID(1),
359 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
360 /* SH7706, SH7707 and SH7709 do not support high level triggered */
361 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
362 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
363 !defined(CONFIG_CPU_SUBTYPE_SH7709)
364 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
365 #endif
366 };
367
368 static int intc_set_sense(unsigned int irq, unsigned int type)
369 {
370 struct intc_desc_int *d = get_intc_desc(irq);
371 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
372 struct intc_handle_int *ihp;
373 unsigned long addr;
374
375 if (!value)
376 return -EINVAL;
377
378 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
379 if (ihp) {
380 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
381 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
382 }
383 return 0;
384 }
385
386 static unsigned int __init intc_get_reg(struct intc_desc_int *d,
387 unsigned long address)
388 {
389 unsigned int k;
390
391 for (k = 0; k < d->nr_reg; k++) {
392 if (d->reg[k] == address)
393 return k;
394 }
395
396 BUG();
397 return 0;
398 }
399
400 static intc_enum __init intc_grp_id(struct intc_desc *desc,
401 intc_enum enum_id)
402 {
403 struct intc_group *g = desc->groups;
404 unsigned int i, j;
405
406 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
407 g = desc->groups + i;
408
409 for (j = 0; g->enum_ids[j]; j++) {
410 if (g->enum_ids[j] != enum_id)
411 continue;
412
413 return g->enum_id;
414 }
415 }
416
417 return 0;
418 }
419
420 static unsigned int __init intc_mask_data(struct intc_desc *desc,
421 struct intc_desc_int *d,
422 intc_enum enum_id, int do_grps)
423 {
424 struct intc_mask_reg *mr = desc->mask_regs;
425 unsigned int i, j, fn, mode;
426 unsigned long reg_e, reg_d;
427
428 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
429 mr = desc->mask_regs + i;
430
431 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
432 if (mr->enum_ids[j] != enum_id)
433 continue;
434
435 if (mr->set_reg && mr->clr_reg) {
436 fn = REG_FN_WRITE_BASE;
437 mode = MODE_DUAL_REG;
438 reg_e = mr->clr_reg;
439 reg_d = mr->set_reg;
440 } else {
441 fn = REG_FN_MODIFY_BASE;
442 if (mr->set_reg) {
443 mode = MODE_ENABLE_REG;
444 reg_e = mr->set_reg;
445 reg_d = mr->set_reg;
446 } else {
447 mode = MODE_MASK_REG;
448 reg_e = mr->clr_reg;
449 reg_d = mr->clr_reg;
450 }
451 }
452
453 fn += (mr->reg_width >> 3) - 1;
454 return _INTC_MK(fn, mode,
455 intc_get_reg(d, reg_e),
456 intc_get_reg(d, reg_d),
457 1,
458 (mr->reg_width - 1) - j);
459 }
460 }
461
462 if (do_grps)
463 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
464
465 return 0;
466 }
467
468 static unsigned int __init intc_prio_data(struct intc_desc *desc,
469 struct intc_desc_int *d,
470 intc_enum enum_id, int do_grps)
471 {
472 struct intc_prio_reg *pr = desc->prio_regs;
473 unsigned int i, j, fn, mode, bit;
474 unsigned long reg_e, reg_d;
475
476 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
477 pr = desc->prio_regs + i;
478
479 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
480 if (pr->enum_ids[j] != enum_id)
481 continue;
482
483 if (pr->set_reg && pr->clr_reg) {
484 fn = REG_FN_WRITE_BASE;
485 mode = MODE_PCLR_REG;
486 reg_e = pr->set_reg;
487 reg_d = pr->clr_reg;
488 } else {
489 fn = REG_FN_MODIFY_BASE;
490 mode = MODE_PRIO_REG;
491 if (!pr->set_reg)
492 BUG();
493 reg_e = pr->set_reg;
494 reg_d = pr->set_reg;
495 }
496
497 fn += (pr->reg_width >> 3) - 1;
498
499 BUG_ON((j + 1) * pr->field_width > pr->reg_width);
500
501 bit = pr->reg_width - ((j + 1) * pr->field_width);
502
503 return _INTC_MK(fn, mode,
504 intc_get_reg(d, reg_e),
505 intc_get_reg(d, reg_d),
506 pr->field_width, bit);
507 }
508 }
509
510 if (do_grps)
511 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
512
513 return 0;
514 }
515
516 static unsigned int __init intc_ack_data(struct intc_desc *desc,
517 struct intc_desc_int *d,
518 intc_enum enum_id)
519 {
520 struct intc_mask_reg *mr = desc->ack_regs;
521 unsigned int i, j, fn, mode;
522 unsigned long reg_e, reg_d;
523
524 for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
525 mr = desc->ack_regs + i;
526
527 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
528 if (mr->enum_ids[j] != enum_id)
529 continue;
530
531 fn = REG_FN_MODIFY_BASE;
532 mode = MODE_ENABLE_REG;
533 reg_e = mr->set_reg;
534 reg_d = mr->set_reg;
535
536 fn += (mr->reg_width >> 3) - 1;
537 return _INTC_MK(fn, mode,
538 intc_get_reg(d, reg_e),
539 intc_get_reg(d, reg_d),
540 1,
541 (mr->reg_width - 1) - j);
542 }
543 }
544
545 return 0;
546 }
547
548 static unsigned int __init intc_sense_data(struct intc_desc *desc,
549 struct intc_desc_int *d,
550 intc_enum enum_id)
551 {
552 struct intc_sense_reg *sr = desc->sense_regs;
553 unsigned int i, j, fn, bit;
554
555 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
556 sr = desc->sense_regs + i;
557
558 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
559 if (sr->enum_ids[j] != enum_id)
560 continue;
561
562 fn = REG_FN_MODIFY_BASE;
563 fn += (sr->reg_width >> 3) - 1;
564
565 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
566
567 bit = sr->reg_width - ((j + 1) * sr->field_width);
568
569 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
570 0, sr->field_width, bit);
571 }
572 }
573
574 return 0;
575 }
576
577 static void __init intc_register_irq(struct intc_desc *desc,
578 struct intc_desc_int *d,
579 intc_enum enum_id,
580 unsigned int irq)
581 {
582 struct intc_handle_int *hp;
583 unsigned int data[2], primary;
584
585 /*
586 * Register the IRQ position with the global IRQ map
587 */
588 set_bit(irq, intc_irq_map);
589
590 /* Prefer single interrupt source bitmap over other combinations:
591 * 1. bitmap, single interrupt source
592 * 2. priority, single interrupt source
593 * 3. bitmap, multiple interrupt sources (groups)
594 * 4. priority, multiple interrupt sources (groups)
595 */
596
597 data[0] = intc_mask_data(desc, d, enum_id, 0);
598 data[1] = intc_prio_data(desc, d, enum_id, 0);
599
600 primary = 0;
601 if (!data[0] && data[1])
602 primary = 1;
603
604 if (!data[0] && !data[1])
605 pr_warning("intc: missing unique irq mask for "
606 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
607
608 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
609 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
610
611 if (!data[primary])
612 primary ^= 1;
613
614 BUG_ON(!data[primary]); /* must have primary masking method */
615
616 disable_irq_nosync(irq);
617 set_irq_chip_and_handler_name(irq, &d->chip,
618 handle_level_irq, "level");
619 set_irq_chip_data(irq, (void *)data[primary]);
620
621 /* set priority level
622 * - this needs to be at least 2 for 5-bit priorities on 7780
623 */
624 intc_prio_level[irq] = 2;
625
626 /* enable secondary masking method if present */
627 if (data[!primary])
628 _intc_enable(irq, data[!primary]);
629
630 /* add irq to d->prio list if priority is available */
631 if (data[1]) {
632 hp = d->prio + d->nr_prio;
633 hp->irq = irq;
634 hp->handle = data[1];
635
636 if (primary) {
637 /*
638 * only secondary priority should access registers, so
639 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
640 */
641
642 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
643 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
644 }
645 d->nr_prio++;
646 }
647
648 /* add irq to d->sense list if sense is available */
649 data[0] = intc_sense_data(desc, d, enum_id);
650 if (data[0]) {
651 (d->sense + d->nr_sense)->irq = irq;
652 (d->sense + d->nr_sense)->handle = data[0];
653 d->nr_sense++;
654 }
655
656 /* irq should be disabled by default */
657 d->chip.mask(irq);
658
659 if (desc->ack_regs)
660 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
661
662 #ifdef CONFIG_ARM
663 set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
664 #endif
665 }
666
667 static unsigned int __init save_reg(struct intc_desc_int *d,
668 unsigned int cnt,
669 unsigned long value,
670 unsigned int smp)
671 {
672 if (value) {
673 d->reg[cnt] = value;
674 #ifdef CONFIG_SMP
675 d->smp[cnt] = smp;
676 #endif
677 return 1;
678 }
679
680 return 0;
681 }
682
683 static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
684 {
685 generic_handle_irq((unsigned int)get_irq_data(irq));
686 }
687
688 void __init register_intc_controller(struct intc_desc *desc)
689 {
690 unsigned int i, k, smp;
691 struct intc_desc_int *d;
692
693 d = kzalloc(sizeof(*d), GFP_NOWAIT);
694
695 INIT_LIST_HEAD(&d->list);
696 list_add(&d->list, &intc_list);
697
698 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
699 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
700 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
701 d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
702
703 d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
704 #ifdef CONFIG_SMP
705 d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
706 #endif
707 k = 0;
708
709 if (desc->mask_regs) {
710 for (i = 0; i < desc->nr_mask_regs; i++) {
711 smp = IS_SMP(desc->mask_regs[i]);
712 k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
713 k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
714 }
715 }
716
717 if (desc->prio_regs) {
718 d->prio = kzalloc(desc->nr_vectors * sizeof(*d->prio), GFP_NOWAIT);
719
720 for (i = 0; i < desc->nr_prio_regs; i++) {
721 smp = IS_SMP(desc->prio_regs[i]);
722 k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
723 k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
724 }
725 }
726
727 if (desc->sense_regs) {
728 d->sense = kzalloc(desc->nr_vectors * sizeof(*d->sense), GFP_NOWAIT);
729
730 for (i = 0; i < desc->nr_sense_regs; i++) {
731 k += save_reg(d, k, desc->sense_regs[i].reg, 0);
732 }
733 }
734
735 d->chip.name = desc->name;
736 d->chip.mask = intc_disable;
737 d->chip.unmask = intc_enable;
738 d->chip.mask_ack = intc_disable;
739 d->chip.enable = intc_enable;
740 d->chip.disable = intc_disable;
741 d->chip.shutdown = intc_disable;
742 d->chip.set_type = intc_set_sense;
743 d->chip.set_wake = intc_set_wake;
744
745 if (desc->ack_regs) {
746 for (i = 0; i < desc->nr_ack_regs; i++)
747 k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
748
749 d->chip.mask_ack = intc_mask_ack;
750 }
751
752 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
753
754 /* register the vectors one by one */
755 for (i = 0; i < desc->nr_vectors; i++) {
756 struct intc_vect *vect = desc->vectors + i;
757 unsigned int irq = evt2irq(vect->vect);
758 struct irq_desc *irq_desc;
759
760 if (!vect->enum_id)
761 continue;
762
763 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
764 if (unlikely(!irq_desc)) {
765 pr_info("can't get irq_desc for %d\n", irq);
766 continue;
767 }
768
769 intc_register_irq(desc, d, vect->enum_id, irq);
770
771 for (k = i + 1; k < desc->nr_vectors; k++) {
772 struct intc_vect *vect2 = desc->vectors + k;
773 unsigned int irq2 = evt2irq(vect2->vect);
774
775 if (vect->enum_id != vect2->enum_id)
776 continue;
777
778 /*
779 * In the case of multi-evt handling and sparse
780 * IRQ support, each vector still needs to have
781 * its own backing irq_desc.
782 */
783 irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id());
784 if (unlikely(!irq_desc)) {
785 pr_info("can't get irq_desc for %d\n", irq2);
786 continue;
787 }
788
789 vect2->enum_id = 0;
790
791 /* redirect this interrupts to the first one */
792 set_irq_chip_and_handler_name(irq2, &d->chip,
793 intc_redirect_irq, "redirect");
794 set_irq_data(irq2, (void *)irq);
795 }
796 }
797 }
798
799 static int intc_suspend(struct sys_device *dev, pm_message_t state)
800 {
801 struct intc_desc_int *d;
802 struct irq_desc *desc;
803 int irq;
804
805 /* get intc controller associated with this sysdev */
806 d = container_of(dev, struct intc_desc_int, sysdev);
807
808 switch (state.event) {
809 case PM_EVENT_ON:
810 if (d->state.event != PM_EVENT_FREEZE)
811 break;
812 for_each_irq_desc(irq, desc) {
813 if (desc->handle_irq == intc_redirect_irq)
814 continue;
815 if (desc->chip != &d->chip)
816 continue;
817 if (desc->status & IRQ_DISABLED)
818 intc_disable(irq);
819 else
820 intc_enable(irq);
821 }
822 break;
823 case PM_EVENT_FREEZE:
824 /* nothing has to be done */
825 break;
826 case PM_EVENT_SUSPEND:
827 /* enable wakeup irqs belonging to this intc controller */
828 for_each_irq_desc(irq, desc) {
829 if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
830 intc_enable(irq);
831 }
832 break;
833 }
834 d->state = state;
835
836 return 0;
837 }
838
839 static int intc_resume(struct sys_device *dev)
840 {
841 return intc_suspend(dev, PMSG_ON);
842 }
843
844 static struct sysdev_class intc_sysdev_class = {
845 .name = "intc",
846 .suspend = intc_suspend,
847 .resume = intc_resume,
848 };
849
850 /* register this intc as sysdev to allow suspend/resume */
851 static int __init register_intc_sysdevs(void)
852 {
853 struct intc_desc_int *d;
854 int error;
855 int id = 0;
856
857 error = sysdev_class_register(&intc_sysdev_class);
858 if (!error) {
859 list_for_each_entry(d, &intc_list, list) {
860 d->sysdev.id = id;
861 d->sysdev.cls = &intc_sysdev_class;
862 error = sysdev_register(&d->sysdev);
863 if (error)
864 break;
865 id++;
866 }
867 }
868
869 if (error)
870 pr_warning("intc: sysdev registration error\n");
871
872 return error;
873 }
874 device_initcall(register_intc_sysdevs);
875
876 /*
877 * Dynamic IRQ allocation and deallocation
878 */
879 static unsigned int create_irq_on_node(unsigned int irq_want, int node)
880 {
881 unsigned int irq = 0, new;
882 unsigned long flags;
883 struct irq_desc *desc;
884
885 spin_lock_irqsave(&vector_lock, flags);
886
887 /*
888 * First try the wanted IRQ, then scan.
889 */
890 if (test_and_set_bit(irq_want, intc_irq_map)) {
891 new = find_first_zero_bit(intc_irq_map, nr_irqs);
892 if (unlikely(new == nr_irqs))
893 goto out_unlock;
894
895 desc = irq_to_desc_alloc_node(new, node);
896 if (unlikely(!desc)) {
897 pr_info("can't get irq_desc for %d\n", new);
898 goto out_unlock;
899 }
900
901 desc = move_irq_desc(desc, node);
902 __set_bit(new, intc_irq_map);
903 irq = new;
904 }
905
906 out_unlock:
907 spin_unlock_irqrestore(&vector_lock, flags);
908
909 if (irq > 0) {
910 dynamic_irq_init(irq);
911 #ifdef CONFIG_ARM
912 set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */
913 #endif
914 }
915
916 return irq;
917 }
918
919 int create_irq(void)
920 {
921 int nid = cpu_to_node(smp_processor_id());
922 int irq;
923
924 irq = create_irq_on_node(NR_IRQS_LEGACY, nid);
925 if (irq == 0)
926 irq = -1;
927
928 return irq;
929 }
930
931 void destroy_irq(unsigned int irq)
932 {
933 unsigned long flags;
934
935 dynamic_irq_cleanup(irq);
936
937 spin_lock_irqsave(&vector_lock, flags);
938 __clear_bit(irq, intc_irq_map);
939 spin_unlock_irqrestore(&vector_lock, flags);
940 }
941
942 int reserve_irq_vector(unsigned int irq)
943 {
944 unsigned long flags;
945 int ret = 0;
946
947 spin_lock_irqsave(&vector_lock, flags);
948 if (test_and_set_bit(irq, intc_irq_map))
949 ret = -EBUSY;
950 spin_unlock_irqrestore(&vector_lock, flags);
951
952 return ret;
953 }
954
955 void reserve_irq_legacy(void)
956 {
957 unsigned long flags;
958 int i, j;
959
960 spin_lock_irqsave(&vector_lock, flags);
961 j = find_first_bit(intc_irq_map, nr_irqs);
962 for (i = 0; i < j; i++)
963 __set_bit(i, intc_irq_map);
964 spin_unlock_irqrestore(&vector_lock, flags);
965 }
Linux kernel - Deliverables
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