drivers/sh/pfc/core.c

   1 /*
   2  * SuperH Pin Function Controller support.
   3  *
   4  * Copyright (C) 2008 Magnus Damm
   5  * Copyright (C) 2009 - 2012 Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11
  12 #define DRV_NAME "sh-pfc"
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/errno.h>
  16 #include <linux/kernel.h>
  17 #include <linux/sh_pfc.h>
  18 #include <linux/module.h>
  19 #include <linux/err.h>
  20 #include <linux/io.h>
  21 #include <linux/bitops.h>
  22 #include <linux/slab.h>
  23 #include <linux/ioport.h>
  24 #include <linux/pinctrl/machine.h>
  25 #include <linux/platform_device.h>
  26
  27 #include "core.h"
  28
  29 static void pfc_iounmap(struct sh_pfc *pfc)
  30 {
  31         int k;
  32
  33         for (k = 0; k < pfc->pdata->num_resources; k++)
  34                 if (pfc->window[k].virt)
  35                         iounmap(pfc->window[k].virt);
  36 }
  37
  38 static int pfc_ioremap(struct sh_pfc *pfc)
  39 {
  40         struct resource *res;
  41         int k;
  42
  43         if (!pfc->pdata->num_resources)
  44                 return 0;
  45
  46         pfc->window = devm_kzalloc(pfc->dev, pfc->pdata->num_resources *
  47                                    sizeof(*pfc->window), GFP_NOWAIT);
  48         if (!pfc->window)
  49                 return -ENOMEM;
  50
  51         for (k = 0; k < pfc->pdata->num_resources; k++) {
  52                 res = pfc->pdata->resource + k;
  53                 WARN_ON(resource_type(res) != IORESOURCE_MEM);
  54                 pfc->window[k].phys = res->start;
  55                 pfc->window[k].size = resource_size(res);
  56                 pfc->window[k].virt = ioremap_nocache(res->start,
  57                                                          resource_size(res));
  58                 if (!pfc->window[k].virt) {
  59                         pfc_iounmap(pfc);
  60                         return -ENOMEM;
  61                 }
  62         }
  63
  64         return 0;
  65 }
  66
  67 static void __iomem *pfc_phys_to_virt(struct sh_pfc *pfc,
  68                                       unsigned long address)
  69 {
  70         struct pfc_window *window;
  71         int k;
  72
  73         /* scan through physical windows and convert address */
  74         for (k = 0; k < pfc->pdata->num_resources; k++) {
  75                 window = pfc->window + k;
  76
  77                 if (address < window->phys)
  78                         continue;
  79
  80                 if (address >= (window->phys + window->size))
  81                         continue;
  82
  83                 return window->virt + (address - window->phys);
  84         }
  85
  86         /* no windows defined, register must be 1:1 mapped virt:phys */
  87         return (void __iomem *)address;
  88 }
  89
  90 static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
  91 {
  92         if (enum_id < r->begin)
  93                 return 0;
  94
  95         if (enum_id > r->end)
  96                 return 0;
  97
  98         return 1;
  99 }
 100
 101 static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
 102                                        unsigned long reg_width)
 103 {
 104         switch (reg_width) {
 105         case 8:
 106                 return ioread8(mapped_reg);
 107         case 16:
 108                 return ioread16(mapped_reg);
 109         case 32:
 110                 return ioread32(mapped_reg);
 111         }
 112
 113         BUG();
 114         return 0;
 115 }
 116
 117 static void gpio_write_raw_reg(void __iomem *mapped_reg,
 118                                unsigned long reg_width,
 119                                unsigned long data)
 120 {
 121         switch (reg_width) {
 122         case 8:
 123                 iowrite8(data, mapped_reg);
 124                 return;
 125         case 16:
 126                 iowrite16(data, mapped_reg);
 127                 return;
 128         case 32:
 129                 iowrite32(data, mapped_reg);
 130                 return;
 131         }
 132
 133         BUG();
 134 }
 135
 136 int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
 137 {
 138         unsigned long pos;
 139
 140         pos = dr->reg_width - (in_pos + 1);
 141
 142         pr_debug("read_bit: addr = %lx, pos = %ld, "
 143                  "r_width = %ld\n", dr->reg, pos, dr->reg_width);
 144
 145         return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
 146 }
 147
 148 void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
 149                       unsigned long value)
 150 {
 151         unsigned long pos;
 152
 153         pos = dr->reg_width - (in_pos + 1);
 154
 155         pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
 156                  "r_width = %ld\n",
 157                  dr->reg, !!value, pos, dr->reg_width);
 158
 159         if (value)
 160                 set_bit(pos, &dr->reg_shadow);
 161         else
 162                 clear_bit(pos, &dr->reg_shadow);
 163
 164         gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
 165 }
 166
 167 static void config_reg_helper(struct sh_pfc *pfc,
 168                               struct pinmux_cfg_reg *crp,
 169                               unsigned long in_pos,
 170                               void __iomem **mapped_regp,
 171                               unsigned long *maskp,
 172                               unsigned long *posp)
 173 {
 174         int k;
 175
 176         *mapped_regp = pfc_phys_to_virt(pfc, crp->reg);
 177
 178         if (crp->field_width) {
 179                 *maskp = (1 << crp->field_width) - 1;
 180                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 181         } else {
 182                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 183                 *posp = crp->reg_width;
 184                 for (k = 0; k <= in_pos; k++)
 185                         *posp -= crp->var_field_width[k];
 186         }
 187 }
 188
 189 static int read_config_reg(struct sh_pfc *pfc,
 190                            struct pinmux_cfg_reg *crp,
 191                            unsigned long field)
 192 {
 193         void __iomem *mapped_reg;
 194         unsigned long mask, pos;
 195
 196         config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 197
 198         pr_debug("read_reg: addr = %lx, field = %ld, "
 199                  "r_width = %ld, f_width = %ld\n",
 200                  crp->reg, field, crp->reg_width, crp->field_width);
 201
 202         return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
 203 }
 204
 205 static void write_config_reg(struct sh_pfc *pfc,
 206                              struct pinmux_cfg_reg *crp,
 207                              unsigned long field, unsigned long value)
 208 {
 209         void __iomem *mapped_reg;
 210         unsigned long mask, pos, data;
 211
 212         config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 213
 214         pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
 215                  "r_width = %ld, f_width = %ld\n",
 216                  crp->reg, value, field, crp->reg_width, crp->field_width);
 217
 218         mask = ~(mask << pos);
 219         value = value << pos;
 220
 221         data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
 222         data &= mask;
 223         data |= value;
 224
 225         if (pfc->pdata->unlock_reg)
 226                 gpio_write_raw_reg(pfc_phys_to_virt(pfc, pfc->pdata->unlock_reg),
 227                                    32, ~data);
 228
 229         gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
 230 }
 231
 232 static int setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
 233 {
 234         struct pinmux_gpio *gpiop = &pfc->pdata->gpios[gpio];
 235         struct pinmux_data_reg *data_reg;
 236         int k, n;
 237
 238         if (!enum_in_range(gpiop->enum_id, &pfc->pdata->data))
 239                 return -1;
 240
 241         k = 0;
 242         while (1) {
 243                 data_reg = pfc->pdata->data_regs + k;
 244
 245                 if (!data_reg->reg_width)
 246                         break;
 247
 248                 data_reg->mapped_reg = pfc_phys_to_virt(pfc, data_reg->reg);
 249
 250                 for (n = 0; n < data_reg->reg_width; n++) {
 251                         if (data_reg->enum_ids[n] == gpiop->enum_id) {
 252                                 gpiop->flags &= ~PINMUX_FLAG_DREG;
 253                                 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
 254                                 gpiop->flags &= ~PINMUX_FLAG_DBIT;
 255                                 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
 256                                 return 0;
 257                         }
 258                 }
 259                 k++;
 260         }
 261
 262         BUG();
 263
 264         return -1;
 265 }
 266
 267 static void setup_data_regs(struct sh_pfc *pfc)
 268 {
 269         struct pinmux_data_reg *drp;
 270         int k;
 271
 272         for (k = pfc->pdata->first_gpio; k <= pfc->pdata->last_gpio; k++)
 273                 setup_data_reg(pfc, k);
 274
 275         k = 0;
 276         while (1) {
 277                 drp = pfc->pdata->data_regs + k;
 278
 279                 if (!drp->reg_width)
 280                         break;
 281
 282                 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
 283                                                     drp->reg_width);
 284                 k++;
 285         }
 286 }
 287
 288 int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
 289                         struct pinmux_data_reg **drp, int *bitp)
 290 {
 291         struct pinmux_gpio *gpiop = &pfc->pdata->gpios[gpio];
 292         int k, n;
 293
 294         if (!enum_in_range(gpiop->enum_id, &pfc->pdata->data))
 295                 return -1;
 296
 297         k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
 298         n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
 299         *drp = pfc->pdata->data_regs + k;
 300         *bitp = n;
 301         return 0;
 302 }
 303
 304 static int get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
 305                           struct pinmux_cfg_reg **crp,
 306                           int *fieldp, int *valuep,
 307                           unsigned long **cntp)
 308 {
 309         struct pinmux_cfg_reg *config_reg;
 310         unsigned long r_width, f_width, curr_width, ncomb;
 311         int k, m, n, pos, bit_pos;
 312
 313         k = 0;
 314         while (1) {
 315                 config_reg = pfc->pdata->cfg_regs + k;
 316
 317                 r_width = config_reg->reg_width;
 318                 f_width = config_reg->field_width;
 319
 320                 if (!r_width)
 321                         break;
 322
 323                 pos = 0;
 324                 m = 0;
 325                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 326                         if (f_width)
 327                                 curr_width = f_width;
 328                         else
 329                                 curr_width = config_reg->var_field_width[m];
 330
 331                         ncomb = 1 << curr_width;
 332                         for (n = 0; n < ncomb; n++) {
 333                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 334                                         *crp = config_reg;
 335                                         *fieldp = m;
 336                                         *valuep = n;
 337                                         *cntp = &config_reg->cnt[m];
 338                                         return 0;
 339                                 }
 340                         }
 341                         pos += ncomb;
 342                         m++;
 343                 }
 344                 k++;
 345         }
 346
 347         return -1;
 348 }
 349
 350 int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
 351                         pinmux_enum_t *enum_idp)
 352 {
 353         pinmux_enum_t enum_id = pfc->pdata->gpios[gpio].enum_id;
 354         pinmux_enum_t *data = pfc->pdata->gpio_data;
 355         int k;
 356
 357         if (!enum_in_range(enum_id, &pfc->pdata->data)) {
 358                 if (!enum_in_range(enum_id, &pfc->pdata->mark)) {
 359                         pr_err("non data/mark enum_id for gpio %d\n", gpio);
 360                         return -1;
 361                 }
 362         }
 363
 364         if (pos) {
 365                 *enum_idp = data[pos + 1];
 366                 return pos + 1;
 367         }
 368
 369         for (k = 0; k < pfc->pdata->gpio_data_size; k++) {
 370                 if (data[k] == enum_id) {
 371                         *enum_idp = data[k + 1];
 372                         return k + 1;
 373                 }
 374         }
 375
 376         pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
 377         return -1;
 378 }
 379
 380 int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
 381                        int cfg_mode)
 382 {
 383         struct pinmux_cfg_reg *cr = NULL;
 384         pinmux_enum_t enum_id;
 385         struct pinmux_range *range;
 386         int in_range, pos, field, value;
 387         unsigned long *cntp;
 388
 389         switch (pinmux_type) {
 390
 391         case PINMUX_TYPE_FUNCTION:
 392                 range = NULL;
 393                 break;
 394
 395         case PINMUX_TYPE_OUTPUT:
 396                 range = &pfc->pdata->output;
 397                 break;
 398
 399         case PINMUX_TYPE_INPUT:
 400                 range = &pfc->pdata->input;
 401                 break;
 402
 403         case PINMUX_TYPE_INPUT_PULLUP:
 404                 range = &pfc->pdata->input_pu;
 405                 break;
 406
 407         case PINMUX_TYPE_INPUT_PULLDOWN:
 408                 range = &pfc->pdata->input_pd;
 409                 break;
 410
 411         default:
 412                 goto out_err;
 413         }
 414
 415         pos = 0;
 416         enum_id = 0;
 417         field = 0;
 418         value = 0;
 419         while (1) {
 420                 pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
 421                 if (pos <= 0)
 422                         goto out_err;
 423
 424                 if (!enum_id)
 425                         break;
 426
 427                 /* first check if this is a function enum */
 428                 in_range = enum_in_range(enum_id, &pfc->pdata->function);
 429                 if (!in_range) {
 430                         /* not a function enum */
 431                         if (range) {
 432                                 /*
 433                                  * other range exists, so this pin is
 434                                  * a regular GPIO pin that now is being
 435                                  * bound to a specific direction.
 436                                  *
 437                                  * for this case we only allow function enums
 438                                  * and the enums that match the other range.
 439                                  */
 440                                 in_range = enum_in_range(enum_id, range);
 441
 442                                 /*
 443                                  * special case pass through for fixed
 444                                  * input-only or output-only pins without
 445                                  * function enum register association.
 446                                  */
 447                                 if (in_range && enum_id == range->force)
 448                                         continue;
 449                         } else {
 450                                 /*
 451                                  * no other range exists, so this pin
 452                                  * must then be of the function type.
 453                                  *
 454                                  * allow function type pins to select
 455                                  * any combination of function/in/out
 456                                  * in their MARK lists.
 457                                  */
 458                                 in_range = 1;
 459                         }
 460                 }
 461
 462                 if (!in_range)
 463                         continue;
 464
 465                 if (get_config_reg(pfc, enum_id, &cr,
 466                                    &field, &value, &cntp) != 0)
 467                         goto out_err;
 468
 469                 switch (cfg_mode) {
 470                 case GPIO_CFG_DRYRUN:
 471                         if (!*cntp ||
 472                             (read_config_reg(pfc, cr, field) != value))
 473                                 continue;
 474                         break;
 475
 476                 case GPIO_CFG_REQ:
 477                         write_config_reg(pfc, cr, field, value);
 478                         *cntp = *cntp + 1;
 479                         break;
 480
 481                 case GPIO_CFG_FREE:
 482                         *cntp = *cntp - 1;
 483                         break;
 484                 }
 485         }
 486
 487         return 0;
 488  out_err:
 489         return -1;
 490 }
 491
 492 static int sh_pfc_probe(struct platform_device *pdev)
 493 {
 494         struct sh_pfc_platform_data *pdata = pdev->dev.platform_data;
 495         struct sh_pfc *pfc;
 496         int ret;
 497
 498         /*
 499          * Ensure that the type encoding fits
 500          */
 501         BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
 502
 503         if (pdata == NULL)
 504                 return -ENODEV;
 505
 506         pfc = devm_kzalloc(&pdev->dev, sizeof(pfc), GFP_KERNEL);
 507         if (pfc == NULL)
 508                 return -ENOMEM;
 509
 510         pfc->pdata = pdata;
 511         pfc->dev = &pdev->dev;
 512
 513         ret = pfc_ioremap(pfc);
 514         if (unlikely(ret < 0))
 515                 return ret;
 516
 517         spin_lock_init(&pfc->lock);
 518
 519         pinctrl_provide_dummies();
 520         setup_data_regs(pfc);
 521
 522         /*
 523          * Initialize pinctrl bindings first
 524          */
 525         ret = sh_pfc_register_pinctrl(pfc);
 526         if (unlikely(ret != 0))
 527                 goto err;
 528
 529 #ifdef CONFIG_GPIO_SH_PFC
 530         /*
 531          * Then the GPIO chip
 532          */
 533         ret = sh_pfc_register_gpiochip(pfc);
 534         if (unlikely(ret != 0)) {
 535                 /*
 536                  * If the GPIO chip fails to come up we still leave the
 537                  * PFC state as it is, given that there are already
 538                  * extant users of it that have succeeded by this point.
 539                  */
 540                 pr_notice("failed to init GPIO chip, ignoring...\n");
 541         }
 542 #endif
 543
 544         platform_set_drvdata(pdev, pfc);
 545
 546         pr_info("%s support registered\n", pdata->name);
 547
 548         return 0;
 549
 550 err:
 551         pfc_iounmap(pfc);
 552         return ret;
 553 }
 554
 555 static int sh_pfc_remove(struct platform_device *pdev)
 556 {
 557         struct sh_pfc *pfc = platform_get_drvdata(pdev);
 558
 559 #ifdef CONFIG_GPIO_SH_PFC
 560         sh_pfc_unregister_gpiochip(pfc);
 561 #endif
 562         sh_pfc_unregister_pinctrl(pfc);
 563
 564         pfc_iounmap(pfc);
 565
 566         platform_set_drvdata(pdev, NULL);
 567
 568         return 0;
 569 }
 570
 571 static const struct platform_device_id sh_pfc_id_table[] = {
 572         { "sh-pfc", 0 },
 573         { },
 574 };
 575 MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
 576
 577 static struct platform_driver sh_pfc_driver = {
 578         .probe          = sh_pfc_probe,
 579         .remove         = sh_pfc_remove,
 580         .id_table       = sh_pfc_id_table,
 581         .driver         = {
 582                 .name   = DRV_NAME,
 583                 .owner  = THIS_MODULE,
 584         },
 585 };
 586
 587 static struct platform_device sh_pfc_device = {
 588         .name           = DRV_NAME,
 589         .id             = -1,
 590 };
 591
 592 int __init register_sh_pfc(struct sh_pfc_platform_data *pdata)
 593 {
 594         int rc;
 595
 596         sh_pfc_device.dev.platform_data = pdata;
 597
 598         rc = platform_driver_register(&sh_pfc_driver);
 599         if (likely(!rc)) {
 600                 rc = platform_device_register(&sh_pfc_device);
 601                 if (unlikely(rc))
 602                         platform_driver_unregister(&sh_pfc_driver);
 603         }
 604
 605         return rc;
 606 }
 607
 608 static void __exit sh_pfc_exit(void)
 609 {
 610         platform_driver_unregister(&sh_pfc_driver);
 611 }
 612 module_exit(sh_pfc_exit);
 613
 614 MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
 615 MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
 616 MODULE_LICENSE("GPL v2");