drivers/sh/pfc/core.c

   1 /*
   2  * SuperH Pin Function Controller support.
   3  *
   4  * Copyright (C) 2008 Magnus Damm
   5  * Copyright (C) 2009 - 2012 Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #define pr_fmt(fmt) "sh_pfc " KBUILD_MODNAME ": " fmt
  12
  13 #include <linux/errno.h>
  14 #include <linux/kernel.h>
  15 #include <linux/sh_pfc.h>
  16 #include <linux/module.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/bitops.h>
  20 #include <linux/slab.h>
  21 #include <linux/ioport.h>
  22 #include <linux/pinctrl/machine.h>
  23
  24 static struct sh_pfc sh_pfc __read_mostly;
  25
  26 static void pfc_iounmap(struct sh_pfc *pfc)
  27 {
  28         int k;
  29
  30         for (k = 0; k < pfc->pdata->num_resources; k++)
  31                 if (pfc->window[k].virt)
  32                         iounmap(pfc->window[k].virt);
  33
  34         kfree(pfc->window);
  35         pfc->window = NULL;
  36 }
  37
  38 static int pfc_ioremap(struct sh_pfc *pfc)
  39 {
  40         struct resource *res;
  41         int k;
  42
  43         if (!pfc->pdata->num_resources)
  44                 return 0;
  45
  46         pfc->window = kzalloc(pfc->pdata->num_resources * sizeof(*pfc->window),
  47                               GFP_NOWAIT);
  48         if (!pfc->window)
  49                 goto err1;
  50
  51         for (k = 0; k < pfc->pdata->num_resources; k++) {
  52                 res = pfc->pdata->resource + k;
  53                 WARN_ON(resource_type(res) != IORESOURCE_MEM);
  54                 pfc->window[k].phys = res->start;
  55                 pfc->window[k].size = resource_size(res);
  56                 pfc->window[k].virt = ioremap_nocache(res->start,
  57                                                          resource_size(res));
  58                 if (!pfc->window[k].virt)
  59                         goto err2;
  60         }
  61
  62         return 0;
  63
  64 err2:
  65         pfc_iounmap(pfc);
  66 err1:
  67         return -1;
  68 }
  69
  70 static void __iomem *pfc_phys_to_virt(struct sh_pfc *pfc,
  71                                       unsigned long address)
  72 {
  73         struct pfc_window *window;
  74         int k;
  75
  76         /* scan through physical windows and convert address */
  77         for (k = 0; k < pfc->pdata->num_resources; k++) {
  78                 window = pfc->window + k;
  79
  80                 if (address < window->phys)
  81                         continue;
  82
  83                 if (address >= (window->phys + window->size))
  84                         continue;
  85
  86                 return window->virt + (address - window->phys);
  87         }
  88
  89         /* no windows defined, register must be 1:1 mapped virt:phys */
  90         return (void __iomem *)address;
  91 }
  92
  93 static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
  94 {
  95         if (enum_id < r->begin)
  96                 return 0;
  97
  98         if (enum_id > r->end)
  99                 return 0;
 100
 101         return 1;
 102 }
 103
 104 static unsigned long gpio_read_raw_reg(void __iomem *mapped_reg,
 105                                        unsigned long reg_width)
 106 {
 107         switch (reg_width) {
 108         case 8:
 109                 return ioread8(mapped_reg);
 110         case 16:
 111                 return ioread16(mapped_reg);
 112         case 32:
 113                 return ioread32(mapped_reg);
 114         }
 115
 116         BUG();
 117         return 0;
 118 }
 119
 120 static void gpio_write_raw_reg(void __iomem *mapped_reg,
 121                                unsigned long reg_width,
 122                                unsigned long data)
 123 {
 124         switch (reg_width) {
 125         case 8:
 126                 iowrite8(data, mapped_reg);
 127                 return;
 128         case 16:
 129                 iowrite16(data, mapped_reg);
 130                 return;
 131         case 32:
 132                 iowrite32(data, mapped_reg);
 133                 return;
 134         }
 135
 136         BUG();
 137 }
 138
 139 int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
 140 {
 141         unsigned long pos;
 142
 143         pos = dr->reg_width - (in_pos + 1);
 144
 145         pr_debug("read_bit: addr = %lx, pos = %ld, "
 146                  "r_width = %ld\n", dr->reg, pos, dr->reg_width);
 147
 148         return (gpio_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
 149 }
 150 EXPORT_SYMBOL_GPL(sh_pfc_read_bit);
 151
 152 void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
 153                       unsigned long value)
 154 {
 155         unsigned long pos;
 156
 157         pos = dr->reg_width - (in_pos + 1);
 158
 159         pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
 160                  "r_width = %ld\n",
 161                  dr->reg, !!value, pos, dr->reg_width);
 162
 163         if (value)
 164                 set_bit(pos, &dr->reg_shadow);
 165         else
 166                 clear_bit(pos, &dr->reg_shadow);
 167
 168         gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
 169 }
 170 EXPORT_SYMBOL_GPL(sh_pfc_write_bit);
 171
 172 static void config_reg_helper(struct sh_pfc *pfc,
 173                               struct pinmux_cfg_reg *crp,
 174                               unsigned long in_pos,
 175                               void __iomem **mapped_regp,
 176                               unsigned long *maskp,
 177                               unsigned long *posp)
 178 {
 179         int k;
 180
 181         *mapped_regp = pfc_phys_to_virt(pfc, crp->reg);
 182
 183         if (crp->field_width) {
 184                 *maskp = (1 << crp->field_width) - 1;
 185                 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
 186         } else {
 187                 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
 188                 *posp = crp->reg_width;
 189                 for (k = 0; k <= in_pos; k++)
 190                         *posp -= crp->var_field_width[k];
 191         }
 192 }
 193
 194 static int read_config_reg(struct sh_pfc *pfc,
 195                            struct pinmux_cfg_reg *crp,
 196                            unsigned long field)
 197 {
 198         void __iomem *mapped_reg;
 199         unsigned long mask, pos;
 200
 201         config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 202
 203         pr_debug("read_reg: addr = %lx, field = %ld, "
 204                  "r_width = %ld, f_width = %ld\n",
 205                  crp->reg, field, crp->reg_width, crp->field_width);
 206
 207         return (gpio_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
 208 }
 209
 210 static void write_config_reg(struct sh_pfc *pfc,
 211                              struct pinmux_cfg_reg *crp,
 212                              unsigned long field, unsigned long value)
 213 {
 214         void __iomem *mapped_reg;
 215         unsigned long mask, pos, data;
 216
 217         config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
 218
 219         pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
 220                  "r_width = %ld, f_width = %ld\n",
 221                  crp->reg, value, field, crp->reg_width, crp->field_width);
 222
 223         mask = ~(mask << pos);
 224         value = value << pos;
 225
 226         data = gpio_read_raw_reg(mapped_reg, crp->reg_width);
 227         data &= mask;
 228         data |= value;
 229
 230         if (pfc->pdata->unlock_reg)
 231                 gpio_write_raw_reg(pfc_phys_to_virt(pfc, pfc->pdata->unlock_reg),
 232                                    32, ~data);
 233
 234         gpio_write_raw_reg(mapped_reg, crp->reg_width, data);
 235 }
 236
 237 static int setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
 238 {
 239         struct pinmux_gpio *gpiop = &pfc->pdata->gpios[gpio];
 240         struct pinmux_data_reg *data_reg;
 241         int k, n;
 242
 243         if (!enum_in_range(gpiop->enum_id, &pfc->pdata->data))
 244                 return -1;
 245
 246         k = 0;
 247         while (1) {
 248                 data_reg = pfc->pdata->data_regs + k;
 249
 250                 if (!data_reg->reg_width)
 251                         break;
 252
 253                 data_reg->mapped_reg = pfc_phys_to_virt(pfc, data_reg->reg);
 254
 255                 for (n = 0; n < data_reg->reg_width; n++) {
 256                         if (data_reg->enum_ids[n] == gpiop->enum_id) {
 257                                 gpiop->flags &= ~PINMUX_FLAG_DREG;
 258                                 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
 259                                 gpiop->flags &= ~PINMUX_FLAG_DBIT;
 260                                 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
 261                                 return 0;
 262                         }
 263                 }
 264                 k++;
 265         }
 266
 267         BUG();
 268
 269         return -1;
 270 }
 271
 272 static void setup_data_regs(struct sh_pfc *pfc)
 273 {
 274         struct pinmux_data_reg *drp;
 275         int k;
 276
 277         for (k = pfc->pdata->first_gpio; k <= pfc->pdata->last_gpio; k++)
 278                 setup_data_reg(pfc, k);
 279
 280         k = 0;
 281         while (1) {
 282                 drp = pfc->pdata->data_regs + k;
 283
 284                 if (!drp->reg_width)
 285                         break;
 286
 287                 drp->reg_shadow = gpio_read_raw_reg(drp->mapped_reg,
 288                                                     drp->reg_width);
 289                 k++;
 290         }
 291 }
 292
 293 int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
 294                         struct pinmux_data_reg **drp, int *bitp)
 295 {
 296         struct pinmux_gpio *gpiop = &pfc->pdata->gpios[gpio];
 297         int k, n;
 298
 299         if (!enum_in_range(gpiop->enum_id, &pfc->pdata->data))
 300                 return -1;
 301
 302         k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
 303         n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
 304         *drp = pfc->pdata->data_regs + k;
 305         *bitp = n;
 306         return 0;
 307 }
 308 EXPORT_SYMBOL_GPL(sh_pfc_get_data_reg);
 309
 310 static int get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
 311                           struct pinmux_cfg_reg **crp,
 312                           int *fieldp, int *valuep,
 313                           unsigned long **cntp)
 314 {
 315         struct pinmux_cfg_reg *config_reg;
 316         unsigned long r_width, f_width, curr_width, ncomb;
 317         int k, m, n, pos, bit_pos;
 318
 319         k = 0;
 320         while (1) {
 321                 config_reg = pfc->pdata->cfg_regs + k;
 322
 323                 r_width = config_reg->reg_width;
 324                 f_width = config_reg->field_width;
 325
 326                 if (!r_width)
 327                         break;
 328
 329                 pos = 0;
 330                 m = 0;
 331                 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
 332                         if (f_width)
 333                                 curr_width = f_width;
 334                         else
 335                                 curr_width = config_reg->var_field_width[m];
 336
 337                         ncomb = 1 << curr_width;
 338                         for (n = 0; n < ncomb; n++) {
 339                                 if (config_reg->enum_ids[pos + n] == enum_id) {
 340                                         *crp = config_reg;
 341                                         *fieldp = m;
 342                                         *valuep = n;
 343                                         *cntp = &config_reg->cnt[m];
 344                                         return 0;
 345                                 }
 346                         }
 347                         pos += ncomb;
 348                         m++;
 349                 }
 350                 k++;
 351         }
 352
 353         return -1;
 354 }
 355
 356 int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
 357                         pinmux_enum_t *enum_idp)
 358 {
 359         pinmux_enum_t enum_id = pfc->pdata->gpios[gpio].enum_id;
 360         pinmux_enum_t *data = pfc->pdata->gpio_data;
 361         int k;
 362
 363         if (!enum_in_range(enum_id, &pfc->pdata->data)) {
 364                 if (!enum_in_range(enum_id, &pfc->pdata->mark)) {
 365                         pr_err("non data/mark enum_id for gpio %d\n", gpio);
 366                         return -1;
 367                 }
 368         }
 369
 370         if (pos) {
 371                 *enum_idp = data[pos + 1];
 372                 return pos + 1;
 373         }
 374
 375         for (k = 0; k < pfc->pdata->gpio_data_size; k++) {
 376                 if (data[k] == enum_id) {
 377                         *enum_idp = data[k + 1];
 378                         return k + 1;
 379                 }
 380         }
 381
 382         pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
 383         return -1;
 384 }
 385 EXPORT_SYMBOL_GPL(sh_pfc_gpio_to_enum);
 386
 387 int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
 388                        int cfg_mode)
 389 {
 390         struct pinmux_cfg_reg *cr = NULL;
 391         pinmux_enum_t enum_id;
 392         struct pinmux_range *range;
 393         int in_range, pos, field, value;
 394         unsigned long *cntp;
 395
 396         switch (pinmux_type) {
 397
 398         case PINMUX_TYPE_FUNCTION:
 399                 range = NULL;
 400                 break;
 401
 402         case PINMUX_TYPE_OUTPUT:
 403                 range = &pfc->pdata->output;
 404                 break;
 405
 406         case PINMUX_TYPE_INPUT:
 407                 range = &pfc->pdata->input;
 408                 break;
 409
 410         case PINMUX_TYPE_INPUT_PULLUP:
 411                 range = &pfc->pdata->input_pu;
 412                 break;
 413
 414         case PINMUX_TYPE_INPUT_PULLDOWN:
 415                 range = &pfc->pdata->input_pd;
 416                 break;
 417
 418         default:
 419                 goto out_err;
 420         }
 421
 422         pos = 0;
 423         enum_id = 0;
 424         field = 0;
 425         value = 0;
 426         while (1) {
 427                 pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
 428                 if (pos <= 0)
 429                         goto out_err;
 430
 431                 if (!enum_id)
 432                         break;
 433
 434                 /* first check if this is a function enum */
 435                 in_range = enum_in_range(enum_id, &pfc->pdata->function);
 436                 if (!in_range) {
 437                         /* not a function enum */
 438                         if (range) {
 439                                 /*
 440                                  * other range exists, so this pin is
 441                                  * a regular GPIO pin that now is being
 442                                  * bound to a specific direction.
 443                                  *
 444                                  * for this case we only allow function enums
 445                                  * and the enums that match the other range.
 446                                  */
 447                                 in_range = enum_in_range(enum_id, range);
 448
 449                                 /*
 450                                  * special case pass through for fixed
 451                                  * input-only or output-only pins without
 452                                  * function enum register association.
 453                                  */
 454                                 if (in_range && enum_id == range->force)
 455                                         continue;
 456                         } else {
 457                                 /*
 458                                  * no other range exists, so this pin
 459                                  * must then be of the function type.
 460                                  *
 461                                  * allow function type pins to select
 462                                  * any combination of function/in/out
 463                                  * in their MARK lists.
 464                                  */
 465                                 in_range = 1;
 466                         }
 467                 }
 468
 469                 if (!in_range)
 470                         continue;
 471
 472                 if (get_config_reg(pfc, enum_id, &cr,
 473                                    &field, &value, &cntp) != 0)
 474                         goto out_err;
 475
 476                 switch (cfg_mode) {
 477                 case GPIO_CFG_DRYRUN:
 478                         if (!*cntp ||
 479                             (read_config_reg(pfc, cr, field) != value))
 480                                 continue;
 481                         break;
 482
 483                 case GPIO_CFG_REQ:
 484                         write_config_reg(pfc, cr, field, value);
 485                         *cntp = *cntp + 1;
 486                         break;
 487
 488                 case GPIO_CFG_FREE:
 489                         *cntp = *cntp - 1;
 490                         break;
 491                 }
 492         }
 493
 494         return 0;
 495  out_err:
 496         return -1;
 497 }
 498 EXPORT_SYMBOL_GPL(sh_pfc_config_gpio);
 499
 500 int register_sh_pfc(struct sh_pfc_platform_data *pdata)
 501 {
 502         int (*initroutine)(struct sh_pfc *) = NULL;
 503         int ret;
 504
 505         /*
 506          * Ensure that the type encoding fits
 507          */
 508         BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
 509
 510         if (sh_pfc.pdata)
 511                 return -EBUSY;
 512
 513         sh_pfc.pdata = pdata;
 514
 515         ret = pfc_ioremap(&sh_pfc);
 516         if (unlikely(ret < 0)) {
 517                 sh_pfc.pdata = NULL;
 518                 return ret;
 519         }
 520
 521         spin_lock_init(&sh_pfc.lock);
 522
 523         pinctrl_provide_dummies();
 524         setup_data_regs(&sh_pfc);
 525
 526         /*
 527          * Initialize pinctrl bindings first
 528          */
 529         initroutine = symbol_request(sh_pfc_register_pinctrl);
 530         if (initroutine) {
 531                 ret = (*initroutine)(&sh_pfc);
 532                 symbol_put_addr(initroutine);
 533
 534                 if (unlikely(ret != 0))
 535                         goto err;
 536         } else {
 537                 pr_err("failed to initialize pinctrl bindings\n");
 538                 goto err;
 539         }
 540
 541         /*
 542          * Then the GPIO chip
 543          */
 544         initroutine = symbol_request(sh_pfc_register_gpiochip);
 545         if (initroutine) {
 546                 ret = (*initroutine)(&sh_pfc);
 547                 symbol_put_addr(initroutine);
 548
 549                 /*
 550                  * If the GPIO chip fails to come up we still leave the
 551                  * PFC state as it is, given that there are already
 552                  * extant users of it that have succeeded by this point.
 553                  */
 554                 if (unlikely(ret != 0)) {
 555                         pr_notice("failed to init GPIO chip, ignoring...\n");
 556                         ret = 0;
 557                 }
 558         }
 559
 560         pr_info("%s support registered\n", sh_pfc.pdata->name);
 561
 562         return 0;
 563
 564 err:
 565         pfc_iounmap(&sh_pfc);
 566         sh_pfc.pdata = NULL;
 567
 568         return ret;
 569 }