projects / deliverable / linux.git / blob
? search:


0e4ebb84ee7f1474e58776b508040a70d24251c5
[deliverable/linux.git] / drivers / soc / mediatek / mtk-pmic-wrap.c
1 /*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Flora Fu, MediaTek
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14 #include <linux/clk.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23
24 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4
25 #define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10
26 #define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14
27 #define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24
28 #define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28
29 #define PWRAP_MT8135_BRIDGE_INT_EN 0x38
30 #define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48
31 #define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50
32 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54
33
34 /* macro for wrapper status */
35 #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff)
36 #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x00000007)
37 #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x00000001)
38 #define PWRAP_STATE_SYNC_IDLE0 (1 << 20)
39 #define PWRAP_STATE_INIT_DONE0 (1 << 21)
40
41 /* macro for WACS FSM */
42 #define PWRAP_WACS_FSM_IDLE 0x00
43 #define PWRAP_WACS_FSM_REQ 0x02
44 #define PWRAP_WACS_FSM_WFDLE 0x04
45 #define PWRAP_WACS_FSM_WFVLDCLR 0x06
46 #define PWRAP_WACS_INIT_DONE 0x01
47 #define PWRAP_WACS_WACS_SYNC_IDLE 0x01
48 #define PWRAP_WACS_SYNC_BUSY 0x00
49
50 /* macro for device wrapper default value */
51 #define PWRAP_DEW_READ_TEST_VAL 0x5aa5
52 #define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
53
54 /* macro for manual command */
55 #define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
56 #define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
57 #define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
58 #define PWRAP_MAN_CMD_OP_CK (0x2 << 8)
59 #define PWRAP_MAN_CMD_OP_OUTS (0x8 << 8)
60 #define PWRAP_MAN_CMD_OP_OUTD (0x9 << 8)
61 #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
62
63 /* macro for Watch Dog Timer Source */
64 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG (1 << 25)
65 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE (1 << 20)
66 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE (1 << 6)
67 #define PWRAP_WDT_SRC_MASK_ALL 0xffffffff
68 #define PWRAP_WDT_SRC_MASK_NO_STAUPD ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
69 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
70 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
71
72 /* defines for slave device wrapper registers */
73 enum dew_regs {
74 PWRAP_DEW_BASE,
75 PWRAP_DEW_DIO_EN,
76 PWRAP_DEW_READ_TEST,
77 PWRAP_DEW_WRITE_TEST,
78 PWRAP_DEW_CRC_EN,
79 PWRAP_DEW_CRC_VAL,
80 PWRAP_DEW_MON_GRP_SEL,
81 PWRAP_DEW_CIPHER_KEY_SEL,
82 PWRAP_DEW_CIPHER_IV_SEL,
83 PWRAP_DEW_CIPHER_RDY,
84 PWRAP_DEW_CIPHER_MODE,
85 PWRAP_DEW_CIPHER_SWRST,
86
87 /* MT6397 only regs */
88 PWRAP_DEW_EVENT_OUT_EN,
89 PWRAP_DEW_EVENT_SRC_EN,
90 PWRAP_DEW_EVENT_SRC,
91 PWRAP_DEW_EVENT_FLAG,
92 PWRAP_DEW_MON_FLAG_SEL,
93 PWRAP_DEW_EVENT_TEST,
94 PWRAP_DEW_CIPHER_LOAD,
95 PWRAP_DEW_CIPHER_START,
96
97 /* MT6323 only regs */
98 PWRAP_DEW_CIPHER_EN,
99 PWRAP_DEW_RDDMY_NO,
100 };
101
102 static const u32 mt6323_regs[] = {
103 [PWRAP_DEW_BASE] = 0x0000,
104 [PWRAP_DEW_DIO_EN] = 0x018a,
105 [PWRAP_DEW_READ_TEST] = 0x018c,
106 [PWRAP_DEW_WRITE_TEST] = 0x018e,
107 [PWRAP_DEW_CRC_EN] = 0x0192,
108 [PWRAP_DEW_CRC_VAL] = 0x0194,
109 [PWRAP_DEW_MON_GRP_SEL] = 0x0196,
110 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198,
111 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,
112 [PWRAP_DEW_CIPHER_EN] = 0x019c,
113 [PWRAP_DEW_CIPHER_RDY] = 0x019e,
114 [PWRAP_DEW_CIPHER_MODE] = 0x01a0,
115 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2,
116 [PWRAP_DEW_RDDMY_NO] = 0x01a4,
117 };
118
119 static const u32 mt6397_regs[] = {
120 [PWRAP_DEW_BASE] = 0xbc00,
121 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
122 [PWRAP_DEW_DIO_EN] = 0xbc02,
123 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
124 [PWRAP_DEW_EVENT_SRC] = 0xbc06,
125 [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
126 [PWRAP_DEW_READ_TEST] = 0xbc0a,
127 [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
128 [PWRAP_DEW_CRC_EN] = 0xbc0e,
129 [PWRAP_DEW_CRC_VAL] = 0xbc10,
130 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
131 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
132 [PWRAP_DEW_EVENT_TEST] = 0xbc16,
133 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
134 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
135 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
136 [PWRAP_DEW_CIPHER_START] = 0xbc1e,
137 [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
138 [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
139 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
140 };
141
142 enum pwrap_regs {
143 PWRAP_MUX_SEL,
144 PWRAP_WRAP_EN,
145 PWRAP_DIO_EN,
146 PWRAP_SIDLY,
147 PWRAP_CSHEXT_WRITE,
148 PWRAP_CSHEXT_READ,
149 PWRAP_CSLEXT_START,
150 PWRAP_CSLEXT_END,
151 PWRAP_STAUPD_PRD,
152 PWRAP_STAUPD_GRPEN,
153 PWRAP_STAUPD_MAN_TRIG,
154 PWRAP_STAUPD_STA,
155 PWRAP_WRAP_STA,
156 PWRAP_HARB_INIT,
157 PWRAP_HARB_HPRIO,
158 PWRAP_HIPRIO_ARB_EN,
159 PWRAP_HARB_STA0,
160 PWRAP_HARB_STA1,
161 PWRAP_MAN_EN,
162 PWRAP_MAN_CMD,
163 PWRAP_MAN_RDATA,
164 PWRAP_MAN_VLDCLR,
165 PWRAP_WACS0_EN,
166 PWRAP_INIT_DONE0,
167 PWRAP_WACS0_CMD,
168 PWRAP_WACS0_RDATA,
169 PWRAP_WACS0_VLDCLR,
170 PWRAP_WACS1_EN,
171 PWRAP_INIT_DONE1,
172 PWRAP_WACS1_CMD,
173 PWRAP_WACS1_RDATA,
174 PWRAP_WACS1_VLDCLR,
175 PWRAP_WACS2_EN,
176 PWRAP_INIT_DONE2,
177 PWRAP_WACS2_CMD,
178 PWRAP_WACS2_RDATA,
179 PWRAP_WACS2_VLDCLR,
180 PWRAP_INT_EN,
181 PWRAP_INT_FLG_RAW,
182 PWRAP_INT_FLG,
183 PWRAP_INT_CLR,
184 PWRAP_SIG_ADR,
185 PWRAP_SIG_MODE,
186 PWRAP_SIG_VALUE,
187 PWRAP_SIG_ERRVAL,
188 PWRAP_CRC_EN,
189 PWRAP_TIMER_EN,
190 PWRAP_TIMER_STA,
191 PWRAP_WDT_UNIT,
192 PWRAP_WDT_SRC_EN,
193 PWRAP_WDT_FLG,
194 PWRAP_DEBUG_INT_SEL,
195 PWRAP_CIPHER_KEY_SEL,
196 PWRAP_CIPHER_IV_SEL,
197 PWRAP_CIPHER_RDY,
198 PWRAP_CIPHER_MODE,
199 PWRAP_CIPHER_SWRST,
200 PWRAP_DCM_EN,
201 PWRAP_DCM_DBC_PRD,
202
203 /* MT8135 only regs */
204 PWRAP_CSHEXT,
205 PWRAP_EVENT_IN_EN,
206 PWRAP_EVENT_DST_EN,
207 PWRAP_RRARB_INIT,
208 PWRAP_RRARB_EN,
209 PWRAP_RRARB_STA0,
210 PWRAP_RRARB_STA1,
211 PWRAP_EVENT_STA,
212 PWRAP_EVENT_STACLR,
213 PWRAP_CIPHER_LOAD,
214 PWRAP_CIPHER_START,
215
216 /* MT8173 only regs */
217 PWRAP_RDDMY,
218 PWRAP_SI_CK_CON,
219 PWRAP_DVFS_ADR0,
220 PWRAP_DVFS_WDATA0,
221 PWRAP_DVFS_ADR1,
222 PWRAP_DVFS_WDATA1,
223 PWRAP_DVFS_ADR2,
224 PWRAP_DVFS_WDATA2,
225 PWRAP_DVFS_ADR3,
226 PWRAP_DVFS_WDATA3,
227 PWRAP_DVFS_ADR4,
228 PWRAP_DVFS_WDATA4,
229 PWRAP_DVFS_ADR5,
230 PWRAP_DVFS_WDATA5,
231 PWRAP_DVFS_ADR6,
232 PWRAP_DVFS_WDATA6,
233 PWRAP_DVFS_ADR7,
234 PWRAP_DVFS_WDATA7,
235 PWRAP_SPMINF_STA,
236 PWRAP_CIPHER_EN,
237 };
238
239 static int mt8173_regs[] = {
240 [PWRAP_MUX_SEL] = 0x0,
241 [PWRAP_WRAP_EN] = 0x4,
242 [PWRAP_DIO_EN] = 0x8,
243 [PWRAP_SIDLY] = 0xc,
244 [PWRAP_RDDMY] = 0x10,
245 [PWRAP_SI_CK_CON] = 0x14,
246 [PWRAP_CSHEXT_WRITE] = 0x18,
247 [PWRAP_CSHEXT_READ] = 0x1c,
248 [PWRAP_CSLEXT_START] = 0x20,
249 [PWRAP_CSLEXT_END] = 0x24,
250 [PWRAP_STAUPD_PRD] = 0x28,
251 [PWRAP_STAUPD_GRPEN] = 0x2c,
252 [PWRAP_STAUPD_MAN_TRIG] = 0x40,
253 [PWRAP_STAUPD_STA] = 0x44,
254 [PWRAP_WRAP_STA] = 0x48,
255 [PWRAP_HARB_INIT] = 0x4c,
256 [PWRAP_HARB_HPRIO] = 0x50,
257 [PWRAP_HIPRIO_ARB_EN] = 0x54,
258 [PWRAP_HARB_STA0] = 0x58,
259 [PWRAP_HARB_STA1] = 0x5c,
260 [PWRAP_MAN_EN] = 0x60,
261 [PWRAP_MAN_CMD] = 0x64,
262 [PWRAP_MAN_RDATA] = 0x68,
263 [PWRAP_MAN_VLDCLR] = 0x6c,
264 [PWRAP_WACS0_EN] = 0x70,
265 [PWRAP_INIT_DONE0] = 0x74,
266 [PWRAP_WACS0_CMD] = 0x78,
267 [PWRAP_WACS0_RDATA] = 0x7c,
268 [PWRAP_WACS0_VLDCLR] = 0x80,
269 [PWRAP_WACS1_EN] = 0x84,
270 [PWRAP_INIT_DONE1] = 0x88,
271 [PWRAP_WACS1_CMD] = 0x8c,
272 [PWRAP_WACS1_RDATA] = 0x90,
273 [PWRAP_WACS1_VLDCLR] = 0x94,
274 [PWRAP_WACS2_EN] = 0x98,
275 [PWRAP_INIT_DONE2] = 0x9c,
276 [PWRAP_WACS2_CMD] = 0xa0,
277 [PWRAP_WACS2_RDATA] = 0xa4,
278 [PWRAP_WACS2_VLDCLR] = 0xa8,
279 [PWRAP_INT_EN] = 0xac,
280 [PWRAP_INT_FLG_RAW] = 0xb0,
281 [PWRAP_INT_FLG] = 0xb4,
282 [PWRAP_INT_CLR] = 0xb8,
283 [PWRAP_SIG_ADR] = 0xbc,
284 [PWRAP_SIG_MODE] = 0xc0,
285 [PWRAP_SIG_VALUE] = 0xc4,
286 [PWRAP_SIG_ERRVAL] = 0xc8,
287 [PWRAP_CRC_EN] = 0xcc,
288 [PWRAP_TIMER_EN] = 0xd0,
289 [PWRAP_TIMER_STA] = 0xd4,
290 [PWRAP_WDT_UNIT] = 0xd8,
291 [PWRAP_WDT_SRC_EN] = 0xdc,
292 [PWRAP_WDT_FLG] = 0xe0,
293 [PWRAP_DEBUG_INT_SEL] = 0xe4,
294 [PWRAP_DVFS_ADR0] = 0xe8,
295 [PWRAP_DVFS_WDATA0] = 0xec,
296 [PWRAP_DVFS_ADR1] = 0xf0,
297 [PWRAP_DVFS_WDATA1] = 0xf4,
298 [PWRAP_DVFS_ADR2] = 0xf8,
299 [PWRAP_DVFS_WDATA2] = 0xfc,
300 [PWRAP_DVFS_ADR3] = 0x100,
301 [PWRAP_DVFS_WDATA3] = 0x104,
302 [PWRAP_DVFS_ADR4] = 0x108,
303 [PWRAP_DVFS_WDATA4] = 0x10c,
304 [PWRAP_DVFS_ADR5] = 0x110,
305 [PWRAP_DVFS_WDATA5] = 0x114,
306 [PWRAP_DVFS_ADR6] = 0x118,
307 [PWRAP_DVFS_WDATA6] = 0x11c,
308 [PWRAP_DVFS_ADR7] = 0x120,
309 [PWRAP_DVFS_WDATA7] = 0x124,
310 [PWRAP_SPMINF_STA] = 0x128,
311 [PWRAP_CIPHER_KEY_SEL] = 0x12c,
312 [PWRAP_CIPHER_IV_SEL] = 0x130,
313 [PWRAP_CIPHER_EN] = 0x134,
314 [PWRAP_CIPHER_RDY] = 0x138,
315 [PWRAP_CIPHER_MODE] = 0x13c,
316 [PWRAP_CIPHER_SWRST] = 0x140,
317 [PWRAP_DCM_EN] = 0x144,
318 [PWRAP_DCM_DBC_PRD] = 0x148,
319 };
320
321 static int mt8135_regs[] = {
322 [PWRAP_MUX_SEL] = 0x0,
323 [PWRAP_WRAP_EN] = 0x4,
324 [PWRAP_DIO_EN] = 0x8,
325 [PWRAP_SIDLY] = 0xc,
326 [PWRAP_CSHEXT] = 0x10,
327 [PWRAP_CSHEXT_WRITE] = 0x14,
328 [PWRAP_CSHEXT_READ] = 0x18,
329 [PWRAP_CSLEXT_START] = 0x1c,
330 [PWRAP_CSLEXT_END] = 0x20,
331 [PWRAP_STAUPD_PRD] = 0x24,
332 [PWRAP_STAUPD_GRPEN] = 0x28,
333 [PWRAP_STAUPD_MAN_TRIG] = 0x2c,
334 [PWRAP_STAUPD_STA] = 0x30,
335 [PWRAP_EVENT_IN_EN] = 0x34,
336 [PWRAP_EVENT_DST_EN] = 0x38,
337 [PWRAP_WRAP_STA] = 0x3c,
338 [PWRAP_RRARB_INIT] = 0x40,
339 [PWRAP_RRARB_EN] = 0x44,
340 [PWRAP_RRARB_STA0] = 0x48,
341 [PWRAP_RRARB_STA1] = 0x4c,
342 [PWRAP_HARB_INIT] = 0x50,
343 [PWRAP_HARB_HPRIO] = 0x54,
344 [PWRAP_HIPRIO_ARB_EN] = 0x58,
345 [PWRAP_HARB_STA0] = 0x5c,
346 [PWRAP_HARB_STA1] = 0x60,
347 [PWRAP_MAN_EN] = 0x64,
348 [PWRAP_MAN_CMD] = 0x68,
349 [PWRAP_MAN_RDATA] = 0x6c,
350 [PWRAP_MAN_VLDCLR] = 0x70,
351 [PWRAP_WACS0_EN] = 0x74,
352 [PWRAP_INIT_DONE0] = 0x78,
353 [PWRAP_WACS0_CMD] = 0x7c,
354 [PWRAP_WACS0_RDATA] = 0x80,
355 [PWRAP_WACS0_VLDCLR] = 0x84,
356 [PWRAP_WACS1_EN] = 0x88,
357 [PWRAP_INIT_DONE1] = 0x8c,
358 [PWRAP_WACS1_CMD] = 0x90,
359 [PWRAP_WACS1_RDATA] = 0x94,
360 [PWRAP_WACS1_VLDCLR] = 0x98,
361 [PWRAP_WACS2_EN] = 0x9c,
362 [PWRAP_INIT_DONE2] = 0xa0,
363 [PWRAP_WACS2_CMD] = 0xa4,
364 [PWRAP_WACS2_RDATA] = 0xa8,
365 [PWRAP_WACS2_VLDCLR] = 0xac,
366 [PWRAP_INT_EN] = 0xb0,
367 [PWRAP_INT_FLG_RAW] = 0xb4,
368 [PWRAP_INT_FLG] = 0xb8,
369 [PWRAP_INT_CLR] = 0xbc,
370 [PWRAP_SIG_ADR] = 0xc0,
371 [PWRAP_SIG_MODE] = 0xc4,
372 [PWRAP_SIG_VALUE] = 0xc8,
373 [PWRAP_SIG_ERRVAL] = 0xcc,
374 [PWRAP_CRC_EN] = 0xd0,
375 [PWRAP_EVENT_STA] = 0xd4,
376 [PWRAP_EVENT_STACLR] = 0xd8,
377 [PWRAP_TIMER_EN] = 0xdc,
378 [PWRAP_TIMER_STA] = 0xe0,
379 [PWRAP_WDT_UNIT] = 0xe4,
380 [PWRAP_WDT_SRC_EN] = 0xe8,
381 [PWRAP_WDT_FLG] = 0xec,
382 [PWRAP_DEBUG_INT_SEL] = 0xf0,
383 [PWRAP_CIPHER_KEY_SEL] = 0x134,
384 [PWRAP_CIPHER_IV_SEL] = 0x138,
385 [PWRAP_CIPHER_LOAD] = 0x13c,
386 [PWRAP_CIPHER_START] = 0x140,
387 [PWRAP_CIPHER_RDY] = 0x144,
388 [PWRAP_CIPHER_MODE] = 0x148,
389 [PWRAP_CIPHER_SWRST] = 0x14c,
390 [PWRAP_DCM_EN] = 0x15c,
391 [PWRAP_DCM_DBC_PRD] = 0x160,
392 };
393
394 enum pmic_type {
395 PMIC_MT6323,
396 PMIC_MT6397,
397 };
398
399 enum pwrap_type {
400 PWRAP_MT8135,
401 PWRAP_MT8173,
402 };
403
404 struct pwrap_slv_type {
405 const u32 *dew_regs;
406 enum pmic_type type;
407 };
408
409 struct pmic_wrapper {
410 struct device *dev;
411 void __iomem *base;
412 struct regmap *regmap;
413 const struct pmic_wrapper_type *master;
414 const struct pwrap_slv_type *slave;
415 struct clk *clk_spi;
416 struct clk *clk_wrap;
417 struct reset_control *rstc;
418
419 struct reset_control *rstc_bridge;
420 void __iomem *bridge_base;
421 };
422
423 struct pmic_wrapper_type {
424 int *regs;
425 enum pwrap_type type;
426 u32 arb_en_all;
427 u32 int_en_all;
428 u32 spi_w;
429 u32 wdt_src;
430 int has_bridge:1;
431 int (*init_reg_clock)(struct pmic_wrapper *wrp);
432 int (*init_soc_specific)(struct pmic_wrapper *wrp);
433 };
434
435 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
436 {
437 return readl(wrp->base + wrp->master->regs[reg]);
438 }
439
440 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
441 {
442 writel(val, wrp->base + wrp->master->regs[reg]);
443 }
444
445 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
446 {
447 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
448
449 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
450 }
451
452 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
453 {
454 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
455
456 return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
457 }
458
459 /*
460 * Timeout issue sometimes caused by the last read command
461 * failed because pmic wrap could not got the FSM_VLDCLR
462 * in time after finishing WACS2_CMD. It made state machine
463 * still on FSM_VLDCLR and timeout next time.
464 * Check the status of FSM and clear the vldclr to recovery the
465 * error.
466 */
467 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
468 {
469 if (pwrap_is_fsm_vldclr(wrp))
470 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
471 }
472
473 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
474 {
475 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
476 }
477
478 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
479 {
480 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
481
482 return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
483 (val & PWRAP_STATE_SYNC_IDLE0);
484 }
485
486 static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
487 bool (*fp)(struct pmic_wrapper *))
488 {
489 unsigned long timeout;
490
491 timeout = jiffies + usecs_to_jiffies(255);
492
493 do {
494 if (time_after(jiffies, timeout))
495 return fp(wrp) ? 0 : -ETIMEDOUT;
496 if (fp(wrp))
497 return 0;
498 } while (1);
499 }
500
501 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
502 {
503 int ret;
504
505 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
506 if (ret) {
507 pwrap_leave_fsm_vldclr(wrp);
508 return ret;
509 }
510
511 pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
512 PWRAP_WACS2_CMD);
513
514 return 0;
515 }
516
517 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
518 {
519 int ret;
520
521 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
522 if (ret) {
523 pwrap_leave_fsm_vldclr(wrp);
524 return ret;
525 }
526
527 pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
528
529 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
530 if (ret)
531 return ret;
532
533 *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
534
535 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
536
537 return 0;
538 }
539
540 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
541 {
542 return pwrap_read(context, adr, rdata);
543 }
544
545 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
546 {
547 return pwrap_write(context, adr, wdata);
548 }
549
550 static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
551 {
552 int ret, i;
553
554 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
555 pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
556 pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
557 pwrap_writel(wrp, 1, PWRAP_MAN_EN);
558 pwrap_writel(wrp, 0, PWRAP_DIO_EN);
559
560 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
561 PWRAP_MAN_CMD);
562 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
563 PWRAP_MAN_CMD);
564 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
565 PWRAP_MAN_CMD);
566
567 for (i = 0; i < 4; i++)
568 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
569 PWRAP_MAN_CMD);
570
571 ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
572 if (ret) {
573 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
574 return ret;
575 }
576
577 pwrap_writel(wrp, 0, PWRAP_MAN_EN);
578 pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
579
580 return 0;
581 }
582
583 /*
584 * pwrap_init_sidly - configure serial input delay
585 *
586 * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
587 * delay. Do a read test with all possible values and chose the best delay.
588 */
589 static int pwrap_init_sidly(struct pmic_wrapper *wrp)
590 {
591 u32 rdata;
592 u32 i;
593 u32 pass = 0;
594 signed char dly[16] = {
595 -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
596 };
597
598 for (i = 0; i < 4; i++) {
599 pwrap_writel(wrp, i, PWRAP_SIDLY);
600 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
601 &rdata);
602 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
603 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
604 pass |= 1 << i;
605 }
606 }
607
608 if (dly[pass] < 0) {
609 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
610 pass);
611 return -EIO;
612 }
613
614 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
615
616 return 0;
617 }
618
619 static int pwrap_mt8135_init_reg_clock(struct pmic_wrapper *wrp)
620 {
621 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
622 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
623 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
624 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
625 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
626
627 return 0;
628 }
629
630 static int pwrap_mt8173_init_reg_clock(struct pmic_wrapper *wrp)
631 {
632 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
633 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
634 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
635 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
636
637 return 0;
638 }
639
640 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
641 {
642 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
643 }
644
645 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
646 {
647 u32 rdata;
648 int ret;
649
650 ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
651 &rdata);
652 if (ret)
653 return 0;
654
655 return rdata == 1;
656 }
657
658 static int pwrap_init_cipher(struct pmic_wrapper *wrp)
659 {
660 int ret;
661 u32 rdata;
662
663 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
664 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
665 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
666 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
667
668 switch (wrp->master->type) {
669 case PWRAP_MT8135:
670 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
671 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
672 break;
673 case PWRAP_MT8173:
674 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
675 break;
676 }
677
678 /* Config cipher mode @PMIC */
679 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
680 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
681 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
682 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
683 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1);
684 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 0x1);
685
686 switch (wrp->slave->type) {
687 case PMIC_MT6397:
688 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
689 0x1);
690 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
691 0x1);
692 break;
693 case PMIC_MT6323:
694 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
695 0x1);
696 break;
697 }
698
699 /* wait for cipher data ready@AP */
700 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
701 if (ret) {
702 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
703 return ret;
704 }
705
706 /* wait for cipher data ready@PMIC */
707 ret = pwrap_wait_for_state(wrp, pwrap_is_pmic_cipher_ready);
708 if (ret) {
709 dev_err(wrp->dev, "timeout waiting for cipher data ready@PMIC\n");
710 return ret;
711 }
712
713 /* wait for cipher mode idle */
714 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
715 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
716 if (ret) {
717 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
718 return ret;
719 }
720
721 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
722
723 /* Write Test */
724 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
725 PWRAP_DEW_WRITE_TEST_VAL) ||
726 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
727 &rdata) ||
728 (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
729 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
730 return -EFAULT;
731 }
732
733 return 0;
734 }
735
736 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
737 {
738 /* enable pwrap events and pwrap bridge in AP side */
739 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
740 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
741 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
742 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
743 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
744 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
745 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
746 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
747 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
748
749 /* enable PMIC event out and sources */
750 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
751 0x1) ||
752 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
753 0xffff)) {
754 dev_err(wrp->dev, "enable dewrap fail\n");
755 return -EFAULT;
756 }
757
758 return 0;
759 }
760
761 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
762 {
763 /* PMIC_DEWRAP enables */
764 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
765 0x1) ||
766 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
767 0xffff)) {
768 dev_err(wrp->dev, "enable dewrap fail\n");
769 return -EFAULT;
770 }
771
772 return 0;
773 }
774
775 static int pwrap_init(struct pmic_wrapper *wrp)
776 {
777 int ret;
778 u32 rdata;
779
780 reset_control_reset(wrp->rstc);
781 if (wrp->rstc_bridge)
782 reset_control_reset(wrp->rstc_bridge);
783
784 if (wrp->master->type == PWRAP_MT8173) {
785 /* Enable DCM */
786 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
787 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
788 }
789
790 /* Reset SPI slave */
791 ret = pwrap_reset_spislave(wrp);
792 if (ret)
793 return ret;
794
795 pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
796
797 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
798
799 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
800
801 ret = wrp->master->init_reg_clock(wrp);
802 if (ret)
803 return ret;
804
805 /* Setup serial input delay */
806 ret = pwrap_init_sidly(wrp);
807 if (ret)
808 return ret;
809
810 /* Enable dual IO mode */
811 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
812
813 /* Check IDLE & INIT_DONE in advance */
814 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
815 if (ret) {
816 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
817 return ret;
818 }
819
820 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
821
822 /* Read Test */
823 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
824 if (rdata != PWRAP_DEW_READ_TEST_VAL) {
825 dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
826 PWRAP_DEW_READ_TEST_VAL, rdata);
827 return -EFAULT;
828 }
829
830 /* Enable encryption */
831 ret = pwrap_init_cipher(wrp);
832 if (ret)
833 return ret;
834
835 /* Signature checking - using CRC */
836 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
837 return -EFAULT;
838
839 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
840 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
841 pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
842 PWRAP_SIG_ADR);
843 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
844
845 if (wrp->master->type == PWRAP_MT8135)
846 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
847
848 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
849 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
850 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
851 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
852 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
853
854 if (wrp->master->init_soc_specific) {
855 ret = wrp->master->init_soc_specific(wrp);
856 if (ret)
857 return ret;
858 }
859
860 /* Setup the init done registers */
861 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
862 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
863 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
864
865 if (wrp->master->has_bridge) {
866 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
867 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
868 }
869
870 return 0;
871 }
872
873 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
874 {
875 u32 rdata;
876 struct pmic_wrapper *wrp = dev_id;
877
878 rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
879
880 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
881
882 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
883
884 return IRQ_HANDLED;
885 }
886
887 static const struct regmap_config pwrap_regmap_config = {
888 .reg_bits = 16,
889 .val_bits = 16,
890 .reg_stride = 2,
891 .reg_read = pwrap_regmap_read,
892 .reg_write = pwrap_regmap_write,
893 .max_register = 0xffff,
894 };
895
896 static const struct pwrap_slv_type pmic_mt6323 = {
897 .dew_regs = mt6323_regs,
898 .type = PMIC_MT6323,
899 };
900
901 static const struct pwrap_slv_type pmic_mt6397 = {
902 .dew_regs = mt6397_regs,
903 .type = PMIC_MT6397,
904 };
905
906 static const struct of_device_id of_slave_match_tbl[] = {
907 {
908 .compatible = "mediatek,mt6323",
909 .data = &pmic_mt6323,
910 }, {
911 .compatible = "mediatek,mt6397",
912 .data = &pmic_mt6397,
913 }, {
914 /* sentinel */
915 }
916 };
917 MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
918
919 static struct pmic_wrapper_type pwrap_mt8135 = {
920 .regs = mt8135_regs,
921 .type = PWRAP_MT8135,
922 .arb_en_all = 0x1ff,
923 .int_en_all = ~(BIT(31) | BIT(1)),
924 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
925 .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
926 .has_bridge = 1,
927 .init_reg_clock = pwrap_mt8135_init_reg_clock,
928 .init_soc_specific = pwrap_mt8135_init_soc_specific,
929 };
930
931 static struct pmic_wrapper_type pwrap_mt8173 = {
932 .regs = mt8173_regs,
933 .type = PWRAP_MT8173,
934 .arb_en_all = 0x3f,
935 .int_en_all = ~(BIT(31) | BIT(1)),
936 .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
937 .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
938 .has_bridge = 0,
939 .init_reg_clock = pwrap_mt8173_init_reg_clock,
940 .init_soc_specific = pwrap_mt8173_init_soc_specific,
941 };
942
943 static struct of_device_id of_pwrap_match_tbl[] = {
944 {
945 .compatible = "mediatek,mt8135-pwrap",
946 .data = &pwrap_mt8135,
947 }, {
948 .compatible = "mediatek,mt8173-pwrap",
949 .data = &pwrap_mt8173,
950 }, {
951 /* sentinel */
952 }
953 };
954 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
955
956 static int pwrap_probe(struct platform_device *pdev)
957 {
958 int ret, irq;
959 struct pmic_wrapper *wrp;
960 struct device_node *np = pdev->dev.of_node;
961 const struct of_device_id *of_id =
962 of_match_device(of_pwrap_match_tbl, &pdev->dev);
963 const struct of_device_id *of_slave_id = NULL;
964 struct resource *res;
965
966 if (pdev->dev.of_node->child)
967 of_slave_id = of_match_node(of_slave_match_tbl,
968 pdev->dev.of_node->child);
969 if (!of_slave_id) {
970 dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
971 return -EINVAL;
972 }
973
974 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
975 if (!wrp)
976 return -ENOMEM;
977
978 platform_set_drvdata(pdev, wrp);
979
980 wrp->master = of_id->data;
981 wrp->slave = of_slave_id->data;
982 wrp->dev = &pdev->dev;
983
984 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
985 wrp->base = devm_ioremap_resource(wrp->dev, res);
986 if (IS_ERR(wrp->base))
987 return PTR_ERR(wrp->base);
988
989 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
990 if (IS_ERR(wrp->rstc)) {
991 ret = PTR_ERR(wrp->rstc);
992 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
993 return ret;
994 }
995
996 if (wrp->master->has_bridge) {
997 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
998 "pwrap-bridge");
999 wrp->bridge_base = devm_ioremap_resource(wrp->dev, res);
1000 if (IS_ERR(wrp->bridge_base))
1001 return PTR_ERR(wrp->bridge_base);
1002
1003 wrp->rstc_bridge = devm_reset_control_get(wrp->dev, "pwrap-bridge");
1004 if (IS_ERR(wrp->rstc_bridge)) {
1005 ret = PTR_ERR(wrp->rstc_bridge);
1006 dev_dbg(wrp->dev, "cannot get pwrap-bridge reset: %d\n", ret);
1007 return ret;
1008 }
1009 }
1010
1011 wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
1012 if (IS_ERR(wrp->clk_spi)) {
1013 dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_spi));
1014 return PTR_ERR(wrp->clk_spi);
1015 }
1016
1017 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
1018 if (IS_ERR(wrp->clk_wrap)) {
1019 dev_dbg(wrp->dev, "failed to get clock: %ld\n", PTR_ERR(wrp->clk_wrap));
1020 return PTR_ERR(wrp->clk_wrap);
1021 }
1022
1023 ret = clk_prepare_enable(wrp->clk_spi);
1024 if (ret)
1025 return ret;
1026
1027 ret = clk_prepare_enable(wrp->clk_wrap);
1028 if (ret)
1029 goto err_out1;
1030
1031 /* Enable internal dynamic clock */
1032 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
1033 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1034
1035 /*
1036 * The PMIC could already be initialized by the bootloader.
1037 * Skip initialization here in this case.
1038 */
1039 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
1040 ret = pwrap_init(wrp);
1041 if (ret) {
1042 dev_dbg(wrp->dev, "init failed with %d\n", ret);
1043 goto err_out2;
1044 }
1045 }
1046
1047 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_INIT_DONE0)) {
1048 dev_dbg(wrp->dev, "initialization isn't finished\n");
1049 return -ENODEV;
1050 }
1051
1052 /* Initialize watchdog, may not be done by the bootloader */
1053 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
1054 /*
1055 * Since STAUPD was not used on mt8173 platform,
1056 * so STAUPD of WDT_SRC which should be turned off
1057 */
1058 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
1059 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
1060 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
1061
1062 irq = platform_get_irq(pdev, 0);
1063 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,
1064 "mt-pmic-pwrap", wrp);
1065 if (ret)
1066 goto err_out2;
1067
1068 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, &pwrap_regmap_config);
1069 if (IS_ERR(wrp->regmap))
1070 return PTR_ERR(wrp->regmap);
1071
1072 ret = of_platform_populate(np, NULL, NULL, wrp->dev);
1073 if (ret) {
1074 dev_dbg(wrp->dev, "failed to create child devices at %s\n",
1075 np->full_name);
1076 goto err_out2;
1077 }
1078
1079 return 0;
1080
1081 err_out2:
1082 clk_disable_unprepare(wrp->clk_wrap);
1083 err_out1:
1084 clk_disable_unprepare(wrp->clk_spi);
1085
1086 return ret;
1087 }
1088
1089 static struct platform_driver pwrap_drv = {
1090 .driver = {
1091 .name = "mt-pmic-pwrap",
1092 .of_match_table = of_match_ptr(of_pwrap_match_tbl),
1093 },
1094 .probe = pwrap_probe,
1095 };
1096
1097 module_platform_driver(pwrap_drv);
1098
1099 MODULE_AUTHOR("Flora Fu, MediaTek");
1100 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
1101 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.05196 seconds and 4 git commands to generate.