2 * OMAP2 McSPI controller driver
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrjölä <juha.yrjola@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
35 #include <linux/slab.h>
37 #include <linux/spi/spi.h>
40 #include <plat/clock.h>
41 #include <plat/mcspi.h>
43 #define OMAP2_MCSPI_MAX_FREQ 48000000
45 /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
46 #define OMAP2_MCSPI_MAX_CTRL 4
48 #define OMAP2_MCSPI_REVISION 0x00
49 #define OMAP2_MCSPI_SYSCONFIG 0x10
50 #define OMAP2_MCSPI_SYSSTATUS 0x14
51 #define OMAP2_MCSPI_IRQSTATUS 0x18
52 #define OMAP2_MCSPI_IRQENABLE 0x1c
53 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
54 #define OMAP2_MCSPI_SYST 0x24
55 #define OMAP2_MCSPI_MODULCTRL 0x28
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0 0x2c
59 #define OMAP2_MCSPI_CHSTAT0 0x30
60 #define OMAP2_MCSPI_CHCTRL0 0x34
61 #define OMAP2_MCSPI_TX0 0x38
62 #define OMAP2_MCSPI_RX0 0x3c
64 /* per-register bitmasks: */
66 #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
67 #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
68 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
69 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
71 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
73 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
74 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
75 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
77 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
78 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
79 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
80 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
81 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
82 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
83 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
84 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
85 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
86 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
87 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
88 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
89 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
90 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
91 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
93 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
94 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
95 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
97 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
99 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
101 /* We have 2 DMA channels per CS, one for RX and one for TX */
102 struct omap2_mcspi_dma
{
109 struct completion dma_tx_completion
;
110 struct completion dma_rx_completion
;
113 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
114 * cache operations; better heuristics consider wordsize and bitrate.
116 #define DMA_MIN_BYTES 160
120 struct work_struct work
;
121 /* lock protects queue and registers */
123 struct list_head msg_queue
;
124 struct spi_master
*master
;
127 /* Virtual base address of the controller */
130 /* SPI1 has 4 channels, while SPI2 has 2 */
131 struct omap2_mcspi_dma
*dma_channels
;
134 struct omap2_mcspi_cs
{
138 struct list_head node
;
139 /* Context save and restore shadow register */
143 /* used for context save and restore, structure members to be updated whenever
144 * corresponding registers are modified.
146 struct omap2_mcspi_regs
{
153 static struct omap2_mcspi_regs omap2_mcspi_ctx
[OMAP2_MCSPI_MAX_CTRL
];
155 static struct workqueue_struct
*omap2_mcspi_wq
;
157 #define MOD_REG_BIT(val, mask, set) do { \
164 static inline void mcspi_write_reg(struct spi_master
*master
,
167 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
169 __raw_writel(val
, mcspi
->base
+ idx
);
172 static inline u32
mcspi_read_reg(struct spi_master
*master
, int idx
)
174 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
176 return __raw_readl(mcspi
->base
+ idx
);
179 static inline void mcspi_write_cs_reg(const struct spi_device
*spi
,
182 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
184 __raw_writel(val
, cs
->base
+ idx
);
187 static inline u32
mcspi_read_cs_reg(const struct spi_device
*spi
, int idx
)
189 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
191 return __raw_readl(cs
->base
+ idx
);
194 static inline u32
mcspi_cached_chconf0(const struct spi_device
*spi
)
196 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
201 static inline void mcspi_write_chconf0(const struct spi_device
*spi
, u32 val
)
203 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
206 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCONF0
, val
);
207 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHCONF0
);
210 static void omap2_mcspi_set_dma_req(const struct spi_device
*spi
,
211 int is_read
, int enable
)
215 l
= mcspi_cached_chconf0(spi
);
217 if (is_read
) /* 1 is read, 0 write */
218 rw
= OMAP2_MCSPI_CHCONF_DMAR
;
220 rw
= OMAP2_MCSPI_CHCONF_DMAW
;
222 MOD_REG_BIT(l
, rw
, enable
);
223 mcspi_write_chconf0(spi
, l
);
226 static void omap2_mcspi_set_enable(const struct spi_device
*spi
, int enable
)
230 l
= enable
? OMAP2_MCSPI_CHCTRL_EN
: 0;
231 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
, l
);
232 /* Flash post-writes */
233 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
);
236 static void omap2_mcspi_force_cs(struct spi_device
*spi
, int cs_active
)
240 l
= mcspi_cached_chconf0(spi
);
241 MOD_REG_BIT(l
, OMAP2_MCSPI_CHCONF_FORCE
, cs_active
);
242 mcspi_write_chconf0(spi
, l
);
245 static void omap2_mcspi_set_master_mode(struct spi_master
*master
)
249 /* setup when switching from (reset default) slave mode
250 * to single-channel master mode
252 l
= mcspi_read_reg(master
, OMAP2_MCSPI_MODULCTRL
);
253 MOD_REG_BIT(l
, OMAP2_MCSPI_MODULCTRL_STEST
, 0);
254 MOD_REG_BIT(l
, OMAP2_MCSPI_MODULCTRL_MS
, 0);
255 MOD_REG_BIT(l
, OMAP2_MCSPI_MODULCTRL_SINGLE
, 1);
256 mcspi_write_reg(master
, OMAP2_MCSPI_MODULCTRL
, l
);
258 omap2_mcspi_ctx
[master
->bus_num
- 1].modulctrl
= l
;
261 static void omap2_mcspi_restore_ctx(struct omap2_mcspi
*mcspi
)
263 struct spi_master
*spi_cntrl
;
264 struct omap2_mcspi_cs
*cs
;
265 spi_cntrl
= mcspi
->master
;
267 /* McSPI: context restore */
268 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_MODULCTRL
,
269 omap2_mcspi_ctx
[spi_cntrl
->bus_num
- 1].modulctrl
);
271 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_SYSCONFIG
,
272 omap2_mcspi_ctx
[spi_cntrl
->bus_num
- 1].sysconfig
);
274 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_WAKEUPENABLE
,
275 omap2_mcspi_ctx
[spi_cntrl
->bus_num
- 1].wakeupenable
);
277 list_for_each_entry(cs
, &omap2_mcspi_ctx
[spi_cntrl
->bus_num
- 1].cs
,
279 __raw_writel(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
281 static void omap2_mcspi_disable_clocks(struct omap2_mcspi
*mcspi
)
283 clk_disable(mcspi
->ick
);
284 clk_disable(mcspi
->fck
);
287 static int omap2_mcspi_enable_clocks(struct omap2_mcspi
*mcspi
)
289 if (clk_enable(mcspi
->ick
))
291 if (clk_enable(mcspi
->fck
))
294 omap2_mcspi_restore_ctx(mcspi
);
299 static int mcspi_wait_for_reg_bit(void __iomem
*reg
, unsigned long bit
)
301 unsigned long timeout
;
303 timeout
= jiffies
+ msecs_to_jiffies(1000);
304 while (!(__raw_readl(reg
) & bit
)) {
305 if (time_after(jiffies
, timeout
))
313 omap2_mcspi_txrx_dma(struct spi_device
*spi
, struct spi_transfer
*xfer
)
315 struct omap2_mcspi
*mcspi
;
316 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
317 struct omap2_mcspi_dma
*mcspi_dma
;
318 unsigned int count
, c
;
319 unsigned long base
, tx_reg
, rx_reg
;
320 int word_len
, data_type
, element_count
;
325 void __iomem
*chstat_reg
;
327 mcspi
= spi_master_get_devdata(spi
->master
);
328 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
329 l
= mcspi_cached_chconf0(spi
);
331 chstat_reg
= cs
->base
+ OMAP2_MCSPI_CHSTAT0
;
335 word_len
= cs
->word_len
;
338 tx_reg
= base
+ OMAP2_MCSPI_TX0
;
339 rx_reg
= base
+ OMAP2_MCSPI_RX0
;
344 data_type
= OMAP_DMA_DATA_TYPE_S8
;
345 element_count
= count
;
346 } else if (word_len
<= 16) {
347 data_type
= OMAP_DMA_DATA_TYPE_S16
;
348 element_count
= count
>> 1;
349 } else /* word_len <= 32 */ {
350 data_type
= OMAP_DMA_DATA_TYPE_S32
;
351 element_count
= count
>> 2;
355 omap_set_dma_transfer_params(mcspi_dma
->dma_tx_channel
,
356 data_type
, element_count
, 1,
357 OMAP_DMA_SYNC_ELEMENT
,
358 mcspi_dma
->dma_tx_sync_dev
, 0);
360 omap_set_dma_dest_params(mcspi_dma
->dma_tx_channel
, 0,
361 OMAP_DMA_AMODE_CONSTANT
,
364 omap_set_dma_src_params(mcspi_dma
->dma_tx_channel
, 0,
365 OMAP_DMA_AMODE_POST_INC
,
370 elements
= element_count
- 1;
371 if (l
& OMAP2_MCSPI_CHCONF_TURBO
)
374 omap_set_dma_transfer_params(mcspi_dma
->dma_rx_channel
,
375 data_type
, elements
, 1,
376 OMAP_DMA_SYNC_ELEMENT
,
377 mcspi_dma
->dma_rx_sync_dev
, 1);
379 omap_set_dma_src_params(mcspi_dma
->dma_rx_channel
, 0,
380 OMAP_DMA_AMODE_CONSTANT
,
383 omap_set_dma_dest_params(mcspi_dma
->dma_rx_channel
, 0,
384 OMAP_DMA_AMODE_POST_INC
,
389 omap_start_dma(mcspi_dma
->dma_tx_channel
);
390 omap2_mcspi_set_dma_req(spi
, 0, 1);
394 omap_start_dma(mcspi_dma
->dma_rx_channel
);
395 omap2_mcspi_set_dma_req(spi
, 1, 1);
399 wait_for_completion(&mcspi_dma
->dma_tx_completion
);
400 dma_unmap_single(&spi
->dev
, xfer
->tx_dma
, count
, DMA_TO_DEVICE
);
402 /* for TX_ONLY mode, be sure all words have shifted out */
404 if (mcspi_wait_for_reg_bit(chstat_reg
,
405 OMAP2_MCSPI_CHSTAT_TXS
) < 0)
406 dev_err(&spi
->dev
, "TXS timed out\n");
407 else if (mcspi_wait_for_reg_bit(chstat_reg
,
408 OMAP2_MCSPI_CHSTAT_EOT
) < 0)
409 dev_err(&spi
->dev
, "EOT timed out\n");
414 wait_for_completion(&mcspi_dma
->dma_rx_completion
);
415 dma_unmap_single(&spi
->dev
, xfer
->rx_dma
, count
, DMA_FROM_DEVICE
);
416 omap2_mcspi_set_enable(spi
, 0);
418 if (l
& OMAP2_MCSPI_CHCONF_TURBO
) {
420 if (likely(mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHSTAT0
)
421 & OMAP2_MCSPI_CHSTAT_RXS
)) {
424 w
= mcspi_read_cs_reg(spi
, OMAP2_MCSPI_RX0
);
426 ((u8
*)xfer
->rx_buf
)[elements
++] = w
;
427 else if (word_len
<= 16)
428 ((u16
*)xfer
->rx_buf
)[elements
++] = w
;
429 else /* word_len <= 32 */
430 ((u32
*)xfer
->rx_buf
)[elements
++] = w
;
433 "DMA RX penultimate word empty");
434 count
-= (word_len
<= 8) ? 2 :
435 (word_len
<= 16) ? 4 :
436 /* word_len <= 32 */ 8;
437 omap2_mcspi_set_enable(spi
, 1);
442 if (likely(mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHSTAT0
)
443 & OMAP2_MCSPI_CHSTAT_RXS
)) {
446 w
= mcspi_read_cs_reg(spi
, OMAP2_MCSPI_RX0
);
448 ((u8
*)xfer
->rx_buf
)[elements
] = w
;
449 else if (word_len
<= 16)
450 ((u16
*)xfer
->rx_buf
)[elements
] = w
;
451 else /* word_len <= 32 */
452 ((u32
*)xfer
->rx_buf
)[elements
] = w
;
454 dev_err(&spi
->dev
, "DMA RX last word empty");
455 count
-= (word_len
<= 8) ? 1 :
456 (word_len
<= 16) ? 2 :
457 /* word_len <= 32 */ 4;
459 omap2_mcspi_set_enable(spi
, 1);
465 omap2_mcspi_txrx_pio(struct spi_device
*spi
, struct spi_transfer
*xfer
)
467 struct omap2_mcspi
*mcspi
;
468 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
469 unsigned int count
, c
;
471 void __iomem
*base
= cs
->base
;
472 void __iomem
*tx_reg
;
473 void __iomem
*rx_reg
;
474 void __iomem
*chstat_reg
;
477 mcspi
= spi_master_get_devdata(spi
->master
);
480 word_len
= cs
->word_len
;
482 l
= mcspi_cached_chconf0(spi
);
484 /* We store the pre-calculated register addresses on stack to speed
485 * up the transfer loop. */
486 tx_reg
= base
+ OMAP2_MCSPI_TX0
;
487 rx_reg
= base
+ OMAP2_MCSPI_RX0
;
488 chstat_reg
= base
+ OMAP2_MCSPI_CHSTAT0
;
500 if (mcspi_wait_for_reg_bit(chstat_reg
,
501 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
502 dev_err(&spi
->dev
, "TXS timed out\n");
505 dev_vdbg(&spi
->dev
, "write-%d %02x\n",
507 __raw_writel(*tx
++, tx_reg
);
510 if (mcspi_wait_for_reg_bit(chstat_reg
,
511 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
512 dev_err(&spi
->dev
, "RXS timed out\n");
516 if (c
== 1 && tx
== NULL
&&
517 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
518 omap2_mcspi_set_enable(spi
, 0);
519 *rx
++ = __raw_readl(rx_reg
);
520 dev_vdbg(&spi
->dev
, "read-%d %02x\n",
521 word_len
, *(rx
- 1));
522 if (mcspi_wait_for_reg_bit(chstat_reg
,
523 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
529 } else if (c
== 0 && tx
== NULL
) {
530 omap2_mcspi_set_enable(spi
, 0);
533 *rx
++ = __raw_readl(rx_reg
);
534 dev_vdbg(&spi
->dev
, "read-%d %02x\n",
535 word_len
, *(rx
- 1));
538 } else if (word_len
<= 16) {
547 if (mcspi_wait_for_reg_bit(chstat_reg
,
548 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
549 dev_err(&spi
->dev
, "TXS timed out\n");
552 dev_vdbg(&spi
->dev
, "write-%d %04x\n",
554 __raw_writel(*tx
++, tx_reg
);
557 if (mcspi_wait_for_reg_bit(chstat_reg
,
558 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
559 dev_err(&spi
->dev
, "RXS timed out\n");
563 if (c
== 2 && tx
== NULL
&&
564 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
565 omap2_mcspi_set_enable(spi
, 0);
566 *rx
++ = __raw_readl(rx_reg
);
567 dev_vdbg(&spi
->dev
, "read-%d %04x\n",
568 word_len
, *(rx
- 1));
569 if (mcspi_wait_for_reg_bit(chstat_reg
,
570 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
576 } else if (c
== 0 && tx
== NULL
) {
577 omap2_mcspi_set_enable(spi
, 0);
580 *rx
++ = __raw_readl(rx_reg
);
581 dev_vdbg(&spi
->dev
, "read-%d %04x\n",
582 word_len
, *(rx
- 1));
585 } else if (word_len
<= 32) {
594 if (mcspi_wait_for_reg_bit(chstat_reg
,
595 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
596 dev_err(&spi
->dev
, "TXS timed out\n");
599 dev_vdbg(&spi
->dev
, "write-%d %08x\n",
601 __raw_writel(*tx
++, tx_reg
);
604 if (mcspi_wait_for_reg_bit(chstat_reg
,
605 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
606 dev_err(&spi
->dev
, "RXS timed out\n");
610 if (c
== 4 && tx
== NULL
&&
611 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
612 omap2_mcspi_set_enable(spi
, 0);
613 *rx
++ = __raw_readl(rx_reg
);
614 dev_vdbg(&spi
->dev
, "read-%d %08x\n",
615 word_len
, *(rx
- 1));
616 if (mcspi_wait_for_reg_bit(chstat_reg
,
617 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
623 } else if (c
== 0 && tx
== NULL
) {
624 omap2_mcspi_set_enable(spi
, 0);
627 *rx
++ = __raw_readl(rx_reg
);
628 dev_vdbg(&spi
->dev
, "read-%d %08x\n",
629 word_len
, *(rx
- 1));
634 /* for TX_ONLY mode, be sure all words have shifted out */
635 if (xfer
->rx_buf
== NULL
) {
636 if (mcspi_wait_for_reg_bit(chstat_reg
,
637 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
638 dev_err(&spi
->dev
, "TXS timed out\n");
639 } else if (mcspi_wait_for_reg_bit(chstat_reg
,
640 OMAP2_MCSPI_CHSTAT_EOT
) < 0)
641 dev_err(&spi
->dev
, "EOT timed out\n");
643 /* disable chan to purge rx datas received in TX_ONLY transfer,
644 * otherwise these rx datas will affect the direct following
647 omap2_mcspi_set_enable(spi
, 0);
650 omap2_mcspi_set_enable(spi
, 1);
654 static u32
omap2_mcspi_calc_divisor(u32 speed_hz
)
658 for (div
= 0; div
< 15; div
++)
659 if (speed_hz
>= (OMAP2_MCSPI_MAX_FREQ
>> div
))
665 /* called only when no transfer is active to this device */
666 static int omap2_mcspi_setup_transfer(struct spi_device
*spi
,
667 struct spi_transfer
*t
)
669 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
670 struct omap2_mcspi
*mcspi
;
671 struct spi_master
*spi_cntrl
;
673 u8 word_len
= spi
->bits_per_word
;
674 u32 speed_hz
= spi
->max_speed_hz
;
676 mcspi
= spi_master_get_devdata(spi
->master
);
677 spi_cntrl
= mcspi
->master
;
679 if (t
!= NULL
&& t
->bits_per_word
)
680 word_len
= t
->bits_per_word
;
682 cs
->word_len
= word_len
;
684 if (t
&& t
->speed_hz
)
685 speed_hz
= t
->speed_hz
;
687 speed_hz
= min_t(u32
, speed_hz
, OMAP2_MCSPI_MAX_FREQ
);
688 div
= omap2_mcspi_calc_divisor(speed_hz
);
690 l
= mcspi_cached_chconf0(spi
);
692 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
693 * REVISIT: this controller could support SPI_3WIRE mode.
695 l
&= ~(OMAP2_MCSPI_CHCONF_IS
|OMAP2_MCSPI_CHCONF_DPE1
);
696 l
|= OMAP2_MCSPI_CHCONF_DPE0
;
699 l
&= ~OMAP2_MCSPI_CHCONF_WL_MASK
;
700 l
|= (word_len
- 1) << 7;
702 /* set chipselect polarity; manage with FORCE */
703 if (!(spi
->mode
& SPI_CS_HIGH
))
704 l
|= OMAP2_MCSPI_CHCONF_EPOL
; /* active-low; normal */
706 l
&= ~OMAP2_MCSPI_CHCONF_EPOL
;
708 /* set clock divisor */
709 l
&= ~OMAP2_MCSPI_CHCONF_CLKD_MASK
;
712 /* set SPI mode 0..3 */
713 if (spi
->mode
& SPI_CPOL
)
714 l
|= OMAP2_MCSPI_CHCONF_POL
;
716 l
&= ~OMAP2_MCSPI_CHCONF_POL
;
717 if (spi
->mode
& SPI_CPHA
)
718 l
|= OMAP2_MCSPI_CHCONF_PHA
;
720 l
&= ~OMAP2_MCSPI_CHCONF_PHA
;
722 mcspi_write_chconf0(spi
, l
);
724 dev_dbg(&spi
->dev
, "setup: speed %d, sample %s edge, clk %s\n",
725 OMAP2_MCSPI_MAX_FREQ
>> div
,
726 (spi
->mode
& SPI_CPHA
) ? "trailing" : "leading",
727 (spi
->mode
& SPI_CPOL
) ? "inverted" : "normal");
732 static void omap2_mcspi_dma_rx_callback(int lch
, u16 ch_status
, void *data
)
734 struct spi_device
*spi
= data
;
735 struct omap2_mcspi
*mcspi
;
736 struct omap2_mcspi_dma
*mcspi_dma
;
738 mcspi
= spi_master_get_devdata(spi
->master
);
739 mcspi_dma
= &(mcspi
->dma_channels
[spi
->chip_select
]);
741 complete(&mcspi_dma
->dma_rx_completion
);
743 /* We must disable the DMA RX request */
744 omap2_mcspi_set_dma_req(spi
, 1, 0);
747 static void omap2_mcspi_dma_tx_callback(int lch
, u16 ch_status
, void *data
)
749 struct spi_device
*spi
= data
;
750 struct omap2_mcspi
*mcspi
;
751 struct omap2_mcspi_dma
*mcspi_dma
;
753 mcspi
= spi_master_get_devdata(spi
->master
);
754 mcspi_dma
= &(mcspi
->dma_channels
[spi
->chip_select
]);
756 complete(&mcspi_dma
->dma_tx_completion
);
758 /* We must disable the DMA TX request */
759 omap2_mcspi_set_dma_req(spi
, 0, 0);
762 static int omap2_mcspi_request_dma(struct spi_device
*spi
)
764 struct spi_master
*master
= spi
->master
;
765 struct omap2_mcspi
*mcspi
;
766 struct omap2_mcspi_dma
*mcspi_dma
;
768 mcspi
= spi_master_get_devdata(master
);
769 mcspi_dma
= mcspi
->dma_channels
+ spi
->chip_select
;
771 if (omap_request_dma(mcspi_dma
->dma_rx_sync_dev
, "McSPI RX",
772 omap2_mcspi_dma_rx_callback
, spi
,
773 &mcspi_dma
->dma_rx_channel
)) {
774 dev_err(&spi
->dev
, "no RX DMA channel for McSPI\n");
778 if (omap_request_dma(mcspi_dma
->dma_tx_sync_dev
, "McSPI TX",
779 omap2_mcspi_dma_tx_callback
, spi
,
780 &mcspi_dma
->dma_tx_channel
)) {
781 omap_free_dma(mcspi_dma
->dma_rx_channel
);
782 mcspi_dma
->dma_rx_channel
= -1;
783 dev_err(&spi
->dev
, "no TX DMA channel for McSPI\n");
787 init_completion(&mcspi_dma
->dma_rx_completion
);
788 init_completion(&mcspi_dma
->dma_tx_completion
);
793 static int omap2_mcspi_setup(struct spi_device
*spi
)
796 struct omap2_mcspi
*mcspi
;
797 struct omap2_mcspi_dma
*mcspi_dma
;
798 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
800 if (spi
->bits_per_word
< 4 || spi
->bits_per_word
> 32) {
801 dev_dbg(&spi
->dev
, "setup: unsupported %d bit words\n",
806 mcspi
= spi_master_get_devdata(spi
->master
);
807 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
810 cs
= kzalloc(sizeof *cs
, GFP_KERNEL
);
813 cs
->base
= mcspi
->base
+ spi
->chip_select
* 0x14;
814 cs
->phys
= mcspi
->phys
+ spi
->chip_select
* 0x14;
816 spi
->controller_state
= cs
;
817 /* Link this to context save list */
818 list_add_tail(&cs
->node
,
819 &omap2_mcspi_ctx
[mcspi
->master
->bus_num
- 1].cs
);
822 if (mcspi_dma
->dma_rx_channel
== -1
823 || mcspi_dma
->dma_tx_channel
== -1) {
824 ret
= omap2_mcspi_request_dma(spi
);
829 if (omap2_mcspi_enable_clocks(mcspi
))
832 ret
= omap2_mcspi_setup_transfer(spi
, NULL
);
833 omap2_mcspi_disable_clocks(mcspi
);
838 static void omap2_mcspi_cleanup(struct spi_device
*spi
)
840 struct omap2_mcspi
*mcspi
;
841 struct omap2_mcspi_dma
*mcspi_dma
;
842 struct omap2_mcspi_cs
*cs
;
844 mcspi
= spi_master_get_devdata(spi
->master
);
846 if (spi
->controller_state
) {
847 /* Unlink controller state from context save list */
848 cs
= spi
->controller_state
;
851 kfree(spi
->controller_state
);
854 if (spi
->chip_select
< spi
->master
->num_chipselect
) {
855 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
857 if (mcspi_dma
->dma_rx_channel
!= -1) {
858 omap_free_dma(mcspi_dma
->dma_rx_channel
);
859 mcspi_dma
->dma_rx_channel
= -1;
861 if (mcspi_dma
->dma_tx_channel
!= -1) {
862 omap_free_dma(mcspi_dma
->dma_tx_channel
);
863 mcspi_dma
->dma_tx_channel
= -1;
868 static void omap2_mcspi_work(struct work_struct
*work
)
870 struct omap2_mcspi
*mcspi
;
872 mcspi
= container_of(work
, struct omap2_mcspi
, work
);
873 spin_lock_irq(&mcspi
->lock
);
875 if (omap2_mcspi_enable_clocks(mcspi
))
878 /* We only enable one channel at a time -- the one whose message is
879 * at the head of the queue -- although this controller would gladly
880 * arbitrate among multiple channels. This corresponds to "single
881 * channel" master mode. As a side effect, we need to manage the
882 * chipselect with the FORCE bit ... CS != channel enable.
884 while (!list_empty(&mcspi
->msg_queue
)) {
885 struct spi_message
*m
;
886 struct spi_device
*spi
;
887 struct spi_transfer
*t
= NULL
;
889 struct omap2_mcspi_cs
*cs
;
890 struct omap2_mcspi_device_config
*cd
;
891 int par_override
= 0;
895 m
= container_of(mcspi
->msg_queue
.next
, struct spi_message
,
898 list_del_init(&m
->queue
);
899 spin_unlock_irq(&mcspi
->lock
);
902 cs
= spi
->controller_state
;
903 cd
= spi
->controller_data
;
905 omap2_mcspi_set_enable(spi
, 1);
906 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
907 if (t
->tx_buf
== NULL
&& t
->rx_buf
== NULL
&& t
->len
) {
911 if (par_override
|| t
->speed_hz
|| t
->bits_per_word
) {
913 status
= omap2_mcspi_setup_transfer(spi
, t
);
916 if (!t
->speed_hz
&& !t
->bits_per_word
)
921 omap2_mcspi_force_cs(spi
, 1);
925 chconf
= mcspi_cached_chconf0(spi
);
926 chconf
&= ~OMAP2_MCSPI_CHCONF_TRM_MASK
;
927 chconf
&= ~OMAP2_MCSPI_CHCONF_TURBO
;
929 if (t
->tx_buf
== NULL
)
930 chconf
|= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY
;
931 else if (t
->rx_buf
== NULL
)
932 chconf
|= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY
;
934 if (cd
&& cd
->turbo_mode
&& t
->tx_buf
== NULL
) {
935 /* Turbo mode is for more than one word */
936 if (t
->len
> ((cs
->word_len
+ 7) >> 3))
937 chconf
|= OMAP2_MCSPI_CHCONF_TURBO
;
940 mcspi_write_chconf0(spi
, chconf
);
945 /* RX_ONLY mode needs dummy data in TX reg */
946 if (t
->tx_buf
== NULL
)
947 __raw_writel(0, cs
->base
950 if (m
->is_dma_mapped
|| t
->len
>= DMA_MIN_BYTES
)
951 count
= omap2_mcspi_txrx_dma(spi
, t
);
953 count
= omap2_mcspi_txrx_pio(spi
, t
);
954 m
->actual_length
+= count
;
956 if (count
!= t
->len
) {
963 udelay(t
->delay_usecs
);
965 /* ignore the "leave it on after last xfer" hint */
967 omap2_mcspi_force_cs(spi
, 0);
972 /* Restore defaults if they were overriden */
975 status
= omap2_mcspi_setup_transfer(spi
, NULL
);
979 omap2_mcspi_force_cs(spi
, 0);
981 omap2_mcspi_set_enable(spi
, 0);
984 m
->complete(m
->context
);
986 spin_lock_irq(&mcspi
->lock
);
989 omap2_mcspi_disable_clocks(mcspi
);
992 spin_unlock_irq(&mcspi
->lock
);
995 static int omap2_mcspi_transfer(struct spi_device
*spi
, struct spi_message
*m
)
997 struct omap2_mcspi
*mcspi
;
999 struct spi_transfer
*t
;
1001 m
->actual_length
= 0;
1004 /* reject invalid messages and transfers */
1005 if (list_empty(&m
->transfers
) || !m
->complete
)
1007 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
1008 const void *tx_buf
= t
->tx_buf
;
1009 void *rx_buf
= t
->rx_buf
;
1010 unsigned len
= t
->len
;
1012 if (t
->speed_hz
> OMAP2_MCSPI_MAX_FREQ
1013 || (len
&& !(rx_buf
|| tx_buf
))
1014 || (t
->bits_per_word
&&
1015 ( t
->bits_per_word
< 4
1016 || t
->bits_per_word
> 32))) {
1017 dev_dbg(&spi
->dev
, "transfer: %d Hz, %d %s%s, %d bpw\n",
1025 if (t
->speed_hz
&& t
->speed_hz
< (OMAP2_MCSPI_MAX_FREQ
>> 15)) {
1026 dev_dbg(&spi
->dev
, "speed_hz %d below minimum %d Hz\n",
1028 OMAP2_MCSPI_MAX_FREQ
>> 15);
1032 if (m
->is_dma_mapped
|| len
< DMA_MIN_BYTES
)
1035 if (tx_buf
!= NULL
) {
1036 t
->tx_dma
= dma_map_single(&spi
->dev
, (void *) tx_buf
,
1037 len
, DMA_TO_DEVICE
);
1038 if (dma_mapping_error(&spi
->dev
, t
->tx_dma
)) {
1039 dev_dbg(&spi
->dev
, "dma %cX %d bytes error\n",
1044 if (rx_buf
!= NULL
) {
1045 t
->rx_dma
= dma_map_single(&spi
->dev
, rx_buf
, t
->len
,
1047 if (dma_mapping_error(&spi
->dev
, t
->rx_dma
)) {
1048 dev_dbg(&spi
->dev
, "dma %cX %d bytes error\n",
1051 dma_unmap_single(&spi
->dev
, t
->tx_dma
,
1052 len
, DMA_TO_DEVICE
);
1058 mcspi
= spi_master_get_devdata(spi
->master
);
1060 spin_lock_irqsave(&mcspi
->lock
, flags
);
1061 list_add_tail(&m
->queue
, &mcspi
->msg_queue
);
1062 queue_work(omap2_mcspi_wq
, &mcspi
->work
);
1063 spin_unlock_irqrestore(&mcspi
->lock
, flags
);
1068 static int __init
omap2_mcspi_reset(struct omap2_mcspi
*mcspi
)
1070 struct spi_master
*master
= mcspi
->master
;
1073 if (omap2_mcspi_enable_clocks(mcspi
))
1076 mcspi_write_reg(master
, OMAP2_MCSPI_SYSCONFIG
,
1077 OMAP2_MCSPI_SYSCONFIG_SOFTRESET
);
1079 tmp
= mcspi_read_reg(master
, OMAP2_MCSPI_SYSSTATUS
);
1080 } while (!(tmp
& OMAP2_MCSPI_SYSSTATUS_RESETDONE
));
1082 tmp
= OMAP2_MCSPI_SYSCONFIG_AUTOIDLE
|
1083 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP
|
1084 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE
;
1085 mcspi_write_reg(master
, OMAP2_MCSPI_SYSCONFIG
, tmp
);
1086 omap2_mcspi_ctx
[master
->bus_num
- 1].sysconfig
= tmp
;
1088 tmp
= OMAP2_MCSPI_WAKEUPENABLE_WKEN
;
1089 mcspi_write_reg(master
, OMAP2_MCSPI_WAKEUPENABLE
, tmp
);
1090 omap2_mcspi_ctx
[master
->bus_num
- 1].wakeupenable
= tmp
;
1092 omap2_mcspi_set_master_mode(master
);
1093 omap2_mcspi_disable_clocks(mcspi
);
1097 static u8 __initdata spi1_rxdma_id
[] = {
1098 OMAP24XX_DMA_SPI1_RX0
,
1099 OMAP24XX_DMA_SPI1_RX1
,
1100 OMAP24XX_DMA_SPI1_RX2
,
1101 OMAP24XX_DMA_SPI1_RX3
,
1104 static u8 __initdata spi1_txdma_id
[] = {
1105 OMAP24XX_DMA_SPI1_TX0
,
1106 OMAP24XX_DMA_SPI1_TX1
,
1107 OMAP24XX_DMA_SPI1_TX2
,
1108 OMAP24XX_DMA_SPI1_TX3
,
1111 static u8 __initdata spi2_rxdma_id
[] = {
1112 OMAP24XX_DMA_SPI2_RX0
,
1113 OMAP24XX_DMA_SPI2_RX1
,
1116 static u8 __initdata spi2_txdma_id
[] = {
1117 OMAP24XX_DMA_SPI2_TX0
,
1118 OMAP24XX_DMA_SPI2_TX1
,
1121 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1122 || defined(CONFIG_ARCH_OMAP4)
1123 static u8 __initdata spi3_rxdma_id
[] = {
1124 OMAP24XX_DMA_SPI3_RX0
,
1125 OMAP24XX_DMA_SPI3_RX1
,
1128 static u8 __initdata spi3_txdma_id
[] = {
1129 OMAP24XX_DMA_SPI3_TX0
,
1130 OMAP24XX_DMA_SPI3_TX1
,
1134 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1135 static u8 __initdata spi4_rxdma_id
[] = {
1136 OMAP34XX_DMA_SPI4_RX0
,
1139 static u8 __initdata spi4_txdma_id
[] = {
1140 OMAP34XX_DMA_SPI4_TX0
,
1144 static int __init
omap2_mcspi_probe(struct platform_device
*pdev
)
1146 struct spi_master
*master
;
1147 struct omap2_mcspi
*mcspi
;
1150 const u8
*rxdma_id
, *txdma_id
;
1151 unsigned num_chipselect
;
1155 rxdma_id
= spi1_rxdma_id
;
1156 txdma_id
= spi1_txdma_id
;
1160 rxdma_id
= spi2_rxdma_id
;
1161 txdma_id
= spi2_txdma_id
;
1164 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1165 || defined(CONFIG_ARCH_OMAP4)
1167 rxdma_id
= spi3_rxdma_id
;
1168 txdma_id
= spi3_txdma_id
;
1172 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1174 rxdma_id
= spi4_rxdma_id
;
1175 txdma_id
= spi4_txdma_id
;
1183 master
= spi_alloc_master(&pdev
->dev
, sizeof *mcspi
);
1184 if (master
== NULL
) {
1185 dev_dbg(&pdev
->dev
, "master allocation failed\n");
1189 /* the spi->mode bits understood by this driver: */
1190 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1193 master
->bus_num
= pdev
->id
;
1195 master
->setup
= omap2_mcspi_setup
;
1196 master
->transfer
= omap2_mcspi_transfer
;
1197 master
->cleanup
= omap2_mcspi_cleanup
;
1198 master
->num_chipselect
= num_chipselect
;
1200 dev_set_drvdata(&pdev
->dev
, master
);
1202 mcspi
= spi_master_get_devdata(master
);
1203 mcspi
->master
= master
;
1205 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1210 if (!request_mem_region(r
->start
, (r
->end
- r
->start
) + 1,
1211 dev_name(&pdev
->dev
))) {
1216 mcspi
->phys
= r
->start
;
1217 mcspi
->base
= ioremap(r
->start
, r
->end
- r
->start
+ 1);
1219 dev_dbg(&pdev
->dev
, "can't ioremap MCSPI\n");
1224 INIT_WORK(&mcspi
->work
, omap2_mcspi_work
);
1226 spin_lock_init(&mcspi
->lock
);
1227 INIT_LIST_HEAD(&mcspi
->msg_queue
);
1228 INIT_LIST_HEAD(&omap2_mcspi_ctx
[master
->bus_num
- 1].cs
);
1230 mcspi
->ick
= clk_get(&pdev
->dev
, "ick");
1231 if (IS_ERR(mcspi
->ick
)) {
1232 dev_dbg(&pdev
->dev
, "can't get mcspi_ick\n");
1233 status
= PTR_ERR(mcspi
->ick
);
1236 mcspi
->fck
= clk_get(&pdev
->dev
, "fck");
1237 if (IS_ERR(mcspi
->fck
)) {
1238 dev_dbg(&pdev
->dev
, "can't get mcspi_fck\n");
1239 status
= PTR_ERR(mcspi
->fck
);
1243 mcspi
->dma_channels
= kcalloc(master
->num_chipselect
,
1244 sizeof(struct omap2_mcspi_dma
),
1247 if (mcspi
->dma_channels
== NULL
)
1250 for (i
= 0; i
< num_chipselect
; i
++) {
1251 mcspi
->dma_channels
[i
].dma_rx_channel
= -1;
1252 mcspi
->dma_channels
[i
].dma_rx_sync_dev
= rxdma_id
[i
];
1253 mcspi
->dma_channels
[i
].dma_tx_channel
= -1;
1254 mcspi
->dma_channels
[i
].dma_tx_sync_dev
= txdma_id
[i
];
1257 if (omap2_mcspi_reset(mcspi
) < 0)
1260 status
= spi_register_master(master
);
1267 kfree(mcspi
->dma_channels
);
1269 clk_put(mcspi
->fck
);
1271 clk_put(mcspi
->ick
);
1273 iounmap(mcspi
->base
);
1275 release_mem_region(r
->start
, (r
->end
- r
->start
) + 1);
1277 spi_master_put(master
);
1281 static int __exit
omap2_mcspi_remove(struct platform_device
*pdev
)
1283 struct spi_master
*master
;
1284 struct omap2_mcspi
*mcspi
;
1285 struct omap2_mcspi_dma
*dma_channels
;
1289 master
= dev_get_drvdata(&pdev
->dev
);
1290 mcspi
= spi_master_get_devdata(master
);
1291 dma_channels
= mcspi
->dma_channels
;
1293 clk_put(mcspi
->fck
);
1294 clk_put(mcspi
->ick
);
1296 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1297 release_mem_region(r
->start
, (r
->end
- r
->start
) + 1);
1300 spi_unregister_master(master
);
1302 kfree(dma_channels
);
1307 /* work with hotplug and coldplug */
1308 MODULE_ALIAS("platform:omap2_mcspi");
1310 #ifdef CONFIG_SUSPEND
1312 * When SPI wake up from off-mode, CS is in activate state. If it was in
1313 * unactive state when driver was suspend, then force it to unactive state at
1316 static int omap2_mcspi_resume(struct device
*dev
)
1318 struct spi_master
*master
= dev_get_drvdata(dev
);
1319 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
1320 struct omap2_mcspi_cs
*cs
;
1322 omap2_mcspi_enable_clocks(mcspi
);
1323 list_for_each_entry(cs
, &omap2_mcspi_ctx
[master
->bus_num
- 1].cs
,
1325 if ((cs
->chconf0
& OMAP2_MCSPI_CHCONF_FORCE
) == 0) {
1328 * We need to toggle CS state for OMAP take this
1329 * change in account.
1331 MOD_REG_BIT(cs
->chconf0
, OMAP2_MCSPI_CHCONF_FORCE
, 1);
1332 __raw_writel(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1333 MOD_REG_BIT(cs
->chconf0
, OMAP2_MCSPI_CHCONF_FORCE
, 0);
1334 __raw_writel(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1337 omap2_mcspi_disable_clocks(mcspi
);
1341 #define omap2_mcspi_resume NULL
1344 static const struct dev_pm_ops omap2_mcspi_pm_ops
= {
1345 .resume
= omap2_mcspi_resume
,
1348 static struct platform_driver omap2_mcspi_driver
= {
1350 .name
= "omap2_mcspi",
1351 .owner
= THIS_MODULE
,
1352 .pm
= &omap2_mcspi_pm_ops
1354 .remove
= __exit_p(omap2_mcspi_remove
),
1358 static int __init
omap2_mcspi_init(void)
1360 omap2_mcspi_wq
= create_singlethread_workqueue(
1361 omap2_mcspi_driver
.driver
.name
);
1362 if (omap2_mcspi_wq
== NULL
)
1364 return platform_driver_probe(&omap2_mcspi_driver
, omap2_mcspi_probe
);
1366 subsys_initcall(omap2_mcspi_init
);
1368 static void __exit
omap2_mcspi_exit(void)
1370 platform_driver_unregister(&omap2_mcspi_driver
);
1372 destroy_workqueue(omap2_mcspi_wq
);
1374 module_exit(omap2_mcspi_exit
);
1376 MODULE_LICENSE("GPL");