projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
omap2_mcspi: Flush posted writes
[deliverable/linux.git] / drivers / spi / omap2_mcspi.c
1 /*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrjölä <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/io.h>
35 #include <linux/slab.h>
36
37 #include <linux/spi/spi.h>
38
39 #include <plat/dma.h>
40 #include <plat/clock.h>
41
42
43 #define OMAP2_MCSPI_MAX_FREQ 48000000
44
45 /* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
46 #define OMAP2_MCSPI_MAX_CTRL 4
47
48 #define OMAP2_MCSPI_REVISION 0x00
49 #define OMAP2_MCSPI_SYSCONFIG 0x10
50 #define OMAP2_MCSPI_SYSSTATUS 0x14
51 #define OMAP2_MCSPI_IRQSTATUS 0x18
52 #define OMAP2_MCSPI_IRQENABLE 0x1c
53 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
54 #define OMAP2_MCSPI_SYST 0x24
55 #define OMAP2_MCSPI_MODULCTRL 0x28
56
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0 0x2c
59 #define OMAP2_MCSPI_CHSTAT0 0x30
60 #define OMAP2_MCSPI_CHCTRL0 0x34
61 #define OMAP2_MCSPI_TX0 0x38
62 #define OMAP2_MCSPI_RX0 0x3c
63
64 /* per-register bitmasks: */
65
66 #define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE BIT(4)
67 #define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2)
68 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
69 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET BIT(1)
70
71 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE BIT(0)
72
73 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
74 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
75 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
76
77 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
78 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
79 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
80 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
81 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
82 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
83 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
84 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
85 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
86 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
87 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
88 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
89 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
90 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
91 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
92
93 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
94 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
95 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
96
97 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
98
99 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
100
101 /* We have 2 DMA channels per CS, one for RX and one for TX */
102 struct omap2_mcspi_dma {
103 int dma_tx_channel;
104 int dma_rx_channel;
105
106 int dma_tx_sync_dev;
107 int dma_rx_sync_dev;
108
109 struct completion dma_tx_completion;
110 struct completion dma_rx_completion;
111 };
112
113 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
114 * cache operations; better heuristics consider wordsize and bitrate.
115 */
116 #define DMA_MIN_BYTES 8
117
118
119 struct omap2_mcspi {
120 struct work_struct work;
121 /* lock protects queue and registers */
122 spinlock_t lock;
123 struct list_head msg_queue;
124 struct spi_master *master;
125 struct clk *ick;
126 struct clk *fck;
127 /* Virtual base address of the controller */
128 void __iomem *base;
129 unsigned long phys;
130 /* SPI1 has 4 channels, while SPI2 has 2 */
131 struct omap2_mcspi_dma *dma_channels;
132 };
133
134 struct omap2_mcspi_cs {
135 void __iomem *base;
136 unsigned long phys;
137 int word_len;
138 struct list_head node;
139 /* Context save and restore shadow register */
140 u32 chconf0;
141 };
142
143 /* used for context save and restore, structure members to be updated whenever
144 * corresponding registers are modified.
145 */
146 struct omap2_mcspi_regs {
147 u32 sysconfig;
148 u32 modulctrl;
149 u32 wakeupenable;
150 struct list_head cs;
151 };
152
153 static struct omap2_mcspi_regs omap2_mcspi_ctx[OMAP2_MCSPI_MAX_CTRL];
154
155 static struct workqueue_struct *omap2_mcspi_wq;
156
157 #define MOD_REG_BIT(val, mask, set) do { \
158 if (set) \
159 val |= mask; \
160 else \
161 val &= ~mask; \
162 } while (0)
163
164 static inline void mcspi_write_reg(struct spi_master *master,
165 int idx, u32 val)
166 {
167 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
168
169 __raw_writel(val, mcspi->base + idx);
170 }
171
172 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
173 {
174 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
175
176 return __raw_readl(mcspi->base + idx);
177 }
178
179 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
180 int idx, u32 val)
181 {
182 struct omap2_mcspi_cs *cs = spi->controller_state;
183
184 __raw_writel(val, cs->base + idx);
185 }
186
187 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
188 {
189 struct omap2_mcspi_cs *cs = spi->controller_state;
190
191 return __raw_readl(cs->base + idx);
192 }
193
194 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
195 {
196 struct omap2_mcspi_cs *cs = spi->controller_state;
197
198 return cs->chconf0;
199 }
200
201 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
202 {
203 struct omap2_mcspi_cs *cs = spi->controller_state;
204
205 cs->chconf0 = val;
206 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
207 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
208 }
209
210 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
211 int is_read, int enable)
212 {
213 u32 l, rw;
214
215 l = mcspi_cached_chconf0(spi);
216
217 if (is_read) /* 1 is read, 0 write */
218 rw = OMAP2_MCSPI_CHCONF_DMAR;
219 else
220 rw = OMAP2_MCSPI_CHCONF_DMAW;
221
222 MOD_REG_BIT(l, rw, enable);
223 mcspi_write_chconf0(spi, l);
224 }
225
226 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
227 {
228 u32 l;
229
230 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
231 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
232 }
233
234 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
235 {
236 u32 l;
237
238 l = mcspi_cached_chconf0(spi);
239 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
240 mcspi_write_chconf0(spi, l);
241 }
242
243 static void omap2_mcspi_set_master_mode(struct spi_master *master)
244 {
245 u32 l;
246
247 /* setup when switching from (reset default) slave mode
248 * to single-channel master mode
249 */
250 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
251 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
252 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
253 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
254 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
255
256 omap2_mcspi_ctx[master->bus_num - 1].modulctrl = l;
257 }
258
259 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
260 {
261 struct spi_master *spi_cntrl;
262 struct omap2_mcspi_cs *cs;
263 spi_cntrl = mcspi->master;
264
265 /* McSPI: context restore */
266 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
267 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
268
269 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
270 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
271
272 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
273 omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
274
275 list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
276 node)
277 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
278 }
279 static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
280 {
281 clk_disable(mcspi->ick);
282 clk_disable(mcspi->fck);
283 }
284
285 static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
286 {
287 if (clk_enable(mcspi->ick))
288 return -ENODEV;
289 if (clk_enable(mcspi->fck))
290 return -ENODEV;
291
292 omap2_mcspi_restore_ctx(mcspi);
293
294 return 0;
295 }
296
297 static unsigned
298 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
299 {
300 struct omap2_mcspi *mcspi;
301 struct omap2_mcspi_cs *cs = spi->controller_state;
302 struct omap2_mcspi_dma *mcspi_dma;
303 unsigned int count, c;
304 unsigned long base, tx_reg, rx_reg;
305 int word_len, data_type, element_count;
306 u8 * rx;
307 const u8 * tx;
308
309 mcspi = spi_master_get_devdata(spi->master);
310 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
311
312 count = xfer->len;
313 c = count;
314 word_len = cs->word_len;
315
316 base = cs->phys;
317 tx_reg = base + OMAP2_MCSPI_TX0;
318 rx_reg = base + OMAP2_MCSPI_RX0;
319 rx = xfer->rx_buf;
320 tx = xfer->tx_buf;
321
322 if (word_len <= 8) {
323 data_type = OMAP_DMA_DATA_TYPE_S8;
324 element_count = count;
325 } else if (word_len <= 16) {
326 data_type = OMAP_DMA_DATA_TYPE_S16;
327 element_count = count >> 1;
328 } else /* word_len <= 32 */ {
329 data_type = OMAP_DMA_DATA_TYPE_S32;
330 element_count = count >> 2;
331 }
332
333 if (tx != NULL) {
334 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
335 data_type, element_count, 1,
336 OMAP_DMA_SYNC_ELEMENT,
337 mcspi_dma->dma_tx_sync_dev, 0);
338
339 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
340 OMAP_DMA_AMODE_CONSTANT,
341 tx_reg, 0, 0);
342
343 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
344 OMAP_DMA_AMODE_POST_INC,
345 xfer->tx_dma, 0, 0);
346 }
347
348 if (rx != NULL) {
349 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
350 data_type, element_count - 1, 1,
351 OMAP_DMA_SYNC_ELEMENT,
352 mcspi_dma->dma_rx_sync_dev, 1);
353
354 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
355 OMAP_DMA_AMODE_CONSTANT,
356 rx_reg, 0, 0);
357
358 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
359 OMAP_DMA_AMODE_POST_INC,
360 xfer->rx_dma, 0, 0);
361 }
362
363 if (tx != NULL) {
364 omap_start_dma(mcspi_dma->dma_tx_channel);
365 omap2_mcspi_set_dma_req(spi, 0, 1);
366 }
367
368 if (rx != NULL) {
369 omap_start_dma(mcspi_dma->dma_rx_channel);
370 omap2_mcspi_set_dma_req(spi, 1, 1);
371 }
372
373 if (tx != NULL) {
374 wait_for_completion(&mcspi_dma->dma_tx_completion);
375 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
376 }
377
378 if (rx != NULL) {
379 wait_for_completion(&mcspi_dma->dma_rx_completion);
380 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
381 omap2_mcspi_set_enable(spi, 0);
382 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
383 & OMAP2_MCSPI_CHSTAT_RXS)) {
384 u32 w;
385
386 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
387 if (word_len <= 8)
388 ((u8 *)xfer->rx_buf)[element_count - 1] = w;
389 else if (word_len <= 16)
390 ((u16 *)xfer->rx_buf)[element_count - 1] = w;
391 else /* word_len <= 32 */
392 ((u32 *)xfer->rx_buf)[element_count - 1] = w;
393 } else {
394 dev_err(&spi->dev, "DMA RX last word empty");
395 count -= (word_len <= 8) ? 1 :
396 (word_len <= 16) ? 2 :
397 /* word_len <= 32 */ 4;
398 }
399 omap2_mcspi_set_enable(spi, 1);
400 }
401 return count;
402 }
403
404 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
405 {
406 unsigned long timeout;
407
408 timeout = jiffies + msecs_to_jiffies(1000);
409 while (!(__raw_readl(reg) & bit)) {
410 if (time_after(jiffies, timeout))
411 return -1;
412 cpu_relax();
413 }
414 return 0;
415 }
416
417 static unsigned
418 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
419 {
420 struct omap2_mcspi *mcspi;
421 struct omap2_mcspi_cs *cs = spi->controller_state;
422 unsigned int count, c;
423 u32 l;
424 void __iomem *base = cs->base;
425 void __iomem *tx_reg;
426 void __iomem *rx_reg;
427 void __iomem *chstat_reg;
428 int word_len;
429
430 mcspi = spi_master_get_devdata(spi->master);
431 count = xfer->len;
432 c = count;
433 word_len = cs->word_len;
434
435 l = mcspi_cached_chconf0(spi);
436 l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
437
438 /* We store the pre-calculated register addresses on stack to speed
439 * up the transfer loop. */
440 tx_reg = base + OMAP2_MCSPI_TX0;
441 rx_reg = base + OMAP2_MCSPI_RX0;
442 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
443
444 if (word_len <= 8) {
445 u8 *rx;
446 const u8 *tx;
447
448 rx = xfer->rx_buf;
449 tx = xfer->tx_buf;
450
451 do {
452 c -= 1;
453 if (tx != NULL) {
454 if (mcspi_wait_for_reg_bit(chstat_reg,
455 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
456 dev_err(&spi->dev, "TXS timed out\n");
457 goto out;
458 }
459 #ifdef VERBOSE
460 dev_dbg(&spi->dev, "write-%d %02x\n",
461 word_len, *tx);
462 #endif
463 __raw_writel(*tx++, tx_reg);
464 }
465 if (rx != NULL) {
466 if (mcspi_wait_for_reg_bit(chstat_reg,
467 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
468 dev_err(&spi->dev, "RXS timed out\n");
469 goto out;
470 }
471 /* prevent last RX_ONLY read from triggering
472 * more word i/o: switch to rx+tx
473 */
474 if (c == 0 && tx == NULL)
475 mcspi_write_chconf0(spi, l);
476 *rx++ = __raw_readl(rx_reg);
477 #ifdef VERBOSE
478 dev_dbg(&spi->dev, "read-%d %02x\n",
479 word_len, *(rx - 1));
480 #endif
481 }
482 } while (c);
483 } else if (word_len <= 16) {
484 u16 *rx;
485 const u16 *tx;
486
487 rx = xfer->rx_buf;
488 tx = xfer->tx_buf;
489 do {
490 c -= 2;
491 if (tx != NULL) {
492 if (mcspi_wait_for_reg_bit(chstat_reg,
493 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
494 dev_err(&spi->dev, "TXS timed out\n");
495 goto out;
496 }
497 #ifdef VERBOSE
498 dev_dbg(&spi->dev, "write-%d %04x\n",
499 word_len, *tx);
500 #endif
501 __raw_writel(*tx++, tx_reg);
502 }
503 if (rx != NULL) {
504 if (mcspi_wait_for_reg_bit(chstat_reg,
505 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
506 dev_err(&spi->dev, "RXS timed out\n");
507 goto out;
508 }
509 /* prevent last RX_ONLY read from triggering
510 * more word i/o: switch to rx+tx
511 */
512 if (c == 0 && tx == NULL)
513 mcspi_write_chconf0(spi, l);
514 *rx++ = __raw_readl(rx_reg);
515 #ifdef VERBOSE
516 dev_dbg(&spi->dev, "read-%d %04x\n",
517 word_len, *(rx - 1));
518 #endif
519 }
520 } while (c);
521 } else if (word_len <= 32) {
522 u32 *rx;
523 const u32 *tx;
524
525 rx = xfer->rx_buf;
526 tx = xfer->tx_buf;
527 do {
528 c -= 4;
529 if (tx != NULL) {
530 if (mcspi_wait_for_reg_bit(chstat_reg,
531 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
532 dev_err(&spi->dev, "TXS timed out\n");
533 goto out;
534 }
535 #ifdef VERBOSE
536 dev_dbg(&spi->dev, "write-%d %04x\n",
537 word_len, *tx);
538 #endif
539 __raw_writel(*tx++, tx_reg);
540 }
541 if (rx != NULL) {
542 if (mcspi_wait_for_reg_bit(chstat_reg,
543 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
544 dev_err(&spi->dev, "RXS timed out\n");
545 goto out;
546 }
547 /* prevent last RX_ONLY read from triggering
548 * more word i/o: switch to rx+tx
549 */
550 if (c == 0 && tx == NULL)
551 mcspi_write_chconf0(spi, l);
552 *rx++ = __raw_readl(rx_reg);
553 #ifdef VERBOSE
554 dev_dbg(&spi->dev, "read-%d %04x\n",
555 word_len, *(rx - 1));
556 #endif
557 }
558 } while (c);
559 }
560
561 /* for TX_ONLY mode, be sure all words have shifted out */
562 if (xfer->rx_buf == NULL) {
563 if (mcspi_wait_for_reg_bit(chstat_reg,
564 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
565 dev_err(&spi->dev, "TXS timed out\n");
566 } else if (mcspi_wait_for_reg_bit(chstat_reg,
567 OMAP2_MCSPI_CHSTAT_EOT) < 0)
568 dev_err(&spi->dev, "EOT timed out\n");
569 }
570 out:
571 return count - c;
572 }
573
574 /* called only when no transfer is active to this device */
575 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
576 struct spi_transfer *t)
577 {
578 struct omap2_mcspi_cs *cs = spi->controller_state;
579 struct omap2_mcspi *mcspi;
580 struct spi_master *spi_cntrl;
581 u32 l = 0, div = 0;
582 u8 word_len = spi->bits_per_word;
583 u32 speed_hz = spi->max_speed_hz;
584
585 mcspi = spi_master_get_devdata(spi->master);
586 spi_cntrl = mcspi->master;
587
588 if (t != NULL && t->bits_per_word)
589 word_len = t->bits_per_word;
590
591 cs->word_len = word_len;
592
593 if (t && t->speed_hz)
594 speed_hz = t->speed_hz;
595
596 if (speed_hz) {
597 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
598 > speed_hz)
599 div++;
600 } else
601 div = 15;
602
603 l = mcspi_cached_chconf0(spi);
604
605 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
606 * REVISIT: this controller could support SPI_3WIRE mode.
607 */
608 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
609 l |= OMAP2_MCSPI_CHCONF_DPE0;
610
611 /* wordlength */
612 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
613 l |= (word_len - 1) << 7;
614
615 /* set chipselect polarity; manage with FORCE */
616 if (!(spi->mode & SPI_CS_HIGH))
617 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
618 else
619 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
620
621 /* set clock divisor */
622 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
623 l |= div << 2;
624
625 /* set SPI mode 0..3 */
626 if (spi->mode & SPI_CPOL)
627 l |= OMAP2_MCSPI_CHCONF_POL;
628 else
629 l &= ~OMAP2_MCSPI_CHCONF_POL;
630 if (spi->mode & SPI_CPHA)
631 l |= OMAP2_MCSPI_CHCONF_PHA;
632 else
633 l &= ~OMAP2_MCSPI_CHCONF_PHA;
634
635 mcspi_write_chconf0(spi, l);
636
637 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
638 OMAP2_MCSPI_MAX_FREQ / (1 << div),
639 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
640 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
641
642 return 0;
643 }
644
645 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
646 {
647 struct spi_device *spi = data;
648 struct omap2_mcspi *mcspi;
649 struct omap2_mcspi_dma *mcspi_dma;
650
651 mcspi = spi_master_get_devdata(spi->master);
652 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
653
654 complete(&mcspi_dma->dma_rx_completion);
655
656 /* We must disable the DMA RX request */
657 omap2_mcspi_set_dma_req(spi, 1, 0);
658 }
659
660 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
661 {
662 struct spi_device *spi = data;
663 struct omap2_mcspi *mcspi;
664 struct omap2_mcspi_dma *mcspi_dma;
665
666 mcspi = spi_master_get_devdata(spi->master);
667 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
668
669 complete(&mcspi_dma->dma_tx_completion);
670
671 /* We must disable the DMA TX request */
672 omap2_mcspi_set_dma_req(spi, 0, 0);
673 }
674
675 static int omap2_mcspi_request_dma(struct spi_device *spi)
676 {
677 struct spi_master *master = spi->master;
678 struct omap2_mcspi *mcspi;
679 struct omap2_mcspi_dma *mcspi_dma;
680
681 mcspi = spi_master_get_devdata(master);
682 mcspi_dma = mcspi->dma_channels + spi->chip_select;
683
684 if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
685 omap2_mcspi_dma_rx_callback, spi,
686 &mcspi_dma->dma_rx_channel)) {
687 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
688 return -EAGAIN;
689 }
690
691 if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
692 omap2_mcspi_dma_tx_callback, spi,
693 &mcspi_dma->dma_tx_channel)) {
694 omap_free_dma(mcspi_dma->dma_rx_channel);
695 mcspi_dma->dma_rx_channel = -1;
696 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
697 return -EAGAIN;
698 }
699
700 init_completion(&mcspi_dma->dma_rx_completion);
701 init_completion(&mcspi_dma->dma_tx_completion);
702
703 return 0;
704 }
705
706 static int omap2_mcspi_setup(struct spi_device *spi)
707 {
708 int ret;
709 struct omap2_mcspi *mcspi;
710 struct omap2_mcspi_dma *mcspi_dma;
711 struct omap2_mcspi_cs *cs = spi->controller_state;
712
713 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
714 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
715 spi->bits_per_word);
716 return -EINVAL;
717 }
718
719 mcspi = spi_master_get_devdata(spi->master);
720 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
721
722 if (!cs) {
723 cs = kzalloc(sizeof *cs, GFP_KERNEL);
724 if (!cs)
725 return -ENOMEM;
726 cs->base = mcspi->base + spi->chip_select * 0x14;
727 cs->phys = mcspi->phys + spi->chip_select * 0x14;
728 cs->chconf0 = 0;
729 spi->controller_state = cs;
730 /* Link this to context save list */
731 list_add_tail(&cs->node,
732 &omap2_mcspi_ctx[mcspi->master->bus_num - 1].cs);
733 }
734
735 if (mcspi_dma->dma_rx_channel == -1
736 || mcspi_dma->dma_tx_channel == -1) {
737 ret = omap2_mcspi_request_dma(spi);
738 if (ret < 0)
739 return ret;
740 }
741
742 if (omap2_mcspi_enable_clocks(mcspi))
743 return -ENODEV;
744
745 ret = omap2_mcspi_setup_transfer(spi, NULL);
746 omap2_mcspi_disable_clocks(mcspi);
747
748 return ret;
749 }
750
751 static void omap2_mcspi_cleanup(struct spi_device *spi)
752 {
753 struct omap2_mcspi *mcspi;
754 struct omap2_mcspi_dma *mcspi_dma;
755 struct omap2_mcspi_cs *cs;
756
757 mcspi = spi_master_get_devdata(spi->master);
758 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
759
760 if (spi->controller_state) {
761 /* Unlink controller state from context save list */
762 cs = spi->controller_state;
763 list_del(&cs->node);
764
765 kfree(spi->controller_state);
766 }
767
768 if (mcspi_dma->dma_rx_channel != -1) {
769 omap_free_dma(mcspi_dma->dma_rx_channel);
770 mcspi_dma->dma_rx_channel = -1;
771 }
772 if (mcspi_dma->dma_tx_channel != -1) {
773 omap_free_dma(mcspi_dma->dma_tx_channel);
774 mcspi_dma->dma_tx_channel = -1;
775 }
776 }
777
778 static void omap2_mcspi_work(struct work_struct *work)
779 {
780 struct omap2_mcspi *mcspi;
781
782 mcspi = container_of(work, struct omap2_mcspi, work);
783 spin_lock_irq(&mcspi->lock);
784
785 if (omap2_mcspi_enable_clocks(mcspi))
786 goto out;
787
788 /* We only enable one channel at a time -- the one whose message is
789 * at the head of the queue -- although this controller would gladly
790 * arbitrate among multiple channels. This corresponds to "single
791 * channel" master mode. As a side effect, we need to manage the
792 * chipselect with the FORCE bit ... CS != channel enable.
793 */
794 while (!list_empty(&mcspi->msg_queue)) {
795 struct spi_message *m;
796 struct spi_device *spi;
797 struct spi_transfer *t = NULL;
798 int cs_active = 0;
799 struct omap2_mcspi_cs *cs;
800 int par_override = 0;
801 int status = 0;
802 u32 chconf;
803
804 m = container_of(mcspi->msg_queue.next, struct spi_message,
805 queue);
806
807 list_del_init(&m->queue);
808 spin_unlock_irq(&mcspi->lock);
809
810 spi = m->spi;
811 cs = spi->controller_state;
812
813 omap2_mcspi_set_enable(spi, 1);
814 list_for_each_entry(t, &m->transfers, transfer_list) {
815 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
816 status = -EINVAL;
817 break;
818 }
819 if (par_override || t->speed_hz || t->bits_per_word) {
820 par_override = 1;
821 status = omap2_mcspi_setup_transfer(spi, t);
822 if (status < 0)
823 break;
824 if (!t->speed_hz && !t->bits_per_word)
825 par_override = 0;
826 }
827
828 if (!cs_active) {
829 omap2_mcspi_force_cs(spi, 1);
830 cs_active = 1;
831 }
832
833 chconf = mcspi_cached_chconf0(spi);
834 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
835 if (t->tx_buf == NULL)
836 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
837 else if (t->rx_buf == NULL)
838 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
839 mcspi_write_chconf0(spi, chconf);
840
841 if (t->len) {
842 unsigned count;
843
844 /* RX_ONLY mode needs dummy data in TX reg */
845 if (t->tx_buf == NULL)
846 __raw_writel(0, cs->base
847 + OMAP2_MCSPI_TX0);
848
849 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
850 count = omap2_mcspi_txrx_dma(spi, t);
851 else
852 count = omap2_mcspi_txrx_pio(spi, t);
853 m->actual_length += count;
854
855 if (count != t->len) {
856 status = -EIO;
857 break;
858 }
859 }
860
861 if (t->delay_usecs)
862 udelay(t->delay_usecs);
863
864 /* ignore the "leave it on after last xfer" hint */
865 if (t->cs_change) {
866 omap2_mcspi_force_cs(spi, 0);
867 cs_active = 0;
868 }
869 }
870
871 /* Restore defaults if they were overriden */
872 if (par_override) {
873 par_override = 0;
874 status = omap2_mcspi_setup_transfer(spi, NULL);
875 }
876
877 if (cs_active)
878 omap2_mcspi_force_cs(spi, 0);
879
880 omap2_mcspi_set_enable(spi, 0);
881
882 m->status = status;
883 m->complete(m->context);
884
885 spin_lock_irq(&mcspi->lock);
886 }
887
888 omap2_mcspi_disable_clocks(mcspi);
889
890 out:
891 spin_unlock_irq(&mcspi->lock);
892 }
893
894 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
895 {
896 struct omap2_mcspi *mcspi;
897 unsigned long flags;
898 struct spi_transfer *t;
899
900 m->actual_length = 0;
901 m->status = 0;
902
903 /* reject invalid messages and transfers */
904 if (list_empty(&m->transfers) || !m->complete)
905 return -EINVAL;
906 list_for_each_entry(t, &m->transfers, transfer_list) {
907 const void *tx_buf = t->tx_buf;
908 void *rx_buf = t->rx_buf;
909 unsigned len = t->len;
910
911 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
912 || (len && !(rx_buf || tx_buf))
913 || (t->bits_per_word &&
914 ( t->bits_per_word < 4
915 || t->bits_per_word > 32))) {
916 dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
917 t->speed_hz,
918 len,
919 tx_buf ? "tx" : "",
920 rx_buf ? "rx" : "",
921 t->bits_per_word);
922 return -EINVAL;
923 }
924 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
925 dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
926 t->speed_hz,
927 OMAP2_MCSPI_MAX_FREQ/(1<<16));
928 return -EINVAL;
929 }
930
931 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
932 continue;
933
934 /* Do DMA mapping "early" for better error reporting and
935 * dcache use. Note that if dma_unmap_single() ever starts
936 * to do real work on ARM, we'd need to clean up mappings
937 * for previous transfers on *ALL* exits of this loop...
938 */
939 if (tx_buf != NULL) {
940 t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
941 len, DMA_TO_DEVICE);
942 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
943 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
944 'T', len);
945 return -EINVAL;
946 }
947 }
948 if (rx_buf != NULL) {
949 t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
950 DMA_FROM_DEVICE);
951 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
952 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
953 'R', len);
954 if (tx_buf != NULL)
955 dma_unmap_single(NULL, t->tx_dma,
956 len, DMA_TO_DEVICE);
957 return -EINVAL;
958 }
959 }
960 }
961
962 mcspi = spi_master_get_devdata(spi->master);
963
964 spin_lock_irqsave(&mcspi->lock, flags);
965 list_add_tail(&m->queue, &mcspi->msg_queue);
966 queue_work(omap2_mcspi_wq, &mcspi->work);
967 spin_unlock_irqrestore(&mcspi->lock, flags);
968
969 return 0;
970 }
971
972 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
973 {
974 struct spi_master *master = mcspi->master;
975 u32 tmp;
976
977 if (omap2_mcspi_enable_clocks(mcspi))
978 return -1;
979
980 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
981 OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
982 do {
983 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
984 } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
985
986 tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
987 OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
988 OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
989 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
990 omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
991
992 tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
993 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
994 omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
995
996 omap2_mcspi_set_master_mode(master);
997 omap2_mcspi_disable_clocks(mcspi);
998 return 0;
999 }
1000
1001 static u8 __initdata spi1_rxdma_id [] = {
1002 OMAP24XX_DMA_SPI1_RX0,
1003 OMAP24XX_DMA_SPI1_RX1,
1004 OMAP24XX_DMA_SPI1_RX2,
1005 OMAP24XX_DMA_SPI1_RX3,
1006 };
1007
1008 static u8 __initdata spi1_txdma_id [] = {
1009 OMAP24XX_DMA_SPI1_TX0,
1010 OMAP24XX_DMA_SPI1_TX1,
1011 OMAP24XX_DMA_SPI1_TX2,
1012 OMAP24XX_DMA_SPI1_TX3,
1013 };
1014
1015 static u8 __initdata spi2_rxdma_id[] = {
1016 OMAP24XX_DMA_SPI2_RX0,
1017 OMAP24XX_DMA_SPI2_RX1,
1018 };
1019
1020 static u8 __initdata spi2_txdma_id[] = {
1021 OMAP24XX_DMA_SPI2_TX0,
1022 OMAP24XX_DMA_SPI2_TX1,
1023 };
1024
1025 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1026 || defined(CONFIG_ARCH_OMAP4)
1027 static u8 __initdata spi3_rxdma_id[] = {
1028 OMAP24XX_DMA_SPI3_RX0,
1029 OMAP24XX_DMA_SPI3_RX1,
1030 };
1031
1032 static u8 __initdata spi3_txdma_id[] = {
1033 OMAP24XX_DMA_SPI3_TX0,
1034 OMAP24XX_DMA_SPI3_TX1,
1035 };
1036 #endif
1037
1038 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1039 static u8 __initdata spi4_rxdma_id[] = {
1040 OMAP34XX_DMA_SPI4_RX0,
1041 };
1042
1043 static u8 __initdata spi4_txdma_id[] = {
1044 OMAP34XX_DMA_SPI4_TX0,
1045 };
1046 #endif
1047
1048 static int __init omap2_mcspi_probe(struct platform_device *pdev)
1049 {
1050 struct spi_master *master;
1051 struct omap2_mcspi *mcspi;
1052 struct resource *r;
1053 int status = 0, i;
1054 const u8 *rxdma_id, *txdma_id;
1055 unsigned num_chipselect;
1056
1057 switch (pdev->id) {
1058 case 1:
1059 rxdma_id = spi1_rxdma_id;
1060 txdma_id = spi1_txdma_id;
1061 num_chipselect = 4;
1062 break;
1063 case 2:
1064 rxdma_id = spi2_rxdma_id;
1065 txdma_id = spi2_txdma_id;
1066 num_chipselect = 2;
1067 break;
1068 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
1069 || defined(CONFIG_ARCH_OMAP4)
1070 case 3:
1071 rxdma_id = spi3_rxdma_id;
1072 txdma_id = spi3_txdma_id;
1073 num_chipselect = 2;
1074 break;
1075 #endif
1076 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1077 case 4:
1078 rxdma_id = spi4_rxdma_id;
1079 txdma_id = spi4_txdma_id;
1080 num_chipselect = 1;
1081 break;
1082 #endif
1083 default:
1084 return -EINVAL;
1085 }
1086
1087 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1088 if (master == NULL) {
1089 dev_dbg(&pdev->dev, "master allocation failed\n");
1090 return -ENOMEM;
1091 }
1092
1093 /* the spi->mode bits understood by this driver: */
1094 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1095
1096 if (pdev->id != -1)
1097 master->bus_num = pdev->id;
1098
1099 master->setup = omap2_mcspi_setup;
1100 master->transfer = omap2_mcspi_transfer;
1101 master->cleanup = omap2_mcspi_cleanup;
1102 master->num_chipselect = num_chipselect;
1103
1104 dev_set_drvdata(&pdev->dev, master);
1105
1106 mcspi = spi_master_get_devdata(master);
1107 mcspi->master = master;
1108
1109 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1110 if (r == NULL) {
1111 status = -ENODEV;
1112 goto err1;
1113 }
1114 if (!request_mem_region(r->start, (r->end - r->start) + 1,
1115 dev_name(&pdev->dev))) {
1116 status = -EBUSY;
1117 goto err1;
1118 }
1119
1120 mcspi->phys = r->start;
1121 mcspi->base = ioremap(r->start, r->end - r->start + 1);
1122 if (!mcspi->base) {
1123 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1124 status = -ENOMEM;
1125 goto err1aa;
1126 }
1127
1128 INIT_WORK(&mcspi->work, omap2_mcspi_work);
1129
1130 spin_lock_init(&mcspi->lock);
1131 INIT_LIST_HEAD(&mcspi->msg_queue);
1132 INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
1133
1134 mcspi->ick = clk_get(&pdev->dev, "ick");
1135 if (IS_ERR(mcspi->ick)) {
1136 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1137 status = PTR_ERR(mcspi->ick);
1138 goto err1a;
1139 }
1140 mcspi->fck = clk_get(&pdev->dev, "fck");
1141 if (IS_ERR(mcspi->fck)) {
1142 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1143 status = PTR_ERR(mcspi->fck);
1144 goto err2;
1145 }
1146
1147 mcspi->dma_channels = kcalloc(master->num_chipselect,
1148 sizeof(struct omap2_mcspi_dma),
1149 GFP_KERNEL);
1150
1151 if (mcspi->dma_channels == NULL)
1152 goto err3;
1153
1154 for (i = 0; i < num_chipselect; i++) {
1155 mcspi->dma_channels[i].dma_rx_channel = -1;
1156 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1157 mcspi->dma_channels[i].dma_tx_channel = -1;
1158 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1159 }
1160
1161 if (omap2_mcspi_reset(mcspi) < 0)
1162 goto err4;
1163
1164 status = spi_register_master(master);
1165 if (status < 0)
1166 goto err4;
1167
1168 return status;
1169
1170 err4:
1171 kfree(mcspi->dma_channels);
1172 err3:
1173 clk_put(mcspi->fck);
1174 err2:
1175 clk_put(mcspi->ick);
1176 err1a:
1177 iounmap(mcspi->base);
1178 err1aa:
1179 release_mem_region(r->start, (r->end - r->start) + 1);
1180 err1:
1181 spi_master_put(master);
1182 return status;
1183 }
1184
1185 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1186 {
1187 struct spi_master *master;
1188 struct omap2_mcspi *mcspi;
1189 struct omap2_mcspi_dma *dma_channels;
1190 struct resource *r;
1191 void __iomem *base;
1192
1193 master = dev_get_drvdata(&pdev->dev);
1194 mcspi = spi_master_get_devdata(master);
1195 dma_channels = mcspi->dma_channels;
1196
1197 clk_put(mcspi->fck);
1198 clk_put(mcspi->ick);
1199
1200 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1201 release_mem_region(r->start, (r->end - r->start) + 1);
1202
1203 base = mcspi->base;
1204 spi_unregister_master(master);
1205 iounmap(base);
1206 kfree(dma_channels);
1207
1208 return 0;
1209 }
1210
1211 /* work with hotplug and coldplug */
1212 MODULE_ALIAS("platform:omap2_mcspi");
1213
1214 static struct platform_driver omap2_mcspi_driver = {
1215 .driver = {
1216 .name = "omap2_mcspi",
1217 .owner = THIS_MODULE,
1218 },
1219 .remove = __exit_p(omap2_mcspi_remove),
1220 };
1221
1222
1223 static int __init omap2_mcspi_init(void)
1224 {
1225 omap2_mcspi_wq = create_singlethread_workqueue(
1226 omap2_mcspi_driver.driver.name);
1227 if (omap2_mcspi_wq == NULL)
1228 return -1;
1229 return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1230 }
1231 subsys_initcall(omap2_mcspi_init);
1232
1233 static void __exit omap2_mcspi_exit(void)
1234 {
1235 platform_driver_unregister(&omap2_mcspi_driver);
1236
1237 destroy_workqueue(omap2_mcspi_wq);
1238 }
1239 module_exit(omap2_mcspi_exit);
1240
1241 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.064173 seconds and 5 git commands to generate.