drivers/spi/spi-ath79.c

   1 /*
   2  * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
   3  *
   4  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * This driver has been based on the spi-gpio.c:
   7  *      Copyright (C) 2006,2008 David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/delay.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/workqueue.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/io.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/spi_bitbang.h>
  24 #include <linux/bitops.h>
  25 #include <linux/gpio.h>
  26 #include <linux/clk.h>
  27 #include <linux/err.h>
  28
  29 #include <asm/mach-ath79/ar71xx_regs.h>
  30 #include <asm/mach-ath79/ath79_spi_platform.h>
  31
  32 #define DRV_NAME        "ath79-spi"
  33
  34 #define ATH79_SPI_RRW_DELAY_FACTOR      12000
  35 #define MHZ                             (1000 * 1000)
  36
  37 struct ath79_spi {
  38         struct spi_bitbang      bitbang;
  39         u32                     ioc_base;
  40         u32                     reg_ctrl;
  41         void __iomem            *base;
  42         struct clk              *clk;
  43         unsigned                rrw_delay;
  44 };
  45
  46 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
  47 {
  48         return ioread32(sp->base + reg);
  49 }
  50
  51 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
  52 {
  53         iowrite32(val, sp->base + reg);
  54 }
  55
  56 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
  57 {
  58         return spi_master_get_devdata(spi->master);
  59 }
  60
  61 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
  62 {
  63         if (nsecs > sp->rrw_delay)
  64                 ndelay(nsecs - sp->rrw_delay);
  65 }
  66
  67 static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
  68 {
  69         struct ath79_spi *sp = ath79_spidev_to_sp(spi);
  70         int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
  71
  72         if (is_active) {
  73                 /* set initial clock polarity */
  74                 if (spi->mode & SPI_CPOL)
  75                         sp->ioc_base |= AR71XX_SPI_IOC_CLK;
  76                 else
  77                         sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
  78
  79                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
  80         }
  81
  82         if (spi->chip_select) {
  83                 struct ath79_spi_controller_data *cdata = spi->controller_data;
  84
  85                 /* SPI is normally active-low */
  86                 gpio_set_value(cdata->gpio, cs_high);
  87         } else {
  88                 if (cs_high)
  89                         sp->ioc_base |= AR71XX_SPI_IOC_CS0;
  90                 else
  91                         sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
  92
  93                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
  94         }
  95
  96 }
  97
  98 static void ath79_spi_enable(struct ath79_spi *sp)
  99 {
 100         /* enable GPIO mode */
 101         ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
 102
 103         /* save CTRL register */
 104         sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
 105         sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
 106
 107         /* TODO: setup speed? */
 108         ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
 109 }
 110
 111 static void ath79_spi_disable(struct ath79_spi *sp)
 112 {
 113         /* restore CTRL register */
 114         ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
 115         /* disable GPIO mode */
 116         ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
 117 }
 118
 119 static int ath79_spi_setup_cs(struct spi_device *spi)
 120 {
 121         struct ath79_spi_controller_data *cdata;
 122         int status;
 123
 124         cdata = spi->controller_data;
 125         if (spi->chip_select && !cdata)
 126                 return -EINVAL;
 127
 128         status = 0;
 129         if (spi->chip_select) {
 130                 unsigned long flags;
 131
 132                 flags = GPIOF_DIR_OUT;
 133                 if (spi->mode & SPI_CS_HIGH)
 134                         flags |= GPIOF_INIT_LOW;
 135                 else
 136                         flags |= GPIOF_INIT_HIGH;
 137
 138                 status = gpio_request_one(cdata->gpio, flags,
 139                                           dev_name(&spi->dev));
 140         }
 141
 142         return status;
 143 }
 144
 145 static void ath79_spi_cleanup_cs(struct spi_device *spi)
 146 {
 147         if (spi->chip_select) {
 148                 struct ath79_spi_controller_data *cdata = spi->controller_data;
 149                 gpio_free(cdata->gpio);
 150         }
 151 }
 152
 153 static int ath79_spi_setup(struct spi_device *spi)
 154 {
 155         int status = 0;
 156
 157         if (!spi->controller_state) {
 158                 status = ath79_spi_setup_cs(spi);
 159                 if (status)
 160                         return status;
 161         }
 162
 163         status = spi_bitbang_setup(spi);
 164         if (status && !spi->controller_state)
 165                 ath79_spi_cleanup_cs(spi);
 166
 167         return status;
 168 }
 169
 170 static void ath79_spi_cleanup(struct spi_device *spi)
 171 {
 172         ath79_spi_cleanup_cs(spi);
 173         spi_bitbang_cleanup(spi);
 174 }
 175
 176 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
 177                                u32 word, u8 bits)
 178 {
 179         struct ath79_spi *sp = ath79_spidev_to_sp(spi);
 180         u32 ioc = sp->ioc_base;
 181
 182         /* clock starts at inactive polarity */
 183         for (word <<= (32 - bits); likely(bits); bits--) {
 184                 u32 out;
 185
 186                 if (word & (1 << 31))
 187                         out = ioc | AR71XX_SPI_IOC_DO;
 188                 else
 189                         out = ioc & ~AR71XX_SPI_IOC_DO;
 190
 191                 /* setup MSB (to slave) on trailing edge */
 192                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
 193                 ath79_spi_delay(sp, nsecs);
 194                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
 195                 ath79_spi_delay(sp, nsecs);
 196                 if (bits == 1)
 197                         ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
 198
 199                 word <<= 1;
 200         }
 201
 202         return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
 203 }
 204
 205 static int ath79_spi_probe(struct platform_device *pdev)
 206 {
 207         struct spi_master *master;
 208         struct ath79_spi *sp;
 209         struct ath79_spi_platform_data *pdata;
 210         struct resource *r;
 211         unsigned long rate;
 212         int ret;
 213
 214         master = spi_alloc_master(&pdev->dev, sizeof(*sp));
 215         if (master == NULL) {
 216                 dev_err(&pdev->dev, "failed to allocate spi master\n");
 217                 return -ENOMEM;
 218         }
 219
 220         sp = spi_master_get_devdata(master);
 221         platform_set_drvdata(pdev, sp);
 222
 223         pdata = dev_get_platdata(&pdev->dev);
 224
 225         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
 226         master->setup = ath79_spi_setup;
 227         master->cleanup = ath79_spi_cleanup;
 228         if (pdata) {
 229                 master->bus_num = pdata->bus_num;
 230                 master->num_chipselect = pdata->num_chipselect;
 231         }
 232
 233         sp->bitbang.master = master;
 234         sp->bitbang.chipselect = ath79_spi_chipselect;
 235         sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
 236         sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
 237         sp->bitbang.flags = SPI_CS_HIGH;
 238
 239         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 240         if (r == NULL) {
 241                 ret = -ENOENT;
 242                 goto err_put_master;
 243         }
 244
 245         sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 246         if (!sp->base) {
 247                 ret = -ENXIO;
 248                 goto err_put_master;
 249         }
 250
 251         sp->clk = devm_clk_get(&pdev->dev, "ahb");
 252         if (IS_ERR(sp->clk)) {
 253                 ret = PTR_ERR(sp->clk);
 254                 goto err_put_master;
 255         }
 256
 257         ret = clk_enable(sp->clk);
 258         if (ret)
 259                 goto err_put_master;
 260
 261         rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
 262         if (!rate) {
 263                 ret = -EINVAL;
 264                 goto err_clk_disable;
 265         }
 266
 267         sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
 268         dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
 269                 sp->rrw_delay);
 270
 271         ath79_spi_enable(sp);
 272         ret = spi_bitbang_start(&sp->bitbang);
 273         if (ret)
 274                 goto err_disable;
 275
 276         return 0;
 277
 278 err_disable:
 279         ath79_spi_disable(sp);
 280 err_clk_disable:
 281         clk_disable(sp->clk);
 282 err_put_master:
 283         spi_master_put(sp->bitbang.master);
 284
 285         return ret;
 286 }
 287
 288 static int ath79_spi_remove(struct platform_device *pdev)
 289 {
 290         struct ath79_spi *sp = platform_get_drvdata(pdev);
 291
 292         spi_bitbang_stop(&sp->bitbang);
 293         ath79_spi_disable(sp);
 294         clk_disable(sp->clk);
 295         spi_master_put(sp->bitbang.master);
 296
 297         return 0;
 298 }
 299
 300 static void ath79_spi_shutdown(struct platform_device *pdev)
 301 {
 302         ath79_spi_remove(pdev);
 303 }
 304
 305 static struct platform_driver ath79_spi_driver = {
 306         .probe          = ath79_spi_probe,
 307         .remove         = ath79_spi_remove,
 308         .shutdown       = ath79_spi_shutdown,
 309         .driver         = {
 310                 .name   = DRV_NAME,
 311                 .owner  = THIS_MODULE,
 312         },
 313 };
 314 module_platform_driver(ath79_spi_driver);
 315
 316 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
 317 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 318 MODULE_LICENSE("GPL v2");
 319 MODULE_ALIAS("platform:" DRV_NAME);