2 * Driver for Atmel AT32 and AT91 SPI Controllers
4 * Copyright (C) 2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/dmaengine.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <linux/platform_data/atmel.h>
23 #include <linux/platform_data/dma-atmel.h>
27 #include <linux/gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/pm_runtime.h>
31 /* SPI register offsets */
34 #define SPI_RDR 0x0008
35 #define SPI_TDR 0x000c
37 #define SPI_IER 0x0014
38 #define SPI_IDR 0x0018
39 #define SPI_IMR 0x001c
40 #define SPI_CSR0 0x0030
41 #define SPI_CSR1 0x0034
42 #define SPI_CSR2 0x0038
43 #define SPI_CSR3 0x003c
44 #define SPI_FMR 0x0040
45 #define SPI_FLR 0x0044
46 #define SPI_VERSION 0x00fc
47 #define SPI_RPR 0x0100
48 #define SPI_RCR 0x0104
49 #define SPI_TPR 0x0108
50 #define SPI_TCR 0x010c
51 #define SPI_RNPR 0x0110
52 #define SPI_RNCR 0x0114
53 #define SPI_TNPR 0x0118
54 #define SPI_TNCR 0x011c
55 #define SPI_PTCR 0x0120
56 #define SPI_PTSR 0x0124
59 #define SPI_SPIEN_OFFSET 0
60 #define SPI_SPIEN_SIZE 1
61 #define SPI_SPIDIS_OFFSET 1
62 #define SPI_SPIDIS_SIZE 1
63 #define SPI_SWRST_OFFSET 7
64 #define SPI_SWRST_SIZE 1
65 #define SPI_LASTXFER_OFFSET 24
66 #define SPI_LASTXFER_SIZE 1
67 #define SPI_TXFCLR_OFFSET 16
68 #define SPI_TXFCLR_SIZE 1
69 #define SPI_RXFCLR_OFFSET 17
70 #define SPI_RXFCLR_SIZE 1
71 #define SPI_FIFOEN_OFFSET 30
72 #define SPI_FIFOEN_SIZE 1
73 #define SPI_FIFODIS_OFFSET 31
74 #define SPI_FIFODIS_SIZE 1
77 #define SPI_MSTR_OFFSET 0
78 #define SPI_MSTR_SIZE 1
79 #define SPI_PS_OFFSET 1
81 #define SPI_PCSDEC_OFFSET 2
82 #define SPI_PCSDEC_SIZE 1
83 #define SPI_FDIV_OFFSET 3
84 #define SPI_FDIV_SIZE 1
85 #define SPI_MODFDIS_OFFSET 4
86 #define SPI_MODFDIS_SIZE 1
87 #define SPI_WDRBT_OFFSET 5
88 #define SPI_WDRBT_SIZE 1
89 #define SPI_LLB_OFFSET 7
90 #define SPI_LLB_SIZE 1
91 #define SPI_PCS_OFFSET 16
92 #define SPI_PCS_SIZE 4
93 #define SPI_DLYBCS_OFFSET 24
94 #define SPI_DLYBCS_SIZE 8
96 /* Bitfields in RDR */
97 #define SPI_RD_OFFSET 0
98 #define SPI_RD_SIZE 16
100 /* Bitfields in TDR */
101 #define SPI_TD_OFFSET 0
102 #define SPI_TD_SIZE 16
104 /* Bitfields in SR */
105 #define SPI_RDRF_OFFSET 0
106 #define SPI_RDRF_SIZE 1
107 #define SPI_TDRE_OFFSET 1
108 #define SPI_TDRE_SIZE 1
109 #define SPI_MODF_OFFSET 2
110 #define SPI_MODF_SIZE 1
111 #define SPI_OVRES_OFFSET 3
112 #define SPI_OVRES_SIZE 1
113 #define SPI_ENDRX_OFFSET 4
114 #define SPI_ENDRX_SIZE 1
115 #define SPI_ENDTX_OFFSET 5
116 #define SPI_ENDTX_SIZE 1
117 #define SPI_RXBUFF_OFFSET 6
118 #define SPI_RXBUFF_SIZE 1
119 #define SPI_TXBUFE_OFFSET 7
120 #define SPI_TXBUFE_SIZE 1
121 #define SPI_NSSR_OFFSET 8
122 #define SPI_NSSR_SIZE 1
123 #define SPI_TXEMPTY_OFFSET 9
124 #define SPI_TXEMPTY_SIZE 1
125 #define SPI_SPIENS_OFFSET 16
126 #define SPI_SPIENS_SIZE 1
127 #define SPI_TXFEF_OFFSET 24
128 #define SPI_TXFEF_SIZE 1
129 #define SPI_TXFFF_OFFSET 25
130 #define SPI_TXFFF_SIZE 1
131 #define SPI_TXFTHF_OFFSET 26
132 #define SPI_TXFTHF_SIZE 1
133 #define SPI_RXFEF_OFFSET 27
134 #define SPI_RXFEF_SIZE 1
135 #define SPI_RXFFF_OFFSET 28
136 #define SPI_RXFFF_SIZE 1
137 #define SPI_RXFTHF_OFFSET 29
138 #define SPI_RXFTHF_SIZE 1
139 #define SPI_TXFPTEF_OFFSET 30
140 #define SPI_TXFPTEF_SIZE 1
141 #define SPI_RXFPTEF_OFFSET 31
142 #define SPI_RXFPTEF_SIZE 1
144 /* Bitfields in CSR0 */
145 #define SPI_CPOL_OFFSET 0
146 #define SPI_CPOL_SIZE 1
147 #define SPI_NCPHA_OFFSET 1
148 #define SPI_NCPHA_SIZE 1
149 #define SPI_CSAAT_OFFSET 3
150 #define SPI_CSAAT_SIZE 1
151 #define SPI_BITS_OFFSET 4
152 #define SPI_BITS_SIZE 4
153 #define SPI_SCBR_OFFSET 8
154 #define SPI_SCBR_SIZE 8
155 #define SPI_DLYBS_OFFSET 16
156 #define SPI_DLYBS_SIZE 8
157 #define SPI_DLYBCT_OFFSET 24
158 #define SPI_DLYBCT_SIZE 8
160 /* Bitfields in RCR */
161 #define SPI_RXCTR_OFFSET 0
162 #define SPI_RXCTR_SIZE 16
164 /* Bitfields in TCR */
165 #define SPI_TXCTR_OFFSET 0
166 #define SPI_TXCTR_SIZE 16
168 /* Bitfields in RNCR */
169 #define SPI_RXNCR_OFFSET 0
170 #define SPI_RXNCR_SIZE 16
172 /* Bitfields in TNCR */
173 #define SPI_TXNCR_OFFSET 0
174 #define SPI_TXNCR_SIZE 16
176 /* Bitfields in PTCR */
177 #define SPI_RXTEN_OFFSET 0
178 #define SPI_RXTEN_SIZE 1
179 #define SPI_RXTDIS_OFFSET 1
180 #define SPI_RXTDIS_SIZE 1
181 #define SPI_TXTEN_OFFSET 8
182 #define SPI_TXTEN_SIZE 1
183 #define SPI_TXTDIS_OFFSET 9
184 #define SPI_TXTDIS_SIZE 1
186 /* Bitfields in FMR */
187 #define SPI_TXRDYM_OFFSET 0
188 #define SPI_TXRDYM_SIZE 2
189 #define SPI_RXRDYM_OFFSET 4
190 #define SPI_RXRDYM_SIZE 2
191 #define SPI_TXFTHRES_OFFSET 16
192 #define SPI_TXFTHRES_SIZE 6
193 #define SPI_RXFTHRES_OFFSET 24
194 #define SPI_RXFTHRES_SIZE 6
196 /* Bitfields in FLR */
197 #define SPI_TXFL_OFFSET 0
198 #define SPI_TXFL_SIZE 6
199 #define SPI_RXFL_OFFSET 16
200 #define SPI_RXFL_SIZE 6
202 /* Constants for BITS */
203 #define SPI_BITS_8_BPT 0
204 #define SPI_BITS_9_BPT 1
205 #define SPI_BITS_10_BPT 2
206 #define SPI_BITS_11_BPT 3
207 #define SPI_BITS_12_BPT 4
208 #define SPI_BITS_13_BPT 5
209 #define SPI_BITS_14_BPT 6
210 #define SPI_BITS_15_BPT 7
211 #define SPI_BITS_16_BPT 8
212 #define SPI_ONE_DATA 0
213 #define SPI_TWO_DATA 1
214 #define SPI_FOUR_DATA 2
216 /* Bit manipulation macros */
217 #define SPI_BIT(name) \
218 (1 << SPI_##name##_OFFSET)
219 #define SPI_BF(name, value) \
220 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
221 #define SPI_BFEXT(name, value) \
222 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
223 #define SPI_BFINS(name, value, old) \
224 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
225 | SPI_BF(name, value))
227 /* Register access macros */
229 #define spi_readl(port, reg) \
230 __raw_readl((port)->regs + SPI_##reg)
231 #define spi_writel(port, reg, value) \
232 __raw_writel((value), (port)->regs + SPI_##reg)
234 #define spi_readw(port, reg) \
235 __raw_readw((port)->regs + SPI_##reg)
236 #define spi_writew(port, reg, value) \
237 __raw_writew((value), (port)->regs + SPI_##reg)
239 #define spi_readb(port, reg) \
240 __raw_readb((port)->regs + SPI_##reg)
241 #define spi_writeb(port, reg, value) \
242 __raw_writeb((value), (port)->regs + SPI_##reg)
244 #define spi_readl(port, reg) \
245 readl_relaxed((port)->regs + SPI_##reg)
246 #define spi_writel(port, reg, value) \
247 writel_relaxed((value), (port)->regs + SPI_##reg)
249 #define spi_readw(port, reg) \
250 readw_relaxed((port)->regs + SPI_##reg)
251 #define spi_writew(port, reg, value) \
252 writew_relaxed((value), (port)->regs + SPI_##reg)
254 #define spi_readb(port, reg) \
255 readb_relaxed((port)->regs + SPI_##reg)
256 #define spi_writeb(port, reg, value) \
257 writeb_relaxed((value), (port)->regs + SPI_##reg)
259 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
260 * cache operations; better heuristics consider wordsize and bitrate.
262 #define DMA_MIN_BYTES 16
264 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
266 #define AUTOSUSPEND_TIMEOUT 2000
268 struct atmel_spi_dma
{
269 struct dma_chan
*chan_rx
;
270 struct dma_chan
*chan_tx
;
271 struct scatterlist sgrx
;
272 struct scatterlist sgtx
;
273 struct dma_async_tx_descriptor
*data_desc_rx
;
274 struct dma_async_tx_descriptor
*data_desc_tx
;
276 struct at_dma_slave dma_slave
;
279 struct atmel_spi_caps
{
282 bool has_dma_support
;
286 * The core SPI transfer engine just talks to a register bank to set up
287 * DMA transfers; transfer queue progress is driven by IRQs. The clock
288 * framework provides the base clock, subdivided for each spi_device.
298 struct platform_device
*pdev
;
300 struct spi_transfer
*current_transfer
;
301 int current_remaining_bytes
;
304 struct completion xfer_completion
;
308 dma_addr_t buffer_dma
;
310 struct atmel_spi_caps caps
;
316 struct atmel_spi_dma dma
;
324 /* Controller-specific per-slave state */
325 struct atmel_spi_device
{
326 unsigned int npcs_pin
;
330 #define BUFFER_SIZE PAGE_SIZE
331 #define INVALID_DMA_ADDRESS 0xffffffff
334 * Version 2 of the SPI controller has
336 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
337 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
339 * - SPI_CSRx.SBCR allows faster clocking
341 static bool atmel_spi_is_v2(struct atmel_spi
*as
)
343 return as
->caps
.is_spi2
;
347 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
348 * they assume that spi slave device state will not change on deselect, so
349 * that automagic deselection is OK. ("NPCSx rises if no data is to be
350 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
351 * controllers have CSAAT and friends.
353 * Since the CSAAT functionality is a bit weird on newer controllers as
354 * well, we use GPIO to control nCSx pins on all controllers, updating
355 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
356 * support active-high chipselects despite the controller's belief that
357 * only active-low devices/systems exists.
359 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
360 * right when driven with GPIO. ("Mode Fault does not allow more than one
361 * Master on Chip Select 0.") No workaround exists for that ... so for
362 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
363 * and (c) will trigger that first erratum in some cases.
366 static void cs_activate(struct atmel_spi
*as
, struct spi_device
*spi
)
368 struct atmel_spi_device
*asd
= spi
->controller_state
;
369 unsigned active
= spi
->mode
& SPI_CS_HIGH
;
372 if (atmel_spi_is_v2(as
)) {
373 spi_writel(as
, CSR0
+ 4 * spi
->chip_select
, asd
->csr
);
374 /* For the low SPI version, there is a issue that PDC transfer
375 * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS
377 spi_writel(as
, CSR0
, asd
->csr
);
378 if (as
->caps
.has_wdrbt
) {
380 SPI_BF(PCS
, ~(0x01 << spi
->chip_select
))
386 SPI_BF(PCS
, ~(0x01 << spi
->chip_select
))
391 mr
= spi_readl(as
, MR
);
392 if (as
->use_cs_gpios
)
393 gpio_set_value(asd
->npcs_pin
, active
);
395 u32 cpol
= (spi
->mode
& SPI_CPOL
) ? SPI_BIT(CPOL
) : 0;
399 /* Make sure clock polarity is correct */
400 for (i
= 0; i
< spi
->master
->num_chipselect
; i
++) {
401 csr
= spi_readl(as
, CSR0
+ 4 * i
);
402 if ((csr
^ cpol
) & SPI_BIT(CPOL
))
403 spi_writel(as
, CSR0
+ 4 * i
,
404 csr
^ SPI_BIT(CPOL
));
407 mr
= spi_readl(as
, MR
);
408 mr
= SPI_BFINS(PCS
, ~(1 << spi
->chip_select
), mr
);
409 if (as
->use_cs_gpios
&& spi
->chip_select
!= 0)
410 gpio_set_value(asd
->npcs_pin
, active
);
411 spi_writel(as
, MR
, mr
);
414 dev_dbg(&spi
->dev
, "activate %u%s, mr %08x\n",
415 asd
->npcs_pin
, active
? " (high)" : "",
419 static void cs_deactivate(struct atmel_spi
*as
, struct spi_device
*spi
)
421 struct atmel_spi_device
*asd
= spi
->controller_state
;
422 unsigned active
= spi
->mode
& SPI_CS_HIGH
;
425 /* only deactivate *this* device; sometimes transfers to
426 * another device may be active when this routine is called.
428 mr
= spi_readl(as
, MR
);
429 if (~SPI_BFEXT(PCS
, mr
) & (1 << spi
->chip_select
)) {
430 mr
= SPI_BFINS(PCS
, 0xf, mr
);
431 spi_writel(as
, MR
, mr
);
434 dev_dbg(&spi
->dev
, "DEactivate %u%s, mr %08x\n",
435 asd
->npcs_pin
, active
? " (low)" : "",
438 if (!as
->use_cs_gpios
)
439 spi_writel(as
, CR
, SPI_BIT(LASTXFER
));
440 else if (atmel_spi_is_v2(as
) || spi
->chip_select
!= 0)
441 gpio_set_value(asd
->npcs_pin
, !active
);
444 static void atmel_spi_lock(struct atmel_spi
*as
) __acquires(&as
->lock
)
446 spin_lock_irqsave(&as
->lock
, as
->flags
);
449 static void atmel_spi_unlock(struct atmel_spi
*as
) __releases(&as
->lock
)
451 spin_unlock_irqrestore(&as
->lock
, as
->flags
);
454 static inline bool atmel_spi_use_dma(struct atmel_spi
*as
,
455 struct spi_transfer
*xfer
)
457 return as
->use_dma
&& xfer
->len
>= DMA_MIN_BYTES
;
460 static int atmel_spi_dma_slave_config(struct atmel_spi
*as
,
461 struct dma_slave_config
*slave_config
,
466 if (bits_per_word
> 8) {
467 slave_config
->dst_addr_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
468 slave_config
->src_addr_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
470 slave_config
->dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
471 slave_config
->src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
474 slave_config
->dst_addr
= (dma_addr_t
)as
->phybase
+ SPI_TDR
;
475 slave_config
->src_addr
= (dma_addr_t
)as
->phybase
+ SPI_RDR
;
476 slave_config
->src_maxburst
= 1;
477 slave_config
->dst_maxburst
= 1;
478 slave_config
->device_fc
= false;
481 * This driver uses fixed peripheral select mode (PS bit set to '0' in
482 * the Mode Register).
483 * So according to the datasheet, when FIFOs are available (and
484 * enabled), the Transmit FIFO operates in Multiple Data Mode.
485 * In this mode, up to 2 data, not 4, can be written into the Transmit
486 * Data Register in a single access.
487 * However, the first data has to be written into the lowest 16 bits and
488 * the second data into the highest 16 bits of the Transmit
489 * Data Register. For 8bit data (the most frequent case), it would
490 * require to rework tx_buf so each data would actualy fit 16 bits.
491 * So we'd rather write only one data at the time. Hence the transmit
492 * path works the same whether FIFOs are available (and enabled) or not.
494 slave_config
->direction
= DMA_MEM_TO_DEV
;
495 if (dmaengine_slave_config(as
->dma
.chan_tx
, slave_config
)) {
496 dev_err(&as
->pdev
->dev
,
497 "failed to configure tx dma channel\n");
502 * This driver configures the spi controller for master mode (MSTR bit
503 * set to '1' in the Mode Register).
504 * So according to the datasheet, when FIFOs are available (and
505 * enabled), the Receive FIFO operates in Single Data Mode.
506 * So the receive path works the same whether FIFOs are available (and
509 slave_config
->direction
= DMA_DEV_TO_MEM
;
510 if (dmaengine_slave_config(as
->dma
.chan_rx
, slave_config
)) {
511 dev_err(&as
->pdev
->dev
,
512 "failed to configure rx dma channel\n");
519 static int atmel_spi_configure_dma(struct atmel_spi
*as
)
521 struct dma_slave_config slave_config
;
522 struct device
*dev
= &as
->pdev
->dev
;
527 dma_cap_set(DMA_SLAVE
, mask
);
529 as
->dma
.chan_tx
= dma_request_slave_channel_reason(dev
, "tx");
530 if (IS_ERR(as
->dma
.chan_tx
)) {
531 err
= PTR_ERR(as
->dma
.chan_tx
);
532 if (err
== -EPROBE_DEFER
) {
533 dev_warn(dev
, "no DMA channel available at the moment\n");
537 "DMA TX channel not available, SPI unable to use DMA\n");
543 * No reason to check EPROBE_DEFER here since we have already requested
544 * tx channel. If it fails here, it's for another reason.
546 as
->dma
.chan_rx
= dma_request_slave_channel(dev
, "rx");
548 if (!as
->dma
.chan_rx
) {
550 "DMA RX channel not available, SPI unable to use DMA\n");
555 err
= atmel_spi_dma_slave_config(as
, &slave_config
, 8);
559 dev_info(&as
->pdev
->dev
,
560 "Using %s (tx) and %s (rx) for DMA transfers\n",
561 dma_chan_name(as
->dma
.chan_tx
),
562 dma_chan_name(as
->dma
.chan_rx
));
566 dma_release_channel(as
->dma
.chan_rx
);
567 if (!IS_ERR(as
->dma
.chan_tx
))
568 dma_release_channel(as
->dma
.chan_tx
);
572 static void atmel_spi_stop_dma(struct atmel_spi
*as
)
575 dmaengine_terminate_all(as
->dma
.chan_rx
);
577 dmaengine_terminate_all(as
->dma
.chan_tx
);
580 static void atmel_spi_release_dma(struct atmel_spi
*as
)
583 dma_release_channel(as
->dma
.chan_rx
);
585 dma_release_channel(as
->dma
.chan_tx
);
588 /* This function is called by the DMA driver from tasklet context */
589 static void dma_callback(void *data
)
591 struct spi_master
*master
= data
;
592 struct atmel_spi
*as
= spi_master_get_devdata(master
);
594 complete(&as
->xfer_completion
);
598 * Next transfer using PIO without FIFO.
600 static void atmel_spi_next_xfer_single(struct spi_master
*master
,
601 struct spi_transfer
*xfer
)
603 struct atmel_spi
*as
= spi_master_get_devdata(master
);
604 unsigned long xfer_pos
= xfer
->len
- as
->current_remaining_bytes
;
606 dev_vdbg(master
->dev
.parent
, "atmel_spi_next_xfer_pio\n");
608 /* Make sure data is not remaining in RDR */
610 while (spi_readl(as
, SR
) & SPI_BIT(RDRF
)) {
616 if (xfer
->bits_per_word
> 8)
617 spi_writel(as
, TDR
, *(u16
*)(xfer
->tx_buf
+ xfer_pos
));
619 spi_writel(as
, TDR
, *(u8
*)(xfer
->tx_buf
+ xfer_pos
));
621 spi_writel(as
, TDR
, 0);
624 dev_dbg(master
->dev
.parent
,
625 " start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
626 xfer
, xfer
->len
, xfer
->tx_buf
, xfer
->rx_buf
,
627 xfer
->bits_per_word
);
629 /* Enable relevant interrupts */
630 spi_writel(as
, IER
, SPI_BIT(RDRF
) | SPI_BIT(OVRES
));
634 * Next transfer using PIO with FIFO.
636 static void atmel_spi_next_xfer_fifo(struct spi_master
*master
,
637 struct spi_transfer
*xfer
)
639 struct atmel_spi
*as
= spi_master_get_devdata(master
);
640 u32 current_remaining_data
, num_data
;
641 u32 offset
= xfer
->len
- as
->current_remaining_bytes
;
642 const u16
*words
= (const u16
*)((u8
*)xfer
->tx_buf
+ offset
);
643 const u8
*bytes
= (const u8
*)((u8
*)xfer
->tx_buf
+ offset
);
647 dev_vdbg(master
->dev
.parent
, "atmel_spi_next_xfer_fifo\n");
649 /* Compute the number of data to transfer in the current iteration */
650 current_remaining_data
= ((xfer
->bits_per_word
> 8) ?
651 ((u32
)as
->current_remaining_bytes
>> 1) :
652 (u32
)as
->current_remaining_bytes
);
653 num_data
= min(current_remaining_data
, as
->fifo_size
);
655 /* Flush RX and TX FIFOs */
656 spi_writel(as
, CR
, SPI_BIT(RXFCLR
) | SPI_BIT(TXFCLR
));
657 while (spi_readl(as
, FLR
))
660 /* Set RX FIFO Threshold to the number of data to transfer */
661 fifomr
= spi_readl(as
, FMR
);
662 spi_writel(as
, FMR
, SPI_BFINS(RXFTHRES
, num_data
, fifomr
));
664 /* Clear FIFO flags in the Status Register, especially RXFTHF */
665 (void)spi_readl(as
, SR
);
668 while (num_data
>= 2) {
670 if (xfer
->bits_per_word
> 8) {
682 spi_writel(as
, TDR
, (td1
<< 16) | td0
);
688 if (xfer
->bits_per_word
> 8)
696 spi_writew(as
, TDR
, td0
);
700 dev_dbg(master
->dev
.parent
,
701 " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n",
702 xfer
, xfer
->len
, xfer
->tx_buf
, xfer
->rx_buf
,
703 xfer
->bits_per_word
);
706 * Enable RX FIFO Threshold Flag interrupt to be notified about
707 * transfer completion.
709 spi_writel(as
, IER
, SPI_BIT(RXFTHF
) | SPI_BIT(OVRES
));
713 * Next transfer using PIO.
715 static void atmel_spi_next_xfer_pio(struct spi_master
*master
,
716 struct spi_transfer
*xfer
)
718 struct atmel_spi
*as
= spi_master_get_devdata(master
);
721 atmel_spi_next_xfer_fifo(master
, xfer
);
723 atmel_spi_next_xfer_single(master
, xfer
);
727 * Submit next transfer for DMA.
729 static int atmel_spi_next_xfer_dma_submit(struct spi_master
*master
,
730 struct spi_transfer
*xfer
,
733 struct atmel_spi
*as
= spi_master_get_devdata(master
);
734 struct dma_chan
*rxchan
= as
->dma
.chan_rx
;
735 struct dma_chan
*txchan
= as
->dma
.chan_tx
;
736 struct dma_async_tx_descriptor
*rxdesc
;
737 struct dma_async_tx_descriptor
*txdesc
;
738 struct dma_slave_config slave_config
;
742 dev_vdbg(master
->dev
.parent
, "atmel_spi_next_xfer_dma_submit\n");
744 /* Check that the channels are available */
745 if (!rxchan
|| !txchan
)
748 /* release lock for DMA operations */
749 atmel_spi_unlock(as
);
751 /* prepare the RX dma transfer */
752 sg_init_table(&as
->dma
.sgrx
, 1);
754 as
->dma
.sgrx
.dma_address
= xfer
->rx_dma
+ xfer
->len
- *plen
;
756 as
->dma
.sgrx
.dma_address
= as
->buffer_dma
;
757 if (len
> BUFFER_SIZE
)
761 /* prepare the TX dma transfer */
762 sg_init_table(&as
->dma
.sgtx
, 1);
764 as
->dma
.sgtx
.dma_address
= xfer
->tx_dma
+ xfer
->len
- *plen
;
766 as
->dma
.sgtx
.dma_address
= as
->buffer_dma
;
767 if (len
> BUFFER_SIZE
)
769 memset(as
->buffer
, 0, len
);
772 sg_dma_len(&as
->dma
.sgtx
) = len
;
773 sg_dma_len(&as
->dma
.sgrx
) = len
;
777 if (atmel_spi_dma_slave_config(as
, &slave_config
, 8))
780 /* Send both scatterlists */
781 rxdesc
= dmaengine_prep_slave_sg(rxchan
, &as
->dma
.sgrx
, 1,
783 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
787 txdesc
= dmaengine_prep_slave_sg(txchan
, &as
->dma
.sgtx
, 1,
789 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
793 dev_dbg(master
->dev
.parent
,
794 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
795 xfer
, xfer
->len
, xfer
->tx_buf
, (unsigned long long)xfer
->tx_dma
,
796 xfer
->rx_buf
, (unsigned long long)xfer
->rx_dma
);
798 /* Enable relevant interrupts */
799 spi_writel(as
, IER
, SPI_BIT(OVRES
));
801 /* Put the callback on the RX transfer only, that should finish last */
802 rxdesc
->callback
= dma_callback
;
803 rxdesc
->callback_param
= master
;
805 /* Submit and fire RX and TX with TX last so we're ready to read! */
806 cookie
= rxdesc
->tx_submit(rxdesc
);
807 if (dma_submit_error(cookie
))
809 cookie
= txdesc
->tx_submit(txdesc
);
810 if (dma_submit_error(cookie
))
812 rxchan
->device
->device_issue_pending(rxchan
);
813 txchan
->device
->device_issue_pending(txchan
);
820 spi_writel(as
, IDR
, SPI_BIT(OVRES
));
821 atmel_spi_stop_dma(as
);
827 static void atmel_spi_next_xfer_data(struct spi_master
*master
,
828 struct spi_transfer
*xfer
,
833 struct atmel_spi
*as
= spi_master_get_devdata(master
);
836 /* use scratch buffer only when rx or tx data is unspecified */
838 *rx_dma
= xfer
->rx_dma
+ xfer
->len
- *plen
;
840 *rx_dma
= as
->buffer_dma
;
841 if (len
> BUFFER_SIZE
)
846 *tx_dma
= xfer
->tx_dma
+ xfer
->len
- *plen
;
848 *tx_dma
= as
->buffer_dma
;
849 if (len
> BUFFER_SIZE
)
851 memset(as
->buffer
, 0, len
);
852 dma_sync_single_for_device(&as
->pdev
->dev
,
853 as
->buffer_dma
, len
, DMA_TO_DEVICE
);
859 static int atmel_spi_set_xfer_speed(struct atmel_spi
*as
,
860 struct spi_device
*spi
,
861 struct spi_transfer
*xfer
)
864 unsigned long bus_hz
;
866 /* v1 chips start out at half the peripheral bus speed. */
867 bus_hz
= clk_get_rate(as
->clk
);
868 if (!atmel_spi_is_v2(as
))
872 * Calculate the lowest divider that satisfies the
873 * constraint, assuming div32/fdiv/mbz == 0.
876 scbr
= DIV_ROUND_UP(bus_hz
, xfer
->speed_hz
);
879 * This can happend if max_speed is null.
880 * In this case, we set the lowest possible speed
885 * If the resulting divider doesn't fit into the
886 * register bitfield, we can't satisfy the constraint.
888 if (scbr
>= (1 << SPI_SCBR_SIZE
)) {
890 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
891 xfer
->speed_hz
, scbr
, bus_hz
/255);
896 "setup: %d Hz too high, scbr %u; max %ld Hz\n",
897 xfer
->speed_hz
, scbr
, bus_hz
);
900 csr
= spi_readl(as
, CSR0
+ 4 * spi
->chip_select
);
901 csr
= SPI_BFINS(SCBR
, scbr
, csr
);
902 spi_writel(as
, CSR0
+ 4 * spi
->chip_select
, csr
);
908 * Submit next transfer for PDC.
909 * lock is held, spi irq is blocked
911 static void atmel_spi_pdc_next_xfer(struct spi_master
*master
,
912 struct spi_message
*msg
,
913 struct spi_transfer
*xfer
)
915 struct atmel_spi
*as
= spi_master_get_devdata(master
);
917 dma_addr_t tx_dma
, rx_dma
;
919 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
921 len
= as
->current_remaining_bytes
;
922 atmel_spi_next_xfer_data(master
, xfer
, &tx_dma
, &rx_dma
, &len
);
923 as
->current_remaining_bytes
-= len
;
925 spi_writel(as
, RPR
, rx_dma
);
926 spi_writel(as
, TPR
, tx_dma
);
928 if (msg
->spi
->bits_per_word
> 8)
930 spi_writel(as
, RCR
, len
);
931 spi_writel(as
, TCR
, len
);
933 dev_dbg(&msg
->spi
->dev
,
934 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
935 xfer
, xfer
->len
, xfer
->tx_buf
,
936 (unsigned long long)xfer
->tx_dma
, xfer
->rx_buf
,
937 (unsigned long long)xfer
->rx_dma
);
939 if (as
->current_remaining_bytes
) {
940 len
= as
->current_remaining_bytes
;
941 atmel_spi_next_xfer_data(master
, xfer
, &tx_dma
, &rx_dma
, &len
);
942 as
->current_remaining_bytes
-= len
;
944 spi_writel(as
, RNPR
, rx_dma
);
945 spi_writel(as
, TNPR
, tx_dma
);
947 if (msg
->spi
->bits_per_word
> 8)
949 spi_writel(as
, RNCR
, len
);
950 spi_writel(as
, TNCR
, len
);
952 dev_dbg(&msg
->spi
->dev
,
953 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n",
954 xfer
, xfer
->len
, xfer
->tx_buf
,
955 (unsigned long long)xfer
->tx_dma
, xfer
->rx_buf
,
956 (unsigned long long)xfer
->rx_dma
);
959 /* REVISIT: We're waiting for RXBUFF before we start the next
960 * transfer because we need to handle some difficult timing
961 * issues otherwise. If we wait for TXBUFE in one transfer and
962 * then starts waiting for RXBUFF in the next, it's difficult
963 * to tell the difference between the RXBUFF interrupt we're
964 * actually waiting for and the RXBUFF interrupt of the
967 * It should be doable, though. Just not now...
969 spi_writel(as
, IER
, SPI_BIT(RXBUFF
) | SPI_BIT(OVRES
));
970 spi_writel(as
, PTCR
, SPI_BIT(TXTEN
) | SPI_BIT(RXTEN
));
974 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
975 * - The buffer is either valid for CPU access, else NULL
976 * - If the buffer is valid, so is its DMA address
978 * This driver manages the dma address unless message->is_dma_mapped.
981 atmel_spi_dma_map_xfer(struct atmel_spi
*as
, struct spi_transfer
*xfer
)
983 struct device
*dev
= &as
->pdev
->dev
;
985 xfer
->tx_dma
= xfer
->rx_dma
= INVALID_DMA_ADDRESS
;
987 /* tx_buf is a const void* where we need a void * for the dma
989 void *nonconst_tx
= (void *)xfer
->tx_buf
;
991 xfer
->tx_dma
= dma_map_single(dev
,
992 nonconst_tx
, xfer
->len
,
994 if (dma_mapping_error(dev
, xfer
->tx_dma
))
998 xfer
->rx_dma
= dma_map_single(dev
,
999 xfer
->rx_buf
, xfer
->len
,
1001 if (dma_mapping_error(dev
, xfer
->rx_dma
)) {
1003 dma_unmap_single(dev
,
1004 xfer
->tx_dma
, xfer
->len
,
1012 static void atmel_spi_dma_unmap_xfer(struct spi_master
*master
,
1013 struct spi_transfer
*xfer
)
1015 if (xfer
->tx_dma
!= INVALID_DMA_ADDRESS
)
1016 dma_unmap_single(master
->dev
.parent
, xfer
->tx_dma
,
1017 xfer
->len
, DMA_TO_DEVICE
);
1018 if (xfer
->rx_dma
!= INVALID_DMA_ADDRESS
)
1019 dma_unmap_single(master
->dev
.parent
, xfer
->rx_dma
,
1020 xfer
->len
, DMA_FROM_DEVICE
);
1023 static void atmel_spi_disable_pdc_transfer(struct atmel_spi
*as
)
1025 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
1029 atmel_spi_pump_single_data(struct atmel_spi
*as
, struct spi_transfer
*xfer
)
1033 unsigned long xfer_pos
= xfer
->len
- as
->current_remaining_bytes
;
1036 if (xfer
->bits_per_word
> 8) {
1037 rxp16
= (u16
*)(((u8
*)xfer
->rx_buf
) + xfer_pos
);
1038 *rxp16
= spi_readl(as
, RDR
);
1040 rxp
= ((u8
*)xfer
->rx_buf
) + xfer_pos
;
1041 *rxp
= spi_readl(as
, RDR
);
1046 if (xfer
->bits_per_word
> 8) {
1047 if (as
->current_remaining_bytes
> 2)
1048 as
->current_remaining_bytes
-= 2;
1050 as
->current_remaining_bytes
= 0;
1052 as
->current_remaining_bytes
--;
1057 atmel_spi_pump_fifo_data(struct atmel_spi
*as
, struct spi_transfer
*xfer
)
1059 u32 fifolr
= spi_readl(as
, FLR
);
1060 u32 num_bytes
, num_data
= SPI_BFEXT(RXFL
, fifolr
);
1061 u32 offset
= xfer
->len
- as
->current_remaining_bytes
;
1062 u16
*words
= (u16
*)((u8
*)xfer
->rx_buf
+ offset
);
1063 u8
*bytes
= (u8
*)((u8
*)xfer
->rx_buf
+ offset
);
1064 u16 rd
; /* RD field is the lowest 16 bits of RDR */
1066 /* Update the number of remaining bytes to transfer */
1067 num_bytes
= ((xfer
->bits_per_word
> 8) ?
1071 if (as
->current_remaining_bytes
> num_bytes
)
1072 as
->current_remaining_bytes
-= num_bytes
;
1074 as
->current_remaining_bytes
= 0;
1076 /* Handle odd number of bytes when data are more than 8bit width */
1077 if (xfer
->bits_per_word
> 8)
1078 as
->current_remaining_bytes
&= ~0x1;
1082 rd
= spi_readl(as
, RDR
);
1084 if (xfer
->bits_per_word
> 8)
1095 * Must update "current_remaining_bytes" to keep track of data
1099 atmel_spi_pump_pio_data(struct atmel_spi
*as
, struct spi_transfer
*xfer
)
1102 atmel_spi_pump_fifo_data(as
, xfer
);
1104 atmel_spi_pump_single_data(as
, xfer
);
1109 * No need for locking in this Interrupt handler: done_status is the
1110 * only information modified.
1113 atmel_spi_pio_interrupt(int irq
, void *dev_id
)
1115 struct spi_master
*master
= dev_id
;
1116 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1117 u32 status
, pending
, imr
;
1118 struct spi_transfer
*xfer
;
1121 imr
= spi_readl(as
, IMR
);
1122 status
= spi_readl(as
, SR
);
1123 pending
= status
& imr
;
1125 if (pending
& SPI_BIT(OVRES
)) {
1127 spi_writel(as
, IDR
, SPI_BIT(OVRES
));
1128 dev_warn(master
->dev
.parent
, "overrun\n");
1131 * When we get an overrun, we disregard the current
1132 * transfer. Data will not be copied back from any
1133 * bounce buffer and msg->actual_len will not be
1134 * updated with the last xfer.
1136 * We will also not process any remaning transfers in
1139 as
->done_status
= -EIO
;
1142 /* Clear any overrun happening while cleaning up */
1145 complete(&as
->xfer_completion
);
1147 } else if (pending
& (SPI_BIT(RDRF
) | SPI_BIT(RXFTHF
))) {
1150 if (as
->current_remaining_bytes
) {
1152 xfer
= as
->current_transfer
;
1153 atmel_spi_pump_pio_data(as
, xfer
);
1154 if (!as
->current_remaining_bytes
)
1155 spi_writel(as
, IDR
, pending
);
1157 complete(&as
->xfer_completion
);
1160 atmel_spi_unlock(as
);
1162 WARN_ONCE(pending
, "IRQ not handled, pending = %x\n", pending
);
1164 spi_writel(as
, IDR
, pending
);
1171 atmel_spi_pdc_interrupt(int irq
, void *dev_id
)
1173 struct spi_master
*master
= dev_id
;
1174 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1175 u32 status
, pending
, imr
;
1178 imr
= spi_readl(as
, IMR
);
1179 status
= spi_readl(as
, SR
);
1180 pending
= status
& imr
;
1182 if (pending
& SPI_BIT(OVRES
)) {
1186 spi_writel(as
, IDR
, (SPI_BIT(RXBUFF
) | SPI_BIT(ENDRX
)
1189 /* Clear any overrun happening while cleaning up */
1192 as
->done_status
= -EIO
;
1194 complete(&as
->xfer_completion
);
1196 } else if (pending
& (SPI_BIT(RXBUFF
) | SPI_BIT(ENDRX
))) {
1199 spi_writel(as
, IDR
, pending
);
1201 complete(&as
->xfer_completion
);
1207 static int atmel_spi_setup(struct spi_device
*spi
)
1209 struct atmel_spi
*as
;
1210 struct atmel_spi_device
*asd
;
1212 unsigned int bits
= spi
->bits_per_word
;
1213 unsigned int npcs_pin
;
1216 as
= spi_master_get_devdata(spi
->master
);
1218 /* see notes above re chipselect */
1219 if (!atmel_spi_is_v2(as
)
1220 && spi
->chip_select
== 0
1221 && (spi
->mode
& SPI_CS_HIGH
)) {
1222 dev_dbg(&spi
->dev
, "setup: can't be active-high\n");
1226 csr
= SPI_BF(BITS
, bits
- 8);
1227 if (spi
->mode
& SPI_CPOL
)
1228 csr
|= SPI_BIT(CPOL
);
1229 if (!(spi
->mode
& SPI_CPHA
))
1230 csr
|= SPI_BIT(NCPHA
);
1231 if (!as
->use_cs_gpios
)
1232 csr
|= SPI_BIT(CSAAT
);
1234 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
1236 * DLYBCT would add delays between words, slowing down transfers.
1237 * It could potentially be useful to cope with DMA bottlenecks, but
1238 * in those cases it's probably best to just use a lower bitrate.
1240 csr
|= SPI_BF(DLYBS
, 0);
1241 csr
|= SPI_BF(DLYBCT
, 0);
1243 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
1244 npcs_pin
= (unsigned long)spi
->controller_data
;
1246 if (!as
->use_cs_gpios
)
1247 npcs_pin
= spi
->chip_select
;
1248 else if (gpio_is_valid(spi
->cs_gpio
))
1249 npcs_pin
= spi
->cs_gpio
;
1251 asd
= spi
->controller_state
;
1253 asd
= kzalloc(sizeof(struct atmel_spi_device
), GFP_KERNEL
);
1257 if (as
->use_cs_gpios
) {
1258 ret
= gpio_request(npcs_pin
, dev_name(&spi
->dev
));
1264 gpio_direction_output(npcs_pin
,
1265 !(spi
->mode
& SPI_CS_HIGH
));
1268 asd
->npcs_pin
= npcs_pin
;
1269 spi
->controller_state
= asd
;
1275 "setup: bpw %u mode 0x%x -> csr%d %08x\n",
1276 bits
, spi
->mode
, spi
->chip_select
, csr
);
1278 if (!atmel_spi_is_v2(as
))
1279 spi_writel(as
, CSR0
+ 4 * spi
->chip_select
, csr
);
1284 static int atmel_spi_one_transfer(struct spi_master
*master
,
1285 struct spi_message
*msg
,
1286 struct spi_transfer
*xfer
)
1288 struct atmel_spi
*as
;
1289 struct spi_device
*spi
= msg
->spi
;
1292 struct atmel_spi_device
*asd
;
1295 unsigned long dma_timeout
;
1297 as
= spi_master_get_devdata(master
);
1299 if (!(xfer
->tx_buf
|| xfer
->rx_buf
) && xfer
->len
) {
1300 dev_dbg(&spi
->dev
, "missing rx or tx buf\n");
1304 if (xfer
->bits_per_word
) {
1305 asd
= spi
->controller_state
;
1306 bits
= (asd
->csr
>> 4) & 0xf;
1307 if (bits
!= xfer
->bits_per_word
- 8) {
1309 "you can't yet change bits_per_word in transfers\n");
1310 return -ENOPROTOOPT
;
1315 * DMA map early, for performance (empties dcache ASAP) and
1316 * better fault reporting.
1318 if ((!msg
->is_dma_mapped
)
1319 && (atmel_spi_use_dma(as
, xfer
) || as
->use_pdc
)) {
1320 if (atmel_spi_dma_map_xfer(as
, xfer
) < 0)
1324 atmel_spi_set_xfer_speed(as
, msg
->spi
, xfer
);
1326 as
->done_status
= 0;
1327 as
->current_transfer
= xfer
;
1328 as
->current_remaining_bytes
= xfer
->len
;
1329 while (as
->current_remaining_bytes
) {
1330 reinit_completion(&as
->xfer_completion
);
1333 atmel_spi_pdc_next_xfer(master
, msg
, xfer
);
1334 } else if (atmel_spi_use_dma(as
, xfer
)) {
1335 len
= as
->current_remaining_bytes
;
1336 ret
= atmel_spi_next_xfer_dma_submit(master
,
1340 "unable to use DMA, fallback to PIO\n");
1341 atmel_spi_next_xfer_pio(master
, xfer
);
1343 as
->current_remaining_bytes
-= len
;
1344 if (as
->current_remaining_bytes
< 0)
1345 as
->current_remaining_bytes
= 0;
1348 atmel_spi_next_xfer_pio(master
, xfer
);
1351 /* interrupts are disabled, so free the lock for schedule */
1352 atmel_spi_unlock(as
);
1353 dma_timeout
= wait_for_completion_timeout(&as
->xfer_completion
,
1356 if (WARN_ON(dma_timeout
== 0)) {
1357 dev_err(&spi
->dev
, "spi transfer timeout\n");
1358 as
->done_status
= -EIO
;
1361 if (as
->done_status
)
1365 if (as
->done_status
) {
1367 dev_warn(master
->dev
.parent
,
1368 "overrun (%u/%u remaining)\n",
1369 spi_readl(as
, TCR
), spi_readl(as
, RCR
));
1372 * Clean up DMA registers and make sure the data
1373 * registers are empty.
1375 spi_writel(as
, RNCR
, 0);
1376 spi_writel(as
, TNCR
, 0);
1377 spi_writel(as
, RCR
, 0);
1378 spi_writel(as
, TCR
, 0);
1379 for (timeout
= 1000; timeout
; timeout
--)
1380 if (spi_readl(as
, SR
) & SPI_BIT(TXEMPTY
))
1383 dev_warn(master
->dev
.parent
,
1384 "timeout waiting for TXEMPTY");
1385 while (spi_readl(as
, SR
) & SPI_BIT(RDRF
))
1388 /* Clear any overrun happening while cleaning up */
1391 } else if (atmel_spi_use_dma(as
, xfer
)) {
1392 atmel_spi_stop_dma(as
);
1395 if (!msg
->is_dma_mapped
1396 && (atmel_spi_use_dma(as
, xfer
) || as
->use_pdc
))
1397 atmel_spi_dma_unmap_xfer(master
, xfer
);
1402 /* only update length if no error */
1403 msg
->actual_length
+= xfer
->len
;
1406 if (!msg
->is_dma_mapped
1407 && (atmel_spi_use_dma(as
, xfer
) || as
->use_pdc
))
1408 atmel_spi_dma_unmap_xfer(master
, xfer
);
1410 if (xfer
->delay_usecs
)
1411 udelay(xfer
->delay_usecs
);
1413 if (xfer
->cs_change
) {
1414 if (list_is_last(&xfer
->transfer_list
,
1418 as
->cs_active
= !as
->cs_active
;
1420 cs_activate(as
, msg
->spi
);
1422 cs_deactivate(as
, msg
->spi
);
1429 static int atmel_spi_transfer_one_message(struct spi_master
*master
,
1430 struct spi_message
*msg
)
1432 struct atmel_spi
*as
;
1433 struct spi_transfer
*xfer
;
1434 struct spi_device
*spi
= msg
->spi
;
1437 as
= spi_master_get_devdata(master
);
1439 dev_dbg(&spi
->dev
, "new message %p submitted for %s\n",
1440 msg
, dev_name(&spi
->dev
));
1443 cs_activate(as
, spi
);
1445 as
->cs_active
= true;
1446 as
->keep_cs
= false;
1449 msg
->actual_length
= 0;
1451 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
1452 ret
= atmel_spi_one_transfer(master
, msg
, xfer
);
1458 atmel_spi_disable_pdc_transfer(as
);
1460 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
1462 " xfer %p: len %u tx %p/%pad rx %p/%pad\n",
1464 xfer
->tx_buf
, &xfer
->tx_dma
,
1465 xfer
->rx_buf
, &xfer
->rx_dma
);
1470 cs_deactivate(as
, msg
->spi
);
1472 atmel_spi_unlock(as
);
1474 msg
->status
= as
->done_status
;
1475 spi_finalize_current_message(spi
->master
);
1480 static void atmel_spi_cleanup(struct spi_device
*spi
)
1482 struct atmel_spi_device
*asd
= spi
->controller_state
;
1483 unsigned gpio
= (unsigned long) spi
->controller_data
;
1488 spi
->controller_state
= NULL
;
1493 static inline unsigned int atmel_get_version(struct atmel_spi
*as
)
1495 return spi_readl(as
, VERSION
) & 0x00000fff;
1498 static void atmel_get_caps(struct atmel_spi
*as
)
1500 unsigned int version
;
1502 version
= atmel_get_version(as
);
1503 dev_info(&as
->pdev
->dev
, "version: 0x%x\n", version
);
1505 as
->caps
.is_spi2
= version
> 0x121;
1506 as
->caps
.has_wdrbt
= version
>= 0x210;
1507 as
->caps
.has_dma_support
= version
>= 0x212;
1510 /*-------------------------------------------------------------------------*/
1512 static int atmel_spi_probe(struct platform_device
*pdev
)
1514 struct resource
*regs
;
1518 struct spi_master
*master
;
1519 struct atmel_spi
*as
;
1521 /* Select default pin state */
1522 pinctrl_pm_select_default_state(&pdev
->dev
);
1524 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1528 irq
= platform_get_irq(pdev
, 0);
1532 clk
= devm_clk_get(&pdev
->dev
, "spi_clk");
1534 return PTR_ERR(clk
);
1536 /* setup spi core then atmel-specific driver state */
1538 master
= spi_alloc_master(&pdev
->dev
, sizeof(*as
));
1542 /* the spi->mode bits understood by this driver: */
1543 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1544 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(8, 16);
1545 master
->dev
.of_node
= pdev
->dev
.of_node
;
1546 master
->bus_num
= pdev
->id
;
1547 master
->num_chipselect
= master
->dev
.of_node
? 0 : 4;
1548 master
->setup
= atmel_spi_setup
;
1549 master
->transfer_one_message
= atmel_spi_transfer_one_message
;
1550 master
->cleanup
= atmel_spi_cleanup
;
1551 master
->auto_runtime_pm
= true;
1552 platform_set_drvdata(pdev
, master
);
1554 as
= spi_master_get_devdata(master
);
1557 * Scratch buffer is used for throwaway rx and tx data.
1558 * It's coherent to minimize dcache pollution.
1560 as
->buffer
= dma_alloc_coherent(&pdev
->dev
, BUFFER_SIZE
,
1561 &as
->buffer_dma
, GFP_KERNEL
);
1565 spin_lock_init(&as
->lock
);
1568 as
->regs
= devm_ioremap_resource(&pdev
->dev
, regs
);
1569 if (IS_ERR(as
->regs
)) {
1570 ret
= PTR_ERR(as
->regs
);
1571 goto out_free_buffer
;
1573 as
->phybase
= regs
->start
;
1577 init_completion(&as
->xfer_completion
);
1581 as
->use_cs_gpios
= true;
1582 if (atmel_spi_is_v2(as
) &&
1583 !of_get_property(pdev
->dev
.of_node
, "cs-gpios", NULL
)) {
1584 as
->use_cs_gpios
= false;
1585 master
->num_chipselect
= 4;
1588 as
->use_dma
= false;
1589 as
->use_pdc
= false;
1590 if (as
->caps
.has_dma_support
) {
1591 ret
= atmel_spi_configure_dma(as
);
1594 else if (ret
== -EPROBE_DEFER
)
1600 if (as
->caps
.has_dma_support
&& !as
->use_dma
)
1601 dev_info(&pdev
->dev
, "Atmel SPI Controller using PIO only\n");
1604 ret
= devm_request_irq(&pdev
->dev
, irq
, atmel_spi_pdc_interrupt
,
1605 0, dev_name(&pdev
->dev
), master
);
1607 ret
= devm_request_irq(&pdev
->dev
, irq
, atmel_spi_pio_interrupt
,
1608 0, dev_name(&pdev
->dev
), master
);
1611 goto out_unmap_regs
;
1613 /* Initialize the hardware */
1614 ret
= clk_prepare_enable(clk
);
1617 spi_writel(as
, CR
, SPI_BIT(SWRST
));
1618 spi_writel(as
, CR
, SPI_BIT(SWRST
)); /* AT91SAM9263 Rev B workaround */
1619 if (as
->caps
.has_wdrbt
) {
1620 spi_writel(as
, MR
, SPI_BIT(WDRBT
) | SPI_BIT(MODFDIS
)
1623 spi_writel(as
, MR
, SPI_BIT(MSTR
) | SPI_BIT(MODFDIS
));
1627 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
1628 spi_writel(as
, CR
, SPI_BIT(SPIEN
));
1631 if (!of_property_read_u32(pdev
->dev
.of_node
, "atmel,fifo-size",
1633 dev_info(&pdev
->dev
, "Using FIFO (%u data)\n", as
->fifo_size
);
1634 spi_writel(as
, CR
, SPI_BIT(FIFOEN
));
1638 dev_info(&pdev
->dev
, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1639 (unsigned long)regs
->start
, irq
);
1641 pm_runtime_set_autosuspend_delay(&pdev
->dev
, AUTOSUSPEND_TIMEOUT
);
1642 pm_runtime_use_autosuspend(&pdev
->dev
);
1643 pm_runtime_set_active(&pdev
->dev
);
1644 pm_runtime_enable(&pdev
->dev
);
1646 ret
= devm_spi_register_master(&pdev
->dev
, master
);
1653 pm_runtime_disable(&pdev
->dev
);
1654 pm_runtime_set_suspended(&pdev
->dev
);
1657 atmel_spi_release_dma(as
);
1659 spi_writel(as
, CR
, SPI_BIT(SWRST
));
1660 spi_writel(as
, CR
, SPI_BIT(SWRST
)); /* AT91SAM9263 Rev B workaround */
1661 clk_disable_unprepare(clk
);
1665 dma_free_coherent(&pdev
->dev
, BUFFER_SIZE
, as
->buffer
,
1668 spi_master_put(master
);
1672 static int atmel_spi_remove(struct platform_device
*pdev
)
1674 struct spi_master
*master
= platform_get_drvdata(pdev
);
1675 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1677 pm_runtime_get_sync(&pdev
->dev
);
1679 /* reset the hardware and block queue progress */
1680 spin_lock_irq(&as
->lock
);
1682 atmel_spi_stop_dma(as
);
1683 atmel_spi_release_dma(as
);
1686 spi_writel(as
, CR
, SPI_BIT(SWRST
));
1687 spi_writel(as
, CR
, SPI_BIT(SWRST
)); /* AT91SAM9263 Rev B workaround */
1689 spin_unlock_irq(&as
->lock
);
1691 dma_free_coherent(&pdev
->dev
, BUFFER_SIZE
, as
->buffer
,
1694 clk_disable_unprepare(as
->clk
);
1696 pm_runtime_put_noidle(&pdev
->dev
);
1697 pm_runtime_disable(&pdev
->dev
);
1703 static int atmel_spi_runtime_suspend(struct device
*dev
)
1705 struct spi_master
*master
= dev_get_drvdata(dev
);
1706 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1708 clk_disable_unprepare(as
->clk
);
1709 pinctrl_pm_select_sleep_state(dev
);
1714 static int atmel_spi_runtime_resume(struct device
*dev
)
1716 struct spi_master
*master
= dev_get_drvdata(dev
);
1717 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1719 pinctrl_pm_select_default_state(dev
);
1721 return clk_prepare_enable(as
->clk
);
1724 static int atmel_spi_suspend(struct device
*dev
)
1726 struct spi_master
*master
= dev_get_drvdata(dev
);
1729 /* Stop the queue running */
1730 ret
= spi_master_suspend(master
);
1732 dev_warn(dev
, "cannot suspend master\n");
1736 if (!pm_runtime_suspended(dev
))
1737 atmel_spi_runtime_suspend(dev
);
1742 static int atmel_spi_resume(struct device
*dev
)
1744 struct spi_master
*master
= dev_get_drvdata(dev
);
1747 if (!pm_runtime_suspended(dev
)) {
1748 ret
= atmel_spi_runtime_resume(dev
);
1753 /* Start the queue running */
1754 ret
= spi_master_resume(master
);
1756 dev_err(dev
, "problem starting queue (%d)\n", ret
);
1761 static const struct dev_pm_ops atmel_spi_pm_ops
= {
1762 SET_SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend
, atmel_spi_resume
)
1763 SET_RUNTIME_PM_OPS(atmel_spi_runtime_suspend
,
1764 atmel_spi_runtime_resume
, NULL
)
1766 #define ATMEL_SPI_PM_OPS (&atmel_spi_pm_ops)
1768 #define ATMEL_SPI_PM_OPS NULL
1771 #if defined(CONFIG_OF)
1772 static const struct of_device_id atmel_spi_dt_ids
[] = {
1773 { .compatible
= "atmel,at91rm9200-spi" },
1777 MODULE_DEVICE_TABLE(of
, atmel_spi_dt_ids
);
1780 static struct platform_driver atmel_spi_driver
= {
1782 .name
= "atmel_spi",
1783 .pm
= ATMEL_SPI_PM_OPS
,
1784 .of_match_table
= of_match_ptr(atmel_spi_dt_ids
),
1786 .probe
= atmel_spi_probe
,
1787 .remove
= atmel_spi_remove
,
1789 module_platform_driver(atmel_spi_driver
);
1791 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1792 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1793 MODULE_LICENSE("GPL");
1794 MODULE_ALIAS("platform:atmel_spi");