drivers/spi/spi-bcm2835.c

   1 /*
   2  * Driver for Broadcom BCM2835 SPI Controllers
   3  *
   4  * Copyright (C) 2012 Chris Boot
   5  * Copyright (C) 2013 Stephen Warren
   6  * Copyright (C) 2015 Martin Sperl
   7  *
   8  * This driver is inspired by:
   9  * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  10  * spi-atmel.c, Copyright (C) 2006 Atmel Corporation
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  */
  22
  23 #include <linux/clk.h>
  24 #include <linux/completion.h>
  25 #include <linux/delay.h>
  26 #include <linux/err.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/of.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/of_gpio.h>
  34 #include <linux/of_device.h>
  35 #include <linux/spi/spi.h>
  36
  37 /* SPI register offsets */
  38 #define BCM2835_SPI_CS                  0x00
  39 #define BCM2835_SPI_FIFO                0x04
  40 #define BCM2835_SPI_CLK                 0x08
  41 #define BCM2835_SPI_DLEN                0x0c
  42 #define BCM2835_SPI_LTOH                0x10
  43 #define BCM2835_SPI_DC                  0x14
  44
  45 /* Bitfields in CS */
  46 #define BCM2835_SPI_CS_LEN_LONG         0x02000000
  47 #define BCM2835_SPI_CS_DMA_LEN          0x01000000
  48 #define BCM2835_SPI_CS_CSPOL2           0x00800000
  49 #define BCM2835_SPI_CS_CSPOL1           0x00400000
  50 #define BCM2835_SPI_CS_CSPOL0           0x00200000
  51 #define BCM2835_SPI_CS_RXF              0x00100000
  52 #define BCM2835_SPI_CS_RXR              0x00080000
  53 #define BCM2835_SPI_CS_TXD              0x00040000
  54 #define BCM2835_SPI_CS_RXD              0x00020000
  55 #define BCM2835_SPI_CS_DONE             0x00010000
  56 #define BCM2835_SPI_CS_LEN              0x00002000
  57 #define BCM2835_SPI_CS_REN              0x00001000
  58 #define BCM2835_SPI_CS_ADCS             0x00000800
  59 #define BCM2835_SPI_CS_INTR             0x00000400
  60 #define BCM2835_SPI_CS_INTD             0x00000200
  61 #define BCM2835_SPI_CS_DMAEN            0x00000100
  62 #define BCM2835_SPI_CS_TA               0x00000080
  63 #define BCM2835_SPI_CS_CSPOL            0x00000040
  64 #define BCM2835_SPI_CS_CLEAR_RX         0x00000020
  65 #define BCM2835_SPI_CS_CLEAR_TX         0x00000010
  66 #define BCM2835_SPI_CS_CPOL             0x00000008
  67 #define BCM2835_SPI_CS_CPHA             0x00000004
  68 #define BCM2835_SPI_CS_CS_10            0x00000002
  69 #define BCM2835_SPI_CS_CS_01            0x00000001
  70
  71 #define BCM2835_SPI_TIMEOUT_MS  30000
  72 #define BCM2835_SPI_MODE_BITS   (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
  73                                 | SPI_NO_CS | SPI_3WIRE)
  74
  75 #define DRV_NAME        "spi-bcm2835"
  76
  77 struct bcm2835_spi {
  78         void __iomem *regs;
  79         struct clk *clk;
  80         int irq;
  81         const u8 *tx_buf;
  82         u8 *rx_buf;
  83         int tx_len;
  84         int rx_len;
  85 };
  86
  87 static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
  88 {
  89         return readl(bs->regs + reg);
  90 }
  91
  92 static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
  93 {
  94         writel(val, bs->regs + reg);
  95 }
  96
  97 static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
  98 {
  99         u8 byte;
 100
 101         while ((bs->rx_len) &&
 102                (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
 103                 byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
 104                 if (bs->rx_buf)
 105                         *bs->rx_buf++ = byte;
 106                 bs->rx_len--;
 107         }
 108 }
 109
 110 static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
 111 {
 112         u8 byte;
 113
 114         while ((bs->tx_len) &&
 115                (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
 116                 byte = bs->tx_buf ? *bs->tx_buf++ : 0;
 117                 bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
 118                 bs->tx_len--;
 119         }
 120 }
 121
 122 static void bcm2835_spi_reset_hw(struct spi_master *master)
 123 {
 124         struct bcm2835_spi *bs = spi_master_get_devdata(master);
 125         u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
 126
 127         /* Disable SPI interrupts and transfer */
 128         cs &= ~(BCM2835_SPI_CS_INTR |
 129                 BCM2835_SPI_CS_INTD |
 130                 BCM2835_SPI_CS_TA);
 131         /* and reset RX/TX FIFOS */
 132         cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
 133
 134         /* and reset the SPI_HW */
 135         bcm2835_wr(bs, BCM2835_SPI_CS, cs);
 136 }
 137
 138 static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
 139 {
 140         struct spi_master *master = dev_id;
 141         struct bcm2835_spi *bs = spi_master_get_devdata(master);
 142
 143         /* Read as many bytes as possible from FIFO */
 144         bcm2835_rd_fifo(bs);
 145         /* Write as many bytes as possible to FIFO */
 146         bcm2835_wr_fifo(bs);
 147
 148         /* based on flags decide if we can finish the transfer */
 149         if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
 150                 /* Transfer complete - reset SPI HW */
 151                 bcm2835_spi_reset_hw(master);
 152                 /* wake up the framework */
 153                 complete(&master->xfer_completion);
 154         }
 155
 156         return IRQ_HANDLED;
 157 }
 158
 159 static int bcm2835_spi_transfer_one(struct spi_master *master,
 160                                     struct spi_device *spi,
 161                                     struct spi_transfer *tfr)
 162 {
 163         struct bcm2835_spi *bs = spi_master_get_devdata(master);
 164         unsigned long spi_hz, clk_hz, cdiv;
 165         u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
 166
 167         /* set clock */
 168         spi_hz = tfr->speed_hz;
 169         clk_hz = clk_get_rate(bs->clk);
 170
 171         if (spi_hz >= clk_hz / 2) {
 172                 cdiv = 2; /* clk_hz/2 is the fastest we can go */
 173         } else if (spi_hz) {
 174                 /* CDIV must be a multiple of two */
 175                 cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
 176                 cdiv += (cdiv % 2);
 177
 178                 if (cdiv >= 65536)
 179                         cdiv = 0; /* 0 is the slowest we can go */
 180         } else {
 181                 cdiv = 0; /* 0 is the slowest we can go */
 182         }
 183         bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
 184
 185         /* handle all the modes */
 186         if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
 187                 cs |= BCM2835_SPI_CS_REN;
 188         if (spi->mode & SPI_CPOL)
 189                 cs |= BCM2835_SPI_CS_CPOL;
 190         if (spi->mode & SPI_CPHA)
 191                 cs |= BCM2835_SPI_CS_CPHA;
 192
 193         /* for gpio_cs set dummy CS so that no HW-CS get changed
 194          * we can not run this in bcm2835_spi_set_cs, as it does
 195          * not get called for cs_gpio cases, so we need to do it here
 196          */
 197         if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS))
 198                 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
 199
 200         /* set transmit buffers and length */
 201         bs->tx_buf = tfr->tx_buf;
 202         bs->rx_buf = tfr->rx_buf;
 203         bs->tx_len = tfr->len;
 204         bs->rx_len = tfr->len;
 205
 206         /*
 207          * Enable the HW block. This will immediately trigger a DONE (TX
 208          * empty) interrupt, upon which we will fill the TX FIFO with the
 209          * first TX bytes. Pre-filling the TX FIFO here to avoid the
 210          * interrupt doesn't work:-(
 211          */
 212         cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
 213         bcm2835_wr(bs, BCM2835_SPI_CS, cs);
 214
 215         /* signal that we need to wait for completion */
 216         return 1;
 217 }
 218
 219 static void bcm2835_spi_handle_err(struct spi_master *master,
 220                                    struct spi_message *msg)
 221 {
 222         bcm2835_spi_reset_hw(master);
 223 }
 224
 225 static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
 226 {
 227         /*
 228          * we can assume that we are "native" as per spi_set_cs
 229          *   calling us ONLY when cs_gpio is not set
 230          * we can also assume that we are CS < 3 as per bcm2835_spi_setup
 231          *   we would not get called because of error handling there.
 232          * the level passed is the electrical level not enabled/disabled
 233          *   so it has to get translated back to enable/disable
 234          *   see spi_set_cs in spi.c for the implementation
 235          */
 236
 237         struct spi_master *master = spi->master;
 238         struct bcm2835_spi *bs = spi_master_get_devdata(master);
 239         u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
 240         bool enable;
 241
 242         /* calculate the enable flag from the passed gpio_level */
 243         enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;
 244
 245         /* set flags for "reverse" polarity in the registers */
 246         if (spi->mode & SPI_CS_HIGH) {
 247                 /* set the correct CS-bits */
 248                 cs |= BCM2835_SPI_CS_CSPOL;
 249                 cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
 250         } else {
 251                 /* clean the CS-bits */
 252                 cs &= ~BCM2835_SPI_CS_CSPOL;
 253                 cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
 254         }
 255
 256         /* select the correct chip_select depending on disabled/enabled */
 257         if (enable) {
 258                 /* set cs correctly */
 259                 if (spi->mode & SPI_NO_CS) {
 260                         /* use the "undefined" chip-select */
 261                         cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
 262                 } else {
 263                         /* set the chip select */
 264                         cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01);
 265                         cs |= spi->chip_select;
 266                 }
 267         } else {
 268                 /* disable CSPOL which puts HW-CS into deselected state */
 269                 cs &= ~BCM2835_SPI_CS_CSPOL;
 270                 /* use the "undefined" chip-select as precaution */
 271                 cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
 272         }
 273
 274         /* finally set the calculated flags in SPI_CS */
 275         bcm2835_wr(bs, BCM2835_SPI_CS, cs);
 276 }
 277
 278 static int bcm2835_spi_setup(struct spi_device *spi)
 279 {
 280         /*
 281          * sanity checking the native-chipselects
 282          */
 283         if (spi->mode & SPI_NO_CS)
 284                 return 0;
 285         if (gpio_is_valid(spi->cs_gpio))
 286                 return 0;
 287         if (spi->chip_select < 3)
 288                 return 0;
 289
 290         /* error in the case of native CS requested with CS-id > 2 */
 291         dev_err(&spi->dev,
 292                 "setup: only three native chip-selects are supported\n"
 293                 );
 294         return -EINVAL;
 295 }
 296
 297 static int bcm2835_spi_probe(struct platform_device *pdev)
 298 {
 299         struct spi_master *master;
 300         struct bcm2835_spi *bs;
 301         struct resource *res;
 302         int err;
 303
 304         master = spi_alloc_master(&pdev->dev, sizeof(*bs));
 305         if (!master) {
 306                 dev_err(&pdev->dev, "spi_alloc_master() failed\n");
 307                 return -ENOMEM;
 308         }
 309
 310         platform_set_drvdata(pdev, master);
 311
 312         master->mode_bits = BCM2835_SPI_MODE_BITS;
 313         master->bits_per_word_mask = SPI_BPW_MASK(8);
 314         master->num_chipselect = 3;
 315         master->setup = bcm2835_spi_setup;
 316         master->set_cs = bcm2835_spi_set_cs;
 317         master->transfer_one = bcm2835_spi_transfer_one;
 318         master->handle_err = bcm2835_spi_handle_err;
 319         master->dev.of_node = pdev->dev.of_node;
 320
 321         bs = spi_master_get_devdata(master);
 322
 323         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 324         bs->regs = devm_ioremap_resource(&pdev->dev, res);
 325         if (IS_ERR(bs->regs)) {
 326                 err = PTR_ERR(bs->regs);
 327                 goto out_master_put;
 328         }
 329
 330         bs->clk = devm_clk_get(&pdev->dev, NULL);
 331         if (IS_ERR(bs->clk)) {
 332                 err = PTR_ERR(bs->clk);
 333                 dev_err(&pdev->dev, "could not get clk: %d\n", err);
 334                 goto out_master_put;
 335         }
 336
 337         bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
 338         if (bs->irq <= 0) {
 339                 dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
 340                 err = bs->irq ? bs->irq : -ENODEV;
 341                 goto out_master_put;
 342         }
 343
 344         clk_prepare_enable(bs->clk);
 345
 346         err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
 347                                dev_name(&pdev->dev), master);
 348         if (err) {
 349                 dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
 350                 goto out_clk_disable;
 351         }
 352
 353         /* initialise the hardware with the default polarities */
 354         bcm2835_wr(bs, BCM2835_SPI_CS,
 355                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
 356
 357         err = devm_spi_register_master(&pdev->dev, master);
 358         if (err) {
 359                 dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
 360                 goto out_clk_disable;
 361         }
 362
 363         return 0;
 364
 365 out_clk_disable:
 366         clk_disable_unprepare(bs->clk);
 367 out_master_put:
 368         spi_master_put(master);
 369         return err;
 370 }
 371
 372 static int bcm2835_spi_remove(struct platform_device *pdev)
 373 {
 374         struct spi_master *master = platform_get_drvdata(pdev);
 375         struct bcm2835_spi *bs = spi_master_get_devdata(master);
 376
 377         /* Clear FIFOs, and disable the HW block */
 378         bcm2835_wr(bs, BCM2835_SPI_CS,
 379                    BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
 380
 381         clk_disable_unprepare(bs->clk);
 382
 383         return 0;
 384 }
 385
 386 static const struct of_device_id bcm2835_spi_match[] = {
 387         { .compatible = "brcm,bcm2835-spi", },
 388         {}
 389 };
 390 MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
 391
 392 static struct platform_driver bcm2835_spi_driver = {
 393         .driver         = {
 394                 .name           = DRV_NAME,
 395                 .of_match_table = bcm2835_spi_match,
 396         },
 397         .probe          = bcm2835_spi_probe,
 398         .remove         = bcm2835_spi_remove,
 399 };
 400 module_platform_driver(bcm2835_spi_driver);
 401
 402 MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
 403 MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
 404 MODULE_LICENSE("GPL v2");