2 * Designware SPI core controller driver (refer pxa2xx_spi.c)
4 * Copyright (c) 2009, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/dma-mapping.h>
21 #include <linux/interrupt.h>
22 #include <linux/module.h>
23 #include <linux/highmem.h>
24 #include <linux/delay.h>
25 #include <linux/slab.h>
26 #include <linux/spi/spi.h>
27 #include <linux/gpio.h>
31 #ifdef CONFIG_DEBUG_FS
32 #include <linux/debugfs.h>
35 #define START_STATE ((void *)0)
36 #define RUNNING_STATE ((void *)1)
37 #define DONE_STATE ((void *)2)
38 #define ERROR_STATE ((void *)-1)
40 /* Slave spi_dev related */
43 u8 cs
; /* chip select pin */
44 u8 n_bytes
; /* current is a 1/2/4 byte op */
45 u8 tmode
; /* TR/TO/RO/EEPROM */
46 u8 type
; /* SPI/SSP/MicroWire */
48 u8 poll_mode
; /* 1 means use poll mode */
55 u16 clk_div
; /* baud rate divider */
56 u32 speed_hz
; /* baud rate */
57 void (*cs_control
)(u32 command
);
60 #ifdef CONFIG_DEBUG_FS
61 #define SPI_REGS_BUFSIZE 1024
62 static ssize_t
spi_show_regs(struct file
*file
, char __user
*user_buf
,
63 size_t count
, loff_t
*ppos
)
70 dws
= file
->private_data
;
72 buf
= kzalloc(SPI_REGS_BUFSIZE
, GFP_KERNEL
);
76 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
77 "MRST SPI0 registers:\n");
78 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
79 "=================================\n");
80 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
81 "CTRL0: \t\t0x%08x\n", dw_readl(dws
, DW_SPI_CTRL0
));
82 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
83 "CTRL1: \t\t0x%08x\n", dw_readl(dws
, DW_SPI_CTRL1
));
84 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
85 "SSIENR: \t0x%08x\n", dw_readl(dws
, DW_SPI_SSIENR
));
86 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
87 "SER: \t\t0x%08x\n", dw_readl(dws
, DW_SPI_SER
));
88 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
89 "BAUDR: \t\t0x%08x\n", dw_readl(dws
, DW_SPI_BAUDR
));
90 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
91 "TXFTLR: \t0x%08x\n", dw_readl(dws
, DW_SPI_TXFLTR
));
92 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
93 "RXFTLR: \t0x%08x\n", dw_readl(dws
, DW_SPI_RXFLTR
));
94 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
95 "TXFLR: \t\t0x%08x\n", dw_readl(dws
, DW_SPI_TXFLR
));
96 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
97 "RXFLR: \t\t0x%08x\n", dw_readl(dws
, DW_SPI_RXFLR
));
98 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
99 "SR: \t\t0x%08x\n", dw_readl(dws
, DW_SPI_SR
));
100 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
101 "IMR: \t\t0x%08x\n", dw_readl(dws
, DW_SPI_IMR
));
102 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
103 "ISR: \t\t0x%08x\n", dw_readl(dws
, DW_SPI_ISR
));
104 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
105 "DMACR: \t\t0x%08x\n", dw_readl(dws
, DW_SPI_DMACR
));
106 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
107 "DMATDLR: \t0x%08x\n", dw_readl(dws
, DW_SPI_DMATDLR
));
108 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
109 "DMARDLR: \t0x%08x\n", dw_readl(dws
, DW_SPI_DMARDLR
));
110 len
+= snprintf(buf
+ len
, SPI_REGS_BUFSIZE
- len
,
111 "=================================\n");
113 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
118 static const struct file_operations mrst_spi_regs_ops
= {
119 .owner
= THIS_MODULE
,
121 .read
= spi_show_regs
,
122 .llseek
= default_llseek
,
125 static int mrst_spi_debugfs_init(struct dw_spi
*dws
)
127 dws
->debugfs
= debugfs_create_dir("mrst_spi", NULL
);
131 debugfs_create_file("registers", S_IFREG
| S_IRUGO
,
132 dws
->debugfs
, (void *)dws
, &mrst_spi_regs_ops
);
136 static void mrst_spi_debugfs_remove(struct dw_spi
*dws
)
139 debugfs_remove_recursive(dws
->debugfs
);
143 static inline int mrst_spi_debugfs_init(struct dw_spi
*dws
)
148 static inline void mrst_spi_debugfs_remove(struct dw_spi
*dws
)
151 #endif /* CONFIG_DEBUG_FS */
153 /* Return the max entries we can fill into tx fifo */
154 static inline u32
tx_max(struct dw_spi
*dws
)
156 u32 tx_left
, tx_room
, rxtx_gap
;
158 tx_left
= (dws
->tx_end
- dws
->tx
) / dws
->n_bytes
;
159 tx_room
= dws
->fifo_len
- dw_readw(dws
, DW_SPI_TXFLR
);
162 * Another concern is about the tx/rx mismatch, we
163 * though to use (dws->fifo_len - rxflr - txflr) as
164 * one maximum value for tx, but it doesn't cover the
165 * data which is out of tx/rx fifo and inside the
166 * shift registers. So a control from sw point of
169 rxtx_gap
= ((dws
->rx_end
- dws
->rx
) - (dws
->tx_end
- dws
->tx
))
172 return min3(tx_left
, tx_room
, (u32
) (dws
->fifo_len
- rxtx_gap
));
175 /* Return the max entries we should read out of rx fifo */
176 static inline u32
rx_max(struct dw_spi
*dws
)
178 u32 rx_left
= (dws
->rx_end
- dws
->rx
) / dws
->n_bytes
;
180 return min(rx_left
, (u32
)dw_readw(dws
, DW_SPI_RXFLR
));
183 static void dw_writer(struct dw_spi
*dws
)
185 u32 max
= tx_max(dws
);
189 /* Set the tx word if the transfer's original "tx" is not null */
190 if (dws
->tx_end
- dws
->len
) {
191 if (dws
->n_bytes
== 1)
192 txw
= *(u8
*)(dws
->tx
);
194 txw
= *(u16
*)(dws
->tx
);
196 dw_writew(dws
, DW_SPI_DR
, txw
);
197 dws
->tx
+= dws
->n_bytes
;
201 static void dw_reader(struct dw_spi
*dws
)
203 u32 max
= rx_max(dws
);
207 rxw
= dw_readw(dws
, DW_SPI_DR
);
208 /* Care rx only if the transfer's original "rx" is not null */
209 if (dws
->rx_end
- dws
->len
) {
210 if (dws
->n_bytes
== 1)
211 *(u8
*)(dws
->rx
) = rxw
;
213 *(u16
*)(dws
->rx
) = rxw
;
215 dws
->rx
+= dws
->n_bytes
;
219 static void *next_transfer(struct dw_spi
*dws
)
221 struct spi_message
*msg
= dws
->cur_msg
;
222 struct spi_transfer
*trans
= dws
->cur_transfer
;
224 /* Move to next transfer */
225 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
227 list_entry(trans
->transfer_list
.next
,
230 return RUNNING_STATE
;
236 * Note: first step is the protocol driver prepares
237 * a dma-capable memory, and this func just need translate
238 * the virt addr to physical
240 static int map_dma_buffers(struct dw_spi
*dws
)
242 if (!dws
->cur_msg
->is_dma_mapped
244 || !dws
->cur_chip
->enable_dma
248 if (dws
->cur_transfer
->tx_dma
)
249 dws
->tx_dma
= dws
->cur_transfer
->tx_dma
;
251 if (dws
->cur_transfer
->rx_dma
)
252 dws
->rx_dma
= dws
->cur_transfer
->rx_dma
;
257 /* Caller already set message->status; dma and pio irqs are blocked */
258 static void giveback(struct dw_spi
*dws
)
260 struct spi_transfer
*last_transfer
;
261 struct spi_message
*msg
;
265 dws
->cur_transfer
= NULL
;
266 dws
->prev_chip
= dws
->cur_chip
;
267 dws
->cur_chip
= NULL
;
270 last_transfer
= list_last_entry(&msg
->transfers
, struct spi_transfer
,
273 if (!last_transfer
->cs_change
)
274 spi_chip_sel(dws
, dws
->cur_msg
->spi
, 0);
276 spi_finalize_current_message(dws
->master
);
279 static void int_error_stop(struct dw_spi
*dws
, const char *msg
)
282 spi_enable_chip(dws
, 0);
284 dev_err(&dws
->master
->dev
, "%s\n", msg
);
285 dws
->cur_msg
->state
= ERROR_STATE
;
286 tasklet_schedule(&dws
->pump_transfers
);
289 void dw_spi_xfer_done(struct dw_spi
*dws
)
291 /* Update total byte transferred return count actual bytes read */
292 dws
->cur_msg
->actual_length
+= dws
->len
;
294 /* Move to next transfer */
295 dws
->cur_msg
->state
= next_transfer(dws
);
297 /* Handle end of message */
298 if (dws
->cur_msg
->state
== DONE_STATE
) {
299 dws
->cur_msg
->status
= 0;
302 tasklet_schedule(&dws
->pump_transfers
);
304 EXPORT_SYMBOL_GPL(dw_spi_xfer_done
);
306 static irqreturn_t
interrupt_transfer(struct dw_spi
*dws
)
308 u16 irq_status
= dw_readw(dws
, DW_SPI_ISR
);
311 if (irq_status
& (SPI_INT_TXOI
| SPI_INT_RXOI
| SPI_INT_RXUI
)) {
312 dw_readw(dws
, DW_SPI_TXOICR
);
313 dw_readw(dws
, DW_SPI_RXOICR
);
314 dw_readw(dws
, DW_SPI_RXUICR
);
315 int_error_stop(dws
, "interrupt_transfer: fifo overrun/underrun");
320 if (dws
->rx_end
== dws
->rx
) {
321 spi_mask_intr(dws
, SPI_INT_TXEI
);
322 dw_spi_xfer_done(dws
);
325 if (irq_status
& SPI_INT_TXEI
) {
326 spi_mask_intr(dws
, SPI_INT_TXEI
);
328 /* Enable TX irq always, it will be disabled when RX finished */
329 spi_umask_intr(dws
, SPI_INT_TXEI
);
335 static irqreturn_t
dw_spi_irq(int irq
, void *dev_id
)
337 struct dw_spi
*dws
= dev_id
;
338 u16 irq_status
= dw_readw(dws
, DW_SPI_ISR
) & 0x3f;
344 spi_mask_intr(dws
, SPI_INT_TXEI
);
348 return dws
->transfer_handler(dws
);
351 /* Must be called inside pump_transfers() */
352 static void poll_transfer(struct dw_spi
*dws
)
358 } while (dws
->rx_end
> dws
->rx
);
360 dw_spi_xfer_done(dws
);
363 static void pump_transfers(unsigned long data
)
365 struct dw_spi
*dws
= (struct dw_spi
*)data
;
366 struct spi_message
*message
= NULL
;
367 struct spi_transfer
*transfer
= NULL
;
368 struct spi_transfer
*previous
= NULL
;
369 struct spi_device
*spi
= NULL
;
370 struct chip_data
*chip
= NULL
;
379 /* Get current state information */
380 message
= dws
->cur_msg
;
381 transfer
= dws
->cur_transfer
;
382 chip
= dws
->cur_chip
;
385 if (unlikely(!chip
->clk_div
))
386 chip
->clk_div
= dws
->max_freq
/ chip
->speed_hz
;
388 if (message
->state
== ERROR_STATE
) {
389 message
->status
= -EIO
;
393 /* Handle end of message */
394 if (message
->state
== DONE_STATE
) {
399 /* Delay if requested at end of transfer*/
400 if (message
->state
== RUNNING_STATE
) {
401 previous
= list_entry(transfer
->transfer_list
.prev
,
404 if (previous
->delay_usecs
)
405 udelay(previous
->delay_usecs
);
408 dws
->n_bytes
= chip
->n_bytes
;
409 dws
->dma_width
= chip
->dma_width
;
410 dws
->cs_control
= chip
->cs_control
;
412 dws
->rx_dma
= transfer
->rx_dma
;
413 dws
->tx_dma
= transfer
->tx_dma
;
414 dws
->tx
= (void *)transfer
->tx_buf
;
415 dws
->tx_end
= dws
->tx
+ transfer
->len
;
416 dws
->rx
= transfer
->rx_buf
;
417 dws
->rx_end
= dws
->rx
+ transfer
->len
;
418 dws
->len
= dws
->cur_transfer
->len
;
419 if (chip
!= dws
->prev_chip
)
424 /* Handle per transfer options for bpw and speed */
425 if (transfer
->speed_hz
) {
426 speed
= chip
->speed_hz
;
428 if (transfer
->speed_hz
!= speed
) {
429 speed
= transfer
->speed_hz
;
431 /* clk_div doesn't support odd number */
432 clk_div
= dws
->max_freq
/ speed
;
433 clk_div
= (clk_div
+ 1) & 0xfffe;
435 chip
->speed_hz
= speed
;
436 chip
->clk_div
= clk_div
;
439 if (transfer
->bits_per_word
) {
440 bits
= transfer
->bits_per_word
;
441 dws
->n_bytes
= dws
->dma_width
= bits
>> 3;
443 | (chip
->type
<< SPI_FRF_OFFSET
)
444 | (spi
->mode
<< SPI_MODE_OFFSET
)
445 | (chip
->tmode
<< SPI_TMOD_OFFSET
);
447 message
->state
= RUNNING_STATE
;
450 * Adjust transfer mode if necessary. Requires platform dependent
451 * chipselect mechanism.
453 if (dws
->cs_control
) {
454 if (dws
->rx
&& dws
->tx
)
455 chip
->tmode
= SPI_TMOD_TR
;
457 chip
->tmode
= SPI_TMOD_RO
;
459 chip
->tmode
= SPI_TMOD_TO
;
461 cr0
&= ~SPI_TMOD_MASK
;
462 cr0
|= (chip
->tmode
<< SPI_TMOD_OFFSET
);
465 /* Check if current transfer is a DMA transaction */
466 dws
->dma_mapped
= map_dma_buffers(dws
);
470 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
472 if (!dws
->dma_mapped
&& !chip
->poll_mode
) {
473 int templen
= dws
->len
/ dws
->n_bytes
;
474 txint_level
= dws
->fifo_len
/ 2;
475 txint_level
= (templen
> txint_level
) ? txint_level
: templen
;
477 imask
|= SPI_INT_TXEI
| SPI_INT_TXOI
| SPI_INT_RXUI
| SPI_INT_RXOI
;
478 dws
->transfer_handler
= interrupt_transfer
;
482 * Reprogram registers only if
483 * 1. chip select changes
484 * 2. clk_div is changed
485 * 3. control value changes
487 if (dw_readw(dws
, DW_SPI_CTRL0
) != cr0
|| cs_change
|| clk_div
|| imask
) {
488 spi_enable_chip(dws
, 0);
490 if (dw_readw(dws
, DW_SPI_CTRL0
) != cr0
)
491 dw_writew(dws
, DW_SPI_CTRL0
, cr0
);
493 spi_set_clk(dws
, clk_div
? clk_div
: chip
->clk_div
);
494 spi_chip_sel(dws
, spi
, 1);
496 /* Set the interrupt mask, for poll mode just disable all int */
497 spi_mask_intr(dws
, 0xff);
499 spi_umask_intr(dws
, imask
);
501 dw_writew(dws
, DW_SPI_TXFLTR
, txint_level
);
503 spi_enable_chip(dws
, 1);
505 dws
->prev_chip
= chip
;
509 dws
->dma_ops
->dma_transfer(dws
, cs_change
);
521 static int dw_spi_transfer_one_message(struct spi_master
*master
,
522 struct spi_message
*msg
)
524 struct dw_spi
*dws
= spi_master_get_devdata(master
);
527 /* Initial message state*/
528 dws
->cur_msg
->state
= START_STATE
;
529 dws
->cur_transfer
= list_entry(dws
->cur_msg
->transfers
.next
,
532 dws
->cur_chip
= spi_get_ctldata(dws
->cur_msg
->spi
);
534 /* Launch transfers */
535 tasklet_schedule(&dws
->pump_transfers
);
540 /* This may be called twice for each spi dev */
541 static int dw_spi_setup(struct spi_device
*spi
)
543 struct dw_spi_chip
*chip_info
= NULL
;
544 struct chip_data
*chip
;
547 /* Only alloc on first setup */
548 chip
= spi_get_ctldata(spi
);
550 chip
= devm_kzalloc(&spi
->dev
, sizeof(struct chip_data
),
554 spi_set_ctldata(spi
, chip
);
558 * Protocol drivers may change the chip settings, so...
559 * if chip_info exists, use it
561 chip_info
= spi
->controller_data
;
563 /* chip_info doesn't always exist */
565 if (chip_info
->cs_control
)
566 chip
->cs_control
= chip_info
->cs_control
;
568 chip
->poll_mode
= chip_info
->poll_mode
;
569 chip
->type
= chip_info
->type
;
571 chip
->rx_threshold
= 0;
572 chip
->tx_threshold
= 0;
574 chip
->enable_dma
= chip_info
->enable_dma
;
577 if (spi
->bits_per_word
== 8) {
580 } else if (spi
->bits_per_word
== 16) {
584 chip
->bits_per_word
= spi
->bits_per_word
;
586 if (!spi
->max_speed_hz
) {
587 dev_err(&spi
->dev
, "No max speed HZ parameter\n");
590 chip
->speed_hz
= spi
->max_speed_hz
;
592 chip
->tmode
= 0; /* Tx & Rx */
593 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
594 chip
->cr0
= (chip
->bits_per_word
- 1)
595 | (chip
->type
<< SPI_FRF_OFFSET
)
596 | (spi
->mode
<< SPI_MODE_OFFSET
)
597 | (chip
->tmode
<< SPI_TMOD_OFFSET
);
599 if (gpio_is_valid(spi
->cs_gpio
)) {
600 ret
= gpio_direction_output(spi
->cs_gpio
,
601 !(spi
->mode
& SPI_CS_HIGH
));
609 /* Restart the controller, disable all interrupts, clean rx fifo */
610 static void spi_hw_init(struct dw_spi
*dws
)
612 spi_enable_chip(dws
, 0);
613 spi_mask_intr(dws
, 0xff);
614 spi_enable_chip(dws
, 1);
617 * Try to detect the FIFO depth if not set by interface driver,
618 * the depth could be from 2 to 256 from HW spec
620 if (!dws
->fifo_len
) {
622 for (fifo
= 2; fifo
<= 257; fifo
++) {
623 dw_writew(dws
, DW_SPI_TXFLTR
, fifo
);
624 if (fifo
!= dw_readw(dws
, DW_SPI_TXFLTR
))
628 dws
->fifo_len
= (fifo
== 257) ? 0 : fifo
;
629 dw_writew(dws
, DW_SPI_TXFLTR
, 0);
633 int dw_spi_add_host(struct device
*dev
, struct dw_spi
*dws
)
635 struct spi_master
*master
;
640 master
= spi_alloc_master(dev
, 0);
644 dws
->master
= master
;
645 dws
->type
= SSI_MOTO_SPI
;
646 dws
->prev_chip
= NULL
;
648 dws
->dma_addr
= (dma_addr_t
)(dws
->paddr
+ 0x60);
649 snprintf(dws
->name
, sizeof(dws
->name
), "dw_spi%d",
652 ret
= devm_request_irq(dev
, dws
->irq
, dw_spi_irq
, IRQF_SHARED
,
655 dev_err(&master
->dev
, "can not get IRQ\n");
656 goto err_free_master
;
659 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
;
660 master
->bits_per_word_mask
= SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
661 master
->bus_num
= dws
->bus_num
;
662 master
->num_chipselect
= dws
->num_cs
;
663 master
->setup
= dw_spi_setup
;
664 master
->transfer_one_message
= dw_spi_transfer_one_message
;
665 master
->max_speed_hz
= dws
->max_freq
;
670 if (dws
->dma_ops
&& dws
->dma_ops
->dma_init
) {
671 ret
= dws
->dma_ops
->dma_init(dws
);
673 dev_warn(&master
->dev
, "DMA init failed\n");
678 tasklet_init(&dws
->pump_transfers
, pump_transfers
, (unsigned long)dws
);
680 spi_master_set_devdata(master
, dws
);
681 ret
= devm_spi_register_master(dev
, master
);
683 dev_err(&master
->dev
, "problem registering spi master\n");
687 mrst_spi_debugfs_init(dws
);
691 if (dws
->dma_ops
&& dws
->dma_ops
->dma_exit
)
692 dws
->dma_ops
->dma_exit(dws
);
693 spi_enable_chip(dws
, 0);
695 spi_master_put(master
);
698 EXPORT_SYMBOL_GPL(dw_spi_add_host
);
700 void dw_spi_remove_host(struct dw_spi
*dws
)
704 mrst_spi_debugfs_remove(dws
);
706 if (dws
->dma_ops
&& dws
->dma_ops
->dma_exit
)
707 dws
->dma_ops
->dma_exit(dws
);
708 spi_enable_chip(dws
, 0);
712 EXPORT_SYMBOL_GPL(dw_spi_remove_host
);
714 int dw_spi_suspend_host(struct dw_spi
*dws
)
718 ret
= spi_master_suspend(dws
->master
);
721 spi_enable_chip(dws
, 0);
725 EXPORT_SYMBOL_GPL(dw_spi_suspend_host
);
727 int dw_spi_resume_host(struct dw_spi
*dws
)
732 ret
= spi_master_resume(dws
->master
);
734 dev_err(&dws
->master
->dev
, "fail to start queue (%d)\n", ret
);
737 EXPORT_SYMBOL_GPL(dw_spi_resume_host
);
739 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
740 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
741 MODULE_LICENSE("GPL v2");