drivers/spi/spi-fsl-dspi.c

   1 /*
   2  * drivers/spi/spi-fsl-dspi.c
   3  *
   4  * Copyright 2013 Freescale Semiconductor, Inc.
   5  *
   6  * Freescale DSPI driver
   7  * This file contains a driver for the Freescale DSPI
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  */
  15
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/errno.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/math64.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/regmap.h>
  30 #include <linux/sched.h>
  31 #include <linux/spi/spi.h>
  32 #include <linux/spi/spi_bitbang.h>
  33 #include <linux/time.h>
  34
  35 #define DRIVER_NAME "fsl-dspi"
  36
  37 #define TRAN_STATE_RX_VOID              0x01
  38 #define TRAN_STATE_TX_VOID              0x02
  39 #define TRAN_STATE_WORD_ODD_NUM 0x04
  40
  41 #define DSPI_FIFO_SIZE                  4
  42
  43 #define SPI_MCR         0x00
  44 #define SPI_MCR_MASTER          (1 << 31)
  45 #define SPI_MCR_PCSIS           (0x3F << 16)
  46 #define SPI_MCR_CLR_TXF (1 << 11)
  47 #define SPI_MCR_CLR_RXF (1 << 10)
  48
  49 #define SPI_TCR                 0x08
  50
  51 #define SPI_CTAR(x)             (0x0c + (((x) & 0x3) * 4))
  52 #define SPI_CTAR_FMSZ(x)        (((x) & 0x0000000f) << 27)
  53 #define SPI_CTAR_CPOL(x)        ((x) << 26)
  54 #define SPI_CTAR_CPHA(x)        ((x) << 25)
  55 #define SPI_CTAR_LSBFE(x)       ((x) << 24)
  56 #define SPI_CTAR_PCSSCK(x)      (((x) & 0x00000003) << 22)
  57 #define SPI_CTAR_PASC(x)        (((x) & 0x00000003) << 20)
  58 #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
  59 #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
  60 #define SPI_CTAR_CSSCK(x)       (((x) & 0x0000000f) << 12)
  61 #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
  62 #define SPI_CTAR_DT(x)          (((x) & 0x0000000f) << 4)
  63 #define SPI_CTAR_BR(x)          ((x) & 0x0000000f)
  64 #define SPI_CTAR_SCALE_BITS     0xf
  65
  66 #define SPI_CTAR0_SLAVE 0x0c
  67
  68 #define SPI_SR                  0x2c
  69 #define SPI_SR_EOQF             0x10000000
  70 #define SPI_SR_TCFQF            0x80000000
  71
  72 #define SPI_RSER                0x30
  73 #define SPI_RSER_EOQFE          0x10000000
  74 #define SPI_RSER_TCFQE          0x80000000
  75
  76 #define SPI_PUSHR               0x34
  77 #define SPI_PUSHR_CONT          (1 << 31)
  78 #define SPI_PUSHR_CTAS(x)       (((x) & 0x00000003) << 28)
  79 #define SPI_PUSHR_EOQ           (1 << 27)
  80 #define SPI_PUSHR_CTCNT (1 << 26)
  81 #define SPI_PUSHR_PCS(x)        (((1 << x) & 0x0000003f) << 16)
  82 #define SPI_PUSHR_TXDATA(x)     ((x) & 0x0000ffff)
  83
  84 #define SPI_PUSHR_SLAVE 0x34
  85
  86 #define SPI_POPR                0x38
  87 #define SPI_POPR_RXDATA(x)      ((x) & 0x0000ffff)
  88
  89 #define SPI_TXFR0               0x3c
  90 #define SPI_TXFR1               0x40
  91 #define SPI_TXFR2               0x44
  92 #define SPI_TXFR3               0x48
  93 #define SPI_RXFR0               0x7c
  94 #define SPI_RXFR1               0x80
  95 #define SPI_RXFR2               0x84
  96 #define SPI_RXFR3               0x88
  97
  98 #define SPI_FRAME_BITS(bits)    SPI_CTAR_FMSZ((bits) - 1)
  99 #define SPI_FRAME_BITS_MASK     SPI_CTAR_FMSZ(0xf)
 100 #define SPI_FRAME_BITS_16       SPI_CTAR_FMSZ(0xf)
 101 #define SPI_FRAME_BITS_8        SPI_CTAR_FMSZ(0x7)
 102
 103 #define SPI_CS_INIT             0x01
 104 #define SPI_CS_ASSERT           0x02
 105 #define SPI_CS_DROP             0x04
 106
 107 struct chip_data {
 108         u32 mcr_val;
 109         u32 ctar_val;
 110         u16 void_write_data;
 111 };
 112
 113 enum dspi_trans_mode {
 114         DSPI_EOQ_MODE = 0,
 115         DSPI_TCFQ_MODE,
 116 };
 117
 118 struct fsl_dspi_devtype_data {
 119         enum dspi_trans_mode trans_mode;
 120 };
 121
 122 static const struct fsl_dspi_devtype_data vf610_data = {
 123         .trans_mode = DSPI_EOQ_MODE,
 124 };
 125
 126 static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
 127         .trans_mode = DSPI_TCFQ_MODE,
 128 };
 129
 130 static const struct fsl_dspi_devtype_data ls2085a_data = {
 131         .trans_mode = DSPI_TCFQ_MODE,
 132 };
 133
 134 struct fsl_dspi {
 135         struct spi_master       *master;
 136         struct platform_device  *pdev;
 137
 138         struct regmap           *regmap;
 139         int                     irq;
 140         struct clk              *clk;
 141
 142         struct spi_transfer     *cur_transfer;
 143         struct spi_message      *cur_msg;
 144         struct chip_data        *cur_chip;
 145         size_t                  len;
 146         void                    *tx;
 147         void                    *tx_end;
 148         void                    *rx;
 149         void                    *rx_end;
 150         char                    dataflags;
 151         u8                      cs;
 152         u16                     void_write_data;
 153         u32                     cs_change;
 154         struct fsl_dspi_devtype_data *devtype_data;
 155
 156         wait_queue_head_t       waitq;
 157         u32                     waitflags;
 158 };
 159
 160 static inline int is_double_byte_mode(struct fsl_dspi *dspi)
 161 {
 162         unsigned int val;
 163
 164         regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
 165
 166         return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
 167 }
 168
 169 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
 170                 unsigned long clkrate)
 171 {
 172         /* Valid baud rate pre-scaler values */
 173         int pbr_tbl[4] = {2, 3, 5, 7};
 174         int brs[16] = { 2,      4,      6,      8,
 175                 16,     32,     64,     128,
 176                 256,    512,    1024,   2048,
 177                 4096,   8192,   16384,  32768 };
 178         int scale_needed, scale, minscale = INT_MAX;
 179         int i, j;
 180
 181         scale_needed = clkrate / speed_hz;
 182         if (clkrate % speed_hz)
 183                 scale_needed++;
 184
 185         for (i = 0; i < ARRAY_SIZE(brs); i++)
 186                 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
 187                         scale = brs[i] * pbr_tbl[j];
 188                         if (scale >= scale_needed) {
 189                                 if (scale < minscale) {
 190                                         minscale = scale;
 191                                         *br = i;
 192                                         *pbr = j;
 193                                 }
 194                                 break;
 195                         }
 196                 }
 197
 198         if (minscale == INT_MAX) {
 199                 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
 200                         speed_hz, clkrate);
 201                 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
 202                 *br =  ARRAY_SIZE(brs) - 1;
 203         }
 204 }
 205
 206 static void ns_delay_scale(char *psc, char *sc, int delay_ns,
 207                 unsigned long clkrate)
 208 {
 209         int pscale_tbl[4] = {1, 3, 5, 7};
 210         int scale_needed, scale, minscale = INT_MAX;
 211         int i, j;
 212         u32 remainder;
 213
 214         scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
 215                         &remainder);
 216         if (remainder)
 217                 scale_needed++;
 218
 219         for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
 220                 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
 221                         scale = pscale_tbl[i] * (2 << j);
 222                         if (scale >= scale_needed) {
 223                                 if (scale < minscale) {
 224                                         minscale = scale;
 225                                         *psc = i;
 226                                         *sc = j;
 227                                 }
 228                                 break;
 229                         }
 230                 }
 231
 232         if (minscale == INT_MAX) {
 233                 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
 234                         delay_ns, clkrate);
 235                 *psc = ARRAY_SIZE(pscale_tbl) - 1;
 236                 *sc = SPI_CTAR_SCALE_BITS;
 237         }
 238 }
 239
 240 static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word)
 241 {
 242         u16 d16;
 243
 244         if (!(dspi->dataflags & TRAN_STATE_TX_VOID))
 245                 d16 = tx_word ? *(u16 *)dspi->tx : *(u8 *)dspi->tx;
 246         else
 247                 d16 = dspi->void_write_data;
 248
 249         dspi->tx += tx_word + 1;
 250         dspi->len -= tx_word + 1;
 251
 252         return  SPI_PUSHR_TXDATA(d16) |
 253                 SPI_PUSHR_PCS(dspi->cs) |
 254                 SPI_PUSHR_CTAS(dspi->cs) |
 255                 SPI_PUSHR_CONT;
 256 }
 257
 258 static void dspi_data_from_popr(struct fsl_dspi *dspi, int rx_word)
 259 {
 260         u16 d;
 261         unsigned int val;
 262
 263         regmap_read(dspi->regmap, SPI_POPR, &val);
 264         d = SPI_POPR_RXDATA(val);
 265
 266         if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
 267                 rx_word ? (*(u16 *)dspi->rx = d) : (*(u8 *)dspi->rx = d);
 268
 269         dspi->rx += rx_word + 1;
 270 }
 271
 272 static int dspi_eoq_write(struct fsl_dspi *dspi)
 273 {
 274         int tx_count = 0;
 275         int tx_word;
 276         u32 dspi_pushr = 0;
 277         int first = 1;
 278
 279         tx_word = is_double_byte_mode(dspi);
 280
 281         while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
 282                 /* If we are in word mode, only have a single byte to transfer
 283                  * switch to byte mode temporarily.  Will switch back at the
 284                  * end of the transfer.
 285                  */
 286                 if (tx_word && (dspi->len == 1)) {
 287                         dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
 288                         regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
 289                                         SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
 290                         tx_word = 0;
 291                 }
 292
 293                 dspi_pushr = dspi_data_to_pushr(dspi, tx_word);
 294
 295                 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
 296                         /* last transfer in the transfer */
 297                         dspi_pushr |= SPI_PUSHR_EOQ;
 298                         if ((dspi->cs_change) && (!dspi->len))
 299                                 dspi_pushr &= ~SPI_PUSHR_CONT;
 300                 } else if (tx_word && (dspi->len == 1))
 301                         dspi_pushr |= SPI_PUSHR_EOQ;
 302
 303                 if (first) {
 304                         first = 0;
 305                         dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
 306                 }
 307
 308                 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
 309
 310                 tx_count++;
 311         }
 312
 313         return tx_count * (tx_word + 1);
 314 }
 315
 316 static int dspi_eoq_read(struct fsl_dspi *dspi)
 317 {
 318         int rx_count = 0;
 319         int rx_word = is_double_byte_mode(dspi);
 320
 321         while ((dspi->rx < dspi->rx_end)
 322                         && (rx_count < DSPI_FIFO_SIZE)) {
 323                 if (rx_word && (dspi->rx_end - dspi->rx) == 1)
 324                         rx_word = 0;
 325
 326                 dspi_data_from_popr(dspi, rx_word);
 327                 rx_count++;
 328         }
 329
 330         return rx_count;
 331 }
 332
 333 static int dspi_tcfq_write(struct fsl_dspi *dspi)
 334 {
 335         int tx_word;
 336         u32 dspi_pushr = 0;
 337
 338         tx_word = is_double_byte_mode(dspi);
 339
 340         if (tx_word && (dspi->len == 1)) {
 341                 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
 342                 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
 343                                 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
 344                 tx_word = 0;
 345         }
 346
 347         dspi_pushr = dspi_data_to_pushr(dspi, tx_word);
 348
 349         if ((dspi->cs_change) && (!dspi->len))
 350                 dspi_pushr &= ~SPI_PUSHR_CONT;
 351
 352         regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
 353
 354         return tx_word + 1;
 355 }
 356
 357 static void dspi_tcfq_read(struct fsl_dspi *dspi)
 358 {
 359         int rx_word = is_double_byte_mode(dspi);
 360
 361         if (rx_word && (dspi->rx_end - dspi->rx) == 1)
 362                 rx_word = 0;
 363
 364         dspi_data_from_popr(dspi, rx_word);
 365 }
 366
 367 static int dspi_transfer_one_message(struct spi_master *master,
 368                 struct spi_message *message)
 369 {
 370         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 371         struct spi_device *spi = message->spi;
 372         struct spi_transfer *transfer;
 373         int status = 0;
 374         enum dspi_trans_mode trans_mode;
 375
 376         message->actual_length = 0;
 377
 378         list_for_each_entry(transfer, &message->transfers, transfer_list) {
 379                 dspi->cur_transfer = transfer;
 380                 dspi->cur_msg = message;
 381                 dspi->cur_chip = spi_get_ctldata(spi);
 382                 dspi->cs = spi->chip_select;
 383                 dspi->cs_change = 0;
 384                 if (dspi->cur_transfer->transfer_list.next
 385                                 == &dspi->cur_msg->transfers)
 386                         dspi->cs_change = 1;
 387                 dspi->void_write_data = dspi->cur_chip->void_write_data;
 388
 389                 dspi->dataflags = 0;
 390                 dspi->tx = (void *)transfer->tx_buf;
 391                 dspi->tx_end = dspi->tx + transfer->len;
 392                 dspi->rx = transfer->rx_buf;
 393                 dspi->rx_end = dspi->rx + transfer->len;
 394                 dspi->len = transfer->len;
 395
 396                 if (!dspi->rx)
 397                         dspi->dataflags |= TRAN_STATE_RX_VOID;
 398
 399                 if (!dspi->tx)
 400                         dspi->dataflags |= TRAN_STATE_TX_VOID;
 401
 402                 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
 403                 regmap_update_bits(dspi->regmap, SPI_MCR,
 404                                 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
 405                                 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
 406                 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
 407                                 dspi->cur_chip->ctar_val);
 408                 if (transfer->speed_hz)
 409                         regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
 410                                         dspi->cur_chip->ctar_val);
 411
 412                 trans_mode = dspi->devtype_data->trans_mode;
 413                 switch (trans_mode) {
 414                 case DSPI_EOQ_MODE:
 415                         regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
 416                         message->actual_length += dspi_eoq_write(dspi);
 417                         break;
 418                 case DSPI_TCFQ_MODE:
 419                         regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
 420                         message->actual_length += dspi_tcfq_write(dspi);
 421                         break;
 422                 default:
 423                         dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
 424                                 trans_mode);
 425                         status = -EINVAL;
 426                         goto out;
 427                 }
 428
 429                 if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
 430                         dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
 431                 dspi->waitflags = 0;
 432
 433                 if (transfer->delay_usecs)
 434                         udelay(transfer->delay_usecs);
 435         }
 436
 437 out:
 438         message->status = status;
 439         spi_finalize_current_message(master);
 440
 441         return status;
 442 }
 443
 444 static int dspi_setup(struct spi_device *spi)
 445 {
 446         struct chip_data *chip;
 447         struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
 448         u32 cs_sck_delay = 0, sck_cs_delay = 0;
 449         unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
 450         unsigned char pasc = 0, asc = 0, fmsz = 0;
 451         unsigned long clkrate;
 452
 453         if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
 454                 fmsz = spi->bits_per_word - 1;
 455         } else {
 456                 pr_err("Invalid wordsize\n");
 457                 return -ENODEV;
 458         }
 459
 460         /* Only alloc on first setup */
 461         chip = spi_get_ctldata(spi);
 462         if (chip == NULL) {
 463                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
 464                 if (!chip)
 465                         return -ENOMEM;
 466         }
 467
 468         of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
 469                         &cs_sck_delay);
 470
 471         of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
 472                         &sck_cs_delay);
 473
 474         chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
 475                 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
 476
 477         chip->void_write_data = 0;
 478
 479         clkrate = clk_get_rate(dspi->clk);
 480         hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
 481
 482         /* Set PCS to SCK delay scale values */
 483         ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
 484
 485         /* Set After SCK delay scale values */
 486         ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
 487
 488         chip->ctar_val =  SPI_CTAR_FMSZ(fmsz)
 489                 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
 490                 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
 491                 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
 492                 | SPI_CTAR_PCSSCK(pcssck)
 493                 | SPI_CTAR_CSSCK(cssck)
 494                 | SPI_CTAR_PASC(pasc)
 495                 | SPI_CTAR_ASC(asc)
 496                 | SPI_CTAR_PBR(pbr)
 497                 | SPI_CTAR_BR(br);
 498
 499         spi_set_ctldata(spi, chip);
 500
 501         return 0;
 502 }
 503
 504 static void dspi_cleanup(struct spi_device *spi)
 505 {
 506         struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
 507
 508         dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
 509                         spi->master->bus_num, spi->chip_select);
 510
 511         kfree(chip);
 512 }
 513
 514 static irqreturn_t dspi_interrupt(int irq, void *dev_id)
 515 {
 516         struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
 517         struct spi_message *msg = dspi->cur_msg;
 518         enum dspi_trans_mode trans_mode;
 519         u32 spi_sr;
 520
 521         regmap_read(dspi->regmap, SPI_SR, &spi_sr);
 522         regmap_write(dspi->regmap, SPI_SR, spi_sr);
 523
 524         trans_mode = dspi->devtype_data->trans_mode;
 525         switch (trans_mode) {
 526         case DSPI_EOQ_MODE:
 527                 dspi_eoq_read(dspi);
 528                 break;
 529         case DSPI_TCFQ_MODE:
 530                 dspi_tcfq_read(dspi);
 531                 break;
 532         default:
 533                 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
 534                         trans_mode);
 535                 return IRQ_HANDLED;
 536         }
 537
 538         if (!dspi->len) {
 539                 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) {
 540                         regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
 541                         SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
 542                         dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM;
 543                 }
 544
 545                 dspi->waitflags = 1;
 546                 wake_up_interruptible(&dspi->waitq);
 547         } else {
 548                 switch (trans_mode) {
 549                 case DSPI_EOQ_MODE:
 550                         msg->actual_length += dspi_eoq_write(dspi);
 551                         break;
 552                 case DSPI_TCFQ_MODE:
 553                         msg->actual_length += dspi_tcfq_write(dspi);
 554                         break;
 555                 default:
 556                         dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
 557                                 trans_mode);
 558                 }
 559         }
 560         return IRQ_HANDLED;
 561 }
 562
 563 static const struct of_device_id fsl_dspi_dt_ids[] = {
 564         { .compatible = "fsl,vf610-dspi", .data = (void *)&vf610_data, },
 565         { .compatible = "fsl,ls1021a-v1.0-dspi",
 566                 .data = (void *)&ls1021a_v1_data, },
 567         { .compatible = "fsl,ls2085a-dspi", .data = (void *)&ls2085a_data, },
 568         { /* sentinel */ }
 569 };
 570 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
 571
 572 #ifdef CONFIG_PM_SLEEP
 573 static int dspi_suspend(struct device *dev)
 574 {
 575         struct spi_master *master = dev_get_drvdata(dev);
 576         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 577
 578         spi_master_suspend(master);
 579         clk_disable_unprepare(dspi->clk);
 580
 581         return 0;
 582 }
 583
 584 static int dspi_resume(struct device *dev)
 585 {
 586         struct spi_master *master = dev_get_drvdata(dev);
 587         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 588
 589         clk_prepare_enable(dspi->clk);
 590         spi_master_resume(master);
 591
 592         return 0;
 593 }
 594 #endif /* CONFIG_PM_SLEEP */
 595
 596 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
 597
 598 static const struct regmap_config dspi_regmap_config = {
 599         .reg_bits = 32,
 600         .val_bits = 32,
 601         .reg_stride = 4,
 602         .max_register = 0x88,
 603 };
 604
 605 static int dspi_probe(struct platform_device *pdev)
 606 {
 607         struct device_node *np = pdev->dev.of_node;
 608         struct spi_master *master;
 609         struct fsl_dspi *dspi;
 610         struct resource *res;
 611         void __iomem *base;
 612         int ret = 0, cs_num, bus_num;
 613         const struct of_device_id *of_id =
 614                         of_match_device(fsl_dspi_dt_ids, &pdev->dev);
 615
 616         master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
 617         if (!master)
 618                 return -ENOMEM;
 619
 620         dspi = spi_master_get_devdata(master);
 621         dspi->pdev = pdev;
 622         dspi->master = master;
 623
 624         master->transfer = NULL;
 625         master->setup = dspi_setup;
 626         master->transfer_one_message = dspi_transfer_one_message;
 627         master->dev.of_node = pdev->dev.of_node;
 628
 629         master->cleanup = dspi_cleanup;
 630         master->mode_bits = SPI_CPOL | SPI_CPHA;
 631         master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
 632                                         SPI_BPW_MASK(16);
 633
 634         ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
 635         if (ret < 0) {
 636                 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
 637                 goto out_master_put;
 638         }
 639         master->num_chipselect = cs_num;
 640
 641         ret = of_property_read_u32(np, "bus-num", &bus_num);
 642         if (ret < 0) {
 643                 dev_err(&pdev->dev, "can't get bus-num\n");
 644                 goto out_master_put;
 645         }
 646         master->bus_num = bus_num;
 647
 648         dspi->devtype_data = (struct fsl_dspi_devtype_data *)of_id->data;
 649         if (!dspi->devtype_data) {
 650                 dev_err(&pdev->dev, "can't get devtype_data\n");
 651                 ret = -EFAULT;
 652                 goto out_master_put;
 653         }
 654
 655         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 656         base = devm_ioremap_resource(&pdev->dev, res);
 657         if (IS_ERR(base)) {
 658                 ret = PTR_ERR(base);
 659                 goto out_master_put;
 660         }
 661
 662         dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
 663                                                 &dspi_regmap_config);
 664         if (IS_ERR(dspi->regmap)) {
 665                 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
 666                                 PTR_ERR(dspi->regmap));
 667                 return PTR_ERR(dspi->regmap);
 668         }
 669
 670         dspi->irq = platform_get_irq(pdev, 0);
 671         if (dspi->irq < 0) {
 672                 dev_err(&pdev->dev, "can't get platform irq\n");
 673                 ret = dspi->irq;
 674                 goto out_master_put;
 675         }
 676
 677         ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
 678                         pdev->name, dspi);
 679         if (ret < 0) {
 680                 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
 681                 goto out_master_put;
 682         }
 683
 684         dspi->clk = devm_clk_get(&pdev->dev, "dspi");
 685         if (IS_ERR(dspi->clk)) {
 686                 ret = PTR_ERR(dspi->clk);
 687                 dev_err(&pdev->dev, "unable to get clock\n");
 688                 goto out_master_put;
 689         }
 690         clk_prepare_enable(dspi->clk);
 691
 692         init_waitqueue_head(&dspi->waitq);
 693         platform_set_drvdata(pdev, master);
 694
 695         ret = spi_register_master(master);
 696         if (ret != 0) {
 697                 dev_err(&pdev->dev, "Problem registering DSPI master\n");
 698                 goto out_clk_put;
 699         }
 700
 701         return ret;
 702
 703 out_clk_put:
 704         clk_disable_unprepare(dspi->clk);
 705 out_master_put:
 706         spi_master_put(master);
 707
 708         return ret;
 709 }
 710
 711 static int dspi_remove(struct platform_device *pdev)
 712 {
 713         struct spi_master *master = platform_get_drvdata(pdev);
 714         struct fsl_dspi *dspi = spi_master_get_devdata(master);
 715
 716         /* Disconnect from the SPI framework */
 717         clk_disable_unprepare(dspi->clk);
 718         spi_unregister_master(dspi->master);
 719         spi_master_put(dspi->master);
 720
 721         return 0;
 722 }
 723
 724 static struct platform_driver fsl_dspi_driver = {
 725         .driver.name    = DRIVER_NAME,
 726         .driver.of_match_table = fsl_dspi_dt_ids,
 727         .driver.owner   = THIS_MODULE,
 728         .driver.pm = &dspi_pm,
 729         .probe          = dspi_probe,
 730         .remove         = dspi_remove,
 731 };
 732 module_platform_driver(fsl_dspi_driver);
 733
 734 MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
 735 MODULE_LICENSE("GPL");
 736 MODULE_ALIAS("platform:" DRIVER_NAME);