2 * Freescale SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
7 * Copyright 2010 Freescale Semiconductor, Inc.
9 * CPM SPI and QE buffer descriptors mode support:
10 * Copyright (c) 2009 MontaVista Software, Inc.
11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
14 * Copyright (c) 2012 Aeroflex Gaisler AB.
15 * Author: Andreas Larsson <andreas@gaisler.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
22 #include <linux/module.h>
23 #include <linux/types.h>
24 #include <linux/kernel.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/irq.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/spi_bitbang.h>
30 #include <linux/platform_device.h>
31 #include <linux/fsl_devices.h>
32 #include <linux/dma-mapping.h>
34 #include <linux/mutex.h>
36 #include <linux/of_platform.h>
37 #include <linux/of_address.h>
38 #include <linux/of_irq.h>
39 #include <linux/gpio.h>
40 #include <linux/of_gpio.h>
42 #include "spi-fsl-lib.h"
43 #include "spi-fsl-cpm.h"
44 #include "spi-fsl-spi.h"
49 struct fsl_spi_match_data
{
53 static struct fsl_spi_match_data of_fsl_spi_fsl_config
= {
57 static struct fsl_spi_match_data of_fsl_spi_grlib_config
= {
61 static struct of_device_id of_fsl_spi_match
[] = {
63 .compatible
= "fsl,spi",
64 .data
= &of_fsl_spi_fsl_config
,
67 .compatible
= "aeroflexgaisler,spictrl",
68 .data
= &of_fsl_spi_grlib_config
,
72 MODULE_DEVICE_TABLE(of
, of_fsl_spi_match
);
74 static int fsl_spi_get_type(struct device
*dev
)
76 const struct of_device_id
*match
;
79 match
= of_match_node(of_fsl_spi_match
, dev
->of_node
);
80 if (match
&& match
->data
)
81 return ((struct fsl_spi_match_data
*)match
->data
)->type
;
86 static void fsl_spi_change_mode(struct spi_device
*spi
)
88 struct mpc8xxx_spi
*mspi
= spi_master_get_devdata(spi
->master
);
89 struct spi_mpc8xxx_cs
*cs
= spi
->controller_state
;
90 struct fsl_spi_reg
*reg_base
= mspi
->reg_base
;
91 __be32 __iomem
*mode
= ®_base
->mode
;
94 if (cs
->hw_mode
== mpc8xxx_spi_read_reg(mode
))
97 /* Turn off IRQs locally to minimize time that SPI is disabled. */
98 local_irq_save(flags
);
100 /* Turn off SPI unit prior changing mode */
101 mpc8xxx_spi_write_reg(mode
, cs
->hw_mode
& ~SPMODE_ENABLE
);
103 /* When in CPM mode, we need to reinit tx and rx. */
104 if (mspi
->flags
& SPI_CPM_MODE
) {
105 fsl_spi_cpm_reinit_txrx(mspi
);
107 mpc8xxx_spi_write_reg(mode
, cs
->hw_mode
);
108 local_irq_restore(flags
);
111 static void fsl_spi_chipselect(struct spi_device
*spi
, int value
)
113 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
114 struct fsl_spi_platform_data
*pdata
;
115 bool pol
= spi
->mode
& SPI_CS_HIGH
;
116 struct spi_mpc8xxx_cs
*cs
= spi
->controller_state
;
118 pdata
= spi
->dev
.parent
->parent
->platform_data
;
120 if (value
== BITBANG_CS_INACTIVE
) {
121 if (pdata
->cs_control
)
122 pdata
->cs_control(spi
, !pol
);
125 if (value
== BITBANG_CS_ACTIVE
) {
126 mpc8xxx_spi
->rx_shift
= cs
->rx_shift
;
127 mpc8xxx_spi
->tx_shift
= cs
->tx_shift
;
128 mpc8xxx_spi
->get_rx
= cs
->get_rx
;
129 mpc8xxx_spi
->get_tx
= cs
->get_tx
;
131 fsl_spi_change_mode(spi
);
133 if (pdata
->cs_control
)
134 pdata
->cs_control(spi
, pol
);
138 static void fsl_spi_qe_cpu_set_shifts(u32
*rx_shift
, u32
*tx_shift
,
139 int bits_per_word
, int msb_first
)
144 if (bits_per_word
<= 8) {
147 } else if (bits_per_word
<= 16) {
152 if (bits_per_word
<= 8)
157 static void fsl_spi_grlib_set_shifts(u32
*rx_shift
, u32
*tx_shift
,
158 int bits_per_word
, int msb_first
)
162 if (bits_per_word
<= 16) {
164 *rx_shift
= 16; /* LSB in bit 16 */
165 *tx_shift
= 32 - bits_per_word
; /* MSB in bit 31 */
167 *rx_shift
= 16 - bits_per_word
; /* MSB in bit 15 */
172 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs
*cs
,
173 struct spi_device
*spi
,
174 struct mpc8xxx_spi
*mpc8xxx_spi
,
179 if (bits_per_word
<= 8) {
180 cs
->get_rx
= mpc8xxx_spi_rx_buf_u8
;
181 cs
->get_tx
= mpc8xxx_spi_tx_buf_u8
;
182 } else if (bits_per_word
<= 16) {
183 cs
->get_rx
= mpc8xxx_spi_rx_buf_u16
;
184 cs
->get_tx
= mpc8xxx_spi_tx_buf_u16
;
185 } else if (bits_per_word
<= 32) {
186 cs
->get_rx
= mpc8xxx_spi_rx_buf_u32
;
187 cs
->get_tx
= mpc8xxx_spi_tx_buf_u32
;
191 if (mpc8xxx_spi
->set_shifts
)
192 mpc8xxx_spi
->set_shifts(&cs
->rx_shift
, &cs
->tx_shift
,
194 !(spi
->mode
& SPI_LSB_FIRST
));
196 mpc8xxx_spi
->rx_shift
= cs
->rx_shift
;
197 mpc8xxx_spi
->tx_shift
= cs
->tx_shift
;
198 mpc8xxx_spi
->get_rx
= cs
->get_rx
;
199 mpc8xxx_spi
->get_tx
= cs
->get_tx
;
201 return bits_per_word
;
204 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs
*cs
,
205 struct spi_device
*spi
,
208 /* QE uses Little Endian for words > 8
209 * so transform all words > 8 into 8 bits
210 * Unfortnatly that doesn't work for LSB so
211 * reject these for now */
212 /* Note: 32 bits word, LSB works iff
213 * tfcr/rfcr is set to CPMFCR_GBL */
214 if (spi
->mode
& SPI_LSB_FIRST
&&
217 if (bits_per_word
> 8)
218 return 8; /* pretend its 8 bits */
219 return bits_per_word
;
222 static int fsl_spi_setup_transfer(struct spi_device
*spi
,
223 struct spi_transfer
*t
)
225 struct mpc8xxx_spi
*mpc8xxx_spi
;
226 int bits_per_word
= 0;
229 struct spi_mpc8xxx_cs
*cs
= spi
->controller_state
;
231 mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
234 bits_per_word
= t
->bits_per_word
;
238 /* spi_transfer level calls that work per-word */
240 bits_per_word
= spi
->bits_per_word
;
243 hz
= spi
->max_speed_hz
;
245 if (!(mpc8xxx_spi
->flags
& SPI_CPM_MODE
))
246 bits_per_word
= mspi_apply_cpu_mode_quirks(cs
, spi
,
249 else if (mpc8xxx_spi
->flags
& SPI_QE
)
250 bits_per_word
= mspi_apply_qe_mode_quirks(cs
, spi
,
253 if (bits_per_word
< 0)
254 return bits_per_word
;
256 if (bits_per_word
== 32)
259 bits_per_word
= bits_per_word
- 1;
261 /* mask out bits we are going to set */
262 cs
->hw_mode
&= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
265 cs
->hw_mode
|= SPMODE_LEN(bits_per_word
);
267 if ((mpc8xxx_spi
->spibrg
/ hz
) > 64) {
268 cs
->hw_mode
|= SPMODE_DIV16
;
269 pm
= (mpc8xxx_spi
->spibrg
- 1) / (hz
* 64) + 1;
271 WARN_ONCE(pm
> 16, "%s: Requested speed is too low: %d Hz. "
272 "Will use %d Hz instead.\n", dev_name(&spi
->dev
),
273 hz
, mpc8xxx_spi
->spibrg
/ 1024);
277 pm
= (mpc8xxx_spi
->spibrg
- 1) / (hz
* 4) + 1;
282 cs
->hw_mode
|= SPMODE_PM(pm
);
284 fsl_spi_change_mode(spi
);
288 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi
*mspi
,
289 struct spi_transfer
*t
, unsigned int len
)
292 struct fsl_spi_reg
*reg_base
= mspi
->reg_base
;
297 mpc8xxx_spi_write_reg(®_base
->mask
, SPIM_NE
);
300 word
= mspi
->get_tx(mspi
);
301 mpc8xxx_spi_write_reg(®_base
->transmit
, word
);
306 static int fsl_spi_bufs(struct spi_device
*spi
, struct spi_transfer
*t
,
309 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
310 struct fsl_spi_reg
*reg_base
;
311 unsigned int len
= t
->len
;
315 reg_base
= mpc8xxx_spi
->reg_base
;
316 bits_per_word
= spi
->bits_per_word
;
317 if (t
->bits_per_word
)
318 bits_per_word
= t
->bits_per_word
;
320 if (bits_per_word
> 8) {
321 /* invalid length? */
326 if (bits_per_word
> 16) {
327 /* invalid length? */
333 mpc8xxx_spi
->tx
= t
->tx_buf
;
334 mpc8xxx_spi
->rx
= t
->rx_buf
;
336 reinit_completion(&mpc8xxx_spi
->done
);
338 if (mpc8xxx_spi
->flags
& SPI_CPM_MODE
)
339 ret
= fsl_spi_cpm_bufs(mpc8xxx_spi
, t
, is_dma_mapped
);
341 ret
= fsl_spi_cpu_bufs(mpc8xxx_spi
, t
, len
);
345 wait_for_completion(&mpc8xxx_spi
->done
);
347 /* disable rx ints */
348 mpc8xxx_spi_write_reg(®_base
->mask
, 0);
350 if (mpc8xxx_spi
->flags
& SPI_CPM_MODE
)
351 fsl_spi_cpm_bufs_complete(mpc8xxx_spi
);
353 return mpc8xxx_spi
->count
;
356 static void fsl_spi_do_one_msg(struct spi_message
*m
)
358 struct spi_device
*spi
= m
->spi
;
359 struct spi_transfer
*t
, *first
;
360 unsigned int cs_change
;
361 const int nsecs
= 50;
364 /* Don't allow changes if CS is active */
365 first
= list_first_entry(&m
->transfers
, struct spi_transfer
,
367 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
368 if ((first
->bits_per_word
!= t
->bits_per_word
) ||
369 (first
->speed_hz
!= t
->speed_hz
)) {
372 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
379 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
380 if (t
->bits_per_word
|| t
->speed_hz
) {
382 status
= fsl_spi_setup_transfer(spi
, t
);
388 fsl_spi_chipselect(spi
, BITBANG_CS_ACTIVE
);
391 cs_change
= t
->cs_change
;
393 status
= fsl_spi_bufs(spi
, t
, m
->is_dma_mapped
);
398 m
->actual_length
+= t
->len
;
401 udelay(t
->delay_usecs
);
405 fsl_spi_chipselect(spi
, BITBANG_CS_INACTIVE
);
412 m
->complete(m
->context
);
414 if (status
|| !cs_change
) {
416 fsl_spi_chipselect(spi
, BITBANG_CS_INACTIVE
);
419 fsl_spi_setup_transfer(spi
, NULL
);
422 static int fsl_spi_setup(struct spi_device
*spi
)
424 struct mpc8xxx_spi
*mpc8xxx_spi
;
425 struct fsl_spi_reg
*reg_base
;
428 struct spi_mpc8xxx_cs
*cs
= spi
->controller_state
;
430 if (!spi
->max_speed_hz
)
434 cs
= devm_kzalloc(&spi
->dev
, sizeof(*cs
), GFP_KERNEL
);
437 spi
->controller_state
= cs
;
439 mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
441 reg_base
= mpc8xxx_spi
->reg_base
;
443 hw_mode
= cs
->hw_mode
; /* Save original settings */
444 cs
->hw_mode
= mpc8xxx_spi_read_reg(®_base
->mode
);
445 /* mask out bits we are going to set */
446 cs
->hw_mode
&= ~(SPMODE_CP_BEGIN_EDGECLK
| SPMODE_CI_INACTIVEHIGH
447 | SPMODE_REV
| SPMODE_LOOP
);
449 if (spi
->mode
& SPI_CPHA
)
450 cs
->hw_mode
|= SPMODE_CP_BEGIN_EDGECLK
;
451 if (spi
->mode
& SPI_CPOL
)
452 cs
->hw_mode
|= SPMODE_CI_INACTIVEHIGH
;
453 if (!(spi
->mode
& SPI_LSB_FIRST
))
454 cs
->hw_mode
|= SPMODE_REV
;
455 if (spi
->mode
& SPI_LOOP
)
456 cs
->hw_mode
|= SPMODE_LOOP
;
458 retval
= fsl_spi_setup_transfer(spi
, NULL
);
460 cs
->hw_mode
= hw_mode
; /* Restore settings */
464 if (mpc8xxx_spi
->type
== TYPE_GRLIB
) {
465 if (gpio_is_valid(spi
->cs_gpio
)) {
468 retval
= gpio_request(spi
->cs_gpio
,
469 dev_name(&spi
->dev
));
473 desel
= !(spi
->mode
& SPI_CS_HIGH
);
474 retval
= gpio_direction_output(spi
->cs_gpio
, desel
);
476 gpio_free(spi
->cs_gpio
);
479 } else if (spi
->cs_gpio
!= -ENOENT
) {
480 if (spi
->cs_gpio
< 0)
484 /* When spi->cs_gpio == -ENOENT, a hole in the phandle list
485 * indicates to use native chipselect if present, or allow for
486 * an always selected chip
490 /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
491 fsl_spi_chipselect(spi
, BITBANG_CS_INACTIVE
);
496 static void fsl_spi_cleanup(struct spi_device
*spi
)
498 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
500 if (mpc8xxx_spi
->type
== TYPE_GRLIB
&& gpio_is_valid(spi
->cs_gpio
))
501 gpio_free(spi
->cs_gpio
);
504 static void fsl_spi_cpu_irq(struct mpc8xxx_spi
*mspi
, u32 events
)
506 struct fsl_spi_reg
*reg_base
= mspi
->reg_base
;
508 /* We need handle RX first */
509 if (events
& SPIE_NE
) {
510 u32 rx_data
= mpc8xxx_spi_read_reg(®_base
->receive
);
513 mspi
->get_rx(rx_data
, mspi
);
516 if ((events
& SPIE_NF
) == 0)
517 /* spin until TX is done */
519 mpc8xxx_spi_read_reg(®_base
->event
)) &
523 /* Clear the events */
524 mpc8xxx_spi_write_reg(®_base
->event
, events
);
528 u32 word
= mspi
->get_tx(mspi
);
530 mpc8xxx_spi_write_reg(®_base
->transmit
, word
);
532 complete(&mspi
->done
);
536 static irqreturn_t
fsl_spi_irq(s32 irq
, void *context_data
)
538 struct mpc8xxx_spi
*mspi
= context_data
;
539 irqreturn_t ret
= IRQ_NONE
;
541 struct fsl_spi_reg
*reg_base
= mspi
->reg_base
;
543 /* Get interrupt events(tx/rx) */
544 events
= mpc8xxx_spi_read_reg(®_base
->event
);
548 dev_dbg(mspi
->dev
, "%s: events %x\n", __func__
, events
);
550 if (mspi
->flags
& SPI_CPM_MODE
)
551 fsl_spi_cpm_irq(mspi
, events
);
553 fsl_spi_cpu_irq(mspi
, events
);
558 static void fsl_spi_remove(struct mpc8xxx_spi
*mspi
)
560 iounmap(mspi
->reg_base
);
561 fsl_spi_cpm_free(mspi
);
564 static void fsl_spi_grlib_cs_control(struct spi_device
*spi
, bool on
)
566 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(spi
->master
);
567 struct fsl_spi_reg
*reg_base
= mpc8xxx_spi
->reg_base
;
569 u16 cs
= spi
->chip_select
;
571 if (gpio_is_valid(spi
->cs_gpio
)) {
572 gpio_set_value(spi
->cs_gpio
, on
);
573 } else if (cs
< mpc8xxx_spi
->native_chipselects
) {
574 slvsel
= mpc8xxx_spi_read_reg(®_base
->slvsel
);
575 slvsel
= on
? (slvsel
| (1 << cs
)) : (slvsel
& ~(1 << cs
));
576 mpc8xxx_spi_write_reg(®_base
->slvsel
, slvsel
);
580 static void fsl_spi_grlib_probe(struct device
*dev
)
582 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
583 struct spi_master
*master
= dev_get_drvdata(dev
);
584 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(master
);
585 struct fsl_spi_reg
*reg_base
= mpc8xxx_spi
->reg_base
;
589 capabilities
= mpc8xxx_spi_read_reg(®_base
->cap
);
591 mpc8xxx_spi
->set_shifts
= fsl_spi_grlib_set_shifts
;
592 mbits
= SPCAP_MAXWLEN(capabilities
);
594 mpc8xxx_spi
->max_bits_per_word
= mbits
+ 1;
596 mpc8xxx_spi
->native_chipselects
= 0;
597 if (SPCAP_SSEN(capabilities
)) {
598 mpc8xxx_spi
->native_chipselects
= SPCAP_SSSZ(capabilities
);
599 mpc8xxx_spi_write_reg(®_base
->slvsel
, 0xffffffff);
601 master
->num_chipselect
= mpc8xxx_spi
->native_chipselects
;
602 pdata
->cs_control
= fsl_spi_grlib_cs_control
;
605 static struct spi_master
* fsl_spi_probe(struct device
*dev
,
606 struct resource
*mem
, unsigned int irq
)
608 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
609 struct spi_master
*master
;
610 struct mpc8xxx_spi
*mpc8xxx_spi
;
611 struct fsl_spi_reg
*reg_base
;
615 master
= spi_alloc_master(dev
, sizeof(struct mpc8xxx_spi
));
616 if (master
== NULL
) {
621 dev_set_drvdata(dev
, master
);
623 ret
= mpc8xxx_spi_probe(dev
, mem
, irq
);
627 master
->setup
= fsl_spi_setup
;
628 master
->cleanup
= fsl_spi_cleanup
;
630 mpc8xxx_spi
= spi_master_get_devdata(master
);
631 mpc8xxx_spi
->spi_do_one_msg
= fsl_spi_do_one_msg
;
632 mpc8xxx_spi
->spi_remove
= fsl_spi_remove
;
633 mpc8xxx_spi
->max_bits_per_word
= 32;
634 mpc8xxx_spi
->type
= fsl_spi_get_type(dev
);
636 ret
= fsl_spi_cpm_init(mpc8xxx_spi
);
640 mpc8xxx_spi
->reg_base
= ioremap(mem
->start
, resource_size(mem
));
641 if (mpc8xxx_spi
->reg_base
== NULL
) {
646 if (mpc8xxx_spi
->type
== TYPE_GRLIB
)
647 fsl_spi_grlib_probe(dev
);
649 master
->bits_per_word_mask
=
650 (SPI_BPW_RANGE_MASK(4, 16) | SPI_BPW_MASK(32)) &
651 SPI_BPW_RANGE_MASK(1, mpc8xxx_spi
->max_bits_per_word
);
653 if (mpc8xxx_spi
->flags
& SPI_QE_CPU_MODE
)
654 mpc8xxx_spi
->set_shifts
= fsl_spi_qe_cpu_set_shifts
;
656 if (mpc8xxx_spi
->set_shifts
)
657 /* 8 bits per word and MSB first */
658 mpc8xxx_spi
->set_shifts(&mpc8xxx_spi
->rx_shift
,
659 &mpc8xxx_spi
->tx_shift
, 8, 1);
661 /* Register for SPI Interrupt */
662 ret
= request_irq(mpc8xxx_spi
->irq
, fsl_spi_irq
,
663 0, "fsl_spi", mpc8xxx_spi
);
668 reg_base
= mpc8xxx_spi
->reg_base
;
670 /* SPI controller initializations */
671 mpc8xxx_spi_write_reg(®_base
->mode
, 0);
672 mpc8xxx_spi_write_reg(®_base
->mask
, 0);
673 mpc8xxx_spi_write_reg(®_base
->command
, 0);
674 mpc8xxx_spi_write_reg(®_base
->event
, 0xffffffff);
676 /* Enable SPI interface */
677 regval
= pdata
->initial_spmode
| SPMODE_INIT_VAL
| SPMODE_ENABLE
;
678 if (mpc8xxx_spi
->max_bits_per_word
< 8) {
679 regval
&= ~SPMODE_LEN(0xF);
680 regval
|= SPMODE_LEN(mpc8xxx_spi
->max_bits_per_word
- 1);
682 if (mpc8xxx_spi
->flags
& SPI_QE_CPU_MODE
)
685 mpc8xxx_spi_write_reg(®_base
->mode
, regval
);
687 ret
= spi_register_master(master
);
691 dev_info(dev
, "at 0x%p (irq = %d), %s mode\n", reg_base
,
692 mpc8xxx_spi
->irq
, mpc8xxx_spi_strmode(mpc8xxx_spi
->flags
));
697 free_irq(mpc8xxx_spi
->irq
, mpc8xxx_spi
);
699 iounmap(mpc8xxx_spi
->reg_base
);
701 fsl_spi_cpm_free(mpc8xxx_spi
);
704 spi_master_put(master
);
709 static void fsl_spi_cs_control(struct spi_device
*spi
, bool on
)
711 struct device
*dev
= spi
->dev
.parent
->parent
;
712 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
713 struct mpc8xxx_spi_probe_info
*pinfo
= to_of_pinfo(pdata
);
714 u16 cs
= spi
->chip_select
;
715 int gpio
= pinfo
->gpios
[cs
];
716 bool alow
= pinfo
->alow_flags
[cs
];
718 gpio_set_value(gpio
, on
^ alow
);
721 static int of_fsl_spi_get_chipselects(struct device
*dev
)
723 struct device_node
*np
= dev
->of_node
;
724 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
725 struct mpc8xxx_spi_probe_info
*pinfo
= to_of_pinfo(pdata
);
730 ngpios
= of_gpio_count(np
);
733 * SPI w/o chip-select line. One SPI device is still permitted
736 pdata
->max_chipselect
= 1;
740 pinfo
->gpios
= kmalloc(ngpios
* sizeof(*pinfo
->gpios
), GFP_KERNEL
);
743 memset(pinfo
->gpios
, -1, ngpios
* sizeof(*pinfo
->gpios
));
745 pinfo
->alow_flags
= kzalloc(ngpios
* sizeof(*pinfo
->alow_flags
),
747 if (!pinfo
->alow_flags
) {
749 goto err_alloc_flags
;
752 for (; i
< ngpios
; i
++) {
754 enum of_gpio_flags flags
;
756 gpio
= of_get_gpio_flags(np
, i
, &flags
);
757 if (!gpio_is_valid(gpio
)) {
758 dev_err(dev
, "invalid gpio #%d: %d\n", i
, gpio
);
763 ret
= gpio_request(gpio
, dev_name(dev
));
765 dev_err(dev
, "can't request gpio #%d: %d\n", i
, ret
);
769 pinfo
->gpios
[i
] = gpio
;
770 pinfo
->alow_flags
[i
] = flags
& OF_GPIO_ACTIVE_LOW
;
772 ret
= gpio_direction_output(pinfo
->gpios
[i
],
773 pinfo
->alow_flags
[i
]);
775 dev_err(dev
, "can't set output direction for gpio "
776 "#%d: %d\n", i
, ret
);
781 pdata
->max_chipselect
= ngpios
;
782 pdata
->cs_control
= fsl_spi_cs_control
;
788 if (gpio_is_valid(pinfo
->gpios
[i
]))
789 gpio_free(pinfo
->gpios
[i
]);
793 kfree(pinfo
->alow_flags
);
794 pinfo
->alow_flags
= NULL
;
801 static int of_fsl_spi_free_chipselects(struct device
*dev
)
803 struct fsl_spi_platform_data
*pdata
= dev_get_platdata(dev
);
804 struct mpc8xxx_spi_probe_info
*pinfo
= to_of_pinfo(pdata
);
810 for (i
= 0; i
< pdata
->max_chipselect
; i
++) {
811 if (gpio_is_valid(pinfo
->gpios
[i
]))
812 gpio_free(pinfo
->gpios
[i
]);
816 kfree(pinfo
->alow_flags
);
820 static int of_fsl_spi_probe(struct platform_device
*ofdev
)
822 struct device
*dev
= &ofdev
->dev
;
823 struct device_node
*np
= ofdev
->dev
.of_node
;
824 struct spi_master
*master
;
829 ret
= of_mpc8xxx_spi_probe(ofdev
);
833 type
= fsl_spi_get_type(&ofdev
->dev
);
834 if (type
== TYPE_FSL
) {
835 ret
= of_fsl_spi_get_chipselects(dev
);
840 ret
= of_address_to_resource(np
, 0, &mem
);
844 irq
= irq_of_parse_and_map(np
, 0);
850 master
= fsl_spi_probe(dev
, &mem
, irq
);
851 if (IS_ERR(master
)) {
852 ret
= PTR_ERR(master
);
859 if (type
== TYPE_FSL
)
860 of_fsl_spi_free_chipselects(dev
);
864 static int of_fsl_spi_remove(struct platform_device
*ofdev
)
866 struct spi_master
*master
= platform_get_drvdata(ofdev
);
867 struct mpc8xxx_spi
*mpc8xxx_spi
= spi_master_get_devdata(master
);
870 ret
= mpc8xxx_spi_remove(&ofdev
->dev
);
873 if (mpc8xxx_spi
->type
== TYPE_FSL
)
874 of_fsl_spi_free_chipselects(&ofdev
->dev
);
878 static struct platform_driver of_fsl_spi_driver
= {
881 .owner
= THIS_MODULE
,
882 .of_match_table
= of_fsl_spi_match
,
884 .probe
= of_fsl_spi_probe
,
885 .remove
= of_fsl_spi_remove
,
888 #ifdef CONFIG_MPC832x_RDB
891 * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
892 * only. The driver should go away soon, since newer MPC8323E-RDB's device
893 * tree can work with OpenFirmware driver. But for now we support old trees
896 static int plat_mpc8xxx_spi_probe(struct platform_device
*pdev
)
898 struct resource
*mem
;
900 struct spi_master
*master
;
902 if (!dev_get_platdata(&pdev
->dev
))
905 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
909 irq
= platform_get_irq(pdev
, 0);
913 master
= fsl_spi_probe(&pdev
->dev
, mem
, irq
);
914 return PTR_ERR_OR_ZERO(master
);
917 static int plat_mpc8xxx_spi_remove(struct platform_device
*pdev
)
919 return mpc8xxx_spi_remove(&pdev
->dev
);
922 MODULE_ALIAS("platform:mpc8xxx_spi");
923 static struct platform_driver mpc8xxx_spi_driver
= {
924 .probe
= plat_mpc8xxx_spi_probe
,
925 .remove
= plat_mpc8xxx_spi_remove
,
927 .name
= "mpc8xxx_spi",
928 .owner
= THIS_MODULE
,
932 static bool legacy_driver_failed
;
934 static void __init
legacy_driver_register(void)
936 legacy_driver_failed
= platform_driver_register(&mpc8xxx_spi_driver
);
939 static void __exit
legacy_driver_unregister(void)
941 if (legacy_driver_failed
)
943 platform_driver_unregister(&mpc8xxx_spi_driver
);
946 static void __init
legacy_driver_register(void) {}
947 static void __exit
legacy_driver_unregister(void) {}
948 #endif /* CONFIG_MPC832x_RDB */
950 static int __init
fsl_spi_init(void)
952 legacy_driver_register();
953 return platform_driver_register(&of_fsl_spi_driver
);
955 module_init(fsl_spi_init
);
957 static void __exit
fsl_spi_exit(void)
959 platform_driver_unregister(&of_fsl_spi_driver
);
960 legacy_driver_unregister();
962 module_exit(fsl_spi_exit
);
964 MODULE_AUTHOR("Kumar Gala");
965 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
966 MODULE_LICENSE("GPL");