drivers/spi/spi-fsl-spi.c

   1 /*
   2  * Freescale SPI controller driver.
   3  *
   4  * Maintainer: Kumar Gala
   5  *
   6  * Copyright (C) 2006 Polycom, Inc.
   7  * Copyright 2010 Freescale Semiconductor, Inc.
   8  *
   9  * CPM SPI and QE buffer descriptors mode support:
  10  * Copyright (c) 2009  MontaVista Software, Inc.
  11  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18 #include <linux/module.h>
  19 #include <linux/types.h>
  20 #include <linux/kernel.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/delay.h>
  23 #include <linux/irq.h>
  24 #include <linux/spi/spi.h>
  25 #include <linux/spi/spi_bitbang.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/fsl_devices.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/mm.h>
  30 #include <linux/mutex.h>
  31 #include <linux/of.h>
  32 #include <linux/of_platform.h>
  33 #include <linux/of_address.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/gpio.h>
  36 #include <linux/of_gpio.h>
  37
  38 #include "spi-fsl-lib.h"
  39 #include "spi-fsl-cpm.h"
  40 #include "spi-fsl-spi.h"
  41
  42 static void fsl_spi_change_mode(struct spi_device *spi)
  43 {
  44         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  45         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  46         struct fsl_spi_reg *reg_base = mspi->reg_base;
  47         __be32 __iomem *mode = &reg_base->mode;
  48         unsigned long flags;
  49
  50         if (cs->hw_mode == mpc8xxx_spi_read_reg(mode))
  51                 return;
  52
  53         /* Turn off IRQs locally to minimize time that SPI is disabled. */
  54         local_irq_save(flags);
  55
  56         /* Turn off SPI unit prior changing mode */
  57         mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE);
  58
  59         /* When in CPM mode, we need to reinit tx and rx. */
  60         if (mspi->flags & SPI_CPM_MODE) {
  61                 fsl_spi_cpm_reinit_txrx(mspi);
  62         }
  63         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
  64         local_irq_restore(flags);
  65 }
  66
  67 static void fsl_spi_chipselect(struct spi_device *spi, int value)
  68 {
  69         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
  70         struct fsl_spi_platform_data *pdata;
  71         bool pol = spi->mode & SPI_CS_HIGH;
  72         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
  73
  74         pdata = spi->dev.parent->parent->platform_data;
  75
  76         if (value == BITBANG_CS_INACTIVE) {
  77                 if (pdata->cs_control)
  78                         pdata->cs_control(spi, !pol);
  79         }
  80
  81         if (value == BITBANG_CS_ACTIVE) {
  82                 mpc8xxx_spi->rx_shift = cs->rx_shift;
  83                 mpc8xxx_spi->tx_shift = cs->tx_shift;
  84                 mpc8xxx_spi->get_rx = cs->get_rx;
  85                 mpc8xxx_spi->get_tx = cs->get_tx;
  86
  87                 fsl_spi_change_mode(spi);
  88
  89                 if (pdata->cs_control)
  90                         pdata->cs_control(spi, pol);
  91         }
  92 }
  93
  94 static void fsl_spi_qe_cpu_set_shifts(u32 *rx_shift, u32 *tx_shift,
  95                                       int bits_per_word, int msb_first)
  96 {
  97         *rx_shift = 0;
  98         *tx_shift = 0;
  99         if (msb_first) {
 100                 if (bits_per_word <= 8) {
 101                         *rx_shift = 16;
 102                         *tx_shift = 24;
 103                 } else if (bits_per_word <= 16) {
 104                         *rx_shift = 16;
 105                         *tx_shift = 16;
 106                 }
 107         } else {
 108                 if (bits_per_word <= 8)
 109                         *rx_shift = 8;
 110         }
 111 }
 112
 113 static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs,
 114                                 struct spi_device *spi,
 115                                 struct mpc8xxx_spi *mpc8xxx_spi,
 116                                 int bits_per_word)
 117 {
 118         cs->rx_shift = 0;
 119         cs->tx_shift = 0;
 120         if (bits_per_word <= 8) {
 121                 cs->get_rx = mpc8xxx_spi_rx_buf_u8;
 122                 cs->get_tx = mpc8xxx_spi_tx_buf_u8;
 123         } else if (bits_per_word <= 16) {
 124                 cs->get_rx = mpc8xxx_spi_rx_buf_u16;
 125                 cs->get_tx = mpc8xxx_spi_tx_buf_u16;
 126         } else if (bits_per_word <= 32) {
 127                 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 128                 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 129         } else
 130                 return -EINVAL;
 131
 132         if (mpc8xxx_spi->set_shifts)
 133                 mpc8xxx_spi->set_shifts(&cs->rx_shift, &cs->tx_shift,
 134                                         bits_per_word,
 135                                         !(spi->mode & SPI_LSB_FIRST));
 136
 137         mpc8xxx_spi->rx_shift = cs->rx_shift;
 138         mpc8xxx_spi->tx_shift = cs->tx_shift;
 139         mpc8xxx_spi->get_rx = cs->get_rx;
 140         mpc8xxx_spi->get_tx = cs->get_tx;
 141
 142         return bits_per_word;
 143 }
 144
 145 static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs,
 146                                 struct spi_device *spi,
 147                                 int bits_per_word)
 148 {
 149         /* QE uses Little Endian for words > 8
 150          * so transform all words > 8 into 8 bits
 151          * Unfortnatly that doesn't work for LSB so
 152          * reject these for now */
 153         /* Note: 32 bits word, LSB works iff
 154          * tfcr/rfcr is set to CPMFCR_GBL */
 155         if (spi->mode & SPI_LSB_FIRST &&
 156             bits_per_word > 8)
 157                 return -EINVAL;
 158         if (bits_per_word > 8)
 159                 return 8; /* pretend its 8 bits */
 160         return bits_per_word;
 161 }
 162
 163 static int fsl_spi_setup_transfer(struct spi_device *spi,
 164                                         struct spi_transfer *t)
 165 {
 166         struct mpc8xxx_spi *mpc8xxx_spi;
 167         int bits_per_word = 0;
 168         u8 pm;
 169         u32 hz = 0;
 170         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 171
 172         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 173
 174         if (t) {
 175                 bits_per_word = t->bits_per_word;
 176                 hz = t->speed_hz;
 177         }
 178
 179         /* spi_transfer level calls that work per-word */
 180         if (!bits_per_word)
 181                 bits_per_word = spi->bits_per_word;
 182
 183         /* Make sure its a bit width we support [4..16, 32] */
 184         if ((bits_per_word < 4)
 185             || ((bits_per_word > 16) && (bits_per_word != 32)))
 186                 return -EINVAL;
 187
 188         if (!hz)
 189                 hz = spi->max_speed_hz;
 190
 191         if (!(mpc8xxx_spi->flags & SPI_CPM_MODE))
 192                 bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi,
 193                                                            mpc8xxx_spi,
 194                                                            bits_per_word);
 195         else if (mpc8xxx_spi->flags & SPI_QE)
 196                 bits_per_word = mspi_apply_qe_mode_quirks(cs, spi,
 197                                                           bits_per_word);
 198
 199         if (bits_per_word < 0)
 200                 return bits_per_word;
 201
 202         if (bits_per_word == 32)
 203                 bits_per_word = 0;
 204         else
 205                 bits_per_word = bits_per_word - 1;
 206
 207         /* mask out bits we are going to set */
 208         cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 209                                   | SPMODE_PM(0xF));
 210
 211         cs->hw_mode |= SPMODE_LEN(bits_per_word);
 212
 213         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 214                 cs->hw_mode |= SPMODE_DIV16;
 215                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1;
 216
 217                 WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. "
 218                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
 219                           hz, mpc8xxx_spi->spibrg / 1024);
 220                 if (pm > 16)
 221                         pm = 16;
 222         } else {
 223                 pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1;
 224         }
 225         if (pm)
 226                 pm--;
 227
 228         cs->hw_mode |= SPMODE_PM(pm);
 229
 230         fsl_spi_change_mode(spi);
 231         return 0;
 232 }
 233
 234 static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi,
 235                                 struct spi_transfer *t, unsigned int len)
 236 {
 237         u32 word;
 238         struct fsl_spi_reg *reg_base = mspi->reg_base;
 239
 240         mspi->count = len;
 241
 242         /* enable rx ints */
 243         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 244
 245         /* transmit word */
 246         word = mspi->get_tx(mspi);
 247         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 248
 249         return 0;
 250 }
 251
 252 static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t,
 253                             bool is_dma_mapped)
 254 {
 255         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 256         struct fsl_spi_reg *reg_base;
 257         unsigned int len = t->len;
 258         u8 bits_per_word;
 259         int ret;
 260
 261         reg_base = mpc8xxx_spi->reg_base;
 262         bits_per_word = spi->bits_per_word;
 263         if (t->bits_per_word)
 264                 bits_per_word = t->bits_per_word;
 265
 266         if (bits_per_word > 8) {
 267                 /* invalid length? */
 268                 if (len & 1)
 269                         return -EINVAL;
 270                 len /= 2;
 271         }
 272         if (bits_per_word > 16) {
 273                 /* invalid length? */
 274                 if (len & 1)
 275                         return -EINVAL;
 276                 len /= 2;
 277         }
 278
 279         mpc8xxx_spi->tx = t->tx_buf;
 280         mpc8xxx_spi->rx = t->rx_buf;
 281
 282         INIT_COMPLETION(mpc8xxx_spi->done);
 283
 284         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 285                 ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped);
 286         else
 287                 ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len);
 288         if (ret)
 289                 return ret;
 290
 291         wait_for_completion(&mpc8xxx_spi->done);
 292
 293         /* disable rx ints */
 294         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 295
 296         if (mpc8xxx_spi->flags & SPI_CPM_MODE)
 297                 fsl_spi_cpm_bufs_complete(mpc8xxx_spi);
 298
 299         return mpc8xxx_spi->count;
 300 }
 301
 302 static void fsl_spi_do_one_msg(struct spi_message *m)
 303 {
 304         struct spi_device *spi = m->spi;
 305         struct spi_transfer *t;
 306         unsigned int cs_change;
 307         const int nsecs = 50;
 308         int status;
 309
 310         cs_change = 1;
 311         status = 0;
 312         list_for_each_entry(t, &m->transfers, transfer_list) {
 313                 if (t->bits_per_word || t->speed_hz) {
 314                         /* Don't allow changes if CS is active */
 315                         status = -EINVAL;
 316
 317                         if (cs_change)
 318                                 status = fsl_spi_setup_transfer(spi, t);
 319                         if (status < 0)
 320                                 break;
 321                 }
 322
 323                 if (cs_change) {
 324                         fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 325                         ndelay(nsecs);
 326                 }
 327                 cs_change = t->cs_change;
 328                 if (t->len)
 329                         status = fsl_spi_bufs(spi, t, m->is_dma_mapped);
 330                 if (status) {
 331                         status = -EMSGSIZE;
 332                         break;
 333                 }
 334                 m->actual_length += t->len;
 335
 336                 if (t->delay_usecs)
 337                         udelay(t->delay_usecs);
 338
 339                 if (cs_change) {
 340                         ndelay(nsecs);
 341                         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 342                         ndelay(nsecs);
 343                 }
 344         }
 345
 346         m->status = status;
 347         m->complete(m->context);
 348
 349         if (status || !cs_change) {
 350                 ndelay(nsecs);
 351                 fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 352         }
 353
 354         fsl_spi_setup_transfer(spi, NULL);
 355 }
 356
 357 static int fsl_spi_setup(struct spi_device *spi)
 358 {
 359         struct mpc8xxx_spi *mpc8xxx_spi;
 360         struct fsl_spi_reg *reg_base;
 361         int retval;
 362         u32 hw_mode;
 363         struct spi_mpc8xxx_cs   *cs = spi->controller_state;
 364
 365         if (!spi->max_speed_hz)
 366                 return -EINVAL;
 367
 368         if (!cs) {
 369                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 370                 if (!cs)
 371                         return -ENOMEM;
 372                 spi->controller_state = cs;
 373         }
 374         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 375
 376         reg_base = mpc8xxx_spi->reg_base;
 377
 378         hw_mode = cs->hw_mode; /* Save original settings */
 379         cs->hw_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 380         /* mask out bits we are going to set */
 381         cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 382                          | SPMODE_REV | SPMODE_LOOP);
 383
 384         if (spi->mode & SPI_CPHA)
 385                 cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 386         if (spi->mode & SPI_CPOL)
 387                 cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 388         if (!(spi->mode & SPI_LSB_FIRST))
 389                 cs->hw_mode |= SPMODE_REV;
 390         if (spi->mode & SPI_LOOP)
 391                 cs->hw_mode |= SPMODE_LOOP;
 392
 393         retval = fsl_spi_setup_transfer(spi, NULL);
 394         if (retval < 0) {
 395                 cs->hw_mode = hw_mode; /* Restore settings */
 396                 return retval;
 397         }
 398
 399         /* Initialize chipselect - might be active for SPI_CS_HIGH mode */
 400         fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 401
 402         return 0;
 403 }
 404
 405 static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 406 {
 407         struct fsl_spi_reg *reg_base = mspi->reg_base;
 408
 409         /* We need handle RX first */
 410         if (events & SPIE_NE) {
 411                 u32 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 412
 413                 if (mspi->rx)
 414                         mspi->get_rx(rx_data, mspi);
 415         }
 416
 417         if ((events & SPIE_NF) == 0)
 418                 /* spin until TX is done */
 419                 while (((events =
 420                         mpc8xxx_spi_read_reg(&reg_base->event)) &
 421                                                 SPIE_NF) == 0)
 422                         cpu_relax();
 423
 424         /* Clear the events */
 425         mpc8xxx_spi_write_reg(&reg_base->event, events);
 426
 427         mspi->count -= 1;
 428         if (mspi->count) {
 429                 u32 word = mspi->get_tx(mspi);
 430
 431                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 432         } else {
 433                 complete(&mspi->done);
 434         }
 435 }
 436
 437 static irqreturn_t fsl_spi_irq(s32 irq, void *context_data)
 438 {
 439         struct mpc8xxx_spi *mspi = context_data;
 440         irqreturn_t ret = IRQ_NONE;
 441         u32 events;
 442         struct fsl_spi_reg *reg_base = mspi->reg_base;
 443
 444         /* Get interrupt events(tx/rx) */
 445         events = mpc8xxx_spi_read_reg(&reg_base->event);
 446         if (events)
 447                 ret = IRQ_HANDLED;
 448
 449         dev_dbg(mspi->dev, "%s: events %x\n", __func__, events);
 450
 451         if (mspi->flags & SPI_CPM_MODE)
 452                 fsl_spi_cpm_irq(mspi, events);
 453         else
 454                 fsl_spi_cpu_irq(mspi, events);
 455
 456         return ret;
 457 }
 458
 459 static void fsl_spi_remove(struct mpc8xxx_spi *mspi)
 460 {
 461         iounmap(mspi->reg_base);
 462         fsl_spi_cpm_free(mspi);
 463 }
 464
 465 static struct spi_master * fsl_spi_probe(struct device *dev,
 466                 struct resource *mem, unsigned int irq)
 467 {
 468         struct fsl_spi_platform_data *pdata = dev->platform_data;
 469         struct spi_master *master;
 470         struct mpc8xxx_spi *mpc8xxx_spi;
 471         struct fsl_spi_reg *reg_base;
 472         u32 regval;
 473         int ret = 0;
 474
 475         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 476         if (master == NULL) {
 477                 ret = -ENOMEM;
 478                 goto err;
 479         }
 480
 481         dev_set_drvdata(dev, master);
 482
 483         ret = mpc8xxx_spi_probe(dev, mem, irq);
 484         if (ret)
 485                 goto err_probe;
 486
 487         master->setup = fsl_spi_setup;
 488
 489         mpc8xxx_spi = spi_master_get_devdata(master);
 490         mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg;
 491         mpc8xxx_spi->spi_remove = fsl_spi_remove;
 492
 493
 494         ret = fsl_spi_cpm_init(mpc8xxx_spi);
 495         if (ret)
 496                 goto err_cpm_init;
 497
 498         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 499                 mpc8xxx_spi->set_shifts = fsl_spi_qe_cpu_set_shifts;
 500
 501         if (mpc8xxx_spi->set_shifts)
 502                 /* 8 bits per word and MSB first */
 503                 mpc8xxx_spi->set_shifts(&mpc8xxx_spi->rx_shift,
 504                                         &mpc8xxx_spi->tx_shift, 8, 1);
 505
 506         mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
 507         if (mpc8xxx_spi->reg_base == NULL) {
 508                 ret = -ENOMEM;
 509                 goto err_ioremap;
 510         }
 511
 512         /* Register for SPI Interrupt */
 513         ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq,
 514                           0, "fsl_spi", mpc8xxx_spi);
 515
 516         if (ret != 0)
 517                 goto free_irq;
 518
 519         reg_base = mpc8xxx_spi->reg_base;
 520
 521         /* SPI controller initializations */
 522         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 523         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 524         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 525         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 526
 527         /* Enable SPI interface */
 528         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 529         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE)
 530                 regval |= SPMODE_OP;
 531
 532         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 533
 534         ret = spi_register_master(master);
 535         if (ret < 0)
 536                 goto unreg_master;
 537
 538         dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base,
 539                  mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags));
 540
 541         return master;
 542
 543 unreg_master:
 544         free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
 545 free_irq:
 546         iounmap(mpc8xxx_spi->reg_base);
 547 err_ioremap:
 548         fsl_spi_cpm_free(mpc8xxx_spi);
 549 err_cpm_init:
 550 err_probe:
 551         spi_master_put(master);
 552 err:
 553         return ERR_PTR(ret);
 554 }
 555
 556 static void fsl_spi_cs_control(struct spi_device *spi, bool on)
 557 {
 558         struct device *dev = spi->dev.parent->parent;
 559         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data);
 560         u16 cs = spi->chip_select;
 561         int gpio = pinfo->gpios[cs];
 562         bool alow = pinfo->alow_flags[cs];
 563
 564         gpio_set_value(gpio, on ^ alow);
 565 }
 566
 567 static int of_fsl_spi_get_chipselects(struct device *dev)
 568 {
 569         struct device_node *np = dev->of_node;
 570         struct fsl_spi_platform_data *pdata = dev->platform_data;
 571         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 572         int ngpios;
 573         int i = 0;
 574         int ret;
 575
 576         ngpios = of_gpio_count(np);
 577         if (ngpios <= 0) {
 578                 /*
 579                  * SPI w/o chip-select line. One SPI device is still permitted
 580                  * though.
 581                  */
 582                 pdata->max_chipselect = 1;
 583                 return 0;
 584         }
 585
 586         pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL);
 587         if (!pinfo->gpios)
 588                 return -ENOMEM;
 589         memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios));
 590
 591         pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags),
 592                                     GFP_KERNEL);
 593         if (!pinfo->alow_flags) {
 594                 ret = -ENOMEM;
 595                 goto err_alloc_flags;
 596         }
 597
 598         for (; i < ngpios; i++) {
 599                 int gpio;
 600                 enum of_gpio_flags flags;
 601
 602                 gpio = of_get_gpio_flags(np, i, &flags);
 603                 if (!gpio_is_valid(gpio)) {
 604                         dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
 605                         ret = gpio;
 606                         goto err_loop;
 607                 }
 608
 609                 ret = gpio_request(gpio, dev_name(dev));
 610                 if (ret) {
 611                         dev_err(dev, "can't request gpio #%d: %d\n", i, ret);
 612                         goto err_loop;
 613                 }
 614
 615                 pinfo->gpios[i] = gpio;
 616                 pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW;
 617
 618                 ret = gpio_direction_output(pinfo->gpios[i],
 619                                             pinfo->alow_flags[i]);
 620                 if (ret) {
 621                         dev_err(dev, "can't set output direction for gpio "
 622                                 "#%d: %d\n", i, ret);
 623                         goto err_loop;
 624                 }
 625         }
 626
 627         pdata->max_chipselect = ngpios;
 628         pdata->cs_control = fsl_spi_cs_control;
 629
 630         return 0;
 631
 632 err_loop:
 633         while (i >= 0) {
 634                 if (gpio_is_valid(pinfo->gpios[i]))
 635                         gpio_free(pinfo->gpios[i]);
 636                 i--;
 637         }
 638
 639         kfree(pinfo->alow_flags);
 640         pinfo->alow_flags = NULL;
 641 err_alloc_flags:
 642         kfree(pinfo->gpios);
 643         pinfo->gpios = NULL;
 644         return ret;
 645 }
 646
 647 static int of_fsl_spi_free_chipselects(struct device *dev)
 648 {
 649         struct fsl_spi_platform_data *pdata = dev->platform_data;
 650         struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata);
 651         int i;
 652
 653         if (!pinfo->gpios)
 654                 return 0;
 655
 656         for (i = 0; i < pdata->max_chipselect; i++) {
 657                 if (gpio_is_valid(pinfo->gpios[i]))
 658                         gpio_free(pinfo->gpios[i]);
 659         }
 660
 661         kfree(pinfo->gpios);
 662         kfree(pinfo->alow_flags);
 663         return 0;
 664 }
 665
 666 static int of_fsl_spi_probe(struct platform_device *ofdev)
 667 {
 668         struct device *dev = &ofdev->dev;
 669         struct device_node *np = ofdev->dev.of_node;
 670         struct spi_master *master;
 671         struct resource mem;
 672         int irq;
 673         int ret = -ENOMEM;
 674
 675         ret = of_mpc8xxx_spi_probe(ofdev);
 676         if (ret)
 677                 return ret;
 678
 679         ret = of_fsl_spi_get_chipselects(dev);
 680         if (ret)
 681                 goto err;
 682
 683         ret = of_address_to_resource(np, 0, &mem);
 684         if (ret)
 685                 goto err;
 686
 687         irq = irq_of_parse_and_map(np, 0);
 688         if (!irq) {
 689                 ret = -EINVAL;
 690                 goto err;
 691         }
 692
 693         master = fsl_spi_probe(dev, &mem, irq);
 694         if (IS_ERR(master)) {
 695                 ret = PTR_ERR(master);
 696                 goto err;
 697         }
 698
 699         return 0;
 700
 701 err:
 702         of_fsl_spi_free_chipselects(dev);
 703         return ret;
 704 }
 705
 706 static int of_fsl_spi_remove(struct platform_device *ofdev)
 707 {
 708         int ret;
 709
 710         ret = mpc8xxx_spi_remove(&ofdev->dev);
 711         if (ret)
 712                 return ret;
 713         of_fsl_spi_free_chipselects(&ofdev->dev);
 714         return 0;
 715 }
 716
 717 static const struct of_device_id of_fsl_spi_match[] = {
 718         { .compatible = "fsl,spi" },
 719         {}
 720 };
 721 MODULE_DEVICE_TABLE(of, of_fsl_spi_match);
 722
 723 static struct platform_driver of_fsl_spi_driver = {
 724         .driver = {
 725                 .name = "fsl_spi",
 726                 .owner = THIS_MODULE,
 727                 .of_match_table = of_fsl_spi_match,
 728         },
 729         .probe          = of_fsl_spi_probe,
 730         .remove         = of_fsl_spi_remove,
 731 };
 732
 733 #ifdef CONFIG_MPC832x_RDB
 734 /*
 735  * XXX XXX XXX
 736  * This is "legacy" platform driver, was used by the MPC8323E-RDB boards
 737  * only. The driver should go away soon, since newer MPC8323E-RDB's device
 738  * tree can work with OpenFirmware driver. But for now we support old trees
 739  * as well.
 740  */
 741 static int plat_mpc8xxx_spi_probe(struct platform_device *pdev)
 742 {
 743         struct resource *mem;
 744         int irq;
 745         struct spi_master *master;
 746
 747         if (!pdev->dev.platform_data)
 748                 return -EINVAL;
 749
 750         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 751         if (!mem)
 752                 return -EINVAL;
 753
 754         irq = platform_get_irq(pdev, 0);
 755         if (irq <= 0)
 756                 return -EINVAL;
 757
 758         master = fsl_spi_probe(&pdev->dev, mem, irq);
 759         return PTR_RET(master);
 760 }
 761
 762 static int plat_mpc8xxx_spi_remove(struct platform_device *pdev)
 763 {
 764         return mpc8xxx_spi_remove(&pdev->dev);
 765 }
 766
 767 MODULE_ALIAS("platform:mpc8xxx_spi");
 768 static struct platform_driver mpc8xxx_spi_driver = {
 769         .probe = plat_mpc8xxx_spi_probe,
 770         .remove = plat_mpc8xxx_spi_remove,
 771         .driver = {
 772                 .name = "mpc8xxx_spi",
 773                 .owner = THIS_MODULE,
 774         },
 775 };
 776
 777 static bool legacy_driver_failed;
 778
 779 static void __init legacy_driver_register(void)
 780 {
 781         legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver);
 782 }
 783
 784 static void __exit legacy_driver_unregister(void)
 785 {
 786         if (legacy_driver_failed)
 787                 return;
 788         platform_driver_unregister(&mpc8xxx_spi_driver);
 789 }
 790 #else
 791 static void __init legacy_driver_register(void) {}
 792 static void __exit legacy_driver_unregister(void) {}
 793 #endif /* CONFIG_MPC832x_RDB */
 794
 795 static int __init fsl_spi_init(void)
 796 {
 797         legacy_driver_register();
 798         return platform_driver_register(&of_fsl_spi_driver);
 799 }
 800 module_init(fsl_spi_init);
 801
 802 static void __exit fsl_spi_exit(void)
 803 {
 804         platform_driver_unregister(&of_fsl_spi_driver);
 805         legacy_driver_unregister();
 806 }
 807 module_exit(fsl_spi_exit);
 808
 809 MODULE_AUTHOR("Kumar Gala");
 810 MODULE_DESCRIPTION("Simple Freescale SPI Driver");
 811 MODULE_LICENSE("GPL");