drivers/spi/spi-mxs.c

   1 /*
   2  * Freescale MXS SPI master driver
   3  *
   4  * Copyright 2012 DENX Software Engineering, GmbH.
   5  * Copyright 2012 Freescale Semiconductor, Inc.
   6  * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
   7  *
   8  * Rework and transition to new API by:
   9  * Marek Vasut <marex@denx.de>
  10  *
  11  * Based on previous attempt by:
  12  * Fabio Estevam <fabio.estevam@freescale.com>
  13  *
  14  * Based on code from U-Boot bootloader by:
  15  * Marek Vasut <marex@denx.de>
  16  *
  17  * Based on spi-stmp.c, which is:
  18  * Author: Dmitry Pervushin <dimka@embeddedalley.com>
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2 of the License, or
  23  * (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  28  * GNU General Public License for more details.
  29  */
  30
  31 #include <linux/kernel.h>
  32 #include <linux/init.h>
  33 #include <linux/ioport.h>
  34 #include <linux/of.h>
  35 #include <linux/of_device.h>
  36 #include <linux/of_gpio.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/dmaengine.h>
  42 #include <linux/highmem.h>
  43 #include <linux/clk.h>
  44 #include <linux/err.h>
  45 #include <linux/completion.h>
  46 #include <linux/gpio.h>
  47 #include <linux/regulator/consumer.h>
  48 #include <linux/module.h>
  49 #include <linux/pinctrl/consumer.h>
  50 #include <linux/stmp_device.h>
  51 #include <linux/spi/spi.h>
  52 #include <linux/spi/mxs-spi.h>
  53
  54 #define DRIVER_NAME             "mxs-spi"
  55
  56 /* Use 10S timeout for very long transfers, it should suffice. */
  57 #define SSP_TIMEOUT             10000
  58
  59 #define SG_MAXLEN               0xff00
  60
  61 struct mxs_spi {
  62         struct mxs_ssp          ssp;
  63         struct completion       c;
  64 };
  65
  66 static int mxs_spi_setup_transfer(struct spi_device *dev,
  67                                 struct spi_transfer *t)
  68 {
  69         struct mxs_spi *spi = spi_master_get_devdata(dev->master);
  70         struct mxs_ssp *ssp = &spi->ssp;
  71         uint8_t bits_per_word;
  72         uint32_t hz = 0;
  73
  74         bits_per_word = dev->bits_per_word;
  75         if (t && t->bits_per_word)
  76                 bits_per_word = t->bits_per_word;
  77
  78         hz = dev->max_speed_hz;
  79         if (t && t->speed_hz)
  80                 hz = min(hz, t->speed_hz);
  81         if (hz == 0) {
  82                 dev_err(&dev->dev, "Cannot continue with zero clock\n");
  83                 return -EINVAL;
  84         }
  85
  86         mxs_ssp_set_clk_rate(ssp, hz);
  87
  88         writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) |
  89                      BF_SSP_CTRL1_WORD_LENGTH
  90                      (BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS) |
  91                      ((dev->mode & SPI_CPOL) ? BM_SSP_CTRL1_POLARITY : 0) |
  92                      ((dev->mode & SPI_CPHA) ? BM_SSP_CTRL1_PHASE : 0),
  93                      ssp->base + HW_SSP_CTRL1(ssp));
  94
  95         writel(0x0, ssp->base + HW_SSP_CMD0);
  96         writel(0x0, ssp->base + HW_SSP_CMD1);
  97
  98         return 0;
  99 }
 100
 101 static int mxs_spi_setup(struct spi_device *dev)
 102 {
 103         int err = 0;
 104
 105         if (!dev->bits_per_word)
 106                 dev->bits_per_word = 8;
 107
 108         if (dev->mode & ~(SPI_CPOL | SPI_CPHA))
 109                 return -EINVAL;
 110
 111         err = mxs_spi_setup_transfer(dev, NULL);
 112         if (err) {
 113                 dev_err(&dev->dev,
 114                         "Failed to setup transfer, error = %d\n", err);
 115         }
 116
 117         return err;
 118 }
 119
 120 static uint32_t mxs_spi_cs_to_reg(unsigned cs)
 121 {
 122         uint32_t select = 0;
 123
 124         /*
 125          * i.MX28 Datasheet: 17.10.1: HW_SSP_CTRL0
 126          *
 127          * The bits BM_SSP_CTRL0_WAIT_FOR_CMD and BM_SSP_CTRL0_WAIT_FOR_IRQ
 128          * in HW_SSP_CTRL0 register do have multiple usage, please refer to
 129          * the datasheet for further details. In SPI mode, they are used to
 130          * toggle the chip-select lines (nCS pins).
 131          */
 132         if (cs & 1)
 133                 select |= BM_SSP_CTRL0_WAIT_FOR_CMD;
 134         if (cs & 2)
 135                 select |= BM_SSP_CTRL0_WAIT_FOR_IRQ;
 136
 137         return select;
 138 }
 139
 140 static void mxs_spi_set_cs(struct mxs_spi *spi, unsigned cs)
 141 {
 142         const uint32_t mask =
 143                 BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ;
 144         uint32_t select;
 145         struct mxs_ssp *ssp = &spi->ssp;
 146
 147         writel(mask, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 148         select = mxs_spi_cs_to_reg(cs);
 149         writel(select, ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 150 }
 151
 152 static inline void mxs_spi_enable(struct mxs_spi *spi)
 153 {
 154         struct mxs_ssp *ssp = &spi->ssp;
 155
 156         writel(BM_SSP_CTRL0_LOCK_CS,
 157                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 158         writel(BM_SSP_CTRL0_IGNORE_CRC,
 159                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 160 }
 161
 162 static inline void mxs_spi_disable(struct mxs_spi *spi)
 163 {
 164         struct mxs_ssp *ssp = &spi->ssp;
 165
 166         writel(BM_SSP_CTRL0_LOCK_CS,
 167                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 168         writel(BM_SSP_CTRL0_IGNORE_CRC,
 169                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 170 }
 171
 172 static int mxs_ssp_wait(struct mxs_spi *spi, int offset, int mask, bool set)
 173 {
 174         const unsigned long timeout = jiffies + msecs_to_jiffies(SSP_TIMEOUT);
 175         struct mxs_ssp *ssp = &spi->ssp;
 176         uint32_t reg;
 177
 178         do {
 179                 reg = readl_relaxed(ssp->base + offset);
 180
 181                 if (!set)
 182                         reg = ~reg;
 183
 184                 reg &= mask;
 185
 186                 if (reg == mask)
 187                         return 0;
 188         } while (time_before(jiffies, timeout));
 189
 190         return -ETIMEDOUT;
 191 }
 192
 193 static void mxs_ssp_dma_irq_callback(void *param)
 194 {
 195         struct mxs_spi *spi = param;
 196         complete(&spi->c);
 197 }
 198
 199 static irqreturn_t mxs_ssp_irq_handler(int irq, void *dev_id)
 200 {
 201         struct mxs_ssp *ssp = dev_id;
 202         dev_err(ssp->dev, "%s[%i] CTRL1=%08x STATUS=%08x\n",
 203                 __func__, __LINE__,
 204                 readl(ssp->base + HW_SSP_CTRL1(ssp)),
 205                 readl(ssp->base + HW_SSP_STATUS(ssp)));
 206         return IRQ_HANDLED;
 207 }
 208
 209 static int mxs_spi_txrx_dma(struct mxs_spi *spi, int cs,
 210                             unsigned char *buf, int len,
 211                             int *first, int *last, int write)
 212 {
 213         struct mxs_ssp *ssp = &spi->ssp;
 214         struct dma_async_tx_descriptor *desc = NULL;
 215         const bool vmalloced_buf = is_vmalloc_addr(buf);
 216         const int desc_len = vmalloced_buf ? PAGE_SIZE : SG_MAXLEN;
 217         const int sgs = DIV_ROUND_UP(len, desc_len);
 218         int sg_count;
 219         int min, ret;
 220         uint32_t ctrl0;
 221         struct page *vm_page;
 222         void *sg_buf;
 223         struct {
 224                 uint32_t                pio[4];
 225                 struct scatterlist      sg;
 226         } *dma_xfer;
 227
 228         if (!len)
 229                 return -EINVAL;
 230
 231         dma_xfer = kzalloc(sizeof(*dma_xfer) * sgs, GFP_KERNEL);
 232         if (!dma_xfer)
 233                 return -ENOMEM;
 234
 235         INIT_COMPLETION(spi->c);
 236
 237         ctrl0 = readl(ssp->base + HW_SSP_CTRL0);
 238         ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
 239         ctrl0 |= BM_SSP_CTRL0_DATA_XFER | mxs_spi_cs_to_reg(cs);
 240
 241         if (*first)
 242                 ctrl0 |= BM_SSP_CTRL0_LOCK_CS;
 243         if (!write)
 244                 ctrl0 |= BM_SSP_CTRL0_READ;
 245
 246         /* Queue the DMA data transfer. */
 247         for (sg_count = 0; sg_count < sgs; sg_count++) {
 248                 min = min(len, desc_len);
 249
 250                 /* Prepare the transfer descriptor. */
 251                 if ((sg_count + 1 == sgs) && *last)
 252                         ctrl0 |= BM_SSP_CTRL0_IGNORE_CRC;
 253
 254                 if (ssp->devid == IMX23_SSP) {
 255                         ctrl0 &= ~BM_SSP_CTRL0_XFER_COUNT;
 256                         ctrl0 |= min;
 257                 }
 258
 259                 dma_xfer[sg_count].pio[0] = ctrl0;
 260                 dma_xfer[sg_count].pio[3] = min;
 261
 262                 if (vmalloced_buf) {
 263                         vm_page = vmalloc_to_page(buf);
 264                         if (!vm_page) {
 265                                 ret = -ENOMEM;
 266                                 goto err_vmalloc;
 267                         }
 268                         sg_buf = page_address(vm_page) +
 269                                 ((size_t)buf & ~PAGE_MASK);
 270                 } else {
 271                         sg_buf = buf;
 272                 }
 273
 274                 sg_init_one(&dma_xfer[sg_count].sg, sg_buf, min);
 275                 ret = dma_map_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
 276                         write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 277
 278                 len -= min;
 279                 buf += min;
 280
 281                 /* Queue the PIO register write transfer. */
 282                 desc = dmaengine_prep_slave_sg(ssp->dmach,
 283                                 (struct scatterlist *)dma_xfer[sg_count].pio,
 284                                 (ssp->devid == IMX23_SSP) ? 1 : 4,
 285                                 DMA_TRANS_NONE,
 286                                 sg_count ? DMA_PREP_INTERRUPT : 0);
 287                 if (!desc) {
 288                         dev_err(ssp->dev,
 289                                 "Failed to get PIO reg. write descriptor.\n");
 290                         ret = -EINVAL;
 291                         goto err_mapped;
 292                 }
 293
 294                 desc = dmaengine_prep_slave_sg(ssp->dmach,
 295                                 &dma_xfer[sg_count].sg, 1,
 296                                 write ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
 297                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 298
 299                 if (!desc) {
 300                         dev_err(ssp->dev,
 301                                 "Failed to get DMA data write descriptor.\n");
 302                         ret = -EINVAL;
 303                         goto err_mapped;
 304                 }
 305         }
 306
 307         /*
 308          * The last descriptor must have this callback,
 309          * to finish the DMA transaction.
 310          */
 311         desc->callback = mxs_ssp_dma_irq_callback;
 312         desc->callback_param = spi;
 313
 314         /* Start the transfer. */
 315         dmaengine_submit(desc);
 316         dma_async_issue_pending(ssp->dmach);
 317
 318         ret = wait_for_completion_timeout(&spi->c,
 319                                 msecs_to_jiffies(SSP_TIMEOUT));
 320         if (!ret) {
 321                 dev_err(ssp->dev, "DMA transfer timeout\n");
 322                 ret = -ETIMEDOUT;
 323                 dmaengine_terminate_all(ssp->dmach);
 324                 goto err_vmalloc;
 325         }
 326
 327         ret = 0;
 328
 329 err_vmalloc:
 330         while (--sg_count >= 0) {
 331 err_mapped:
 332                 dma_unmap_sg(ssp->dev, &dma_xfer[sg_count].sg, 1,
 333                         write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 334         }
 335
 336         kfree(dma_xfer);
 337
 338         return ret;
 339 }
 340
 341 static int mxs_spi_txrx_pio(struct mxs_spi *spi, int cs,
 342                             unsigned char *buf, int len,
 343                             int *first, int *last, int write)
 344 {
 345         struct mxs_ssp *ssp = &spi->ssp;
 346
 347         if (*first)
 348                 mxs_spi_enable(spi);
 349
 350         mxs_spi_set_cs(spi, cs);
 351
 352         while (len--) {
 353                 if (*last && len == 0)
 354                         mxs_spi_disable(spi);
 355
 356                 if (ssp->devid == IMX23_SSP) {
 357                         writel(BM_SSP_CTRL0_XFER_COUNT,
 358                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 359                         writel(1,
 360                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 361                 } else {
 362                         writel(1, ssp->base + HW_SSP_XFER_SIZE);
 363                 }
 364
 365                 if (write)
 366                         writel(BM_SSP_CTRL0_READ,
 367                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
 368                 else
 369                         writel(BM_SSP_CTRL0_READ,
 370                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 371
 372                 writel(BM_SSP_CTRL0_RUN,
 373                                 ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 374
 375                 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 1))
 376                         return -ETIMEDOUT;
 377
 378                 if (write)
 379                         writel(*buf, ssp->base + HW_SSP_DATA(ssp));
 380
 381                 writel(BM_SSP_CTRL0_DATA_XFER,
 382                              ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
 383
 384                 if (!write) {
 385                         if (mxs_ssp_wait(spi, HW_SSP_STATUS(ssp),
 386                                                 BM_SSP_STATUS_FIFO_EMPTY, 0))
 387                                 return -ETIMEDOUT;
 388
 389                         *buf = (readl(ssp->base + HW_SSP_DATA(ssp)) & 0xff);
 390                 }
 391
 392                 if (mxs_ssp_wait(spi, HW_SSP_CTRL0, BM_SSP_CTRL0_RUN, 0))
 393                         return -ETIMEDOUT;
 394
 395                 buf++;
 396         }
 397
 398         if (len <= 0)
 399                 return 0;
 400
 401         return -ETIMEDOUT;
 402 }
 403
 404 static int mxs_spi_transfer_one(struct spi_master *master,
 405                                 struct spi_message *m)
 406 {
 407         struct mxs_spi *spi = spi_master_get_devdata(master);
 408         struct mxs_ssp *ssp = &spi->ssp;
 409         int first, last;
 410         struct spi_transfer *t, *tmp_t;
 411         int status = 0;
 412         int cs;
 413
 414         first = last = 0;
 415
 416         cs = m->spi->chip_select;
 417
 418         list_for_each_entry_safe(t, tmp_t, &m->transfers, transfer_list) {
 419
 420                 status = mxs_spi_setup_transfer(m->spi, t);
 421                 if (status)
 422                         break;
 423
 424                 if (&t->transfer_list == m->transfers.next)
 425                         first = 1;
 426                 if (&t->transfer_list == m->transfers.prev)
 427                         last = 1;
 428                 if ((t->rx_buf && t->tx_buf) || (t->rx_dma && t->tx_dma)) {
 429                         dev_err(ssp->dev,
 430                                 "Cannot send and receive simultaneously\n");
 431                         status = -EINVAL;
 432                         break;
 433                 }
 434
 435                 /*
 436                  * Small blocks can be transfered via PIO.
 437                  * Measured by empiric means:
 438                  *
 439                  * dd if=/dev/mtdblock0 of=/dev/null bs=1024k count=1
 440                  *
 441                  * DMA only: 2.164808 seconds, 473.0KB/s
 442                  * Combined: 1.676276 seconds, 610.9KB/s
 443                  */
 444                 if (t->len < 32) {
 445                         writel(BM_SSP_CTRL1_DMA_ENABLE,
 446                                 ssp->base + HW_SSP_CTRL1(ssp) +
 447                                 STMP_OFFSET_REG_CLR);
 448
 449                         if (t->tx_buf)
 450                                 status = mxs_spi_txrx_pio(spi, cs,
 451                                                 (void *)t->tx_buf,
 452                                                 t->len, &first, &last, 1);
 453                         if (t->rx_buf)
 454                                 status = mxs_spi_txrx_pio(spi, cs,
 455                                                 t->rx_buf, t->len,
 456                                                 &first, &last, 0);
 457                 } else {
 458                         writel(BM_SSP_CTRL1_DMA_ENABLE,
 459                                 ssp->base + HW_SSP_CTRL1(ssp) +
 460                                 STMP_OFFSET_REG_SET);
 461
 462                         if (t->tx_buf)
 463                                 status = mxs_spi_txrx_dma(spi, cs,
 464                                                 (void *)t->tx_buf, t->len,
 465                                                 &first, &last, 1);
 466                         if (t->rx_buf)
 467                                 status = mxs_spi_txrx_dma(spi, cs,
 468                                                 t->rx_buf, t->len,
 469                                                 &first, &last, 0);
 470                 }
 471
 472                 if (status) {
 473                         stmp_reset_block(ssp->base);
 474                         break;
 475                 }
 476
 477                 m->actual_length += t->len;
 478                 first = last = 0;
 479         }
 480
 481         m->status = status;
 482         spi_finalize_current_message(master);
 483
 484         return status;
 485 }
 486
 487 static const struct of_device_id mxs_spi_dt_ids[] = {
 488         { .compatible = "fsl,imx23-spi", .data = (void *) IMX23_SSP, },
 489         { .compatible = "fsl,imx28-spi", .data = (void *) IMX28_SSP, },
 490         { /* sentinel */ }
 491 };
 492 MODULE_DEVICE_TABLE(of, mxs_spi_dt_ids);
 493
 494 static int mxs_spi_probe(struct platform_device *pdev)
 495 {
 496         const struct of_device_id *of_id =
 497                         of_match_device(mxs_spi_dt_ids, &pdev->dev);
 498         struct device_node *np = pdev->dev.of_node;
 499         struct spi_master *master;
 500         struct mxs_spi *spi;
 501         struct mxs_ssp *ssp;
 502         struct resource *iores;
 503         struct pinctrl *pinctrl;
 504         struct clk *clk;
 505         void __iomem *base;
 506         int devid, clk_freq;
 507         int ret = 0, irq_err;
 508
 509         /*
 510          * Default clock speed for the SPI core. 160MHz seems to
 511          * work reasonably well with most SPI flashes, so use this
 512          * as a default. Override with "clock-frequency" DT prop.
 513          */
 514         const int clk_freq_default = 160000000;
 515
 516         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 517         irq_err = platform_get_irq(pdev, 0);
 518         if (!iores || irq_err < 0)
 519                 return -EINVAL;
 520
 521         base = devm_ioremap_resource(&pdev->dev, iores);
 522         if (IS_ERR(base))
 523                 return PTR_ERR(base);
 524
 525         pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
 526         if (IS_ERR(pinctrl))
 527                 return PTR_ERR(pinctrl);
 528
 529         clk = devm_clk_get(&pdev->dev, NULL);
 530         if (IS_ERR(clk))
 531                 return PTR_ERR(clk);
 532
 533         devid = (enum mxs_ssp_id) of_id->data;
 534         ret = of_property_read_u32(np, "clock-frequency",
 535                                    &clk_freq);
 536         if (ret)
 537                 clk_freq = clk_freq_default;
 538
 539         master = spi_alloc_master(&pdev->dev, sizeof(*spi));
 540         if (!master)
 541                 return -ENOMEM;
 542
 543         master->transfer_one_message = mxs_spi_transfer_one;
 544         master->setup = mxs_spi_setup;
 545         master->bits_per_word_mask = SPI_BPW_MASK(8);
 546         master->mode_bits = SPI_CPOL | SPI_CPHA;
 547         master->num_chipselect = 3;
 548         master->dev.of_node = np;
 549         master->flags = SPI_MASTER_HALF_DUPLEX;
 550
 551         spi = spi_master_get_devdata(master);
 552         ssp = &spi->ssp;
 553         ssp->dev = &pdev->dev;
 554         ssp->clk = clk;
 555         ssp->base = base;
 556         ssp->devid = devid;
 557
 558         init_completion(&spi->c);
 559
 560         ret = devm_request_irq(&pdev->dev, irq_err, mxs_ssp_irq_handler, 0,
 561                                DRIVER_NAME, ssp);
 562         if (ret)
 563                 goto out_master_free;
 564
 565         ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
 566         if (!ssp->dmach) {
 567                 dev_err(ssp->dev, "Failed to request DMA\n");
 568                 ret = -ENODEV;
 569                 goto out_master_free;
 570         }
 571
 572         clk_prepare_enable(ssp->clk);
 573         clk_set_rate(ssp->clk, clk_freq);
 574         ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
 575
 576         stmp_reset_block(ssp->base);
 577
 578         platform_set_drvdata(pdev, master);
 579
 580         ret = spi_register_master(master);
 581         if (ret) {
 582                 dev_err(&pdev->dev, "Cannot register SPI master, %d\n", ret);
 583                 goto out_free_dma;
 584         }
 585
 586         return 0;
 587
 588 out_free_dma:
 589         dma_release_channel(ssp->dmach);
 590         clk_disable_unprepare(ssp->clk);
 591 out_master_free:
 592         spi_master_put(master);
 593         return ret;
 594 }
 595
 596 static int mxs_spi_remove(struct platform_device *pdev)
 597 {
 598         struct spi_master *master;
 599         struct mxs_spi *spi;
 600         struct mxs_ssp *ssp;
 601
 602         master = spi_master_get(platform_get_drvdata(pdev));
 603         spi = spi_master_get_devdata(master);
 604         ssp = &spi->ssp;
 605
 606         spi_unregister_master(master);
 607
 608         dma_release_channel(ssp->dmach);
 609
 610         clk_disable_unprepare(ssp->clk);
 611
 612         spi_master_put(master);
 613
 614         return 0;
 615 }
 616
 617 static struct platform_driver mxs_spi_driver = {
 618         .probe  = mxs_spi_probe,
 619         .remove = mxs_spi_remove,
 620         .driver = {
 621                 .name   = DRIVER_NAME,
 622                 .owner  = THIS_MODULE,
 623                 .of_match_table = mxs_spi_dt_ids,
 624         },
 625 };
 626
 627 module_platform_driver(mxs_spi_driver);
 628
 629 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
 630 MODULE_DESCRIPTION("MXS SPI master driver");
 631 MODULE_LICENSE("GPL");
 632 MODULE_ALIAS("platform:mxs-spi");