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x86: Move call to print_modules() out of show_regs()
[deliverable/linux.git] / drivers / spi / spi-omap2-mcspi.c
1 /*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/io.h>
35 #include <linux/slab.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39
40 #include <linux/spi/spi.h>
41
42 #include <plat/dma.h>
43 #include <plat/clock.h>
44 #include <plat/mcspi.h>
45
46 #define OMAP2_MCSPI_MAX_FREQ 48000000
47 #define SPI_AUTOSUSPEND_TIMEOUT 2000
48
49 #define OMAP2_MCSPI_REVISION 0x00
50 #define OMAP2_MCSPI_SYSSTATUS 0x14
51 #define OMAP2_MCSPI_IRQSTATUS 0x18
52 #define OMAP2_MCSPI_IRQENABLE 0x1c
53 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
54 #define OMAP2_MCSPI_SYST 0x24
55 #define OMAP2_MCSPI_MODULCTRL 0x28
56
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0 0x2c
59 #define OMAP2_MCSPI_CHSTAT0 0x30
60 #define OMAP2_MCSPI_CHCTRL0 0x34
61 #define OMAP2_MCSPI_TX0 0x38
62 #define OMAP2_MCSPI_RX0 0x3c
63
64 /* per-register bitmasks: */
65
66 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
67 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
68 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
69
70 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
71 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
72 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
73 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
74 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
75 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
76 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
77 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
78 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
79 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
80 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
81 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
82 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
83 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
84 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
85
86 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
87 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
88 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
89
90 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
91
92 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
93
94 /* We have 2 DMA channels per CS, one for RX and one for TX */
95 struct omap2_mcspi_dma {
96 int dma_tx_channel;
97 int dma_rx_channel;
98
99 int dma_tx_sync_dev;
100 int dma_rx_sync_dev;
101
102 struct completion dma_tx_completion;
103 struct completion dma_rx_completion;
104 };
105
106 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
107 * cache operations; better heuristics consider wordsize and bitrate.
108 */
109 #define DMA_MIN_BYTES 160
110
111
112 /*
113 * Used for context save and restore, structure members to be updated whenever
114 * corresponding registers are modified.
115 */
116 struct omap2_mcspi_regs {
117 u32 modulctrl;
118 u32 wakeupenable;
119 struct list_head cs;
120 };
121
122 struct omap2_mcspi {
123 struct spi_master *master;
124 /* Virtual base address of the controller */
125 void __iomem *base;
126 unsigned long phys;
127 /* SPI1 has 4 channels, while SPI2 has 2 */
128 struct omap2_mcspi_dma *dma_channels;
129 struct device *dev;
130 struct omap2_mcspi_regs ctx;
131 };
132
133 struct omap2_mcspi_cs {
134 void __iomem *base;
135 unsigned long phys;
136 int word_len;
137 struct list_head node;
138 /* Context save and restore shadow register */
139 u32 chconf0;
140 };
141
142 #define MOD_REG_BIT(val, mask, set) do { \
143 if (set) \
144 val |= mask; \
145 else \
146 val &= ~mask; \
147 } while (0)
148
149 static inline void mcspi_write_reg(struct spi_master *master,
150 int idx, u32 val)
151 {
152 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
153
154 __raw_writel(val, mcspi->base + idx);
155 }
156
157 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
158 {
159 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
160
161 return __raw_readl(mcspi->base + idx);
162 }
163
164 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
165 int idx, u32 val)
166 {
167 struct omap2_mcspi_cs *cs = spi->controller_state;
168
169 __raw_writel(val, cs->base + idx);
170 }
171
172 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
173 {
174 struct omap2_mcspi_cs *cs = spi->controller_state;
175
176 return __raw_readl(cs->base + idx);
177 }
178
179 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
180 {
181 struct omap2_mcspi_cs *cs = spi->controller_state;
182
183 return cs->chconf0;
184 }
185
186 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
187 {
188 struct omap2_mcspi_cs *cs = spi->controller_state;
189
190 cs->chconf0 = val;
191 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
192 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
193 }
194
195 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
196 int is_read, int enable)
197 {
198 u32 l, rw;
199
200 l = mcspi_cached_chconf0(spi);
201
202 if (is_read) /* 1 is read, 0 write */
203 rw = OMAP2_MCSPI_CHCONF_DMAR;
204 else
205 rw = OMAP2_MCSPI_CHCONF_DMAW;
206
207 MOD_REG_BIT(l, rw, enable);
208 mcspi_write_chconf0(spi, l);
209 }
210
211 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
212 {
213 u32 l;
214
215 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
216 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
217 /* Flash post-writes */
218 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
219 }
220
221 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
222 {
223 u32 l;
224
225 l = mcspi_cached_chconf0(spi);
226 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
227 mcspi_write_chconf0(spi, l);
228 }
229
230 static void omap2_mcspi_set_master_mode(struct spi_master *master)
231 {
232 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
233 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
234 u32 l;
235
236 /*
237 * Setup when switching from (reset default) slave mode
238 * to single-channel master mode
239 */
240 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
241 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
242 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
243 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
244 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
245
246 ctx->modulctrl = l;
247 }
248
249 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
250 {
251 struct spi_master *spi_cntrl = mcspi->master;
252 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
253 struct omap2_mcspi_cs *cs;
254
255 /* McSPI: context restore */
256 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
257 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
258
259 list_for_each_entry(cs, &ctx->cs, node)
260 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
261 }
262 static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
263 {
264 pm_runtime_mark_last_busy(mcspi->dev);
265 pm_runtime_put_autosuspend(mcspi->dev);
266 }
267
268 static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
269 {
270 return pm_runtime_get_sync(mcspi->dev);
271 }
272
273 static int omap2_prepare_transfer(struct spi_master *master)
274 {
275 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
276
277 pm_runtime_get_sync(mcspi->dev);
278 return 0;
279 }
280
281 static int omap2_unprepare_transfer(struct spi_master *master)
282 {
283 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
284
285 pm_runtime_mark_last_busy(mcspi->dev);
286 pm_runtime_put_autosuspend(mcspi->dev);
287 return 0;
288 }
289
290 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
291 {
292 unsigned long timeout;
293
294 timeout = jiffies + msecs_to_jiffies(1000);
295 while (!(__raw_readl(reg) & bit)) {
296 if (time_after(jiffies, timeout))
297 return -1;
298 cpu_relax();
299 }
300 return 0;
301 }
302
303 static unsigned
304 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
305 {
306 struct omap2_mcspi *mcspi;
307 struct omap2_mcspi_cs *cs = spi->controller_state;
308 struct omap2_mcspi_dma *mcspi_dma;
309 unsigned int count, c;
310 unsigned long base, tx_reg, rx_reg;
311 int word_len, data_type, element_count;
312 int elements = 0;
313 u32 l;
314 u8 * rx;
315 const u8 * tx;
316 void __iomem *chstat_reg;
317
318 mcspi = spi_master_get_devdata(spi->master);
319 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
320 l = mcspi_cached_chconf0(spi);
321
322 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
323
324 count = xfer->len;
325 c = count;
326 word_len = cs->word_len;
327
328 base = cs->phys;
329 tx_reg = base + OMAP2_MCSPI_TX0;
330 rx_reg = base + OMAP2_MCSPI_RX0;
331 rx = xfer->rx_buf;
332 tx = xfer->tx_buf;
333
334 if (word_len <= 8) {
335 data_type = OMAP_DMA_DATA_TYPE_S8;
336 element_count = count;
337 } else if (word_len <= 16) {
338 data_type = OMAP_DMA_DATA_TYPE_S16;
339 element_count = count >> 1;
340 } else /* word_len <= 32 */ {
341 data_type = OMAP_DMA_DATA_TYPE_S32;
342 element_count = count >> 2;
343 }
344
345 if (tx != NULL) {
346 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
347 data_type, element_count, 1,
348 OMAP_DMA_SYNC_ELEMENT,
349 mcspi_dma->dma_tx_sync_dev, 0);
350
351 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
352 OMAP_DMA_AMODE_CONSTANT,
353 tx_reg, 0, 0);
354
355 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
356 OMAP_DMA_AMODE_POST_INC,
357 xfer->tx_dma, 0, 0);
358 }
359
360 if (rx != NULL) {
361 elements = element_count - 1;
362 if (l & OMAP2_MCSPI_CHCONF_TURBO)
363 elements--;
364
365 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
366 data_type, elements, 1,
367 OMAP_DMA_SYNC_ELEMENT,
368 mcspi_dma->dma_rx_sync_dev, 1);
369
370 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
371 OMAP_DMA_AMODE_CONSTANT,
372 rx_reg, 0, 0);
373
374 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
375 OMAP_DMA_AMODE_POST_INC,
376 xfer->rx_dma, 0, 0);
377 }
378
379 if (tx != NULL) {
380 omap_start_dma(mcspi_dma->dma_tx_channel);
381 omap2_mcspi_set_dma_req(spi, 0, 1);
382 }
383
384 if (rx != NULL) {
385 omap_start_dma(mcspi_dma->dma_rx_channel);
386 omap2_mcspi_set_dma_req(spi, 1, 1);
387 }
388
389 if (tx != NULL) {
390 wait_for_completion(&mcspi_dma->dma_tx_completion);
391 dma_unmap_single(&spi->dev, xfer->tx_dma, count, DMA_TO_DEVICE);
392
393 /* for TX_ONLY mode, be sure all words have shifted out */
394 if (rx == NULL) {
395 if (mcspi_wait_for_reg_bit(chstat_reg,
396 OMAP2_MCSPI_CHSTAT_TXS) < 0)
397 dev_err(&spi->dev, "TXS timed out\n");
398 else if (mcspi_wait_for_reg_bit(chstat_reg,
399 OMAP2_MCSPI_CHSTAT_EOT) < 0)
400 dev_err(&spi->dev, "EOT timed out\n");
401 }
402 }
403
404 if (rx != NULL) {
405 wait_for_completion(&mcspi_dma->dma_rx_completion);
406 dma_unmap_single(&spi->dev, xfer->rx_dma, count, DMA_FROM_DEVICE);
407 omap2_mcspi_set_enable(spi, 0);
408
409 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
410
411 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
412 & OMAP2_MCSPI_CHSTAT_RXS)) {
413 u32 w;
414
415 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
416 if (word_len <= 8)
417 ((u8 *)xfer->rx_buf)[elements++] = w;
418 else if (word_len <= 16)
419 ((u16 *)xfer->rx_buf)[elements++] = w;
420 else /* word_len <= 32 */
421 ((u32 *)xfer->rx_buf)[elements++] = w;
422 } else {
423 dev_err(&spi->dev,
424 "DMA RX penultimate word empty");
425 count -= (word_len <= 8) ? 2 :
426 (word_len <= 16) ? 4 :
427 /* word_len <= 32 */ 8;
428 omap2_mcspi_set_enable(spi, 1);
429 return count;
430 }
431 }
432
433 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
434 & OMAP2_MCSPI_CHSTAT_RXS)) {
435 u32 w;
436
437 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
438 if (word_len <= 8)
439 ((u8 *)xfer->rx_buf)[elements] = w;
440 else if (word_len <= 16)
441 ((u16 *)xfer->rx_buf)[elements] = w;
442 else /* word_len <= 32 */
443 ((u32 *)xfer->rx_buf)[elements] = w;
444 } else {
445 dev_err(&spi->dev, "DMA RX last word empty");
446 count -= (word_len <= 8) ? 1 :
447 (word_len <= 16) ? 2 :
448 /* word_len <= 32 */ 4;
449 }
450 omap2_mcspi_set_enable(spi, 1);
451 }
452 return count;
453 }
454
455 static unsigned
456 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
457 {
458 struct omap2_mcspi *mcspi;
459 struct omap2_mcspi_cs *cs = spi->controller_state;
460 unsigned int count, c;
461 u32 l;
462 void __iomem *base = cs->base;
463 void __iomem *tx_reg;
464 void __iomem *rx_reg;
465 void __iomem *chstat_reg;
466 int word_len;
467
468 mcspi = spi_master_get_devdata(spi->master);
469 count = xfer->len;
470 c = count;
471 word_len = cs->word_len;
472
473 l = mcspi_cached_chconf0(spi);
474
475 /* We store the pre-calculated register addresses on stack to speed
476 * up the transfer loop. */
477 tx_reg = base + OMAP2_MCSPI_TX0;
478 rx_reg = base + OMAP2_MCSPI_RX0;
479 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
480
481 if (c < (word_len>>3))
482 return 0;
483
484 if (word_len <= 8) {
485 u8 *rx;
486 const u8 *tx;
487
488 rx = xfer->rx_buf;
489 tx = xfer->tx_buf;
490
491 do {
492 c -= 1;
493 if (tx != NULL) {
494 if (mcspi_wait_for_reg_bit(chstat_reg,
495 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
496 dev_err(&spi->dev, "TXS timed out\n");
497 goto out;
498 }
499 dev_vdbg(&spi->dev, "write-%d %02x\n",
500 word_len, *tx);
501 __raw_writel(*tx++, tx_reg);
502 }
503 if (rx != NULL) {
504 if (mcspi_wait_for_reg_bit(chstat_reg,
505 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
506 dev_err(&spi->dev, "RXS timed out\n");
507 goto out;
508 }
509
510 if (c == 1 && tx == NULL &&
511 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
512 omap2_mcspi_set_enable(spi, 0);
513 *rx++ = __raw_readl(rx_reg);
514 dev_vdbg(&spi->dev, "read-%d %02x\n",
515 word_len, *(rx - 1));
516 if (mcspi_wait_for_reg_bit(chstat_reg,
517 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
518 dev_err(&spi->dev,
519 "RXS timed out\n");
520 goto out;
521 }
522 c = 0;
523 } else if (c == 0 && tx == NULL) {
524 omap2_mcspi_set_enable(spi, 0);
525 }
526
527 *rx++ = __raw_readl(rx_reg);
528 dev_vdbg(&spi->dev, "read-%d %02x\n",
529 word_len, *(rx - 1));
530 }
531 } while (c);
532 } else if (word_len <= 16) {
533 u16 *rx;
534 const u16 *tx;
535
536 rx = xfer->rx_buf;
537 tx = xfer->tx_buf;
538 do {
539 c -= 2;
540 if (tx != NULL) {
541 if (mcspi_wait_for_reg_bit(chstat_reg,
542 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
543 dev_err(&spi->dev, "TXS timed out\n");
544 goto out;
545 }
546 dev_vdbg(&spi->dev, "write-%d %04x\n",
547 word_len, *tx);
548 __raw_writel(*tx++, tx_reg);
549 }
550 if (rx != NULL) {
551 if (mcspi_wait_for_reg_bit(chstat_reg,
552 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
553 dev_err(&spi->dev, "RXS timed out\n");
554 goto out;
555 }
556
557 if (c == 2 && tx == NULL &&
558 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
559 omap2_mcspi_set_enable(spi, 0);
560 *rx++ = __raw_readl(rx_reg);
561 dev_vdbg(&spi->dev, "read-%d %04x\n",
562 word_len, *(rx - 1));
563 if (mcspi_wait_for_reg_bit(chstat_reg,
564 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
565 dev_err(&spi->dev,
566 "RXS timed out\n");
567 goto out;
568 }
569 c = 0;
570 } else if (c == 0 && tx == NULL) {
571 omap2_mcspi_set_enable(spi, 0);
572 }
573
574 *rx++ = __raw_readl(rx_reg);
575 dev_vdbg(&spi->dev, "read-%d %04x\n",
576 word_len, *(rx - 1));
577 }
578 } while (c >= 2);
579 } else if (word_len <= 32) {
580 u32 *rx;
581 const u32 *tx;
582
583 rx = xfer->rx_buf;
584 tx = xfer->tx_buf;
585 do {
586 c -= 4;
587 if (tx != NULL) {
588 if (mcspi_wait_for_reg_bit(chstat_reg,
589 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
590 dev_err(&spi->dev, "TXS timed out\n");
591 goto out;
592 }
593 dev_vdbg(&spi->dev, "write-%d %08x\n",
594 word_len, *tx);
595 __raw_writel(*tx++, tx_reg);
596 }
597 if (rx != NULL) {
598 if (mcspi_wait_for_reg_bit(chstat_reg,
599 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
600 dev_err(&spi->dev, "RXS timed out\n");
601 goto out;
602 }
603
604 if (c == 4 && tx == NULL &&
605 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
606 omap2_mcspi_set_enable(spi, 0);
607 *rx++ = __raw_readl(rx_reg);
608 dev_vdbg(&spi->dev, "read-%d %08x\n",
609 word_len, *(rx - 1));
610 if (mcspi_wait_for_reg_bit(chstat_reg,
611 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
612 dev_err(&spi->dev,
613 "RXS timed out\n");
614 goto out;
615 }
616 c = 0;
617 } else if (c == 0 && tx == NULL) {
618 omap2_mcspi_set_enable(spi, 0);
619 }
620
621 *rx++ = __raw_readl(rx_reg);
622 dev_vdbg(&spi->dev, "read-%d %08x\n",
623 word_len, *(rx - 1));
624 }
625 } while (c >= 4);
626 }
627
628 /* for TX_ONLY mode, be sure all words have shifted out */
629 if (xfer->rx_buf == NULL) {
630 if (mcspi_wait_for_reg_bit(chstat_reg,
631 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
632 dev_err(&spi->dev, "TXS timed out\n");
633 } else if (mcspi_wait_for_reg_bit(chstat_reg,
634 OMAP2_MCSPI_CHSTAT_EOT) < 0)
635 dev_err(&spi->dev, "EOT timed out\n");
636
637 /* disable chan to purge rx datas received in TX_ONLY transfer,
638 * otherwise these rx datas will affect the direct following
639 * RX_ONLY transfer.
640 */
641 omap2_mcspi_set_enable(spi, 0);
642 }
643 out:
644 omap2_mcspi_set_enable(spi, 1);
645 return count - c;
646 }
647
648 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
649 {
650 u32 div;
651
652 for (div = 0; div < 15; div++)
653 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
654 return div;
655
656 return 15;
657 }
658
659 /* called only when no transfer is active to this device */
660 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
661 struct spi_transfer *t)
662 {
663 struct omap2_mcspi_cs *cs = spi->controller_state;
664 struct omap2_mcspi *mcspi;
665 struct spi_master *spi_cntrl;
666 u32 l = 0, div = 0;
667 u8 word_len = spi->bits_per_word;
668 u32 speed_hz = spi->max_speed_hz;
669
670 mcspi = spi_master_get_devdata(spi->master);
671 spi_cntrl = mcspi->master;
672
673 if (t != NULL && t->bits_per_word)
674 word_len = t->bits_per_word;
675
676 cs->word_len = word_len;
677
678 if (t && t->speed_hz)
679 speed_hz = t->speed_hz;
680
681 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
682 div = omap2_mcspi_calc_divisor(speed_hz);
683
684 l = mcspi_cached_chconf0(spi);
685
686 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
687 * REVISIT: this controller could support SPI_3WIRE mode.
688 */
689 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
690 l |= OMAP2_MCSPI_CHCONF_DPE0;
691
692 /* wordlength */
693 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
694 l |= (word_len - 1) << 7;
695
696 /* set chipselect polarity; manage with FORCE */
697 if (!(spi->mode & SPI_CS_HIGH))
698 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
699 else
700 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
701
702 /* set clock divisor */
703 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
704 l |= div << 2;
705
706 /* set SPI mode 0..3 */
707 if (spi->mode & SPI_CPOL)
708 l |= OMAP2_MCSPI_CHCONF_POL;
709 else
710 l &= ~OMAP2_MCSPI_CHCONF_POL;
711 if (spi->mode & SPI_CPHA)
712 l |= OMAP2_MCSPI_CHCONF_PHA;
713 else
714 l &= ~OMAP2_MCSPI_CHCONF_PHA;
715
716 mcspi_write_chconf0(spi, l);
717
718 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
719 OMAP2_MCSPI_MAX_FREQ >> div,
720 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
721 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
722
723 return 0;
724 }
725
726 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
727 {
728 struct spi_device *spi = data;
729 struct omap2_mcspi *mcspi;
730 struct omap2_mcspi_dma *mcspi_dma;
731
732 mcspi = spi_master_get_devdata(spi->master);
733 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
734
735 complete(&mcspi_dma->dma_rx_completion);
736
737 /* We must disable the DMA RX request */
738 omap2_mcspi_set_dma_req(spi, 1, 0);
739 }
740
741 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
742 {
743 struct spi_device *spi = data;
744 struct omap2_mcspi *mcspi;
745 struct omap2_mcspi_dma *mcspi_dma;
746
747 mcspi = spi_master_get_devdata(spi->master);
748 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
749
750 complete(&mcspi_dma->dma_tx_completion);
751
752 /* We must disable the DMA TX request */
753 omap2_mcspi_set_dma_req(spi, 0, 0);
754 }
755
756 static int omap2_mcspi_request_dma(struct spi_device *spi)
757 {
758 struct spi_master *master = spi->master;
759 struct omap2_mcspi *mcspi;
760 struct omap2_mcspi_dma *mcspi_dma;
761
762 mcspi = spi_master_get_devdata(master);
763 mcspi_dma = mcspi->dma_channels + spi->chip_select;
764
765 if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
766 omap2_mcspi_dma_rx_callback, spi,
767 &mcspi_dma->dma_rx_channel)) {
768 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
769 return -EAGAIN;
770 }
771
772 if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
773 omap2_mcspi_dma_tx_callback, spi,
774 &mcspi_dma->dma_tx_channel)) {
775 omap_free_dma(mcspi_dma->dma_rx_channel);
776 mcspi_dma->dma_rx_channel = -1;
777 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
778 return -EAGAIN;
779 }
780
781 init_completion(&mcspi_dma->dma_rx_completion);
782 init_completion(&mcspi_dma->dma_tx_completion);
783
784 return 0;
785 }
786
787 static int omap2_mcspi_setup(struct spi_device *spi)
788 {
789 int ret;
790 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
791 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
792 struct omap2_mcspi_dma *mcspi_dma;
793 struct omap2_mcspi_cs *cs = spi->controller_state;
794
795 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
796 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
797 spi->bits_per_word);
798 return -EINVAL;
799 }
800
801 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
802
803 if (!cs) {
804 cs = devm_kzalloc(&spi->dev , sizeof *cs, GFP_KERNEL);
805 if (!cs)
806 return -ENOMEM;
807 cs->base = mcspi->base + spi->chip_select * 0x14;
808 cs->phys = mcspi->phys + spi->chip_select * 0x14;
809 cs->chconf0 = 0;
810 spi->controller_state = cs;
811 /* Link this to context save list */
812 list_add_tail(&cs->node, &ctx->cs);
813 }
814
815 if (mcspi_dma->dma_rx_channel == -1
816 || mcspi_dma->dma_tx_channel == -1) {
817 ret = omap2_mcspi_request_dma(spi);
818 if (ret < 0)
819 return ret;
820 }
821
822 ret = omap2_mcspi_enable_clocks(mcspi);
823 if (ret < 0)
824 return ret;
825
826 ret = omap2_mcspi_setup_transfer(spi, NULL);
827 omap2_mcspi_disable_clocks(mcspi);
828
829 return ret;
830 }
831
832 static void omap2_mcspi_cleanup(struct spi_device *spi)
833 {
834 struct omap2_mcspi *mcspi;
835 struct omap2_mcspi_dma *mcspi_dma;
836 struct omap2_mcspi_cs *cs;
837
838 mcspi = spi_master_get_devdata(spi->master);
839
840 if (spi->controller_state) {
841 /* Unlink controller state from context save list */
842 cs = spi->controller_state;
843 list_del(&cs->node);
844
845 }
846
847 if (spi->chip_select < spi->master->num_chipselect) {
848 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
849
850 if (mcspi_dma->dma_rx_channel != -1) {
851 omap_free_dma(mcspi_dma->dma_rx_channel);
852 mcspi_dma->dma_rx_channel = -1;
853 }
854 if (mcspi_dma->dma_tx_channel != -1) {
855 omap_free_dma(mcspi_dma->dma_tx_channel);
856 mcspi_dma->dma_tx_channel = -1;
857 }
858 }
859 }
860
861 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
862 {
863
864 /* We only enable one channel at a time -- the one whose message is
865 * -- although this controller would gladly
866 * arbitrate among multiple channels. This corresponds to "single
867 * channel" master mode. As a side effect, we need to manage the
868 * chipselect with the FORCE bit ... CS != channel enable.
869 */
870
871 struct spi_device *spi;
872 struct spi_transfer *t = NULL;
873 int cs_active = 0;
874 struct omap2_mcspi_cs *cs;
875 struct omap2_mcspi_device_config *cd;
876 int par_override = 0;
877 int status = 0;
878 u32 chconf;
879
880 spi = m->spi;
881 cs = spi->controller_state;
882 cd = spi->controller_data;
883
884 omap2_mcspi_set_enable(spi, 1);
885 list_for_each_entry(t, &m->transfers, transfer_list) {
886 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
887 status = -EINVAL;
888 break;
889 }
890 if (par_override || t->speed_hz || t->bits_per_word) {
891 par_override = 1;
892 status = omap2_mcspi_setup_transfer(spi, t);
893 if (status < 0)
894 break;
895 if (!t->speed_hz && !t->bits_per_word)
896 par_override = 0;
897 }
898
899 if (!cs_active) {
900 omap2_mcspi_force_cs(spi, 1);
901 cs_active = 1;
902 }
903
904 chconf = mcspi_cached_chconf0(spi);
905 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
906 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
907
908 if (t->tx_buf == NULL)
909 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
910 else if (t->rx_buf == NULL)
911 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
912
913 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
914 /* Turbo mode is for more than one word */
915 if (t->len > ((cs->word_len + 7) >> 3))
916 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
917 }
918
919 mcspi_write_chconf0(spi, chconf);
920
921 if (t->len) {
922 unsigned count;
923
924 /* RX_ONLY mode needs dummy data in TX reg */
925 if (t->tx_buf == NULL)
926 __raw_writel(0, cs->base
927 + OMAP2_MCSPI_TX0);
928
929 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
930 count = omap2_mcspi_txrx_dma(spi, t);
931 else
932 count = omap2_mcspi_txrx_pio(spi, t);
933 m->actual_length += count;
934
935 if (count != t->len) {
936 status = -EIO;
937 break;
938 }
939 }
940
941 if (t->delay_usecs)
942 udelay(t->delay_usecs);
943
944 /* ignore the "leave it on after last xfer" hint */
945 if (t->cs_change) {
946 omap2_mcspi_force_cs(spi, 0);
947 cs_active = 0;
948 }
949 }
950 /* Restore defaults if they were overriden */
951 if (par_override) {
952 par_override = 0;
953 status = omap2_mcspi_setup_transfer(spi, NULL);
954 }
955
956 if (cs_active)
957 omap2_mcspi_force_cs(spi, 0);
958
959 omap2_mcspi_set_enable(spi, 0);
960
961 m->status = status;
962
963 }
964
965 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
966 struct spi_message *m)
967 {
968 struct omap2_mcspi *mcspi;
969 struct spi_transfer *t;
970
971 mcspi = spi_master_get_devdata(master);
972 m->actual_length = 0;
973 m->status = 0;
974
975 /* reject invalid messages and transfers */
976 if (list_empty(&m->transfers))
977 return -EINVAL;
978 list_for_each_entry(t, &m->transfers, transfer_list) {
979 const void *tx_buf = t->tx_buf;
980 void *rx_buf = t->rx_buf;
981 unsigned len = t->len;
982
983 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
984 || (len && !(rx_buf || tx_buf))
985 || (t->bits_per_word &&
986 ( t->bits_per_word < 4
987 || t->bits_per_word > 32))) {
988 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
989 t->speed_hz,
990 len,
991 tx_buf ? "tx" : "",
992 rx_buf ? "rx" : "",
993 t->bits_per_word);
994 return -EINVAL;
995 }
996 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
997 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
998 t->speed_hz,
999 OMAP2_MCSPI_MAX_FREQ >> 15);
1000 return -EINVAL;
1001 }
1002
1003 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1004 continue;
1005
1006 if (tx_buf != NULL) {
1007 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1008 len, DMA_TO_DEVICE);
1009 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1010 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1011 'T', len);
1012 return -EINVAL;
1013 }
1014 }
1015 if (rx_buf != NULL) {
1016 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1017 DMA_FROM_DEVICE);
1018 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1019 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1020 'R', len);
1021 if (tx_buf != NULL)
1022 dma_unmap_single(mcspi->dev, t->tx_dma,
1023 len, DMA_TO_DEVICE);
1024 return -EINVAL;
1025 }
1026 }
1027 }
1028
1029 omap2_mcspi_work(mcspi, m);
1030 spi_finalize_current_message(master);
1031 return 0;
1032 }
1033
1034 static int __init omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1035 {
1036 struct spi_master *master = mcspi->master;
1037 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1038 int ret = 0;
1039
1040 ret = omap2_mcspi_enable_clocks(mcspi);
1041 if (ret < 0)
1042 return ret;
1043
1044 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1045 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1046 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1047
1048 omap2_mcspi_set_master_mode(master);
1049 omap2_mcspi_disable_clocks(mcspi);
1050 return 0;
1051 }
1052
1053 static int omap_mcspi_runtime_resume(struct device *dev)
1054 {
1055 struct omap2_mcspi *mcspi;
1056 struct spi_master *master;
1057
1058 master = dev_get_drvdata(dev);
1059 mcspi = spi_master_get_devdata(master);
1060 omap2_mcspi_restore_ctx(mcspi);
1061
1062 return 0;
1063 }
1064
1065 static struct omap2_mcspi_platform_config omap2_pdata = {
1066 .regs_offset = 0,
1067 };
1068
1069 static struct omap2_mcspi_platform_config omap4_pdata = {
1070 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1071 };
1072
1073 static const struct of_device_id omap_mcspi_of_match[] = {
1074 {
1075 .compatible = "ti,omap2-mcspi",
1076 .data = &omap2_pdata,
1077 },
1078 {
1079 .compatible = "ti,omap4-mcspi",
1080 .data = &omap4_pdata,
1081 },
1082 { },
1083 };
1084 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1085
1086 static int __devinit omap2_mcspi_probe(struct platform_device *pdev)
1087 {
1088 struct spi_master *master;
1089 struct omap2_mcspi_platform_config *pdata;
1090 struct omap2_mcspi *mcspi;
1091 struct resource *r;
1092 int status = 0, i;
1093 u32 regs_offset = 0;
1094 static int bus_num = 1;
1095 struct device_node *node = pdev->dev.of_node;
1096 const struct of_device_id *match;
1097
1098 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1099 if (master == NULL) {
1100 dev_dbg(&pdev->dev, "master allocation failed\n");
1101 return -ENOMEM;
1102 }
1103
1104 /* the spi->mode bits understood by this driver: */
1105 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1106
1107 master->setup = omap2_mcspi_setup;
1108 master->prepare_transfer_hardware = omap2_prepare_transfer;
1109 master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1110 master->transfer_one_message = omap2_mcspi_transfer_one_message;
1111 master->cleanup = omap2_mcspi_cleanup;
1112 master->dev.of_node = node;
1113
1114 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1115 if (match) {
1116 u32 num_cs = 1; /* default number of chipselect */
1117 pdata = match->data;
1118
1119 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1120 master->num_chipselect = num_cs;
1121 master->bus_num = bus_num++;
1122 } else {
1123 pdata = pdev->dev.platform_data;
1124 master->num_chipselect = pdata->num_cs;
1125 if (pdev->id != -1)
1126 master->bus_num = pdev->id;
1127 }
1128 regs_offset = pdata->regs_offset;
1129
1130 dev_set_drvdata(&pdev->dev, master);
1131
1132 mcspi = spi_master_get_devdata(master);
1133 mcspi->master = master;
1134
1135 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1136 if (r == NULL) {
1137 status = -ENODEV;
1138 goto free_master;
1139 }
1140
1141 r->start += regs_offset;
1142 r->end += regs_offset;
1143 mcspi->phys = r->start;
1144
1145 mcspi->base = devm_request_and_ioremap(&pdev->dev, r);
1146 if (!mcspi->base) {
1147 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1148 status = -ENOMEM;
1149 goto free_master;
1150 }
1151
1152 mcspi->dev = &pdev->dev;
1153
1154 INIT_LIST_HEAD(&mcspi->ctx.cs);
1155
1156 mcspi->dma_channels = kcalloc(master->num_chipselect,
1157 sizeof(struct omap2_mcspi_dma),
1158 GFP_KERNEL);
1159
1160 if (mcspi->dma_channels == NULL)
1161 goto free_master;
1162
1163 for (i = 0; i < master->num_chipselect; i++) {
1164 char dma_ch_name[14];
1165 struct resource *dma_res;
1166
1167 sprintf(dma_ch_name, "rx%d", i);
1168 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1169 dma_ch_name);
1170 if (!dma_res) {
1171 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1172 status = -ENODEV;
1173 break;
1174 }
1175
1176 mcspi->dma_channels[i].dma_rx_channel = -1;
1177 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1178 sprintf(dma_ch_name, "tx%d", i);
1179 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1180 dma_ch_name);
1181 if (!dma_res) {
1182 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1183 status = -ENODEV;
1184 break;
1185 }
1186
1187 mcspi->dma_channels[i].dma_tx_channel = -1;
1188 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1189 }
1190
1191 if (status < 0)
1192 goto dma_chnl_free;
1193
1194 pm_runtime_use_autosuspend(&pdev->dev);
1195 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1196 pm_runtime_enable(&pdev->dev);
1197
1198 if (status || omap2_mcspi_master_setup(mcspi) < 0)
1199 goto disable_pm;
1200
1201 status = spi_register_master(master);
1202 if (status < 0)
1203 goto err_spi_register;
1204
1205 return status;
1206
1207 err_spi_register:
1208 spi_master_put(master);
1209 disable_pm:
1210 pm_runtime_disable(&pdev->dev);
1211 dma_chnl_free:
1212 kfree(mcspi->dma_channels);
1213 free_master:
1214 kfree(master);
1215 platform_set_drvdata(pdev, NULL);
1216 return status;
1217 }
1218
1219 static int __devexit omap2_mcspi_remove(struct platform_device *pdev)
1220 {
1221 struct spi_master *master;
1222 struct omap2_mcspi *mcspi;
1223 struct omap2_mcspi_dma *dma_channels;
1224
1225 master = dev_get_drvdata(&pdev->dev);
1226 mcspi = spi_master_get_devdata(master);
1227 dma_channels = mcspi->dma_channels;
1228
1229 omap2_mcspi_disable_clocks(mcspi);
1230 pm_runtime_disable(&pdev->dev);
1231
1232 spi_unregister_master(master);
1233 kfree(dma_channels);
1234 platform_set_drvdata(pdev, NULL);
1235
1236 return 0;
1237 }
1238
1239 /* work with hotplug and coldplug */
1240 MODULE_ALIAS("platform:omap2_mcspi");
1241
1242 #ifdef CONFIG_SUSPEND
1243 /*
1244 * When SPI wake up from off-mode, CS is in activate state. If it was in
1245 * unactive state when driver was suspend, then force it to unactive state at
1246 * wake up.
1247 */
1248 static int omap2_mcspi_resume(struct device *dev)
1249 {
1250 struct spi_master *master = dev_get_drvdata(dev);
1251 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1252 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1253 struct omap2_mcspi_cs *cs;
1254
1255 omap2_mcspi_enable_clocks(mcspi);
1256 list_for_each_entry(cs, &ctx->cs, node) {
1257 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1258 /*
1259 * We need to toggle CS state for OMAP take this
1260 * change in account.
1261 */
1262 MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 1);
1263 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1264 MOD_REG_BIT(cs->chconf0, OMAP2_MCSPI_CHCONF_FORCE, 0);
1265 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1266 }
1267 }
1268 omap2_mcspi_disable_clocks(mcspi);
1269 return 0;
1270 }
1271 #else
1272 #define omap2_mcspi_resume NULL
1273 #endif
1274
1275 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1276 .resume = omap2_mcspi_resume,
1277 .runtime_resume = omap_mcspi_runtime_resume,
1278 };
1279
1280 static struct platform_driver omap2_mcspi_driver = {
1281 .driver = {
1282 .name = "omap2_mcspi",
1283 .owner = THIS_MODULE,
1284 .pm = &omap2_mcspi_pm_ops,
1285 .of_match_table = omap_mcspi_of_match,
1286 },
1287 .probe = omap2_mcspi_probe,
1288 .remove = __devexit_p(omap2_mcspi_remove),
1289 };
1290
1291 module_platform_driver(omap2_mcspi_driver);
1292 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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