2 * OMAP2 McSPI controller driver
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/interrupt.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/delay.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/dmaengine.h>
31 #include <linux/omap-dma.h>
32 #include <linux/platform_device.h>
33 #include <linux/err.h>
34 #include <linux/clk.h>
36 #include <linux/slab.h>
37 #include <linux/pm_runtime.h>
39 #include <linux/of_device.h>
40 #include <linux/gcd.h>
42 #include <linux/spi/spi.h>
44 #include <linux/platform_data/spi-omap2-mcspi.h>
46 #define OMAP2_MCSPI_MAX_FREQ 48000000
47 #define OMAP2_MCSPI_MAX_DIVIDER 4096
48 #define OMAP2_MCSPI_MAX_FIFODEPTH 64
49 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
50 #define SPI_AUTOSUSPEND_TIMEOUT 2000
52 #define OMAP2_MCSPI_REVISION 0x00
53 #define OMAP2_MCSPI_SYSSTATUS 0x14
54 #define OMAP2_MCSPI_IRQSTATUS 0x18
55 #define OMAP2_MCSPI_IRQENABLE 0x1c
56 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
57 #define OMAP2_MCSPI_SYST 0x24
58 #define OMAP2_MCSPI_MODULCTRL 0x28
59 #define OMAP2_MCSPI_XFERLEVEL 0x7c
61 /* per-channel banks, 0x14 bytes each, first is: */
62 #define OMAP2_MCSPI_CHCONF0 0x2c
63 #define OMAP2_MCSPI_CHSTAT0 0x30
64 #define OMAP2_MCSPI_CHCTRL0 0x34
65 #define OMAP2_MCSPI_TX0 0x38
66 #define OMAP2_MCSPI_RX0 0x3c
68 /* per-register bitmasks: */
69 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
71 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
72 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
73 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
75 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
76 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
77 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
78 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
79 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
80 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
81 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
82 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
83 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
84 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
85 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
86 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
87 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
88 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
89 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
90 #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
91 #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
92 #define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
94 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
95 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
96 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
97 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
99 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
100 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
102 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
104 /* We have 2 DMA channels per CS, one for RX and one for TX */
105 struct omap2_mcspi_dma
{
106 struct dma_chan
*dma_tx
;
107 struct dma_chan
*dma_rx
;
112 struct completion dma_tx_completion
;
113 struct completion dma_rx_completion
;
115 char dma_rx_ch_name
[14];
116 char dma_tx_ch_name
[14];
119 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
120 * cache operations; better heuristics consider wordsize and bitrate.
122 #define DMA_MIN_BYTES 160
126 * Used for context save and restore, structure members to be updated whenever
127 * corresponding registers are modified.
129 struct omap2_mcspi_regs
{
136 struct spi_master
*master
;
137 /* Virtual base address of the controller */
140 /* SPI1 has 4 channels, while SPI2 has 2 */
141 struct omap2_mcspi_dma
*dma_channels
;
143 struct omap2_mcspi_regs ctx
;
145 unsigned int pin_dir
:1;
148 struct omap2_mcspi_cs
{
153 struct list_head node
;
154 /* Context save and restore shadow register */
155 u32 chconf0
, chctrl0
;
158 static inline void mcspi_write_reg(struct spi_master
*master
,
161 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
163 writel_relaxed(val
, mcspi
->base
+ idx
);
166 static inline u32
mcspi_read_reg(struct spi_master
*master
, int idx
)
168 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
170 return readl_relaxed(mcspi
->base
+ idx
);
173 static inline void mcspi_write_cs_reg(const struct spi_device
*spi
,
176 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
178 writel_relaxed(val
, cs
->base
+ idx
);
181 static inline u32
mcspi_read_cs_reg(const struct spi_device
*spi
, int idx
)
183 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
185 return readl_relaxed(cs
->base
+ idx
);
188 static inline u32
mcspi_cached_chconf0(const struct spi_device
*spi
)
190 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
195 static inline void mcspi_write_chconf0(const struct spi_device
*spi
, u32 val
)
197 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
200 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCONF0
, val
);
201 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHCONF0
);
204 static inline int mcspi_bytes_per_word(int word_len
)
208 else if (word_len
<= 16)
210 else /* word_len <= 32 */
214 static void omap2_mcspi_set_dma_req(const struct spi_device
*spi
,
215 int is_read
, int enable
)
219 l
= mcspi_cached_chconf0(spi
);
221 if (is_read
) /* 1 is read, 0 write */
222 rw
= OMAP2_MCSPI_CHCONF_DMAR
;
224 rw
= OMAP2_MCSPI_CHCONF_DMAW
;
231 mcspi_write_chconf0(spi
, l
);
234 static void omap2_mcspi_set_enable(const struct spi_device
*spi
, int enable
)
236 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
241 l
|= OMAP2_MCSPI_CHCTRL_EN
;
243 l
&= ~OMAP2_MCSPI_CHCTRL_EN
;
245 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
, cs
->chctrl0
);
246 /* Flash post-writes */
247 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
);
250 static void omap2_mcspi_force_cs(struct spi_device
*spi
, int cs_active
)
254 l
= mcspi_cached_chconf0(spi
);
256 l
|= OMAP2_MCSPI_CHCONF_FORCE
;
258 l
&= ~OMAP2_MCSPI_CHCONF_FORCE
;
260 mcspi_write_chconf0(spi
, l
);
263 static void omap2_mcspi_set_master_mode(struct spi_master
*master
)
265 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
266 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
270 * Setup when switching from (reset default) slave mode
271 * to single-channel master mode
273 l
= mcspi_read_reg(master
, OMAP2_MCSPI_MODULCTRL
);
274 l
&= ~(OMAP2_MCSPI_MODULCTRL_STEST
| OMAP2_MCSPI_MODULCTRL_MS
);
275 l
|= OMAP2_MCSPI_MODULCTRL_SINGLE
;
276 mcspi_write_reg(master
, OMAP2_MCSPI_MODULCTRL
, l
);
281 static void omap2_mcspi_set_fifo(const struct spi_device
*spi
,
282 struct spi_transfer
*t
, int enable
)
284 struct spi_master
*master
= spi
->master
;
285 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
286 struct omap2_mcspi
*mcspi
;
288 int max_fifo_depth
, fifo_depth
, bytes_per_word
;
289 u32 chconf
, xferlevel
;
291 mcspi
= spi_master_get_devdata(master
);
293 chconf
= mcspi_cached_chconf0(spi
);
295 bytes_per_word
= mcspi_bytes_per_word(cs
->word_len
);
296 if (t
->len
% bytes_per_word
!= 0)
299 if (t
->rx_buf
!= NULL
&& t
->tx_buf
!= NULL
)
300 max_fifo_depth
= OMAP2_MCSPI_MAX_FIFODEPTH
/ 2;
302 max_fifo_depth
= OMAP2_MCSPI_MAX_FIFODEPTH
;
304 fifo_depth
= gcd(t
->len
, max_fifo_depth
);
305 if (fifo_depth
< 2 || fifo_depth
% bytes_per_word
!= 0)
308 wcnt
= t
->len
/ bytes_per_word
;
309 if (wcnt
> OMAP2_MCSPI_MAX_FIFOWCNT
)
312 xferlevel
= wcnt
<< 16;
313 if (t
->rx_buf
!= NULL
) {
314 chconf
|= OMAP2_MCSPI_CHCONF_FFER
;
315 xferlevel
|= (fifo_depth
- 1) << 8;
317 if (t
->tx_buf
!= NULL
) {
318 chconf
|= OMAP2_MCSPI_CHCONF_FFET
;
319 xferlevel
|= fifo_depth
- 1;
322 mcspi_write_reg(master
, OMAP2_MCSPI_XFERLEVEL
, xferlevel
);
323 mcspi_write_chconf0(spi
, chconf
);
324 mcspi
->fifo_depth
= fifo_depth
;
330 if (t
->rx_buf
!= NULL
)
331 chconf
&= ~OMAP2_MCSPI_CHCONF_FFER
;
333 chconf
&= ~OMAP2_MCSPI_CHCONF_FFET
;
335 mcspi_write_chconf0(spi
, chconf
);
336 mcspi
->fifo_depth
= 0;
339 static void omap2_mcspi_restore_ctx(struct omap2_mcspi
*mcspi
)
341 struct spi_master
*spi_cntrl
= mcspi
->master
;
342 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
343 struct omap2_mcspi_cs
*cs
;
345 /* McSPI: context restore */
346 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_MODULCTRL
, ctx
->modulctrl
);
347 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_WAKEUPENABLE
, ctx
->wakeupenable
);
349 list_for_each_entry(cs
, &ctx
->cs
, node
)
350 writel_relaxed(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
353 static int mcspi_wait_for_reg_bit(void __iomem
*reg
, unsigned long bit
)
355 unsigned long timeout
;
357 timeout
= jiffies
+ msecs_to_jiffies(1000);
358 while (!(readl_relaxed(reg
) & bit
)) {
359 if (time_after(jiffies
, timeout
)) {
360 if (!(readl_relaxed(reg
) & bit
))
370 static void omap2_mcspi_rx_callback(void *data
)
372 struct spi_device
*spi
= data
;
373 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
374 struct omap2_mcspi_dma
*mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
376 /* We must disable the DMA RX request */
377 omap2_mcspi_set_dma_req(spi
, 1, 0);
379 complete(&mcspi_dma
->dma_rx_completion
);
382 static void omap2_mcspi_tx_callback(void *data
)
384 struct spi_device
*spi
= data
;
385 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
386 struct omap2_mcspi_dma
*mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
388 /* We must disable the DMA TX request */
389 omap2_mcspi_set_dma_req(spi
, 0, 0);
391 complete(&mcspi_dma
->dma_tx_completion
);
394 static void omap2_mcspi_tx_dma(struct spi_device
*spi
,
395 struct spi_transfer
*xfer
,
396 struct dma_slave_config cfg
)
398 struct omap2_mcspi
*mcspi
;
399 struct omap2_mcspi_dma
*mcspi_dma
;
402 mcspi
= spi_master_get_devdata(spi
->master
);
403 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
406 if (mcspi_dma
->dma_tx
) {
407 struct dma_async_tx_descriptor
*tx
;
408 struct scatterlist sg
;
410 dmaengine_slave_config(mcspi_dma
->dma_tx
, &cfg
);
412 sg_init_table(&sg
, 1);
413 sg_dma_address(&sg
) = xfer
->tx_dma
;
414 sg_dma_len(&sg
) = xfer
->len
;
416 tx
= dmaengine_prep_slave_sg(mcspi_dma
->dma_tx
, &sg
, 1,
417 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
419 tx
->callback
= omap2_mcspi_tx_callback
;
420 tx
->callback_param
= spi
;
421 dmaengine_submit(tx
);
423 /* FIXME: fall back to PIO? */
426 dma_async_issue_pending(mcspi_dma
->dma_tx
);
427 omap2_mcspi_set_dma_req(spi
, 0, 1);
432 omap2_mcspi_rx_dma(struct spi_device
*spi
, struct spi_transfer
*xfer
,
433 struct dma_slave_config cfg
,
436 struct omap2_mcspi
*mcspi
;
437 struct omap2_mcspi_dma
*mcspi_dma
;
438 unsigned int count
, dma_count
;
441 int word_len
, element_count
;
442 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
443 mcspi
= spi_master_get_devdata(spi
->master
);
444 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
446 dma_count
= xfer
->len
;
448 if (mcspi
->fifo_depth
== 0)
451 word_len
= cs
->word_len
;
452 l
= mcspi_cached_chconf0(spi
);
455 element_count
= count
;
456 else if (word_len
<= 16)
457 element_count
= count
>> 1;
458 else /* word_len <= 32 */
459 element_count
= count
>> 2;
461 if (mcspi_dma
->dma_rx
) {
462 struct dma_async_tx_descriptor
*tx
;
463 struct scatterlist sg
;
465 dmaengine_slave_config(mcspi_dma
->dma_rx
, &cfg
);
467 if ((l
& OMAP2_MCSPI_CHCONF_TURBO
) && mcspi
->fifo_depth
== 0)
470 sg_init_table(&sg
, 1);
471 sg_dma_address(&sg
) = xfer
->rx_dma
;
472 sg_dma_len(&sg
) = dma_count
;
474 tx
= dmaengine_prep_slave_sg(mcspi_dma
->dma_rx
, &sg
, 1,
475 DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
|
478 tx
->callback
= omap2_mcspi_rx_callback
;
479 tx
->callback_param
= spi
;
480 dmaengine_submit(tx
);
482 /* FIXME: fall back to PIO? */
486 dma_async_issue_pending(mcspi_dma
->dma_rx
);
487 omap2_mcspi_set_dma_req(spi
, 1, 1);
489 wait_for_completion(&mcspi_dma
->dma_rx_completion
);
490 dma_unmap_single(mcspi
->dev
, xfer
->rx_dma
, count
,
493 if (mcspi
->fifo_depth
> 0)
496 omap2_mcspi_set_enable(spi
, 0);
498 elements
= element_count
- 1;
500 if (l
& OMAP2_MCSPI_CHCONF_TURBO
) {
503 if (likely(mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHSTAT0
)
504 & OMAP2_MCSPI_CHSTAT_RXS
)) {
507 w
= mcspi_read_cs_reg(spi
, OMAP2_MCSPI_RX0
);
509 ((u8
*)xfer
->rx_buf
)[elements
++] = w
;
510 else if (word_len
<= 16)
511 ((u16
*)xfer
->rx_buf
)[elements
++] = w
;
512 else /* word_len <= 32 */
513 ((u32
*)xfer
->rx_buf
)[elements
++] = w
;
515 int bytes_per_word
= mcspi_bytes_per_word(word_len
);
516 dev_err(&spi
->dev
, "DMA RX penultimate word empty\n");
517 count
-= (bytes_per_word
<< 1);
518 omap2_mcspi_set_enable(spi
, 1);
522 if (likely(mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHSTAT0
)
523 & OMAP2_MCSPI_CHSTAT_RXS
)) {
526 w
= mcspi_read_cs_reg(spi
, OMAP2_MCSPI_RX0
);
528 ((u8
*)xfer
->rx_buf
)[elements
] = w
;
529 else if (word_len
<= 16)
530 ((u16
*)xfer
->rx_buf
)[elements
] = w
;
531 else /* word_len <= 32 */
532 ((u32
*)xfer
->rx_buf
)[elements
] = w
;
534 dev_err(&spi
->dev
, "DMA RX last word empty\n");
535 count
-= mcspi_bytes_per_word(word_len
);
537 omap2_mcspi_set_enable(spi
, 1);
542 omap2_mcspi_txrx_dma(struct spi_device
*spi
, struct spi_transfer
*xfer
)
544 struct omap2_mcspi
*mcspi
;
545 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
546 struct omap2_mcspi_dma
*mcspi_dma
;
551 struct dma_slave_config cfg
;
552 enum dma_slave_buswidth width
;
555 void __iomem
*chstat_reg
;
556 void __iomem
*irqstat_reg
;
559 mcspi
= spi_master_get_devdata(spi
->master
);
560 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
561 l
= mcspi_cached_chconf0(spi
);
564 if (cs
->word_len
<= 8) {
565 width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
567 } else if (cs
->word_len
<= 16) {
568 width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
571 width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
578 if (mcspi
->fifo_depth
> 0) {
579 if (count
> mcspi
->fifo_depth
)
580 burst
= mcspi
->fifo_depth
/ es
;
585 memset(&cfg
, 0, sizeof(cfg
));
586 cfg
.src_addr
= cs
->phys
+ OMAP2_MCSPI_RX0
;
587 cfg
.dst_addr
= cs
->phys
+ OMAP2_MCSPI_TX0
;
588 cfg
.src_addr_width
= width
;
589 cfg
.dst_addr_width
= width
;
590 cfg
.src_maxburst
= burst
;
591 cfg
.dst_maxburst
= burst
;
597 omap2_mcspi_tx_dma(spi
, xfer
, cfg
);
600 count
= omap2_mcspi_rx_dma(spi
, xfer
, cfg
, es
);
603 wait_for_completion(&mcspi_dma
->dma_tx_completion
);
604 dma_unmap_single(mcspi
->dev
, xfer
->tx_dma
, xfer
->len
,
607 if (mcspi
->fifo_depth
> 0) {
608 irqstat_reg
= mcspi
->base
+ OMAP2_MCSPI_IRQSTATUS
;
610 if (mcspi_wait_for_reg_bit(irqstat_reg
,
611 OMAP2_MCSPI_IRQSTATUS_EOW
) < 0)
612 dev_err(&spi
->dev
, "EOW timed out\n");
614 mcspi_write_reg(mcspi
->master
, OMAP2_MCSPI_IRQSTATUS
,
615 OMAP2_MCSPI_IRQSTATUS_EOW
);
618 /* for TX_ONLY mode, be sure all words have shifted out */
620 chstat_reg
= cs
->base
+ OMAP2_MCSPI_CHSTAT0
;
621 if (mcspi
->fifo_depth
> 0) {
622 wait_res
= mcspi_wait_for_reg_bit(chstat_reg
,
623 OMAP2_MCSPI_CHSTAT_TXFFE
);
625 dev_err(&spi
->dev
, "TXFFE timed out\n");
627 wait_res
= mcspi_wait_for_reg_bit(chstat_reg
,
628 OMAP2_MCSPI_CHSTAT_TXS
);
630 dev_err(&spi
->dev
, "TXS timed out\n");
633 (mcspi_wait_for_reg_bit(chstat_reg
,
634 OMAP2_MCSPI_CHSTAT_EOT
) < 0))
635 dev_err(&spi
->dev
, "EOT timed out\n");
642 omap2_mcspi_txrx_pio(struct spi_device
*spi
, struct spi_transfer
*xfer
)
644 struct omap2_mcspi
*mcspi
;
645 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
646 unsigned int count
, c
;
648 void __iomem
*base
= cs
->base
;
649 void __iomem
*tx_reg
;
650 void __iomem
*rx_reg
;
651 void __iomem
*chstat_reg
;
654 mcspi
= spi_master_get_devdata(spi
->master
);
657 word_len
= cs
->word_len
;
659 l
= mcspi_cached_chconf0(spi
);
661 /* We store the pre-calculated register addresses on stack to speed
662 * up the transfer loop. */
663 tx_reg
= base
+ OMAP2_MCSPI_TX0
;
664 rx_reg
= base
+ OMAP2_MCSPI_RX0
;
665 chstat_reg
= base
+ OMAP2_MCSPI_CHSTAT0
;
667 if (c
< (word_len
>>3))
680 if (mcspi_wait_for_reg_bit(chstat_reg
,
681 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
682 dev_err(&spi
->dev
, "TXS timed out\n");
685 dev_vdbg(&spi
->dev
, "write-%d %02x\n",
687 writel_relaxed(*tx
++, tx_reg
);
690 if (mcspi_wait_for_reg_bit(chstat_reg
,
691 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
692 dev_err(&spi
->dev
, "RXS timed out\n");
696 if (c
== 1 && tx
== NULL
&&
697 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
698 omap2_mcspi_set_enable(spi
, 0);
699 *rx
++ = readl_relaxed(rx_reg
);
700 dev_vdbg(&spi
->dev
, "read-%d %02x\n",
701 word_len
, *(rx
- 1));
702 if (mcspi_wait_for_reg_bit(chstat_reg
,
703 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
709 } else if (c
== 0 && tx
== NULL
) {
710 omap2_mcspi_set_enable(spi
, 0);
713 *rx
++ = readl_relaxed(rx_reg
);
714 dev_vdbg(&spi
->dev
, "read-%d %02x\n",
715 word_len
, *(rx
- 1));
718 } else if (word_len
<= 16) {
727 if (mcspi_wait_for_reg_bit(chstat_reg
,
728 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
729 dev_err(&spi
->dev
, "TXS timed out\n");
732 dev_vdbg(&spi
->dev
, "write-%d %04x\n",
734 writel_relaxed(*tx
++, tx_reg
);
737 if (mcspi_wait_for_reg_bit(chstat_reg
,
738 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
739 dev_err(&spi
->dev
, "RXS timed out\n");
743 if (c
== 2 && tx
== NULL
&&
744 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
745 omap2_mcspi_set_enable(spi
, 0);
746 *rx
++ = readl_relaxed(rx_reg
);
747 dev_vdbg(&spi
->dev
, "read-%d %04x\n",
748 word_len
, *(rx
- 1));
749 if (mcspi_wait_for_reg_bit(chstat_reg
,
750 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
756 } else if (c
== 0 && tx
== NULL
) {
757 omap2_mcspi_set_enable(spi
, 0);
760 *rx
++ = readl_relaxed(rx_reg
);
761 dev_vdbg(&spi
->dev
, "read-%d %04x\n",
762 word_len
, *(rx
- 1));
765 } else if (word_len
<= 32) {
774 if (mcspi_wait_for_reg_bit(chstat_reg
,
775 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
776 dev_err(&spi
->dev
, "TXS timed out\n");
779 dev_vdbg(&spi
->dev
, "write-%d %08x\n",
781 writel_relaxed(*tx
++, tx_reg
);
784 if (mcspi_wait_for_reg_bit(chstat_reg
,
785 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
786 dev_err(&spi
->dev
, "RXS timed out\n");
790 if (c
== 4 && tx
== NULL
&&
791 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
792 omap2_mcspi_set_enable(spi
, 0);
793 *rx
++ = readl_relaxed(rx_reg
);
794 dev_vdbg(&spi
->dev
, "read-%d %08x\n",
795 word_len
, *(rx
- 1));
796 if (mcspi_wait_for_reg_bit(chstat_reg
,
797 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
803 } else if (c
== 0 && tx
== NULL
) {
804 omap2_mcspi_set_enable(spi
, 0);
807 *rx
++ = readl_relaxed(rx_reg
);
808 dev_vdbg(&spi
->dev
, "read-%d %08x\n",
809 word_len
, *(rx
- 1));
814 /* for TX_ONLY mode, be sure all words have shifted out */
815 if (xfer
->rx_buf
== NULL
) {
816 if (mcspi_wait_for_reg_bit(chstat_reg
,
817 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
818 dev_err(&spi
->dev
, "TXS timed out\n");
819 } else if (mcspi_wait_for_reg_bit(chstat_reg
,
820 OMAP2_MCSPI_CHSTAT_EOT
) < 0)
821 dev_err(&spi
->dev
, "EOT timed out\n");
823 /* disable chan to purge rx datas received in TX_ONLY transfer,
824 * otherwise these rx datas will affect the direct following
827 omap2_mcspi_set_enable(spi
, 0);
830 omap2_mcspi_set_enable(spi
, 1);
834 static u32
omap2_mcspi_calc_divisor(u32 speed_hz
)
838 for (div
= 0; div
< 15; div
++)
839 if (speed_hz
>= (OMAP2_MCSPI_MAX_FREQ
>> div
))
845 /* called only when no transfer is active to this device */
846 static int omap2_mcspi_setup_transfer(struct spi_device
*spi
,
847 struct spi_transfer
*t
)
849 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
850 struct omap2_mcspi
*mcspi
;
851 struct spi_master
*spi_cntrl
;
852 u32 l
= 0, clkd
= 0, div
, extclk
= 0, clkg
= 0;
853 u8 word_len
= spi
->bits_per_word
;
854 u32 speed_hz
= spi
->max_speed_hz
;
856 mcspi
= spi_master_get_devdata(spi
->master
);
857 spi_cntrl
= mcspi
->master
;
859 if (t
!= NULL
&& t
->bits_per_word
)
860 word_len
= t
->bits_per_word
;
862 cs
->word_len
= word_len
;
864 if (t
&& t
->speed_hz
)
865 speed_hz
= t
->speed_hz
;
867 speed_hz
= min_t(u32
, speed_hz
, OMAP2_MCSPI_MAX_FREQ
);
868 if (speed_hz
< (OMAP2_MCSPI_MAX_FREQ
/ OMAP2_MCSPI_MAX_DIVIDER
)) {
869 clkd
= omap2_mcspi_calc_divisor(speed_hz
);
870 speed_hz
= OMAP2_MCSPI_MAX_FREQ
>> clkd
;
873 div
= (OMAP2_MCSPI_MAX_FREQ
+ speed_hz
- 1) / speed_hz
;
874 speed_hz
= OMAP2_MCSPI_MAX_FREQ
/ div
;
875 clkd
= (div
- 1) & 0xf;
876 extclk
= (div
- 1) >> 4;
877 clkg
= OMAP2_MCSPI_CHCONF_CLKG
;
880 l
= mcspi_cached_chconf0(spi
);
882 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
883 * REVISIT: this controller could support SPI_3WIRE mode.
885 if (mcspi
->pin_dir
== MCSPI_PINDIR_D0_IN_D1_OUT
) {
886 l
&= ~OMAP2_MCSPI_CHCONF_IS
;
887 l
&= ~OMAP2_MCSPI_CHCONF_DPE1
;
888 l
|= OMAP2_MCSPI_CHCONF_DPE0
;
890 l
|= OMAP2_MCSPI_CHCONF_IS
;
891 l
|= OMAP2_MCSPI_CHCONF_DPE1
;
892 l
&= ~OMAP2_MCSPI_CHCONF_DPE0
;
896 l
&= ~OMAP2_MCSPI_CHCONF_WL_MASK
;
897 l
|= (word_len
- 1) << 7;
899 /* set chipselect polarity; manage with FORCE */
900 if (!(spi
->mode
& SPI_CS_HIGH
))
901 l
|= OMAP2_MCSPI_CHCONF_EPOL
; /* active-low; normal */
903 l
&= ~OMAP2_MCSPI_CHCONF_EPOL
;
905 /* set clock divisor */
906 l
&= ~OMAP2_MCSPI_CHCONF_CLKD_MASK
;
909 /* set clock granularity */
910 l
&= ~OMAP2_MCSPI_CHCONF_CLKG
;
913 cs
->chctrl0
&= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK
;
914 cs
->chctrl0
|= extclk
<< 8;
915 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
, cs
->chctrl0
);
918 /* set SPI mode 0..3 */
919 if (spi
->mode
& SPI_CPOL
)
920 l
|= OMAP2_MCSPI_CHCONF_POL
;
922 l
&= ~OMAP2_MCSPI_CHCONF_POL
;
923 if (spi
->mode
& SPI_CPHA
)
924 l
|= OMAP2_MCSPI_CHCONF_PHA
;
926 l
&= ~OMAP2_MCSPI_CHCONF_PHA
;
928 mcspi_write_chconf0(spi
, l
);
930 cs
->mode
= spi
->mode
;
932 dev_dbg(&spi
->dev
, "setup: speed %d, sample %s edge, clk %s\n",
934 (spi
->mode
& SPI_CPHA
) ? "trailing" : "leading",
935 (spi
->mode
& SPI_CPOL
) ? "inverted" : "normal");
941 * Note that we currently allow DMA only if we get a channel
942 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
944 static int omap2_mcspi_request_dma(struct spi_device
*spi
)
946 struct spi_master
*master
= spi
->master
;
947 struct omap2_mcspi
*mcspi
;
948 struct omap2_mcspi_dma
*mcspi_dma
;
952 mcspi
= spi_master_get_devdata(master
);
953 mcspi_dma
= mcspi
->dma_channels
+ spi
->chip_select
;
955 init_completion(&mcspi_dma
->dma_rx_completion
);
956 init_completion(&mcspi_dma
->dma_tx_completion
);
959 dma_cap_set(DMA_SLAVE
, mask
);
960 sig
= mcspi_dma
->dma_rx_sync_dev
;
963 dma_request_slave_channel_compat(mask
, omap_dma_filter_fn
,
965 mcspi_dma
->dma_rx_ch_name
);
966 if (!mcspi_dma
->dma_rx
)
969 sig
= mcspi_dma
->dma_tx_sync_dev
;
971 dma_request_slave_channel_compat(mask
, omap_dma_filter_fn
,
973 mcspi_dma
->dma_tx_ch_name
);
975 if (!mcspi_dma
->dma_tx
) {
976 dma_release_channel(mcspi_dma
->dma_rx
);
977 mcspi_dma
->dma_rx
= NULL
;
984 dev_warn(&spi
->dev
, "not using DMA for McSPI\n");
988 static int omap2_mcspi_setup(struct spi_device
*spi
)
991 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
992 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
993 struct omap2_mcspi_dma
*mcspi_dma
;
994 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
996 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
999 cs
= kzalloc(sizeof *cs
, GFP_KERNEL
);
1002 cs
->base
= mcspi
->base
+ spi
->chip_select
* 0x14;
1003 cs
->phys
= mcspi
->phys
+ spi
->chip_select
* 0x14;
1007 spi
->controller_state
= cs
;
1008 /* Link this to context save list */
1009 list_add_tail(&cs
->node
, &ctx
->cs
);
1012 if (!mcspi_dma
->dma_rx
|| !mcspi_dma
->dma_tx
) {
1013 ret
= omap2_mcspi_request_dma(spi
);
1014 if (ret
< 0 && ret
!= -EAGAIN
)
1018 ret
= pm_runtime_get_sync(mcspi
->dev
);
1022 ret
= omap2_mcspi_setup_transfer(spi
, NULL
);
1023 pm_runtime_mark_last_busy(mcspi
->dev
);
1024 pm_runtime_put_autosuspend(mcspi
->dev
);
1029 static void omap2_mcspi_cleanup(struct spi_device
*spi
)
1031 struct omap2_mcspi
*mcspi
;
1032 struct omap2_mcspi_dma
*mcspi_dma
;
1033 struct omap2_mcspi_cs
*cs
;
1035 mcspi
= spi_master_get_devdata(spi
->master
);
1037 if (spi
->controller_state
) {
1038 /* Unlink controller state from context save list */
1039 cs
= spi
->controller_state
;
1040 list_del(&cs
->node
);
1045 if (spi
->chip_select
< spi
->master
->num_chipselect
) {
1046 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
1048 if (mcspi_dma
->dma_rx
) {
1049 dma_release_channel(mcspi_dma
->dma_rx
);
1050 mcspi_dma
->dma_rx
= NULL
;
1052 if (mcspi_dma
->dma_tx
) {
1053 dma_release_channel(mcspi_dma
->dma_tx
);
1054 mcspi_dma
->dma_tx
= NULL
;
1059 static void omap2_mcspi_work(struct omap2_mcspi
*mcspi
, struct spi_message
*m
)
1062 /* We only enable one channel at a time -- the one whose message is
1063 * -- although this controller would gladly
1064 * arbitrate among multiple channels. This corresponds to "single
1065 * channel" master mode. As a side effect, we need to manage the
1066 * chipselect with the FORCE bit ... CS != channel enable.
1069 struct spi_device
*spi
;
1070 struct spi_transfer
*t
= NULL
;
1071 struct spi_master
*master
;
1072 struct omap2_mcspi_dma
*mcspi_dma
;
1074 struct omap2_mcspi_cs
*cs
;
1075 struct omap2_mcspi_device_config
*cd
;
1076 int par_override
= 0;
1081 master
= spi
->master
;
1082 mcspi_dma
= mcspi
->dma_channels
+ spi
->chip_select
;
1083 cs
= spi
->controller_state
;
1084 cd
= spi
->controller_data
;
1087 * The slave driver could have changed spi->mode in which case
1088 * it will be different from cs->mode (the current hardware setup).
1089 * If so, set par_override (even though its not a parity issue) so
1090 * omap2_mcspi_setup_transfer will be called to configure the hardware
1091 * with the correct mode on the first iteration of the loop below.
1093 if (spi
->mode
!= cs
->mode
)
1096 omap2_mcspi_set_enable(spi
, 0);
1097 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
1098 if (t
->tx_buf
== NULL
&& t
->rx_buf
== NULL
&& t
->len
) {
1103 (t
->speed_hz
!= spi
->max_speed_hz
) ||
1104 (t
->bits_per_word
!= spi
->bits_per_word
)) {
1106 status
= omap2_mcspi_setup_transfer(spi
, t
);
1109 if (t
->speed_hz
== spi
->max_speed_hz
&&
1110 t
->bits_per_word
== spi
->bits_per_word
)
1113 if (cd
&& cd
->cs_per_word
) {
1114 chconf
= mcspi
->ctx
.modulctrl
;
1115 chconf
&= ~OMAP2_MCSPI_MODULCTRL_SINGLE
;
1116 mcspi_write_reg(master
, OMAP2_MCSPI_MODULCTRL
, chconf
);
1117 mcspi
->ctx
.modulctrl
=
1118 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_MODULCTRL
);
1123 omap2_mcspi_force_cs(spi
, 1);
1127 chconf
= mcspi_cached_chconf0(spi
);
1128 chconf
&= ~OMAP2_MCSPI_CHCONF_TRM_MASK
;
1129 chconf
&= ~OMAP2_MCSPI_CHCONF_TURBO
;
1131 if (t
->tx_buf
== NULL
)
1132 chconf
|= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY
;
1133 else if (t
->rx_buf
== NULL
)
1134 chconf
|= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY
;
1136 if (cd
&& cd
->turbo_mode
&& t
->tx_buf
== NULL
) {
1137 /* Turbo mode is for more than one word */
1138 if (t
->len
> ((cs
->word_len
+ 7) >> 3))
1139 chconf
|= OMAP2_MCSPI_CHCONF_TURBO
;
1142 mcspi_write_chconf0(spi
, chconf
);
1147 if ((mcspi_dma
->dma_rx
&& mcspi_dma
->dma_tx
) &&
1148 (m
->is_dma_mapped
|| t
->len
>= DMA_MIN_BYTES
))
1149 omap2_mcspi_set_fifo(spi
, t
, 1);
1151 omap2_mcspi_set_enable(spi
, 1);
1153 /* RX_ONLY mode needs dummy data in TX reg */
1154 if (t
->tx_buf
== NULL
)
1155 writel_relaxed(0, cs
->base
1158 if ((mcspi_dma
->dma_rx
&& mcspi_dma
->dma_tx
) &&
1159 (m
->is_dma_mapped
|| t
->len
>= DMA_MIN_BYTES
))
1160 count
= omap2_mcspi_txrx_dma(spi
, t
);
1162 count
= omap2_mcspi_txrx_pio(spi
, t
);
1163 m
->actual_length
+= count
;
1165 if (count
!= t
->len
) {
1172 udelay(t
->delay_usecs
);
1174 /* ignore the "leave it on after last xfer" hint */
1176 omap2_mcspi_force_cs(spi
, 0);
1180 omap2_mcspi_set_enable(spi
, 0);
1182 if (mcspi
->fifo_depth
> 0)
1183 omap2_mcspi_set_fifo(spi
, t
, 0);
1185 /* Restore defaults if they were overriden */
1188 status
= omap2_mcspi_setup_transfer(spi
, NULL
);
1192 omap2_mcspi_force_cs(spi
, 0);
1194 if (cd
&& cd
->cs_per_word
) {
1195 chconf
= mcspi
->ctx
.modulctrl
;
1196 chconf
|= OMAP2_MCSPI_MODULCTRL_SINGLE
;
1197 mcspi_write_reg(master
, OMAP2_MCSPI_MODULCTRL
, chconf
);
1198 mcspi
->ctx
.modulctrl
=
1199 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_MODULCTRL
);
1202 omap2_mcspi_set_enable(spi
, 0);
1204 if (mcspi
->fifo_depth
> 0 && t
)
1205 omap2_mcspi_set_fifo(spi
, t
, 0);
1210 static int omap2_mcspi_transfer_one_message(struct spi_master
*master
,
1211 struct spi_message
*m
)
1213 struct spi_device
*spi
;
1214 struct omap2_mcspi
*mcspi
;
1215 struct omap2_mcspi_dma
*mcspi_dma
;
1216 struct spi_transfer
*t
;
1219 mcspi
= spi_master_get_devdata(master
);
1220 mcspi_dma
= mcspi
->dma_channels
+ spi
->chip_select
;
1221 m
->actual_length
= 0;
1224 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
1225 const void *tx_buf
= t
->tx_buf
;
1226 void *rx_buf
= t
->rx_buf
;
1227 unsigned len
= t
->len
;
1229 if ((len
&& !(rx_buf
|| tx_buf
))) {
1230 dev_dbg(mcspi
->dev
, "transfer: %d Hz, %d %s%s, %d bpw\n",
1239 if (m
->is_dma_mapped
|| len
< DMA_MIN_BYTES
)
1242 if (mcspi_dma
->dma_tx
&& tx_buf
!= NULL
) {
1243 t
->tx_dma
= dma_map_single(mcspi
->dev
, (void *) tx_buf
,
1244 len
, DMA_TO_DEVICE
);
1245 if (dma_mapping_error(mcspi
->dev
, t
->tx_dma
)) {
1246 dev_dbg(mcspi
->dev
, "dma %cX %d bytes error\n",
1251 if (mcspi_dma
->dma_rx
&& rx_buf
!= NULL
) {
1252 t
->rx_dma
= dma_map_single(mcspi
->dev
, rx_buf
, t
->len
,
1254 if (dma_mapping_error(mcspi
->dev
, t
->rx_dma
)) {
1255 dev_dbg(mcspi
->dev
, "dma %cX %d bytes error\n",
1258 dma_unmap_single(mcspi
->dev
, t
->tx_dma
,
1259 len
, DMA_TO_DEVICE
);
1265 omap2_mcspi_work(mcspi
, m
);
1266 spi_finalize_current_message(master
);
1270 static int omap2_mcspi_master_setup(struct omap2_mcspi
*mcspi
)
1272 struct spi_master
*master
= mcspi
->master
;
1273 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
1276 ret
= pm_runtime_get_sync(mcspi
->dev
);
1280 mcspi_write_reg(master
, OMAP2_MCSPI_WAKEUPENABLE
,
1281 OMAP2_MCSPI_WAKEUPENABLE_WKEN
);
1282 ctx
->wakeupenable
= OMAP2_MCSPI_WAKEUPENABLE_WKEN
;
1284 omap2_mcspi_set_master_mode(master
);
1285 pm_runtime_mark_last_busy(mcspi
->dev
);
1286 pm_runtime_put_autosuspend(mcspi
->dev
);
1290 static int omap_mcspi_runtime_resume(struct device
*dev
)
1292 struct omap2_mcspi
*mcspi
;
1293 struct spi_master
*master
;
1295 master
= dev_get_drvdata(dev
);
1296 mcspi
= spi_master_get_devdata(master
);
1297 omap2_mcspi_restore_ctx(mcspi
);
1302 static struct omap2_mcspi_platform_config omap2_pdata
= {
1306 static struct omap2_mcspi_platform_config omap4_pdata
= {
1307 .regs_offset
= OMAP4_MCSPI_REG_OFFSET
,
1310 static const struct of_device_id omap_mcspi_of_match
[] = {
1312 .compatible
= "ti,omap2-mcspi",
1313 .data
= &omap2_pdata
,
1316 .compatible
= "ti,omap4-mcspi",
1317 .data
= &omap4_pdata
,
1321 MODULE_DEVICE_TABLE(of
, omap_mcspi_of_match
);
1323 static int omap2_mcspi_probe(struct platform_device
*pdev
)
1325 struct spi_master
*master
;
1326 const struct omap2_mcspi_platform_config
*pdata
;
1327 struct omap2_mcspi
*mcspi
;
1330 u32 regs_offset
= 0;
1331 static int bus_num
= 1;
1332 struct device_node
*node
= pdev
->dev
.of_node
;
1333 const struct of_device_id
*match
;
1335 master
= spi_alloc_master(&pdev
->dev
, sizeof *mcspi
);
1336 if (master
== NULL
) {
1337 dev_dbg(&pdev
->dev
, "master allocation failed\n");
1341 /* the spi->mode bits understood by this driver: */
1342 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1343 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(4, 32);
1344 master
->setup
= omap2_mcspi_setup
;
1345 master
->auto_runtime_pm
= true;
1346 master
->transfer_one_message
= omap2_mcspi_transfer_one_message
;
1347 master
->cleanup
= omap2_mcspi_cleanup
;
1348 master
->dev
.of_node
= node
;
1349 master
->max_speed_hz
= OMAP2_MCSPI_MAX_FREQ
;
1350 master
->min_speed_hz
= OMAP2_MCSPI_MAX_FREQ
>> 15;
1352 platform_set_drvdata(pdev
, master
);
1354 mcspi
= spi_master_get_devdata(master
);
1355 mcspi
->master
= master
;
1357 match
= of_match_device(omap_mcspi_of_match
, &pdev
->dev
);
1359 u32 num_cs
= 1; /* default number of chipselect */
1360 pdata
= match
->data
;
1362 of_property_read_u32(node
, "ti,spi-num-cs", &num_cs
);
1363 master
->num_chipselect
= num_cs
;
1364 master
->bus_num
= bus_num
++;
1365 if (of_get_property(node
, "ti,pindir-d0-out-d1-in", NULL
))
1366 mcspi
->pin_dir
= MCSPI_PINDIR_D0_OUT_D1_IN
;
1368 pdata
= dev_get_platdata(&pdev
->dev
);
1369 master
->num_chipselect
= pdata
->num_cs
;
1371 master
->bus_num
= pdev
->id
;
1372 mcspi
->pin_dir
= pdata
->pin_dir
;
1374 regs_offset
= pdata
->regs_offset
;
1376 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1382 r
->start
+= regs_offset
;
1383 r
->end
+= regs_offset
;
1384 mcspi
->phys
= r
->start
;
1386 mcspi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
1387 if (IS_ERR(mcspi
->base
)) {
1388 status
= PTR_ERR(mcspi
->base
);
1392 mcspi
->dev
= &pdev
->dev
;
1394 INIT_LIST_HEAD(&mcspi
->ctx
.cs
);
1396 mcspi
->dma_channels
= devm_kcalloc(&pdev
->dev
, master
->num_chipselect
,
1397 sizeof(struct omap2_mcspi_dma
),
1399 if (mcspi
->dma_channels
== NULL
) {
1404 for (i
= 0; i
< master
->num_chipselect
; i
++) {
1405 char *dma_rx_ch_name
= mcspi
->dma_channels
[i
].dma_rx_ch_name
;
1406 char *dma_tx_ch_name
= mcspi
->dma_channels
[i
].dma_tx_ch_name
;
1407 struct resource
*dma_res
;
1409 sprintf(dma_rx_ch_name
, "rx%d", i
);
1410 if (!pdev
->dev
.of_node
) {
1412 platform_get_resource_byname(pdev
,
1417 "cannot get DMA RX channel\n");
1422 mcspi
->dma_channels
[i
].dma_rx_sync_dev
=
1425 sprintf(dma_tx_ch_name
, "tx%d", i
);
1426 if (!pdev
->dev
.of_node
) {
1428 platform_get_resource_byname(pdev
,
1433 "cannot get DMA TX channel\n");
1438 mcspi
->dma_channels
[i
].dma_tx_sync_dev
=
1446 pm_runtime_use_autosuspend(&pdev
->dev
);
1447 pm_runtime_set_autosuspend_delay(&pdev
->dev
, SPI_AUTOSUSPEND_TIMEOUT
);
1448 pm_runtime_enable(&pdev
->dev
);
1450 status
= omap2_mcspi_master_setup(mcspi
);
1454 status
= devm_spi_register_master(&pdev
->dev
, master
);
1461 pm_runtime_disable(&pdev
->dev
);
1463 spi_master_put(master
);
1467 static int omap2_mcspi_remove(struct platform_device
*pdev
)
1469 struct spi_master
*master
= platform_get_drvdata(pdev
);
1470 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
1472 pm_runtime_put_sync(mcspi
->dev
);
1473 pm_runtime_disable(&pdev
->dev
);
1478 /* work with hotplug and coldplug */
1479 MODULE_ALIAS("platform:omap2_mcspi");
1481 #ifdef CONFIG_SUSPEND
1483 * When SPI wake up from off-mode, CS is in activate state. If it was in
1484 * unactive state when driver was suspend, then force it to unactive state at
1487 static int omap2_mcspi_resume(struct device
*dev
)
1489 struct spi_master
*master
= dev_get_drvdata(dev
);
1490 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
1491 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
1492 struct omap2_mcspi_cs
*cs
;
1494 pm_runtime_get_sync(mcspi
->dev
);
1495 list_for_each_entry(cs
, &ctx
->cs
, node
) {
1496 if ((cs
->chconf0
& OMAP2_MCSPI_CHCONF_FORCE
) == 0) {
1498 * We need to toggle CS state for OMAP take this
1499 * change in account.
1501 cs
->chconf0
|= OMAP2_MCSPI_CHCONF_FORCE
;
1502 writel_relaxed(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1503 cs
->chconf0
&= ~OMAP2_MCSPI_CHCONF_FORCE
;
1504 writel_relaxed(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1507 pm_runtime_mark_last_busy(mcspi
->dev
);
1508 pm_runtime_put_autosuspend(mcspi
->dev
);
1512 #define omap2_mcspi_resume NULL
1515 static const struct dev_pm_ops omap2_mcspi_pm_ops
= {
1516 .resume
= omap2_mcspi_resume
,
1517 .runtime_resume
= omap_mcspi_runtime_resume
,
1520 static struct platform_driver omap2_mcspi_driver
= {
1522 .name
= "omap2_mcspi",
1523 .owner
= THIS_MODULE
,
1524 .pm
= &omap2_mcspi_pm_ops
,
1525 .of_match_table
= omap_mcspi_of_match
,
1527 .probe
= omap2_mcspi_probe
,
1528 .remove
= omap2_mcspi_remove
,
1531 module_platform_driver(omap2_mcspi_driver
);
1532 MODULE_LICENSE("GPL");