2 * OMAP2 McSPI controller driver
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
35 #include <linux/slab.h>
36 #include <linux/pm_runtime.h>
38 #include <linux/of_device.h>
40 #include <linux/spi/spi.h>
43 #include <plat/clock.h>
44 #include <plat/mcspi.h>
46 #define OMAP2_MCSPI_MAX_FREQ 48000000
47 #define SPI_AUTOSUSPEND_TIMEOUT 2000
49 #define OMAP2_MCSPI_REVISION 0x00
50 #define OMAP2_MCSPI_SYSSTATUS 0x14
51 #define OMAP2_MCSPI_IRQSTATUS 0x18
52 #define OMAP2_MCSPI_IRQENABLE 0x1c
53 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
54 #define OMAP2_MCSPI_SYST 0x24
55 #define OMAP2_MCSPI_MODULCTRL 0x28
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0 0x2c
59 #define OMAP2_MCSPI_CHSTAT0 0x30
60 #define OMAP2_MCSPI_CHCTRL0 0x34
61 #define OMAP2_MCSPI_TX0 0x38
62 #define OMAP2_MCSPI_RX0 0x3c
64 /* per-register bitmasks: */
66 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
67 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
68 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
70 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
71 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
72 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
73 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
74 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
75 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
76 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
77 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
78 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
79 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
80 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
81 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
82 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
83 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
84 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
86 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
87 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
88 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
90 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
92 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
94 /* We have 2 DMA channels per CS, one for RX and one for TX */
95 struct omap2_mcspi_dma
{
102 struct completion dma_tx_completion
;
103 struct completion dma_rx_completion
;
106 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
107 * cache operations; better heuristics consider wordsize and bitrate.
109 #define DMA_MIN_BYTES 160
113 * Used for context save and restore, structure members to be updated whenever
114 * corresponding registers are modified.
116 struct omap2_mcspi_regs
{
123 struct spi_master
*master
;
124 /* Virtual base address of the controller */
127 /* SPI1 has 4 channels, while SPI2 has 2 */
128 struct omap2_mcspi_dma
*dma_channels
;
130 struct omap2_mcspi_regs ctx
;
133 struct omap2_mcspi_cs
{
137 struct list_head node
;
138 /* Context save and restore shadow register */
142 #define MOD_REG_BIT(val, mask, set) do { \
149 static inline void mcspi_write_reg(struct spi_master
*master
,
152 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
154 __raw_writel(val
, mcspi
->base
+ idx
);
157 static inline u32
mcspi_read_reg(struct spi_master
*master
, int idx
)
159 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
161 return __raw_readl(mcspi
->base
+ idx
);
164 static inline void mcspi_write_cs_reg(const struct spi_device
*spi
,
167 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
169 __raw_writel(val
, cs
->base
+ idx
);
172 static inline u32
mcspi_read_cs_reg(const struct spi_device
*spi
, int idx
)
174 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
176 return __raw_readl(cs
->base
+ idx
);
179 static inline u32
mcspi_cached_chconf0(const struct spi_device
*spi
)
181 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
186 static inline void mcspi_write_chconf0(const struct spi_device
*spi
, u32 val
)
188 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
191 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCONF0
, val
);
192 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHCONF0
);
195 static void omap2_mcspi_set_dma_req(const struct spi_device
*spi
,
196 int is_read
, int enable
)
200 l
= mcspi_cached_chconf0(spi
);
202 if (is_read
) /* 1 is read, 0 write */
203 rw
= OMAP2_MCSPI_CHCONF_DMAR
;
205 rw
= OMAP2_MCSPI_CHCONF_DMAW
;
207 MOD_REG_BIT(l
, rw
, enable
);
208 mcspi_write_chconf0(spi
, l
);
211 static void omap2_mcspi_set_enable(const struct spi_device
*spi
, int enable
)
215 l
= enable
? OMAP2_MCSPI_CHCTRL_EN
: 0;
216 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
, l
);
217 /* Flash post-writes */
218 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
);
221 static void omap2_mcspi_force_cs(struct spi_device
*spi
, int cs_active
)
225 l
= mcspi_cached_chconf0(spi
);
226 MOD_REG_BIT(l
, OMAP2_MCSPI_CHCONF_FORCE
, cs_active
);
227 mcspi_write_chconf0(spi
, l
);
230 static void omap2_mcspi_set_master_mode(struct spi_master
*master
)
232 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
233 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
237 * Setup when switching from (reset default) slave mode
238 * to single-channel master mode
240 l
= mcspi_read_reg(master
, OMAP2_MCSPI_MODULCTRL
);
241 MOD_REG_BIT(l
, OMAP2_MCSPI_MODULCTRL_STEST
, 0);
242 MOD_REG_BIT(l
, OMAP2_MCSPI_MODULCTRL_MS
, 0);
243 MOD_REG_BIT(l
, OMAP2_MCSPI_MODULCTRL_SINGLE
, 1);
244 mcspi_write_reg(master
, OMAP2_MCSPI_MODULCTRL
, l
);
249 static void omap2_mcspi_restore_ctx(struct omap2_mcspi
*mcspi
)
251 struct spi_master
*spi_cntrl
= mcspi
->master
;
252 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
253 struct omap2_mcspi_cs
*cs
;
255 /* McSPI: context restore */
256 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_MODULCTRL
, ctx
->modulctrl
);
257 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_WAKEUPENABLE
, ctx
->wakeupenable
);
259 list_for_each_entry(cs
, &ctx
->cs
, node
)
260 __raw_writel(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
262 static void omap2_mcspi_disable_clocks(struct omap2_mcspi
*mcspi
)
264 pm_runtime_mark_last_busy(mcspi
->dev
);
265 pm_runtime_put_autosuspend(mcspi
->dev
);
268 static int omap2_mcspi_enable_clocks(struct omap2_mcspi
*mcspi
)
270 return pm_runtime_get_sync(mcspi
->dev
);
273 static int omap2_prepare_transfer(struct spi_master
*master
)
275 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
277 pm_runtime_get_sync(mcspi
->dev
);
281 static int omap2_unprepare_transfer(struct spi_master
*master
)
283 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
285 pm_runtime_mark_last_busy(mcspi
->dev
);
286 pm_runtime_put_autosuspend(mcspi
->dev
);
290 static int mcspi_wait_for_reg_bit(void __iomem
*reg
, unsigned long bit
)
292 unsigned long timeout
;
294 timeout
= jiffies
+ msecs_to_jiffies(1000);
295 while (!(__raw_readl(reg
) & bit
)) {
296 if (time_after(jiffies
, timeout
))
304 omap2_mcspi_txrx_dma(struct spi_device
*spi
, struct spi_transfer
*xfer
)
306 struct omap2_mcspi
*mcspi
;
307 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
308 struct omap2_mcspi_dma
*mcspi_dma
;
309 unsigned int count
, c
;
310 unsigned long base
, tx_reg
, rx_reg
;
311 int word_len
, data_type
, element_count
;
316 void __iomem
*chstat_reg
;
318 mcspi
= spi_master_get_devdata(spi
->master
);
319 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
320 l
= mcspi_cached_chconf0(spi
);
322 chstat_reg
= cs
->base
+ OMAP2_MCSPI_CHSTAT0
;
326 word_len
= cs
->word_len
;
329 tx_reg
= base
+ OMAP2_MCSPI_TX0
;
330 rx_reg
= base
+ OMAP2_MCSPI_RX0
;
335 data_type
= OMAP_DMA_DATA_TYPE_S8
;
336 element_count
= count
;
337 } else if (word_len
<= 16) {
338 data_type
= OMAP_DMA_DATA_TYPE_S16
;
339 element_count
= count
>> 1;
340 } else /* word_len <= 32 */ {
341 data_type
= OMAP_DMA_DATA_TYPE_S32
;
342 element_count
= count
>> 2;
346 omap_set_dma_transfer_params(mcspi_dma
->dma_tx_channel
,
347 data_type
, element_count
, 1,
348 OMAP_DMA_SYNC_ELEMENT
,
349 mcspi_dma
->dma_tx_sync_dev
, 0);
351 omap_set_dma_dest_params(mcspi_dma
->dma_tx_channel
, 0,
352 OMAP_DMA_AMODE_CONSTANT
,
355 omap_set_dma_src_params(mcspi_dma
->dma_tx_channel
, 0,
356 OMAP_DMA_AMODE_POST_INC
,
361 elements
= element_count
- 1;
362 if (l
& OMAP2_MCSPI_CHCONF_TURBO
)
365 omap_set_dma_transfer_params(mcspi_dma
->dma_rx_channel
,
366 data_type
, elements
, 1,
367 OMAP_DMA_SYNC_ELEMENT
,
368 mcspi_dma
->dma_rx_sync_dev
, 1);
370 omap_set_dma_src_params(mcspi_dma
->dma_rx_channel
, 0,
371 OMAP_DMA_AMODE_CONSTANT
,
374 omap_set_dma_dest_params(mcspi_dma
->dma_rx_channel
, 0,
375 OMAP_DMA_AMODE_POST_INC
,
380 omap_start_dma(mcspi_dma
->dma_tx_channel
);
381 omap2_mcspi_set_dma_req(spi
, 0, 1);
385 omap_start_dma(mcspi_dma
->dma_rx_channel
);
386 omap2_mcspi_set_dma_req(spi
, 1, 1);
390 wait_for_completion(&mcspi_dma
->dma_tx_completion
);
391 dma_unmap_single(mcspi
->dev
, xfer
->tx_dma
, count
,
394 /* for TX_ONLY mode, be sure all words have shifted out */
396 if (mcspi_wait_for_reg_bit(chstat_reg
,
397 OMAP2_MCSPI_CHSTAT_TXS
) < 0)
398 dev_err(&spi
->dev
, "TXS timed out\n");
399 else if (mcspi_wait_for_reg_bit(chstat_reg
,
400 OMAP2_MCSPI_CHSTAT_EOT
) < 0)
401 dev_err(&spi
->dev
, "EOT timed out\n");
406 wait_for_completion(&mcspi_dma
->dma_rx_completion
);
407 dma_unmap_single(mcspi
->dev
, xfer
->rx_dma
, count
,
409 omap2_mcspi_set_enable(spi
, 0);
411 if (l
& OMAP2_MCSPI_CHCONF_TURBO
) {
413 if (likely(mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHSTAT0
)
414 & OMAP2_MCSPI_CHSTAT_RXS
)) {
417 w
= mcspi_read_cs_reg(spi
, OMAP2_MCSPI_RX0
);
419 ((u8
*)xfer
->rx_buf
)[elements
++] = w
;
420 else if (word_len
<= 16)
421 ((u16
*)xfer
->rx_buf
)[elements
++] = w
;
422 else /* word_len <= 32 */
423 ((u32
*)xfer
->rx_buf
)[elements
++] = w
;
426 "DMA RX penultimate word empty");
427 count
-= (word_len
<= 8) ? 2 :
428 (word_len
<= 16) ? 4 :
429 /* word_len <= 32 */ 8;
430 omap2_mcspi_set_enable(spi
, 1);
435 if (likely(mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHSTAT0
)
436 & OMAP2_MCSPI_CHSTAT_RXS
)) {
439 w
= mcspi_read_cs_reg(spi
, OMAP2_MCSPI_RX0
);
441 ((u8
*)xfer
->rx_buf
)[elements
] = w
;
442 else if (word_len
<= 16)
443 ((u16
*)xfer
->rx_buf
)[elements
] = w
;
444 else /* word_len <= 32 */
445 ((u32
*)xfer
->rx_buf
)[elements
] = w
;
447 dev_err(&spi
->dev
, "DMA RX last word empty");
448 count
-= (word_len
<= 8) ? 1 :
449 (word_len
<= 16) ? 2 :
450 /* word_len <= 32 */ 4;
452 omap2_mcspi_set_enable(spi
, 1);
458 omap2_mcspi_txrx_pio(struct spi_device
*spi
, struct spi_transfer
*xfer
)
460 struct omap2_mcspi
*mcspi
;
461 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
462 unsigned int count
, c
;
464 void __iomem
*base
= cs
->base
;
465 void __iomem
*tx_reg
;
466 void __iomem
*rx_reg
;
467 void __iomem
*chstat_reg
;
470 mcspi
= spi_master_get_devdata(spi
->master
);
473 word_len
= cs
->word_len
;
475 l
= mcspi_cached_chconf0(spi
);
477 /* We store the pre-calculated register addresses on stack to speed
478 * up the transfer loop. */
479 tx_reg
= base
+ OMAP2_MCSPI_TX0
;
480 rx_reg
= base
+ OMAP2_MCSPI_RX0
;
481 chstat_reg
= base
+ OMAP2_MCSPI_CHSTAT0
;
483 if (c
< (word_len
>>3))
496 if (mcspi_wait_for_reg_bit(chstat_reg
,
497 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
498 dev_err(&spi
->dev
, "TXS timed out\n");
501 dev_vdbg(&spi
->dev
, "write-%d %02x\n",
503 __raw_writel(*tx
++, tx_reg
);
506 if (mcspi_wait_for_reg_bit(chstat_reg
,
507 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
508 dev_err(&spi
->dev
, "RXS timed out\n");
512 if (c
== 1 && tx
== NULL
&&
513 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
514 omap2_mcspi_set_enable(spi
, 0);
515 *rx
++ = __raw_readl(rx_reg
);
516 dev_vdbg(&spi
->dev
, "read-%d %02x\n",
517 word_len
, *(rx
- 1));
518 if (mcspi_wait_for_reg_bit(chstat_reg
,
519 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
525 } else if (c
== 0 && tx
== NULL
) {
526 omap2_mcspi_set_enable(spi
, 0);
529 *rx
++ = __raw_readl(rx_reg
);
530 dev_vdbg(&spi
->dev
, "read-%d %02x\n",
531 word_len
, *(rx
- 1));
534 } else if (word_len
<= 16) {
543 if (mcspi_wait_for_reg_bit(chstat_reg
,
544 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
545 dev_err(&spi
->dev
, "TXS timed out\n");
548 dev_vdbg(&spi
->dev
, "write-%d %04x\n",
550 __raw_writel(*tx
++, tx_reg
);
553 if (mcspi_wait_for_reg_bit(chstat_reg
,
554 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
555 dev_err(&spi
->dev
, "RXS timed out\n");
559 if (c
== 2 && tx
== NULL
&&
560 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
561 omap2_mcspi_set_enable(spi
, 0);
562 *rx
++ = __raw_readl(rx_reg
);
563 dev_vdbg(&spi
->dev
, "read-%d %04x\n",
564 word_len
, *(rx
- 1));
565 if (mcspi_wait_for_reg_bit(chstat_reg
,
566 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
572 } else if (c
== 0 && tx
== NULL
) {
573 omap2_mcspi_set_enable(spi
, 0);
576 *rx
++ = __raw_readl(rx_reg
);
577 dev_vdbg(&spi
->dev
, "read-%d %04x\n",
578 word_len
, *(rx
- 1));
581 } else if (word_len
<= 32) {
590 if (mcspi_wait_for_reg_bit(chstat_reg
,
591 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
592 dev_err(&spi
->dev
, "TXS timed out\n");
595 dev_vdbg(&spi
->dev
, "write-%d %08x\n",
597 __raw_writel(*tx
++, tx_reg
);
600 if (mcspi_wait_for_reg_bit(chstat_reg
,
601 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
602 dev_err(&spi
->dev
, "RXS timed out\n");
606 if (c
== 4 && tx
== NULL
&&
607 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
608 omap2_mcspi_set_enable(spi
, 0);
609 *rx
++ = __raw_readl(rx_reg
);
610 dev_vdbg(&spi
->dev
, "read-%d %08x\n",
611 word_len
, *(rx
- 1));
612 if (mcspi_wait_for_reg_bit(chstat_reg
,
613 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
619 } else if (c
== 0 && tx
== NULL
) {
620 omap2_mcspi_set_enable(spi
, 0);
623 *rx
++ = __raw_readl(rx_reg
);
624 dev_vdbg(&spi
->dev
, "read-%d %08x\n",
625 word_len
, *(rx
- 1));
630 /* for TX_ONLY mode, be sure all words have shifted out */
631 if (xfer
->rx_buf
== NULL
) {
632 if (mcspi_wait_for_reg_bit(chstat_reg
,
633 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
634 dev_err(&spi
->dev
, "TXS timed out\n");
635 } else if (mcspi_wait_for_reg_bit(chstat_reg
,
636 OMAP2_MCSPI_CHSTAT_EOT
) < 0)
637 dev_err(&spi
->dev
, "EOT timed out\n");
639 /* disable chan to purge rx datas received in TX_ONLY transfer,
640 * otherwise these rx datas will affect the direct following
643 omap2_mcspi_set_enable(spi
, 0);
646 omap2_mcspi_set_enable(spi
, 1);
650 static u32
omap2_mcspi_calc_divisor(u32 speed_hz
)
654 for (div
= 0; div
< 15; div
++)
655 if (speed_hz
>= (OMAP2_MCSPI_MAX_FREQ
>> div
))
661 /* called only when no transfer is active to this device */
662 static int omap2_mcspi_setup_transfer(struct spi_device
*spi
,
663 struct spi_transfer
*t
)
665 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
666 struct omap2_mcspi
*mcspi
;
667 struct spi_master
*spi_cntrl
;
669 u8 word_len
= spi
->bits_per_word
;
670 u32 speed_hz
= spi
->max_speed_hz
;
672 mcspi
= spi_master_get_devdata(spi
->master
);
673 spi_cntrl
= mcspi
->master
;
675 if (t
!= NULL
&& t
->bits_per_word
)
676 word_len
= t
->bits_per_word
;
678 cs
->word_len
= word_len
;
680 if (t
&& t
->speed_hz
)
681 speed_hz
= t
->speed_hz
;
683 speed_hz
= min_t(u32
, speed_hz
, OMAP2_MCSPI_MAX_FREQ
);
684 div
= omap2_mcspi_calc_divisor(speed_hz
);
686 l
= mcspi_cached_chconf0(spi
);
688 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
689 * REVISIT: this controller could support SPI_3WIRE mode.
691 l
&= ~(OMAP2_MCSPI_CHCONF_IS
|OMAP2_MCSPI_CHCONF_DPE1
);
692 l
|= OMAP2_MCSPI_CHCONF_DPE0
;
695 l
&= ~OMAP2_MCSPI_CHCONF_WL_MASK
;
696 l
|= (word_len
- 1) << 7;
698 /* set chipselect polarity; manage with FORCE */
699 if (!(spi
->mode
& SPI_CS_HIGH
))
700 l
|= OMAP2_MCSPI_CHCONF_EPOL
; /* active-low; normal */
702 l
&= ~OMAP2_MCSPI_CHCONF_EPOL
;
704 /* set clock divisor */
705 l
&= ~OMAP2_MCSPI_CHCONF_CLKD_MASK
;
708 /* set SPI mode 0..3 */
709 if (spi
->mode
& SPI_CPOL
)
710 l
|= OMAP2_MCSPI_CHCONF_POL
;
712 l
&= ~OMAP2_MCSPI_CHCONF_POL
;
713 if (spi
->mode
& SPI_CPHA
)
714 l
|= OMAP2_MCSPI_CHCONF_PHA
;
716 l
&= ~OMAP2_MCSPI_CHCONF_PHA
;
718 mcspi_write_chconf0(spi
, l
);
720 dev_dbg(&spi
->dev
, "setup: speed %d, sample %s edge, clk %s\n",
721 OMAP2_MCSPI_MAX_FREQ
>> div
,
722 (spi
->mode
& SPI_CPHA
) ? "trailing" : "leading",
723 (spi
->mode
& SPI_CPOL
) ? "inverted" : "normal");
728 static void omap2_mcspi_dma_rx_callback(int lch
, u16 ch_status
, void *data
)
730 struct spi_device
*spi
= data
;
731 struct omap2_mcspi
*mcspi
;
732 struct omap2_mcspi_dma
*mcspi_dma
;
734 mcspi
= spi_master_get_devdata(spi
->master
);
735 mcspi_dma
= &(mcspi
->dma_channels
[spi
->chip_select
]);
737 complete(&mcspi_dma
->dma_rx_completion
);
739 /* We must disable the DMA RX request */
740 omap2_mcspi_set_dma_req(spi
, 1, 0);
743 static void omap2_mcspi_dma_tx_callback(int lch
, u16 ch_status
, void *data
)
745 struct spi_device
*spi
= data
;
746 struct omap2_mcspi
*mcspi
;
747 struct omap2_mcspi_dma
*mcspi_dma
;
749 mcspi
= spi_master_get_devdata(spi
->master
);
750 mcspi_dma
= &(mcspi
->dma_channels
[spi
->chip_select
]);
752 complete(&mcspi_dma
->dma_tx_completion
);
754 /* We must disable the DMA TX request */
755 omap2_mcspi_set_dma_req(spi
, 0, 0);
758 static int omap2_mcspi_request_dma(struct spi_device
*spi
)
760 struct spi_master
*master
= spi
->master
;
761 struct omap2_mcspi
*mcspi
;
762 struct omap2_mcspi_dma
*mcspi_dma
;
764 mcspi
= spi_master_get_devdata(master
);
765 mcspi_dma
= mcspi
->dma_channels
+ spi
->chip_select
;
767 if (omap_request_dma(mcspi_dma
->dma_rx_sync_dev
, "McSPI RX",
768 omap2_mcspi_dma_rx_callback
, spi
,
769 &mcspi_dma
->dma_rx_channel
)) {
770 dev_err(&spi
->dev
, "no RX DMA channel for McSPI\n");
774 if (omap_request_dma(mcspi_dma
->dma_tx_sync_dev
, "McSPI TX",
775 omap2_mcspi_dma_tx_callback
, spi
,
776 &mcspi_dma
->dma_tx_channel
)) {
777 omap_free_dma(mcspi_dma
->dma_rx_channel
);
778 mcspi_dma
->dma_rx_channel
= -1;
779 dev_err(&spi
->dev
, "no TX DMA channel for McSPI\n");
783 init_completion(&mcspi_dma
->dma_rx_completion
);
784 init_completion(&mcspi_dma
->dma_tx_completion
);
789 static int omap2_mcspi_setup(struct spi_device
*spi
)
792 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
793 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
794 struct omap2_mcspi_dma
*mcspi_dma
;
795 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
797 if (spi
->bits_per_word
< 4 || spi
->bits_per_word
> 32) {
798 dev_dbg(&spi
->dev
, "setup: unsupported %d bit words\n",
803 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
806 cs
= kzalloc(sizeof *cs
, GFP_KERNEL
);
809 cs
->base
= mcspi
->base
+ spi
->chip_select
* 0x14;
810 cs
->phys
= mcspi
->phys
+ spi
->chip_select
* 0x14;
812 spi
->controller_state
= cs
;
813 /* Link this to context save list */
814 list_add_tail(&cs
->node
, &ctx
->cs
);
817 if (mcspi_dma
->dma_rx_channel
== -1
818 || mcspi_dma
->dma_tx_channel
== -1) {
819 ret
= omap2_mcspi_request_dma(spi
);
824 ret
= omap2_mcspi_enable_clocks(mcspi
);
828 ret
= omap2_mcspi_setup_transfer(spi
, NULL
);
829 omap2_mcspi_disable_clocks(mcspi
);
834 static void omap2_mcspi_cleanup(struct spi_device
*spi
)
836 struct omap2_mcspi
*mcspi
;
837 struct omap2_mcspi_dma
*mcspi_dma
;
838 struct omap2_mcspi_cs
*cs
;
840 mcspi
= spi_master_get_devdata(spi
->master
);
842 if (spi
->controller_state
) {
843 /* Unlink controller state from context save list */
844 cs
= spi
->controller_state
;
850 if (spi
->chip_select
< spi
->master
->num_chipselect
) {
851 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
853 if (mcspi_dma
->dma_rx_channel
!= -1) {
854 omap_free_dma(mcspi_dma
->dma_rx_channel
);
855 mcspi_dma
->dma_rx_channel
= -1;
857 if (mcspi_dma
->dma_tx_channel
!= -1) {
858 omap_free_dma(mcspi_dma
->dma_tx_channel
);
859 mcspi_dma
->dma_tx_channel
= -1;
864 static void omap2_mcspi_work(struct omap2_mcspi
*mcspi
, struct spi_message
*m
)
867 /* We only enable one channel at a time -- the one whose message is
868 * -- although this controller would gladly
869 * arbitrate among multiple channels. This corresponds to "single
870 * channel" master mode. As a side effect, we need to manage the
871 * chipselect with the FORCE bit ... CS != channel enable.
874 struct spi_device
*spi
;
875 struct spi_transfer
*t
= NULL
;
877 struct omap2_mcspi_cs
*cs
;
878 struct omap2_mcspi_device_config
*cd
;
879 int par_override
= 0;
884 cs
= spi
->controller_state
;
885 cd
= spi
->controller_data
;
887 omap2_mcspi_set_enable(spi
, 1);
888 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
889 if (t
->tx_buf
== NULL
&& t
->rx_buf
== NULL
&& t
->len
) {
893 if (par_override
|| t
->speed_hz
|| t
->bits_per_word
) {
895 status
= omap2_mcspi_setup_transfer(spi
, t
);
898 if (!t
->speed_hz
&& !t
->bits_per_word
)
903 omap2_mcspi_force_cs(spi
, 1);
907 chconf
= mcspi_cached_chconf0(spi
);
908 chconf
&= ~OMAP2_MCSPI_CHCONF_TRM_MASK
;
909 chconf
&= ~OMAP2_MCSPI_CHCONF_TURBO
;
911 if (t
->tx_buf
== NULL
)
912 chconf
|= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY
;
913 else if (t
->rx_buf
== NULL
)
914 chconf
|= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY
;
916 if (cd
&& cd
->turbo_mode
&& t
->tx_buf
== NULL
) {
917 /* Turbo mode is for more than one word */
918 if (t
->len
> ((cs
->word_len
+ 7) >> 3))
919 chconf
|= OMAP2_MCSPI_CHCONF_TURBO
;
922 mcspi_write_chconf0(spi
, chconf
);
927 /* RX_ONLY mode needs dummy data in TX reg */
928 if (t
->tx_buf
== NULL
)
929 __raw_writel(0, cs
->base
932 if (m
->is_dma_mapped
|| t
->len
>= DMA_MIN_BYTES
)
933 count
= omap2_mcspi_txrx_dma(spi
, t
);
935 count
= omap2_mcspi_txrx_pio(spi
, t
);
936 m
->actual_length
+= count
;
938 if (count
!= t
->len
) {
945 udelay(t
->delay_usecs
);
947 /* ignore the "leave it on after last xfer" hint */
949 omap2_mcspi_force_cs(spi
, 0);
953 /* Restore defaults if they were overriden */
956 status
= omap2_mcspi_setup_transfer(spi
, NULL
);
960 omap2_mcspi_force_cs(spi
, 0);
962 omap2_mcspi_set_enable(spi
, 0);
968 static int omap2_mcspi_transfer_one_message(struct spi_master
*master
,
969 struct spi_message
*m
)
971 struct omap2_mcspi
*mcspi
;
972 struct spi_transfer
*t
;
974 mcspi
= spi_master_get_devdata(master
);
975 m
->actual_length
= 0;
978 /* reject invalid messages and transfers */
979 if (list_empty(&m
->transfers
))
981 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
982 const void *tx_buf
= t
->tx_buf
;
983 void *rx_buf
= t
->rx_buf
;
984 unsigned len
= t
->len
;
986 if (t
->speed_hz
> OMAP2_MCSPI_MAX_FREQ
987 || (len
&& !(rx_buf
|| tx_buf
))
988 || (t
->bits_per_word
&&
989 ( t
->bits_per_word
< 4
990 || t
->bits_per_word
> 32))) {
991 dev_dbg(mcspi
->dev
, "transfer: %d Hz, %d %s%s, %d bpw\n",
999 if (t
->speed_hz
&& t
->speed_hz
< (OMAP2_MCSPI_MAX_FREQ
>> 15)) {
1000 dev_dbg(mcspi
->dev
, "speed_hz %d below minimum %d Hz\n",
1002 OMAP2_MCSPI_MAX_FREQ
>> 15);
1006 if (m
->is_dma_mapped
|| len
< DMA_MIN_BYTES
)
1009 if (tx_buf
!= NULL
) {
1010 t
->tx_dma
= dma_map_single(mcspi
->dev
, (void *) tx_buf
,
1011 len
, DMA_TO_DEVICE
);
1012 if (dma_mapping_error(mcspi
->dev
, t
->tx_dma
)) {
1013 dev_dbg(mcspi
->dev
, "dma %cX %d bytes error\n",
1018 if (rx_buf
!= NULL
) {
1019 t
->rx_dma
= dma_map_single(mcspi
->dev
, rx_buf
, t
->len
,
1021 if (dma_mapping_error(mcspi
->dev
, t
->rx_dma
)) {
1022 dev_dbg(mcspi
->dev
, "dma %cX %d bytes error\n",
1025 dma_unmap_single(mcspi
->dev
, t
->tx_dma
,
1026 len
, DMA_TO_DEVICE
);
1032 omap2_mcspi_work(mcspi
, m
);
1033 spi_finalize_current_message(master
);
1037 static int __devinit
omap2_mcspi_master_setup(struct omap2_mcspi
*mcspi
)
1039 struct spi_master
*master
= mcspi
->master
;
1040 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
1043 ret
= omap2_mcspi_enable_clocks(mcspi
);
1047 mcspi_write_reg(master
, OMAP2_MCSPI_WAKEUPENABLE
,
1048 OMAP2_MCSPI_WAKEUPENABLE_WKEN
);
1049 ctx
->wakeupenable
= OMAP2_MCSPI_WAKEUPENABLE_WKEN
;
1051 omap2_mcspi_set_master_mode(master
);
1052 omap2_mcspi_disable_clocks(mcspi
);
1056 static int omap_mcspi_runtime_resume(struct device
*dev
)
1058 struct omap2_mcspi
*mcspi
;
1059 struct spi_master
*master
;
1061 master
= dev_get_drvdata(dev
);
1062 mcspi
= spi_master_get_devdata(master
);
1063 omap2_mcspi_restore_ctx(mcspi
);
1068 static struct omap2_mcspi_platform_config omap2_pdata
= {
1072 static struct omap2_mcspi_platform_config omap4_pdata
= {
1073 .regs_offset
= OMAP4_MCSPI_REG_OFFSET
,
1076 static const struct of_device_id omap_mcspi_of_match
[] = {
1078 .compatible
= "ti,omap2-mcspi",
1079 .data
= &omap2_pdata
,
1082 .compatible
= "ti,omap4-mcspi",
1083 .data
= &omap4_pdata
,
1087 MODULE_DEVICE_TABLE(of
, omap_mcspi_of_match
);
1089 static int __devinit
omap2_mcspi_probe(struct platform_device
*pdev
)
1091 struct spi_master
*master
;
1092 struct omap2_mcspi_platform_config
*pdata
;
1093 struct omap2_mcspi
*mcspi
;
1096 u32 regs_offset
= 0;
1097 static int bus_num
= 1;
1098 struct device_node
*node
= pdev
->dev
.of_node
;
1099 const struct of_device_id
*match
;
1101 master
= spi_alloc_master(&pdev
->dev
, sizeof *mcspi
);
1102 if (master
== NULL
) {
1103 dev_dbg(&pdev
->dev
, "master allocation failed\n");
1107 /* the spi->mode bits understood by this driver: */
1108 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1110 master
->setup
= omap2_mcspi_setup
;
1111 master
->prepare_transfer_hardware
= omap2_prepare_transfer
;
1112 master
->unprepare_transfer_hardware
= omap2_unprepare_transfer
;
1113 master
->transfer_one_message
= omap2_mcspi_transfer_one_message
;
1114 master
->cleanup
= omap2_mcspi_cleanup
;
1115 master
->dev
.of_node
= node
;
1117 match
= of_match_device(omap_mcspi_of_match
, &pdev
->dev
);
1119 u32 num_cs
= 1; /* default number of chipselect */
1120 pdata
= match
->data
;
1122 of_property_read_u32(node
, "ti,spi-num-cs", &num_cs
);
1123 master
->num_chipselect
= num_cs
;
1124 master
->bus_num
= bus_num
++;
1126 pdata
= pdev
->dev
.platform_data
;
1127 master
->num_chipselect
= pdata
->num_cs
;
1129 master
->bus_num
= pdev
->id
;
1131 regs_offset
= pdata
->regs_offset
;
1133 dev_set_drvdata(&pdev
->dev
, master
);
1135 mcspi
= spi_master_get_devdata(master
);
1136 mcspi
->master
= master
;
1138 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1144 r
->start
+= regs_offset
;
1145 r
->end
+= regs_offset
;
1146 mcspi
->phys
= r
->start
;
1148 mcspi
->base
= devm_request_and_ioremap(&pdev
->dev
, r
);
1150 dev_dbg(&pdev
->dev
, "can't ioremap MCSPI\n");
1155 mcspi
->dev
= &pdev
->dev
;
1157 INIT_LIST_HEAD(&mcspi
->ctx
.cs
);
1159 mcspi
->dma_channels
= kcalloc(master
->num_chipselect
,
1160 sizeof(struct omap2_mcspi_dma
),
1163 if (mcspi
->dma_channels
== NULL
)
1166 for (i
= 0; i
< master
->num_chipselect
; i
++) {
1167 char dma_ch_name
[14];
1168 struct resource
*dma_res
;
1170 sprintf(dma_ch_name
, "rx%d", i
);
1171 dma_res
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
,
1174 dev_dbg(&pdev
->dev
, "cannot get DMA RX channel\n");
1179 mcspi
->dma_channels
[i
].dma_rx_channel
= -1;
1180 mcspi
->dma_channels
[i
].dma_rx_sync_dev
= dma_res
->start
;
1181 sprintf(dma_ch_name
, "tx%d", i
);
1182 dma_res
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
,
1185 dev_dbg(&pdev
->dev
, "cannot get DMA TX channel\n");
1190 mcspi
->dma_channels
[i
].dma_tx_channel
= -1;
1191 mcspi
->dma_channels
[i
].dma_tx_sync_dev
= dma_res
->start
;
1197 pm_runtime_use_autosuspend(&pdev
->dev
);
1198 pm_runtime_set_autosuspend_delay(&pdev
->dev
, SPI_AUTOSUSPEND_TIMEOUT
);
1199 pm_runtime_enable(&pdev
->dev
);
1201 if (status
|| omap2_mcspi_master_setup(mcspi
) < 0)
1204 status
= spi_register_master(master
);
1206 goto err_spi_register
;
1211 spi_master_put(master
);
1213 pm_runtime_disable(&pdev
->dev
);
1215 kfree(mcspi
->dma_channels
);
1218 platform_set_drvdata(pdev
, NULL
);
1222 static int __devexit
omap2_mcspi_remove(struct platform_device
*pdev
)
1224 struct spi_master
*master
;
1225 struct omap2_mcspi
*mcspi
;
1226 struct omap2_mcspi_dma
*dma_channels
;
1228 master
= dev_get_drvdata(&pdev
->dev
);
1229 mcspi
= spi_master_get_devdata(master
);
1230 dma_channels
= mcspi
->dma_channels
;
1232 omap2_mcspi_disable_clocks(mcspi
);
1233 pm_runtime_disable(&pdev
->dev
);
1235 spi_unregister_master(master
);
1236 kfree(dma_channels
);
1237 platform_set_drvdata(pdev
, NULL
);
1242 /* work with hotplug and coldplug */
1243 MODULE_ALIAS("platform:omap2_mcspi");
1245 #ifdef CONFIG_SUSPEND
1247 * When SPI wake up from off-mode, CS is in activate state. If it was in
1248 * unactive state when driver was suspend, then force it to unactive state at
1251 static int omap2_mcspi_resume(struct device
*dev
)
1253 struct spi_master
*master
= dev_get_drvdata(dev
);
1254 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
1255 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
1256 struct omap2_mcspi_cs
*cs
;
1258 omap2_mcspi_enable_clocks(mcspi
);
1259 list_for_each_entry(cs
, &ctx
->cs
, node
) {
1260 if ((cs
->chconf0
& OMAP2_MCSPI_CHCONF_FORCE
) == 0) {
1262 * We need to toggle CS state for OMAP take this
1263 * change in account.
1265 MOD_REG_BIT(cs
->chconf0
, OMAP2_MCSPI_CHCONF_FORCE
, 1);
1266 __raw_writel(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1267 MOD_REG_BIT(cs
->chconf0
, OMAP2_MCSPI_CHCONF_FORCE
, 0);
1268 __raw_writel(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1271 omap2_mcspi_disable_clocks(mcspi
);
1275 #define omap2_mcspi_resume NULL
1278 static const struct dev_pm_ops omap2_mcspi_pm_ops
= {
1279 .resume
= omap2_mcspi_resume
,
1280 .runtime_resume
= omap_mcspi_runtime_resume
,
1283 static struct platform_driver omap2_mcspi_driver
= {
1285 .name
= "omap2_mcspi",
1286 .owner
= THIS_MODULE
,
1287 .pm
= &omap2_mcspi_pm_ops
,
1288 .of_match_table
= omap_mcspi_of_match
,
1290 .probe
= omap2_mcspi_probe
,
1291 .remove
= __devexit_p(omap2_mcspi_remove
),
1294 module_platform_driver(omap2_mcspi_driver
);
1295 MODULE_LICENSE("GPL");