2 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
4 * Copyright (C) 2008-2012 ST-Ericsson AB
5 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
9 * Initial version inspired by:
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
11 * Initial adoption to PL022 by:
12 * Sachin Verma <sachin.verma@st.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/device.h>
28 #include <linux/ioport.h>
29 #include <linux/errno.h>
30 #include <linux/interrupt.h>
31 #include <linux/spi/spi.h>
32 #include <linux/delay.h>
33 #include <linux/clk.h>
34 #include <linux/err.h>
35 #include <linux/amba/bus.h>
36 #include <linux/amba/pl022.h>
38 #include <linux/slab.h>
39 #include <linux/dmaengine.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/scatterlist.h>
42 #include <linux/pm_runtime.h>
43 #include <linux/gpio.h>
44 #include <linux/of_gpio.h>
45 #include <linux/pinctrl/consumer.h>
48 * This macro is used to define some register default values.
49 * reg is masked with mask, the OR:ed with an (again masked)
50 * val shifted sb steps to the left.
52 #define SSP_WRITE_BITS(reg, val, mask, sb) \
53 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
56 * This macro is also used to define some default values.
57 * It will just shift val by sb steps to the left and mask
58 * the result with mask.
60 #define GEN_MASK_BITS(val, mask, sb) \
61 (((val)<<(sb)) & (mask))
64 #define DO_NOT_DRIVE_TX 1
66 #define DO_NOT_QUEUE_DMA 0
73 * Macros to access SSP Registers with their offsets
75 #define SSP_CR0(r) (r + 0x000)
76 #define SSP_CR1(r) (r + 0x004)
77 #define SSP_DR(r) (r + 0x008)
78 #define SSP_SR(r) (r + 0x00C)
79 #define SSP_CPSR(r) (r + 0x010)
80 #define SSP_IMSC(r) (r + 0x014)
81 #define SSP_RIS(r) (r + 0x018)
82 #define SSP_MIS(r) (r + 0x01C)
83 #define SSP_ICR(r) (r + 0x020)
84 #define SSP_DMACR(r) (r + 0x024)
85 #define SSP_ITCR(r) (r + 0x080)
86 #define SSP_ITIP(r) (r + 0x084)
87 #define SSP_ITOP(r) (r + 0x088)
88 #define SSP_TDR(r) (r + 0x08C)
90 #define SSP_PID0(r) (r + 0xFE0)
91 #define SSP_PID1(r) (r + 0xFE4)
92 #define SSP_PID2(r) (r + 0xFE8)
93 #define SSP_PID3(r) (r + 0xFEC)
95 #define SSP_CID0(r) (r + 0xFF0)
96 #define SSP_CID1(r) (r + 0xFF4)
97 #define SSP_CID2(r) (r + 0xFF8)
98 #define SSP_CID3(r) (r + 0xFFC)
101 * SSP Control Register 0 - SSP_CR0
103 #define SSP_CR0_MASK_DSS (0x0FUL << 0)
104 #define SSP_CR0_MASK_FRF (0x3UL << 4)
105 #define SSP_CR0_MASK_SPO (0x1UL << 6)
106 #define SSP_CR0_MASK_SPH (0x1UL << 7)
107 #define SSP_CR0_MASK_SCR (0xFFUL << 8)
110 * The ST version of this block moves som bits
111 * in SSP_CR0 and extends it to 32 bits
113 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
114 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
115 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
116 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
119 * SSP Control Register 0 - SSP_CR1
121 #define SSP_CR1_MASK_LBM (0x1UL << 0)
122 #define SSP_CR1_MASK_SSE (0x1UL << 1)
123 #define SSP_CR1_MASK_MS (0x1UL << 2)
124 #define SSP_CR1_MASK_SOD (0x1UL << 3)
127 * The ST version of this block adds some bits
130 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
131 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
132 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
133 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
134 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
135 /* This one is only in the PL023 variant */
136 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
139 * SSP Status Register - SSP_SR
141 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
142 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
143 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
144 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
145 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
148 * SSP Clock Prescale Register - SSP_CPSR
150 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
153 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
155 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
156 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
157 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
158 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
161 * SSP Raw Interrupt Status Register - SSP_RIS
163 /* Receive Overrun Raw Interrupt status */
164 #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
165 /* Receive Timeout Raw Interrupt status */
166 #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
167 /* Receive FIFO Raw Interrupt status */
168 #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
169 /* Transmit FIFO Raw Interrupt status */
170 #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
173 * SSP Masked Interrupt Status Register - SSP_MIS
175 /* Receive Overrun Masked Interrupt status */
176 #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
177 /* Receive Timeout Masked Interrupt status */
178 #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
179 /* Receive FIFO Masked Interrupt status */
180 #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
181 /* Transmit FIFO Masked Interrupt status */
182 #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
185 * SSP Interrupt Clear Register - SSP_ICR
187 /* Receive Overrun Raw Clear Interrupt bit */
188 #define SSP_ICR_MASK_RORIC (0x1UL << 0)
189 /* Receive Timeout Clear Interrupt bit */
190 #define SSP_ICR_MASK_RTIC (0x1UL << 1)
193 * SSP DMA Control Register - SSP_DMACR
195 /* Receive DMA Enable bit */
196 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
197 /* Transmit DMA Enable bit */
198 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
201 * SSP Integration Test control Register - SSP_ITCR
203 #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
204 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
207 * SSP Integration Test Input Register - SSP_ITIP
209 #define ITIP_MASK_SSPRXD (0x1UL << 0)
210 #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
211 #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
212 #define ITIP_MASK_RXDMAC (0x1UL << 3)
213 #define ITIP_MASK_TXDMAC (0x1UL << 4)
214 #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
217 * SSP Integration Test output Register - SSP_ITOP
219 #define ITOP_MASK_SSPTXD (0x1UL << 0)
220 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
221 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
222 #define ITOP_MASK_SSPOEn (0x1UL << 3)
223 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
224 #define ITOP_MASK_RORINTR (0x1UL << 5)
225 #define ITOP_MASK_RTINTR (0x1UL << 6)
226 #define ITOP_MASK_RXINTR (0x1UL << 7)
227 #define ITOP_MASK_TXINTR (0x1UL << 8)
228 #define ITOP_MASK_INTR (0x1UL << 9)
229 #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
230 #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
231 #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
232 #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
235 * SSP Test Data Register - SSP_TDR
237 #define TDR_MASK_TESTDATA (0xFFFFFFFF)
241 * we use the spi_message.state (void *) pointer to
242 * hold a single state value, that's why all this
243 * (void *) casting is done here.
245 #define STATE_START ((void *) 0)
246 #define STATE_RUNNING ((void *) 1)
247 #define STATE_DONE ((void *) 2)
248 #define STATE_ERROR ((void *) -1)
251 * SSP State - Whether Enabled or Disabled
253 #define SSP_DISABLED (0)
254 #define SSP_ENABLED (1)
257 * SSP DMA State - Whether DMA Enabled or Disabled
259 #define SSP_DMA_DISABLED (0)
260 #define SSP_DMA_ENABLED (1)
265 #define SSP_DEFAULT_CLKRATE 0x2
266 #define SSP_DEFAULT_PRESCALE 0x40
269 * SSP Clock Parameter ranges
271 #define CPSDVR_MIN 0x02
272 #define CPSDVR_MAX 0xFE
277 * SSP Interrupt related Macros
279 #define DEFAULT_SSP_REG_IMSC 0x0UL
280 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
281 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
283 #define CLEAR_ALL_INTERRUPTS 0x3
285 #define SPI_POLLING_TIMEOUT 1000
288 * The type of reading going on on this chip
298 * The type of writing going on on this chip
308 * struct vendor_data - vendor-specific config parameters
309 * for PL022 derivates
310 * @fifodepth: depth of FIFOs (both)
311 * @max_bpw: maximum number of bits per word
312 * @unidir: supports unidirection transfers
313 * @extended_cr: 32 bit wide control register 0 with extra
314 * features and extra features in CR1 as found in the ST variants
315 * @pl023: supports a subset of the ST extensions called "PL023"
327 * struct pl022 - This is the private SSP driver data structure
328 * @adev: AMBA device model hookup
329 * @vendor: vendor data for the IP block
330 * @phybase: the physical memory where the SSP device resides
331 * @virtbase: the virtual memory where the SSP is mapped
332 * @clk: outgoing clock "SPICLK" for the SPI bus
333 * @master: SPI framework hookup
334 * @master_info: controller-specific data from machine setup
335 * @kworker: thread struct for message pump
336 * @kworker_task: pointer to task for message pump kworker thread
337 * @pump_messages: work struct for scheduling work to the message pump
338 * @queue_lock: spinlock to syncronise access to message queue
339 * @queue: message queue
340 * @busy: message pump is busy
341 * @running: message pump is running
342 * @pump_transfers: Tasklet used in Interrupt Transfer mode
343 * @cur_msg: Pointer to current spi_message being processed
344 * @cur_transfer: Pointer to current spi_transfer
345 * @cur_chip: pointer to current clients chip(assigned from controller_state)
346 * @next_msg_cs_active: the next message in the queue has been examined
347 * and it was found that it uses the same chip select as the previous
348 * message, so we left it active after the previous transfer, and it's
350 * @tx: current position in TX buffer to be read
351 * @tx_end: end position in TX buffer to be read
352 * @rx: current position in RX buffer to be written
353 * @rx_end: end position in RX buffer to be written
354 * @read: the type of read currently going on
355 * @write: the type of write currently going on
356 * @exp_fifo_level: expected FIFO level
357 * @dma_rx_channel: optional channel for RX DMA
358 * @dma_tx_channel: optional channel for TX DMA
359 * @sgt_rx: scattertable for the RX transfer
360 * @sgt_tx: scattertable for the TX transfer
361 * @dummypage: a dummy page used for driving data on the bus with DMA
362 * @cur_cs: current chip select (gpio)
363 * @chipselects: list of chipselects (gpios)
366 struct amba_device
*adev
;
367 struct vendor_data
*vendor
;
368 resource_size_t phybase
;
369 void __iomem
*virtbase
;
371 struct spi_master
*master
;
372 struct pl022_ssp_controller
*master_info
;
373 /* Message per-transfer pump */
374 struct tasklet_struct pump_transfers
;
375 struct spi_message
*cur_msg
;
376 struct spi_transfer
*cur_transfer
;
377 struct chip_data
*cur_chip
;
378 bool next_msg_cs_active
;
383 enum ssp_reading read
;
384 enum ssp_writing write
;
386 enum ssp_rx_level_trig rx_lev_trig
;
387 enum ssp_tx_level_trig tx_lev_trig
;
389 #ifdef CONFIG_DMA_ENGINE
390 struct dma_chan
*dma_rx_channel
;
391 struct dma_chan
*dma_tx_channel
;
392 struct sg_table sgt_rx
;
393 struct sg_table sgt_tx
;
402 * struct chip_data - To maintain runtime state of SSP for each client chip
403 * @cr0: Value of control register CR0 of SSP - on later ST variants this
404 * register is 32 bits wide rather than just 16
405 * @cr1: Value of control register CR1 of SSP
406 * @dmacr: Value of DMA control Register of SSP
407 * @cpsr: Value of Clock prescale register
408 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
409 * @enable_dma: Whether to enable DMA or not
410 * @read: function ptr to be used to read when doing xfer for this chip
411 * @write: function ptr to be used to write when doing xfer for this chip
412 * @cs_control: chip select callback provided by chip
413 * @xfer_type: polling/interrupt/DMA
415 * Runtime state of the SSP controller, maintained per chip,
416 * This would be set according to the current message that would be served
425 enum ssp_reading read
;
426 enum ssp_writing write
;
427 void (*cs_control
) (u32 command
);
432 * null_cs_control - Dummy chip select function
433 * @command: select/delect the chip
435 * If no chip select function is provided by client this is used as dummy
438 static void null_cs_control(u32 command
)
440 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command
);
443 static void pl022_cs_control(struct pl022
*pl022
, u32 command
)
445 if (gpio_is_valid(pl022
->cur_cs
))
446 gpio_set_value(pl022
->cur_cs
, command
);
448 pl022
->cur_chip
->cs_control(command
);
452 * giveback - current spi_message is over, schedule next message and call
453 * callback of this message. Assumes that caller already
454 * set message->status; dma and pio irqs are blocked
455 * @pl022: SSP driver private data structure
457 static void giveback(struct pl022
*pl022
)
459 struct spi_transfer
*last_transfer
;
460 pl022
->next_msg_cs_active
= false;
462 last_transfer
= list_last_entry(&pl022
->cur_msg
->transfers
,
463 struct spi_transfer
, transfer_list
);
465 /* Delay if requested before any change in chip select */
466 if (last_transfer
->delay_usecs
)
468 * FIXME: This runs in interrupt context.
469 * Is this really smart?
471 udelay(last_transfer
->delay_usecs
);
473 if (!last_transfer
->cs_change
) {
474 struct spi_message
*next_msg
;
477 * cs_change was not set. We can keep the chip select
478 * enabled if there is message in the queue and it is
479 * for the same spi device.
481 * We cannot postpone this until pump_messages, because
482 * after calling msg->complete (below) the driver that
483 * sent the current message could be unloaded, which
484 * could invalidate the cs_control() callback...
486 /* get a pointer to the next message, if any */
487 next_msg
= spi_get_next_queued_message(pl022
->master
);
490 * see if the next and current messages point
491 * to the same spi device.
493 if (next_msg
&& next_msg
->spi
!= pl022
->cur_msg
->spi
)
495 if (!next_msg
|| pl022
->cur_msg
->state
== STATE_ERROR
)
496 pl022_cs_control(pl022
, SSP_CHIP_DESELECT
);
498 pl022
->next_msg_cs_active
= true;
502 pl022
->cur_msg
= NULL
;
503 pl022
->cur_transfer
= NULL
;
504 pl022
->cur_chip
= NULL
;
505 spi_finalize_current_message(pl022
->master
);
507 /* disable the SPI/SSP operation */
508 writew((readw(SSP_CR1(pl022
->virtbase
)) &
509 (~SSP_CR1_MASK_SSE
)), SSP_CR1(pl022
->virtbase
));
514 * flush - flush the FIFO to reach a clean state
515 * @pl022: SSP driver private data structure
517 static int flush(struct pl022
*pl022
)
519 unsigned long limit
= loops_per_jiffy
<< 1;
521 dev_dbg(&pl022
->adev
->dev
, "flush\n");
523 while (readw(SSP_SR(pl022
->virtbase
)) & SSP_SR_MASK_RNE
)
524 readw(SSP_DR(pl022
->virtbase
));
525 } while ((readw(SSP_SR(pl022
->virtbase
)) & SSP_SR_MASK_BSY
) && limit
--);
527 pl022
->exp_fifo_level
= 0;
533 * restore_state - Load configuration of current chip
534 * @pl022: SSP driver private data structure
536 static void restore_state(struct pl022
*pl022
)
538 struct chip_data
*chip
= pl022
->cur_chip
;
540 if (pl022
->vendor
->extended_cr
)
541 writel(chip
->cr0
, SSP_CR0(pl022
->virtbase
));
543 writew(chip
->cr0
, SSP_CR0(pl022
->virtbase
));
544 writew(chip
->cr1
, SSP_CR1(pl022
->virtbase
));
545 writew(chip
->dmacr
, SSP_DMACR(pl022
->virtbase
));
546 writew(chip
->cpsr
, SSP_CPSR(pl022
->virtbase
));
547 writew(DISABLE_ALL_INTERRUPTS
, SSP_IMSC(pl022
->virtbase
));
548 writew(CLEAR_ALL_INTERRUPTS
, SSP_ICR(pl022
->virtbase
));
552 * Default SSP Register Values
554 #define DEFAULT_SSP_REG_CR0 ( \
555 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
556 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
557 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
558 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
559 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
562 /* ST versions have slightly different bit layout */
563 #define DEFAULT_SSP_REG_CR0_ST ( \
564 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
565 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
566 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
567 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
568 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
569 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
570 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
573 /* The PL023 version is slightly different again */
574 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
575 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
576 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
577 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
578 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
581 #define DEFAULT_SSP_REG_CR1 ( \
582 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
583 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
584 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
585 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
588 /* ST versions extend this register to use all 16 bits */
589 #define DEFAULT_SSP_REG_CR1_ST ( \
590 DEFAULT_SSP_REG_CR1 | \
591 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
592 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
593 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
594 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
595 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
599 * The PL023 variant has further differences: no loopback mode, no microwire
600 * support, and a new clock feedback delay setting.
602 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
603 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
604 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
605 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
606 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
607 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
608 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
609 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
610 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
613 #define DEFAULT_SSP_REG_CPSR ( \
614 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
617 #define DEFAULT_SSP_REG_DMACR (\
618 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
619 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
623 * load_ssp_default_config - Load default configuration for SSP
624 * @pl022: SSP driver private data structure
626 static void load_ssp_default_config(struct pl022
*pl022
)
628 if (pl022
->vendor
->pl023
) {
629 writel(DEFAULT_SSP_REG_CR0_ST_PL023
, SSP_CR0(pl022
->virtbase
));
630 writew(DEFAULT_SSP_REG_CR1_ST_PL023
, SSP_CR1(pl022
->virtbase
));
631 } else if (pl022
->vendor
->extended_cr
) {
632 writel(DEFAULT_SSP_REG_CR0_ST
, SSP_CR0(pl022
->virtbase
));
633 writew(DEFAULT_SSP_REG_CR1_ST
, SSP_CR1(pl022
->virtbase
));
635 writew(DEFAULT_SSP_REG_CR0
, SSP_CR0(pl022
->virtbase
));
636 writew(DEFAULT_SSP_REG_CR1
, SSP_CR1(pl022
->virtbase
));
638 writew(DEFAULT_SSP_REG_DMACR
, SSP_DMACR(pl022
->virtbase
));
639 writew(DEFAULT_SSP_REG_CPSR
, SSP_CPSR(pl022
->virtbase
));
640 writew(DISABLE_ALL_INTERRUPTS
, SSP_IMSC(pl022
->virtbase
));
641 writew(CLEAR_ALL_INTERRUPTS
, SSP_ICR(pl022
->virtbase
));
645 * This will write to TX and read from RX according to the parameters
648 static void readwriter(struct pl022
*pl022
)
652 * The FIFO depth is different between primecell variants.
653 * I believe filling in too much in the FIFO might cause
654 * errons in 8bit wide transfers on ARM variants (just 8 words
655 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
657 * To prevent this issue, the TX FIFO is only filled to the
658 * unused RX FIFO fill length, regardless of what the TX
659 * FIFO status flag indicates.
661 dev_dbg(&pl022
->adev
->dev
,
662 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
663 __func__
, pl022
->rx
, pl022
->rx_end
, pl022
->tx
, pl022
->tx_end
);
665 /* Read as much as you can */
666 while ((readw(SSP_SR(pl022
->virtbase
)) & SSP_SR_MASK_RNE
)
667 && (pl022
->rx
< pl022
->rx_end
)) {
668 switch (pl022
->read
) {
670 readw(SSP_DR(pl022
->virtbase
));
673 *(u8
*) (pl022
->rx
) =
674 readw(SSP_DR(pl022
->virtbase
)) & 0xFFU
;
677 *(u16
*) (pl022
->rx
) =
678 (u16
) readw(SSP_DR(pl022
->virtbase
));
681 *(u32
*) (pl022
->rx
) =
682 readl(SSP_DR(pl022
->virtbase
));
685 pl022
->rx
+= (pl022
->cur_chip
->n_bytes
);
686 pl022
->exp_fifo_level
--;
689 * Write as much as possible up to the RX FIFO size
691 while ((pl022
->exp_fifo_level
< pl022
->vendor
->fifodepth
)
692 && (pl022
->tx
< pl022
->tx_end
)) {
693 switch (pl022
->write
) {
695 writew(0x0, SSP_DR(pl022
->virtbase
));
698 writew(*(u8
*) (pl022
->tx
), SSP_DR(pl022
->virtbase
));
701 writew((*(u16
*) (pl022
->tx
)), SSP_DR(pl022
->virtbase
));
704 writel(*(u32
*) (pl022
->tx
), SSP_DR(pl022
->virtbase
));
707 pl022
->tx
+= (pl022
->cur_chip
->n_bytes
);
708 pl022
->exp_fifo_level
++;
710 * This inner reader takes care of things appearing in the RX
711 * FIFO as we're transmitting. This will happen a lot since the
712 * clock starts running when you put things into the TX FIFO,
713 * and then things are continuously clocked into the RX FIFO.
715 while ((readw(SSP_SR(pl022
->virtbase
)) & SSP_SR_MASK_RNE
)
716 && (pl022
->rx
< pl022
->rx_end
)) {
717 switch (pl022
->read
) {
719 readw(SSP_DR(pl022
->virtbase
));
722 *(u8
*) (pl022
->rx
) =
723 readw(SSP_DR(pl022
->virtbase
)) & 0xFFU
;
726 *(u16
*) (pl022
->rx
) =
727 (u16
) readw(SSP_DR(pl022
->virtbase
));
730 *(u32
*) (pl022
->rx
) =
731 readl(SSP_DR(pl022
->virtbase
));
734 pl022
->rx
+= (pl022
->cur_chip
->n_bytes
);
735 pl022
->exp_fifo_level
--;
739 * When we exit here the TX FIFO should be full and the RX FIFO
745 * next_transfer - Move to the Next transfer in the current spi message
746 * @pl022: SSP driver private data structure
748 * This function moves though the linked list of spi transfers in the
749 * current spi message and returns with the state of current spi
750 * message i.e whether its last transfer is done(STATE_DONE) or
751 * Next transfer is ready(STATE_RUNNING)
753 static void *next_transfer(struct pl022
*pl022
)
755 struct spi_message
*msg
= pl022
->cur_msg
;
756 struct spi_transfer
*trans
= pl022
->cur_transfer
;
758 /* Move to next transfer */
759 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
760 pl022
->cur_transfer
=
761 list_entry(trans
->transfer_list
.next
,
762 struct spi_transfer
, transfer_list
);
763 return STATE_RUNNING
;
769 * This DMA functionality is only compiled in if we have
770 * access to the generic DMA devices/DMA engine.
772 #ifdef CONFIG_DMA_ENGINE
773 static void unmap_free_dma_scatter(struct pl022
*pl022
)
775 /* Unmap and free the SG tables */
776 dma_unmap_sg(pl022
->dma_tx_channel
->device
->dev
, pl022
->sgt_tx
.sgl
,
777 pl022
->sgt_tx
.nents
, DMA_TO_DEVICE
);
778 dma_unmap_sg(pl022
->dma_rx_channel
->device
->dev
, pl022
->sgt_rx
.sgl
,
779 pl022
->sgt_rx
.nents
, DMA_FROM_DEVICE
);
780 sg_free_table(&pl022
->sgt_rx
);
781 sg_free_table(&pl022
->sgt_tx
);
784 static void dma_callback(void *data
)
786 struct pl022
*pl022
= data
;
787 struct spi_message
*msg
= pl022
->cur_msg
;
789 BUG_ON(!pl022
->sgt_rx
.sgl
);
793 * Optionally dump out buffers to inspect contents, this is
794 * good if you want to convince yourself that the loopback
795 * read/write contents are the same, when adopting to a new
799 struct scatterlist
*sg
;
802 dma_sync_sg_for_cpu(&pl022
->adev
->dev
,
807 for_each_sg(pl022
->sgt_rx
.sgl
, sg
, pl022
->sgt_rx
.nents
, i
) {
808 dev_dbg(&pl022
->adev
->dev
, "SPI RX SG ENTRY: %d", i
);
809 print_hex_dump(KERN_ERR
, "SPI RX: ",
817 for_each_sg(pl022
->sgt_tx
.sgl
, sg
, pl022
->sgt_tx
.nents
, i
) {
818 dev_dbg(&pl022
->adev
->dev
, "SPI TX SG ENTRY: %d", i
);
819 print_hex_dump(KERN_ERR
, "SPI TX: ",
830 unmap_free_dma_scatter(pl022
);
832 /* Update total bytes transferred */
833 msg
->actual_length
+= pl022
->cur_transfer
->len
;
834 if (pl022
->cur_transfer
->cs_change
)
835 pl022_cs_control(pl022
, SSP_CHIP_DESELECT
);
837 /* Move to next transfer */
838 msg
->state
= next_transfer(pl022
);
839 tasklet_schedule(&pl022
->pump_transfers
);
842 static void setup_dma_scatter(struct pl022
*pl022
,
845 struct sg_table
*sgtab
)
847 struct scatterlist
*sg
;
848 int bytesleft
= length
;
854 for_each_sg(sgtab
->sgl
, sg
, sgtab
->nents
, i
) {
856 * If there are less bytes left than what fits
857 * in the current page (plus page alignment offset)
858 * we just feed in this, else we stuff in as much
861 if (bytesleft
< (PAGE_SIZE
- offset_in_page(bufp
)))
862 mapbytes
= bytesleft
;
864 mapbytes
= PAGE_SIZE
- offset_in_page(bufp
);
865 sg_set_page(sg
, virt_to_page(bufp
),
866 mapbytes
, offset_in_page(bufp
));
868 bytesleft
-= mapbytes
;
869 dev_dbg(&pl022
->adev
->dev
,
870 "set RX/TX target page @ %p, %d bytes, %d left\n",
871 bufp
, mapbytes
, bytesleft
);
874 /* Map the dummy buffer on every page */
875 for_each_sg(sgtab
->sgl
, sg
, sgtab
->nents
, i
) {
876 if (bytesleft
< PAGE_SIZE
)
877 mapbytes
= bytesleft
;
879 mapbytes
= PAGE_SIZE
;
880 sg_set_page(sg
, virt_to_page(pl022
->dummypage
),
882 bytesleft
-= mapbytes
;
883 dev_dbg(&pl022
->adev
->dev
,
884 "set RX/TX to dummy page %d bytes, %d left\n",
885 mapbytes
, bytesleft
);
893 * configure_dma - configures the channels for the next transfer
894 * @pl022: SSP driver's private data structure
896 static int configure_dma(struct pl022
*pl022
)
898 struct dma_slave_config rx_conf
= {
899 .src_addr
= SSP_DR(pl022
->phybase
),
900 .direction
= DMA_DEV_TO_MEM
,
903 struct dma_slave_config tx_conf
= {
904 .dst_addr
= SSP_DR(pl022
->phybase
),
905 .direction
= DMA_MEM_TO_DEV
,
910 int rx_sglen
, tx_sglen
;
911 struct dma_chan
*rxchan
= pl022
->dma_rx_channel
;
912 struct dma_chan
*txchan
= pl022
->dma_tx_channel
;
913 struct dma_async_tx_descriptor
*rxdesc
;
914 struct dma_async_tx_descriptor
*txdesc
;
916 /* Check that the channels are available */
917 if (!rxchan
|| !txchan
)
921 * If supplied, the DMA burstsize should equal the FIFO trigger level.
922 * Notice that the DMA engine uses one-to-one mapping. Since we can
923 * not trigger on 2 elements this needs explicit mapping rather than
926 switch (pl022
->rx_lev_trig
) {
927 case SSP_RX_1_OR_MORE_ELEM
:
928 rx_conf
.src_maxburst
= 1;
930 case SSP_RX_4_OR_MORE_ELEM
:
931 rx_conf
.src_maxburst
= 4;
933 case SSP_RX_8_OR_MORE_ELEM
:
934 rx_conf
.src_maxburst
= 8;
936 case SSP_RX_16_OR_MORE_ELEM
:
937 rx_conf
.src_maxburst
= 16;
939 case SSP_RX_32_OR_MORE_ELEM
:
940 rx_conf
.src_maxburst
= 32;
943 rx_conf
.src_maxburst
= pl022
->vendor
->fifodepth
>> 1;
947 switch (pl022
->tx_lev_trig
) {
948 case SSP_TX_1_OR_MORE_EMPTY_LOC
:
949 tx_conf
.dst_maxburst
= 1;
951 case SSP_TX_4_OR_MORE_EMPTY_LOC
:
952 tx_conf
.dst_maxburst
= 4;
954 case SSP_TX_8_OR_MORE_EMPTY_LOC
:
955 tx_conf
.dst_maxburst
= 8;
957 case SSP_TX_16_OR_MORE_EMPTY_LOC
:
958 tx_conf
.dst_maxburst
= 16;
960 case SSP_TX_32_OR_MORE_EMPTY_LOC
:
961 tx_conf
.dst_maxburst
= 32;
964 tx_conf
.dst_maxburst
= pl022
->vendor
->fifodepth
>> 1;
968 switch (pl022
->read
) {
970 /* Use the same as for writing */
971 rx_conf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_UNDEFINED
;
974 rx_conf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
977 rx_conf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
980 rx_conf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
984 switch (pl022
->write
) {
986 /* Use the same as for reading */
987 tx_conf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_UNDEFINED
;
990 tx_conf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
993 tx_conf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
996 tx_conf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1000 /* SPI pecularity: we need to read and write the same width */
1001 if (rx_conf
.src_addr_width
== DMA_SLAVE_BUSWIDTH_UNDEFINED
)
1002 rx_conf
.src_addr_width
= tx_conf
.dst_addr_width
;
1003 if (tx_conf
.dst_addr_width
== DMA_SLAVE_BUSWIDTH_UNDEFINED
)
1004 tx_conf
.dst_addr_width
= rx_conf
.src_addr_width
;
1005 BUG_ON(rx_conf
.src_addr_width
!= tx_conf
.dst_addr_width
);
1007 dmaengine_slave_config(rxchan
, &rx_conf
);
1008 dmaengine_slave_config(txchan
, &tx_conf
);
1010 /* Create sglists for the transfers */
1011 pages
= DIV_ROUND_UP(pl022
->cur_transfer
->len
, PAGE_SIZE
);
1012 dev_dbg(&pl022
->adev
->dev
, "using %d pages for transfer\n", pages
);
1014 ret
= sg_alloc_table(&pl022
->sgt_rx
, pages
, GFP_ATOMIC
);
1016 goto err_alloc_rx_sg
;
1018 ret
= sg_alloc_table(&pl022
->sgt_tx
, pages
, GFP_ATOMIC
);
1020 goto err_alloc_tx_sg
;
1022 /* Fill in the scatterlists for the RX+TX buffers */
1023 setup_dma_scatter(pl022
, pl022
->rx
,
1024 pl022
->cur_transfer
->len
, &pl022
->sgt_rx
);
1025 setup_dma_scatter(pl022
, pl022
->tx
,
1026 pl022
->cur_transfer
->len
, &pl022
->sgt_tx
);
1028 /* Map DMA buffers */
1029 rx_sglen
= dma_map_sg(rxchan
->device
->dev
, pl022
->sgt_rx
.sgl
,
1030 pl022
->sgt_rx
.nents
, DMA_FROM_DEVICE
);
1034 tx_sglen
= dma_map_sg(txchan
->device
->dev
, pl022
->sgt_tx
.sgl
,
1035 pl022
->sgt_tx
.nents
, DMA_TO_DEVICE
);
1039 /* Send both scatterlists */
1040 rxdesc
= dmaengine_prep_slave_sg(rxchan
,
1044 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1048 txdesc
= dmaengine_prep_slave_sg(txchan
,
1052 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1056 /* Put the callback on the RX transfer only, that should finish last */
1057 rxdesc
->callback
= dma_callback
;
1058 rxdesc
->callback_param
= pl022
;
1060 /* Submit and fire RX and TX with TX last so we're ready to read! */
1061 dmaengine_submit(rxdesc
);
1062 dmaengine_submit(txdesc
);
1063 dma_async_issue_pending(rxchan
);
1064 dma_async_issue_pending(txchan
);
1065 pl022
->dma_running
= true;
1070 dmaengine_terminate_all(txchan
);
1072 dmaengine_terminate_all(rxchan
);
1073 dma_unmap_sg(txchan
->device
->dev
, pl022
->sgt_tx
.sgl
,
1074 pl022
->sgt_tx
.nents
, DMA_TO_DEVICE
);
1076 dma_unmap_sg(rxchan
->device
->dev
, pl022
->sgt_rx
.sgl
,
1077 pl022
->sgt_tx
.nents
, DMA_FROM_DEVICE
);
1079 sg_free_table(&pl022
->sgt_tx
);
1081 sg_free_table(&pl022
->sgt_rx
);
1086 static int pl022_dma_probe(struct pl022
*pl022
)
1088 dma_cap_mask_t mask
;
1090 /* Try to acquire a generic DMA engine slave channel */
1092 dma_cap_set(DMA_SLAVE
, mask
);
1094 * We need both RX and TX channels to do DMA, else do none
1097 pl022
->dma_rx_channel
= dma_request_channel(mask
,
1098 pl022
->master_info
->dma_filter
,
1099 pl022
->master_info
->dma_rx_param
);
1100 if (!pl022
->dma_rx_channel
) {
1101 dev_dbg(&pl022
->adev
->dev
, "no RX DMA channel!\n");
1105 pl022
->dma_tx_channel
= dma_request_channel(mask
,
1106 pl022
->master_info
->dma_filter
,
1107 pl022
->master_info
->dma_tx_param
);
1108 if (!pl022
->dma_tx_channel
) {
1109 dev_dbg(&pl022
->adev
->dev
, "no TX DMA channel!\n");
1113 pl022
->dummypage
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
1114 if (!pl022
->dummypage
) {
1115 dev_dbg(&pl022
->adev
->dev
, "no DMA dummypage!\n");
1116 goto err_no_dummypage
;
1119 dev_info(&pl022
->adev
->dev
, "setup for DMA on RX %s, TX %s\n",
1120 dma_chan_name(pl022
->dma_rx_channel
),
1121 dma_chan_name(pl022
->dma_tx_channel
));
1126 dma_release_channel(pl022
->dma_tx_channel
);
1128 dma_release_channel(pl022
->dma_rx_channel
);
1129 pl022
->dma_rx_channel
= NULL
;
1131 dev_err(&pl022
->adev
->dev
,
1132 "Failed to work in dma mode, work without dma!\n");
1136 static int pl022_dma_autoprobe(struct pl022
*pl022
)
1138 struct device
*dev
= &pl022
->adev
->dev
;
1140 /* automatically configure DMA channels from platform, normally using DT */
1141 pl022
->dma_rx_channel
= dma_request_slave_channel(dev
, "rx");
1142 if (!pl022
->dma_rx_channel
)
1145 pl022
->dma_tx_channel
= dma_request_slave_channel(dev
, "tx");
1146 if (!pl022
->dma_tx_channel
)
1149 pl022
->dummypage
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
1150 if (!pl022
->dummypage
)
1151 goto err_no_dummypage
;
1156 dma_release_channel(pl022
->dma_tx_channel
);
1157 pl022
->dma_tx_channel
= NULL
;
1159 dma_release_channel(pl022
->dma_rx_channel
);
1160 pl022
->dma_rx_channel
= NULL
;
1165 static void terminate_dma(struct pl022
*pl022
)
1167 struct dma_chan
*rxchan
= pl022
->dma_rx_channel
;
1168 struct dma_chan
*txchan
= pl022
->dma_tx_channel
;
1170 dmaengine_terminate_all(rxchan
);
1171 dmaengine_terminate_all(txchan
);
1172 unmap_free_dma_scatter(pl022
);
1173 pl022
->dma_running
= false;
1176 static void pl022_dma_remove(struct pl022
*pl022
)
1178 if (pl022
->dma_running
)
1179 terminate_dma(pl022
);
1180 if (pl022
->dma_tx_channel
)
1181 dma_release_channel(pl022
->dma_tx_channel
);
1182 if (pl022
->dma_rx_channel
)
1183 dma_release_channel(pl022
->dma_rx_channel
);
1184 kfree(pl022
->dummypage
);
1188 static inline int configure_dma(struct pl022
*pl022
)
1193 static inline int pl022_dma_autoprobe(struct pl022
*pl022
)
1198 static inline int pl022_dma_probe(struct pl022
*pl022
)
1203 static inline void pl022_dma_remove(struct pl022
*pl022
)
1209 * pl022_interrupt_handler - Interrupt handler for SSP controller
1211 * This function handles interrupts generated for an interrupt based transfer.
1212 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1213 * current message's state as STATE_ERROR and schedule the tasklet
1214 * pump_transfers which will do the postprocessing of the current message by
1215 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1216 * more data, and writes data in TX FIFO till it is not full. If we complete
1217 * the transfer we move to the next transfer and schedule the tasklet.
1219 static irqreturn_t
pl022_interrupt_handler(int irq
, void *dev_id
)
1221 struct pl022
*pl022
= dev_id
;
1222 struct spi_message
*msg
= pl022
->cur_msg
;
1226 if (unlikely(!msg
)) {
1227 dev_err(&pl022
->adev
->dev
,
1228 "bad message state in interrupt handler");
1233 /* Read the Interrupt Status Register */
1234 irq_status
= readw(SSP_MIS(pl022
->virtbase
));
1236 if (unlikely(!irq_status
))
1240 * This handles the FIFO interrupts, the timeout
1241 * interrupts are flatly ignored, they cannot be
1244 if (unlikely(irq_status
& SSP_MIS_MASK_RORMIS
)) {
1246 * Overrun interrupt - bail out since our Data has been
1249 dev_err(&pl022
->adev
->dev
, "FIFO overrun\n");
1250 if (readw(SSP_SR(pl022
->virtbase
)) & SSP_SR_MASK_RFF
)
1251 dev_err(&pl022
->adev
->dev
,
1252 "RXFIFO is full\n");
1253 if (readw(SSP_SR(pl022
->virtbase
)) & SSP_SR_MASK_TNF
)
1254 dev_err(&pl022
->adev
->dev
,
1255 "TXFIFO is full\n");
1258 * Disable and clear interrupts, disable SSP,
1259 * mark message with bad status so it can be
1262 writew(DISABLE_ALL_INTERRUPTS
,
1263 SSP_IMSC(pl022
->virtbase
));
1264 writew(CLEAR_ALL_INTERRUPTS
, SSP_ICR(pl022
->virtbase
));
1265 writew((readw(SSP_CR1(pl022
->virtbase
)) &
1266 (~SSP_CR1_MASK_SSE
)), SSP_CR1(pl022
->virtbase
));
1267 msg
->state
= STATE_ERROR
;
1269 /* Schedule message queue handler */
1270 tasklet_schedule(&pl022
->pump_transfers
);
1276 if ((pl022
->tx
== pl022
->tx_end
) && (flag
== 0)) {
1278 /* Disable Transmit interrupt, enable receive interrupt */
1279 writew((readw(SSP_IMSC(pl022
->virtbase
)) &
1280 ~SSP_IMSC_MASK_TXIM
) | SSP_IMSC_MASK_RXIM
,
1281 SSP_IMSC(pl022
->virtbase
));
1285 * Since all transactions must write as much as shall be read,
1286 * we can conclude the entire transaction once RX is complete.
1287 * At this point, all TX will always be finished.
1289 if (pl022
->rx
>= pl022
->rx_end
) {
1290 writew(DISABLE_ALL_INTERRUPTS
,
1291 SSP_IMSC(pl022
->virtbase
));
1292 writew(CLEAR_ALL_INTERRUPTS
, SSP_ICR(pl022
->virtbase
));
1293 if (unlikely(pl022
->rx
> pl022
->rx_end
)) {
1294 dev_warn(&pl022
->adev
->dev
, "read %u surplus "
1295 "bytes (did you request an odd "
1296 "number of bytes on a 16bit bus?)\n",
1297 (u32
) (pl022
->rx
- pl022
->rx_end
));
1299 /* Update total bytes transferred */
1300 msg
->actual_length
+= pl022
->cur_transfer
->len
;
1301 if (pl022
->cur_transfer
->cs_change
)
1302 pl022_cs_control(pl022
, SSP_CHIP_DESELECT
);
1303 /* Move to next transfer */
1304 msg
->state
= next_transfer(pl022
);
1305 tasklet_schedule(&pl022
->pump_transfers
);
1313 * This sets up the pointers to memory for the next message to
1314 * send out on the SPI bus.
1316 static int set_up_next_transfer(struct pl022
*pl022
,
1317 struct spi_transfer
*transfer
)
1321 /* Sanity check the message for this bus width */
1322 residue
= pl022
->cur_transfer
->len
% pl022
->cur_chip
->n_bytes
;
1323 if (unlikely(residue
!= 0)) {
1324 dev_err(&pl022
->adev
->dev
,
1325 "message of %u bytes to transmit but the current "
1326 "chip bus has a data width of %u bytes!\n",
1327 pl022
->cur_transfer
->len
,
1328 pl022
->cur_chip
->n_bytes
);
1329 dev_err(&pl022
->adev
->dev
, "skipping this message\n");
1332 pl022
->tx
= (void *)transfer
->tx_buf
;
1333 pl022
->tx_end
= pl022
->tx
+ pl022
->cur_transfer
->len
;
1334 pl022
->rx
= (void *)transfer
->rx_buf
;
1335 pl022
->rx_end
= pl022
->rx
+ pl022
->cur_transfer
->len
;
1337 pl022
->tx
? pl022
->cur_chip
->write
: WRITING_NULL
;
1338 pl022
->read
= pl022
->rx
? pl022
->cur_chip
->read
: READING_NULL
;
1343 * pump_transfers - Tasklet function which schedules next transfer
1344 * when running in interrupt or DMA transfer mode.
1345 * @data: SSP driver private data structure
1348 static void pump_transfers(unsigned long data
)
1350 struct pl022
*pl022
= (struct pl022
*) data
;
1351 struct spi_message
*message
= NULL
;
1352 struct spi_transfer
*transfer
= NULL
;
1353 struct spi_transfer
*previous
= NULL
;
1355 /* Get current state information */
1356 message
= pl022
->cur_msg
;
1357 transfer
= pl022
->cur_transfer
;
1359 /* Handle for abort */
1360 if (message
->state
== STATE_ERROR
) {
1361 message
->status
= -EIO
;
1366 /* Handle end of message */
1367 if (message
->state
== STATE_DONE
) {
1368 message
->status
= 0;
1373 /* Delay if requested at end of transfer before CS change */
1374 if (message
->state
== STATE_RUNNING
) {
1375 previous
= list_entry(transfer
->transfer_list
.prev
,
1376 struct spi_transfer
,
1378 if (previous
->delay_usecs
)
1380 * FIXME: This runs in interrupt context.
1381 * Is this really smart?
1383 udelay(previous
->delay_usecs
);
1385 /* Reselect chip select only if cs_change was requested */
1386 if (previous
->cs_change
)
1387 pl022_cs_control(pl022
, SSP_CHIP_SELECT
);
1390 message
->state
= STATE_RUNNING
;
1393 if (set_up_next_transfer(pl022
, transfer
)) {
1394 message
->state
= STATE_ERROR
;
1395 message
->status
= -EIO
;
1399 /* Flush the FIFOs and let's go! */
1402 if (pl022
->cur_chip
->enable_dma
) {
1403 if (configure_dma(pl022
)) {
1404 dev_dbg(&pl022
->adev
->dev
,
1405 "configuration of DMA failed, fall back to interrupt mode\n");
1406 goto err_config_dma
;
1412 /* enable all interrupts except RX */
1413 writew(ENABLE_ALL_INTERRUPTS
& ~SSP_IMSC_MASK_RXIM
, SSP_IMSC(pl022
->virtbase
));
1416 static void do_interrupt_dma_transfer(struct pl022
*pl022
)
1419 * Default is to enable all interrupts except RX -
1420 * this will be enabled once TX is complete
1422 u32 irqflags
= ENABLE_ALL_INTERRUPTS
& ~SSP_IMSC_MASK_RXIM
;
1424 /* Enable target chip, if not already active */
1425 if (!pl022
->next_msg_cs_active
)
1426 pl022_cs_control(pl022
, SSP_CHIP_SELECT
);
1428 if (set_up_next_transfer(pl022
, pl022
->cur_transfer
)) {
1430 pl022
->cur_msg
->state
= STATE_ERROR
;
1431 pl022
->cur_msg
->status
= -EIO
;
1435 /* If we're using DMA, set up DMA here */
1436 if (pl022
->cur_chip
->enable_dma
) {
1437 /* Configure DMA transfer */
1438 if (configure_dma(pl022
)) {
1439 dev_dbg(&pl022
->adev
->dev
,
1440 "configuration of DMA failed, fall back to interrupt mode\n");
1441 goto err_config_dma
;
1443 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1444 irqflags
= DISABLE_ALL_INTERRUPTS
;
1447 /* Enable SSP, turn on interrupts */
1448 writew((readw(SSP_CR1(pl022
->virtbase
)) | SSP_CR1_MASK_SSE
),
1449 SSP_CR1(pl022
->virtbase
));
1450 writew(irqflags
, SSP_IMSC(pl022
->virtbase
));
1453 static void do_polling_transfer(struct pl022
*pl022
)
1455 struct spi_message
*message
= NULL
;
1456 struct spi_transfer
*transfer
= NULL
;
1457 struct spi_transfer
*previous
= NULL
;
1458 struct chip_data
*chip
;
1459 unsigned long time
, timeout
;
1461 chip
= pl022
->cur_chip
;
1462 message
= pl022
->cur_msg
;
1464 while (message
->state
!= STATE_DONE
) {
1465 /* Handle for abort */
1466 if (message
->state
== STATE_ERROR
)
1468 transfer
= pl022
->cur_transfer
;
1470 /* Delay if requested at end of transfer */
1471 if (message
->state
== STATE_RUNNING
) {
1473 list_entry(transfer
->transfer_list
.prev
,
1474 struct spi_transfer
, transfer_list
);
1475 if (previous
->delay_usecs
)
1476 udelay(previous
->delay_usecs
);
1477 if (previous
->cs_change
)
1478 pl022_cs_control(pl022
, SSP_CHIP_SELECT
);
1481 message
->state
= STATE_RUNNING
;
1482 if (!pl022
->next_msg_cs_active
)
1483 pl022_cs_control(pl022
, SSP_CHIP_SELECT
);
1486 /* Configuration Changing Per Transfer */
1487 if (set_up_next_transfer(pl022
, transfer
)) {
1489 message
->state
= STATE_ERROR
;
1492 /* Flush FIFOs and enable SSP */
1494 writew((readw(SSP_CR1(pl022
->virtbase
)) | SSP_CR1_MASK_SSE
),
1495 SSP_CR1(pl022
->virtbase
));
1497 dev_dbg(&pl022
->adev
->dev
, "polling transfer ongoing ...\n");
1499 timeout
= jiffies
+ msecs_to_jiffies(SPI_POLLING_TIMEOUT
);
1500 while (pl022
->tx
< pl022
->tx_end
|| pl022
->rx
< pl022
->rx_end
) {
1503 if (time_after(time
, timeout
)) {
1504 dev_warn(&pl022
->adev
->dev
,
1505 "%s: timeout!\n", __func__
);
1506 message
->state
= STATE_ERROR
;
1512 /* Update total byte transferred */
1513 message
->actual_length
+= pl022
->cur_transfer
->len
;
1514 if (pl022
->cur_transfer
->cs_change
)
1515 pl022_cs_control(pl022
, SSP_CHIP_DESELECT
);
1516 /* Move to next transfer */
1517 message
->state
= next_transfer(pl022
);
1520 /* Handle end of message */
1521 if (message
->state
== STATE_DONE
)
1522 message
->status
= 0;
1524 message
->status
= -EIO
;
1530 static int pl022_transfer_one_message(struct spi_master
*master
,
1531 struct spi_message
*msg
)
1533 struct pl022
*pl022
= spi_master_get_devdata(master
);
1535 /* Initial message state */
1536 pl022
->cur_msg
= msg
;
1537 msg
->state
= STATE_START
;
1539 pl022
->cur_transfer
= list_entry(msg
->transfers
.next
,
1540 struct spi_transfer
, transfer_list
);
1542 /* Setup the SPI using the per chip configuration */
1543 pl022
->cur_chip
= spi_get_ctldata(msg
->spi
);
1544 pl022
->cur_cs
= pl022
->chipselects
[msg
->spi
->chip_select
];
1546 restore_state(pl022
);
1549 if (pl022
->cur_chip
->xfer_type
== POLLING_TRANSFER
)
1550 do_polling_transfer(pl022
);
1552 do_interrupt_dma_transfer(pl022
);
1557 static int pl022_unprepare_transfer_hardware(struct spi_master
*master
)
1559 struct pl022
*pl022
= spi_master_get_devdata(master
);
1561 /* nothing more to do - disable spi/ssp and power off */
1562 writew((readw(SSP_CR1(pl022
->virtbase
)) &
1563 (~SSP_CR1_MASK_SSE
)), SSP_CR1(pl022
->virtbase
));
1568 static int verify_controller_parameters(struct pl022
*pl022
,
1569 struct pl022_config_chip
const *chip_info
)
1571 if ((chip_info
->iface
< SSP_INTERFACE_MOTOROLA_SPI
)
1572 || (chip_info
->iface
> SSP_INTERFACE_UNIDIRECTIONAL
)) {
1573 dev_err(&pl022
->adev
->dev
,
1574 "interface is configured incorrectly\n");
1577 if ((chip_info
->iface
== SSP_INTERFACE_UNIDIRECTIONAL
) &&
1578 (!pl022
->vendor
->unidir
)) {
1579 dev_err(&pl022
->adev
->dev
,
1580 "unidirectional mode not supported in this "
1581 "hardware version\n");
1584 if ((chip_info
->hierarchy
!= SSP_MASTER
)
1585 && (chip_info
->hierarchy
!= SSP_SLAVE
)) {
1586 dev_err(&pl022
->adev
->dev
,
1587 "hierarchy is configured incorrectly\n");
1590 if ((chip_info
->com_mode
!= INTERRUPT_TRANSFER
)
1591 && (chip_info
->com_mode
!= DMA_TRANSFER
)
1592 && (chip_info
->com_mode
!= POLLING_TRANSFER
)) {
1593 dev_err(&pl022
->adev
->dev
,
1594 "Communication mode is configured incorrectly\n");
1597 switch (chip_info
->rx_lev_trig
) {
1598 case SSP_RX_1_OR_MORE_ELEM
:
1599 case SSP_RX_4_OR_MORE_ELEM
:
1600 case SSP_RX_8_OR_MORE_ELEM
:
1601 /* These are always OK, all variants can handle this */
1603 case SSP_RX_16_OR_MORE_ELEM
:
1604 if (pl022
->vendor
->fifodepth
< 16) {
1605 dev_err(&pl022
->adev
->dev
,
1606 "RX FIFO Trigger Level is configured incorrectly\n");
1610 case SSP_RX_32_OR_MORE_ELEM
:
1611 if (pl022
->vendor
->fifodepth
< 32) {
1612 dev_err(&pl022
->adev
->dev
,
1613 "RX FIFO Trigger Level is configured incorrectly\n");
1618 dev_err(&pl022
->adev
->dev
,
1619 "RX FIFO Trigger Level is configured incorrectly\n");
1622 switch (chip_info
->tx_lev_trig
) {
1623 case SSP_TX_1_OR_MORE_EMPTY_LOC
:
1624 case SSP_TX_4_OR_MORE_EMPTY_LOC
:
1625 case SSP_TX_8_OR_MORE_EMPTY_LOC
:
1626 /* These are always OK, all variants can handle this */
1628 case SSP_TX_16_OR_MORE_EMPTY_LOC
:
1629 if (pl022
->vendor
->fifodepth
< 16) {
1630 dev_err(&pl022
->adev
->dev
,
1631 "TX FIFO Trigger Level is configured incorrectly\n");
1635 case SSP_TX_32_OR_MORE_EMPTY_LOC
:
1636 if (pl022
->vendor
->fifodepth
< 32) {
1637 dev_err(&pl022
->adev
->dev
,
1638 "TX FIFO Trigger Level is configured incorrectly\n");
1643 dev_err(&pl022
->adev
->dev
,
1644 "TX FIFO Trigger Level is configured incorrectly\n");
1647 if (chip_info
->iface
== SSP_INTERFACE_NATIONAL_MICROWIRE
) {
1648 if ((chip_info
->ctrl_len
< SSP_BITS_4
)
1649 || (chip_info
->ctrl_len
> SSP_BITS_32
)) {
1650 dev_err(&pl022
->adev
->dev
,
1651 "CTRL LEN is configured incorrectly\n");
1654 if ((chip_info
->wait_state
!= SSP_MWIRE_WAIT_ZERO
)
1655 && (chip_info
->wait_state
!= SSP_MWIRE_WAIT_ONE
)) {
1656 dev_err(&pl022
->adev
->dev
,
1657 "Wait State is configured incorrectly\n");
1660 /* Half duplex is only available in the ST Micro version */
1661 if (pl022
->vendor
->extended_cr
) {
1662 if ((chip_info
->duplex
!=
1663 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX
)
1664 && (chip_info
->duplex
!=
1665 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX
)) {
1666 dev_err(&pl022
->adev
->dev
,
1667 "Microwire duplex mode is configured incorrectly\n");
1671 if (chip_info
->duplex
!= SSP_MICROWIRE_CHANNEL_FULL_DUPLEX
)
1672 dev_err(&pl022
->adev
->dev
,
1673 "Microwire half duplex mode requested,"
1674 " but this is only available in the"
1675 " ST version of PL022\n");
1682 static inline u32
spi_rate(u32 rate
, u16 cpsdvsr
, u16 scr
)
1684 return rate
/ (cpsdvsr
* (1 + scr
));
1687 static int calculate_effective_freq(struct pl022
*pl022
, int freq
, struct
1688 ssp_clock_params
* clk_freq
)
1690 /* Lets calculate the frequency parameters */
1691 u16 cpsdvsr
= CPSDVR_MIN
, scr
= SCR_MIN
;
1692 u32 rate
, max_tclk
, min_tclk
, best_freq
= 0, best_cpsdvsr
= 0,
1693 best_scr
= 0, tmp
, found
= 0;
1695 rate
= clk_get_rate(pl022
->clk
);
1696 /* cpsdvscr = 2 & scr 0 */
1697 max_tclk
= spi_rate(rate
, CPSDVR_MIN
, SCR_MIN
);
1698 /* cpsdvsr = 254 & scr = 255 */
1699 min_tclk
= spi_rate(rate
, CPSDVR_MAX
, SCR_MAX
);
1701 if (freq
> max_tclk
)
1702 dev_warn(&pl022
->adev
->dev
,
1703 "Max speed that can be programmed is %d Hz, you requested %d\n",
1706 if (freq
< min_tclk
) {
1707 dev_err(&pl022
->adev
->dev
,
1708 "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
1714 * best_freq will give closest possible available rate (<= requested
1715 * freq) for all values of scr & cpsdvsr.
1717 while ((cpsdvsr
<= CPSDVR_MAX
) && !found
) {
1718 while (scr
<= SCR_MAX
) {
1719 tmp
= spi_rate(rate
, cpsdvsr
, scr
);
1722 /* we need lower freq */
1728 * If found exact value, mark found and break.
1729 * If found more closer value, update and break.
1731 if (tmp
> best_freq
) {
1733 best_cpsdvsr
= cpsdvsr
;
1740 * increased scr will give lower rates, which are not
1749 WARN(!best_freq
, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1752 clk_freq
->cpsdvsr
= (u8
) (best_cpsdvsr
& 0xFF);
1753 clk_freq
->scr
= (u8
) (best_scr
& 0xFF);
1754 dev_dbg(&pl022
->adev
->dev
,
1755 "SSP Target Frequency is: %u, Effective Frequency is %u\n",
1757 dev_dbg(&pl022
->adev
->dev
, "SSP cpsdvsr = %d, scr = %d\n",
1758 clk_freq
->cpsdvsr
, clk_freq
->scr
);
1764 * A piece of default chip info unless the platform
1767 static const struct pl022_config_chip pl022_default_chip_info
= {
1768 .com_mode
= POLLING_TRANSFER
,
1769 .iface
= SSP_INTERFACE_MOTOROLA_SPI
,
1770 .hierarchy
= SSP_SLAVE
,
1771 .slave_tx_disable
= DO_NOT_DRIVE_TX
,
1772 .rx_lev_trig
= SSP_RX_1_OR_MORE_ELEM
,
1773 .tx_lev_trig
= SSP_TX_1_OR_MORE_EMPTY_LOC
,
1774 .ctrl_len
= SSP_BITS_8
,
1775 .wait_state
= SSP_MWIRE_WAIT_ZERO
,
1776 .duplex
= SSP_MICROWIRE_CHANNEL_FULL_DUPLEX
,
1777 .cs_control
= null_cs_control
,
1781 * pl022_setup - setup function registered to SPI master framework
1782 * @spi: spi device which is requesting setup
1784 * This function is registered to the SPI framework for this SPI master
1785 * controller. If it is the first time when setup is called by this device,
1786 * this function will initialize the runtime state for this chip and save
1787 * the same in the device structure. Else it will update the runtime info
1788 * with the updated chip info. Nothing is really being written to the
1789 * controller hardware here, that is not done until the actual transfer
1792 static int pl022_setup(struct spi_device
*spi
)
1794 struct pl022_config_chip
const *chip_info
;
1795 struct pl022_config_chip chip_info_dt
;
1796 struct chip_data
*chip
;
1797 struct ssp_clock_params clk_freq
= { .cpsdvsr
= 0, .scr
= 0};
1799 struct pl022
*pl022
= spi_master_get_devdata(spi
->master
);
1800 unsigned int bits
= spi
->bits_per_word
;
1802 struct device_node
*np
= spi
->dev
.of_node
;
1804 if (!spi
->max_speed_hz
)
1807 /* Get controller_state if one is supplied */
1808 chip
= spi_get_ctldata(spi
);
1811 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
1814 "cannot allocate controller state\n");
1818 "allocated memory for controller's runtime state\n");
1821 /* Get controller data if one is supplied */
1822 chip_info
= spi
->controller_data
;
1824 if (chip_info
== NULL
) {
1826 chip_info_dt
= pl022_default_chip_info
;
1828 chip_info_dt
.hierarchy
= SSP_MASTER
;
1829 of_property_read_u32(np
, "pl022,interface",
1830 &chip_info_dt
.iface
);
1831 of_property_read_u32(np
, "pl022,com-mode",
1832 &chip_info_dt
.com_mode
);
1833 of_property_read_u32(np
, "pl022,rx-level-trig",
1834 &chip_info_dt
.rx_lev_trig
);
1835 of_property_read_u32(np
, "pl022,tx-level-trig",
1836 &chip_info_dt
.tx_lev_trig
);
1837 of_property_read_u32(np
, "pl022,ctrl-len",
1838 &chip_info_dt
.ctrl_len
);
1839 of_property_read_u32(np
, "pl022,wait-state",
1840 &chip_info_dt
.wait_state
);
1841 of_property_read_u32(np
, "pl022,duplex",
1842 &chip_info_dt
.duplex
);
1844 chip_info
= &chip_info_dt
;
1846 chip_info
= &pl022_default_chip_info
;
1847 /* spi_board_info.controller_data not is supplied */
1849 "using default controller_data settings\n");
1853 "using user supplied controller_data settings\n");
1856 * We can override with custom divisors, else we use the board
1859 if ((0 == chip_info
->clk_freq
.cpsdvsr
)
1860 && (0 == chip_info
->clk_freq
.scr
)) {
1861 status
= calculate_effective_freq(pl022
,
1865 goto err_config_params
;
1867 memcpy(&clk_freq
, &chip_info
->clk_freq
, sizeof(clk_freq
));
1868 if ((clk_freq
.cpsdvsr
% 2) != 0)
1870 clk_freq
.cpsdvsr
- 1;
1872 if ((clk_freq
.cpsdvsr
< CPSDVR_MIN
)
1873 || (clk_freq
.cpsdvsr
> CPSDVR_MAX
)) {
1876 "cpsdvsr is configured incorrectly\n");
1877 goto err_config_params
;
1880 status
= verify_controller_parameters(pl022
, chip_info
);
1882 dev_err(&spi
->dev
, "controller data is incorrect");
1883 goto err_config_params
;
1886 pl022
->rx_lev_trig
= chip_info
->rx_lev_trig
;
1887 pl022
->tx_lev_trig
= chip_info
->tx_lev_trig
;
1889 /* Now set controller state based on controller data */
1890 chip
->xfer_type
= chip_info
->com_mode
;
1891 if (!chip_info
->cs_control
) {
1892 chip
->cs_control
= null_cs_control
;
1893 if (!gpio_is_valid(pl022
->chipselects
[spi
->chip_select
]))
1895 "invalid chip select\n");
1897 chip
->cs_control
= chip_info
->cs_control
;
1899 /* Check bits per word with vendor specific range */
1900 if ((bits
<= 3) || (bits
> pl022
->vendor
->max_bpw
)) {
1902 dev_err(&spi
->dev
, "illegal data size for this controller!\n");
1903 dev_err(&spi
->dev
, "This controller can only handle 4 <= n <= %d bit words\n",
1904 pl022
->vendor
->max_bpw
);
1905 goto err_config_params
;
1906 } else if (bits
<= 8) {
1907 dev_dbg(&spi
->dev
, "4 <= n <=8 bits per word\n");
1909 chip
->read
= READING_U8
;
1910 chip
->write
= WRITING_U8
;
1911 } else if (bits
<= 16) {
1912 dev_dbg(&spi
->dev
, "9 <= n <= 16 bits per word\n");
1914 chip
->read
= READING_U16
;
1915 chip
->write
= WRITING_U16
;
1917 dev_dbg(&spi
->dev
, "17 <= n <= 32 bits per word\n");
1919 chip
->read
= READING_U32
;
1920 chip
->write
= WRITING_U32
;
1923 /* Now Initialize all register settings required for this chip */
1928 if ((chip_info
->com_mode
== DMA_TRANSFER
)
1929 && ((pl022
->master_info
)->enable_dma
)) {
1930 chip
->enable_dma
= true;
1931 dev_dbg(&spi
->dev
, "DMA mode set in controller state\n");
1932 SSP_WRITE_BITS(chip
->dmacr
, SSP_DMA_ENABLED
,
1933 SSP_DMACR_MASK_RXDMAE
, 0);
1934 SSP_WRITE_BITS(chip
->dmacr
, SSP_DMA_ENABLED
,
1935 SSP_DMACR_MASK_TXDMAE
, 1);
1937 chip
->enable_dma
= false;
1938 dev_dbg(&spi
->dev
, "DMA mode NOT set in controller state\n");
1939 SSP_WRITE_BITS(chip
->dmacr
, SSP_DMA_DISABLED
,
1940 SSP_DMACR_MASK_RXDMAE
, 0);
1941 SSP_WRITE_BITS(chip
->dmacr
, SSP_DMA_DISABLED
,
1942 SSP_DMACR_MASK_TXDMAE
, 1);
1945 chip
->cpsr
= clk_freq
.cpsdvsr
;
1947 /* Special setup for the ST micro extended control registers */
1948 if (pl022
->vendor
->extended_cr
) {
1951 if (pl022
->vendor
->pl023
) {
1952 /* These bits are only in the PL023 */
1953 SSP_WRITE_BITS(chip
->cr1
, chip_info
->clkdelay
,
1954 SSP_CR1_MASK_FBCLKDEL_ST
, 13);
1956 /* These bits are in the PL022 but not PL023 */
1957 SSP_WRITE_BITS(chip
->cr0
, chip_info
->duplex
,
1958 SSP_CR0_MASK_HALFDUP_ST
, 5);
1959 SSP_WRITE_BITS(chip
->cr0
, chip_info
->ctrl_len
,
1960 SSP_CR0_MASK_CSS_ST
, 16);
1961 SSP_WRITE_BITS(chip
->cr0
, chip_info
->iface
,
1962 SSP_CR0_MASK_FRF_ST
, 21);
1963 SSP_WRITE_BITS(chip
->cr1
, chip_info
->wait_state
,
1964 SSP_CR1_MASK_MWAIT_ST
, 6);
1966 SSP_WRITE_BITS(chip
->cr0
, bits
- 1,
1967 SSP_CR0_MASK_DSS_ST
, 0);
1969 if (spi
->mode
& SPI_LSB_FIRST
) {
1976 SSP_WRITE_BITS(chip
->cr1
, tmp
, SSP_CR1_MASK_RENDN_ST
, 4);
1977 SSP_WRITE_BITS(chip
->cr1
, etx
, SSP_CR1_MASK_TENDN_ST
, 5);
1978 SSP_WRITE_BITS(chip
->cr1
, chip_info
->rx_lev_trig
,
1979 SSP_CR1_MASK_RXIFLSEL_ST
, 7);
1980 SSP_WRITE_BITS(chip
->cr1
, chip_info
->tx_lev_trig
,
1981 SSP_CR1_MASK_TXIFLSEL_ST
, 10);
1983 SSP_WRITE_BITS(chip
->cr0
, bits
- 1,
1984 SSP_CR0_MASK_DSS
, 0);
1985 SSP_WRITE_BITS(chip
->cr0
, chip_info
->iface
,
1986 SSP_CR0_MASK_FRF
, 4);
1989 /* Stuff that is common for all versions */
1990 if (spi
->mode
& SPI_CPOL
)
1991 tmp
= SSP_CLK_POL_IDLE_HIGH
;
1993 tmp
= SSP_CLK_POL_IDLE_LOW
;
1994 SSP_WRITE_BITS(chip
->cr0
, tmp
, SSP_CR0_MASK_SPO
, 6);
1996 if (spi
->mode
& SPI_CPHA
)
1997 tmp
= SSP_CLK_SECOND_EDGE
;
1999 tmp
= SSP_CLK_FIRST_EDGE
;
2000 SSP_WRITE_BITS(chip
->cr0
, tmp
, SSP_CR0_MASK_SPH
, 7);
2002 SSP_WRITE_BITS(chip
->cr0
, clk_freq
.scr
, SSP_CR0_MASK_SCR
, 8);
2003 /* Loopback is available on all versions except PL023 */
2004 if (pl022
->vendor
->loopback
) {
2005 if (spi
->mode
& SPI_LOOP
)
2006 tmp
= LOOPBACK_ENABLED
;
2008 tmp
= LOOPBACK_DISABLED
;
2009 SSP_WRITE_BITS(chip
->cr1
, tmp
, SSP_CR1_MASK_LBM
, 0);
2011 SSP_WRITE_BITS(chip
->cr1
, SSP_DISABLED
, SSP_CR1_MASK_SSE
, 1);
2012 SSP_WRITE_BITS(chip
->cr1
, chip_info
->hierarchy
, SSP_CR1_MASK_MS
, 2);
2013 SSP_WRITE_BITS(chip
->cr1
, chip_info
->slave_tx_disable
, SSP_CR1_MASK_SOD
,
2016 /* Save controller_state */
2017 spi_set_ctldata(spi
, chip
);
2020 spi_set_ctldata(spi
, NULL
);
2026 * pl022_cleanup - cleanup function registered to SPI master framework
2027 * @spi: spi device which is requesting cleanup
2029 * This function is registered to the SPI framework for this SPI master
2030 * controller. It will free the runtime state of chip.
2032 static void pl022_cleanup(struct spi_device
*spi
)
2034 struct chip_data
*chip
= spi_get_ctldata(spi
);
2036 spi_set_ctldata(spi
, NULL
);
2040 static struct pl022_ssp_controller
*
2041 pl022_platform_data_dt_get(struct device
*dev
)
2043 struct device_node
*np
= dev
->of_node
;
2044 struct pl022_ssp_controller
*pd
;
2048 dev_err(dev
, "no dt node defined\n");
2052 pd
= devm_kzalloc(dev
, sizeof(struct pl022_ssp_controller
), GFP_KERNEL
);
2054 dev_err(dev
, "cannot allocate platform data memory\n");
2060 of_property_read_u32(np
, "num-cs", &tmp
);
2061 pd
->num_chipselect
= tmp
;
2062 of_property_read_u32(np
, "pl022,autosuspend-delay",
2063 &pd
->autosuspend_delay
);
2064 pd
->rt
= of_property_read_bool(np
, "pl022,rt");
2069 static int pl022_probe(struct amba_device
*adev
, const struct amba_id
*id
)
2071 struct device
*dev
= &adev
->dev
;
2072 struct pl022_ssp_controller
*platform_info
=
2073 dev_get_platdata(&adev
->dev
);
2074 struct spi_master
*master
;
2075 struct pl022
*pl022
= NULL
; /*Data for this driver */
2076 struct device_node
*np
= adev
->dev
.of_node
;
2077 int status
= 0, i
, num_cs
;
2079 dev_info(&adev
->dev
,
2080 "ARM PL022 driver, device ID: 0x%08x\n", adev
->periphid
);
2081 if (!platform_info
&& IS_ENABLED(CONFIG_OF
))
2082 platform_info
= pl022_platform_data_dt_get(dev
);
2084 if (!platform_info
) {
2085 dev_err(dev
, "probe: no platform data defined\n");
2089 if (platform_info
->num_chipselect
) {
2090 num_cs
= platform_info
->num_chipselect
;
2092 dev_err(dev
, "probe: no chip select defined\n");
2096 /* Allocate master with space for data */
2097 master
= spi_alloc_master(dev
, sizeof(struct pl022
));
2098 if (master
== NULL
) {
2099 dev_err(&adev
->dev
, "probe - cannot alloc SPI master\n");
2103 pl022
= spi_master_get_devdata(master
);
2104 pl022
->master
= master
;
2105 pl022
->master_info
= platform_info
;
2107 pl022
->vendor
= id
->data
;
2108 pl022
->chipselects
= devm_kzalloc(dev
, num_cs
* sizeof(int),
2112 * Bus Number Which has been Assigned to this SSP controller
2115 master
->bus_num
= platform_info
->bus_id
;
2116 master
->num_chipselect
= num_cs
;
2117 master
->cleanup
= pl022_cleanup
;
2118 master
->setup
= pl022_setup
;
2119 master
->auto_runtime_pm
= true;
2120 master
->transfer_one_message
= pl022_transfer_one_message
;
2121 master
->unprepare_transfer_hardware
= pl022_unprepare_transfer_hardware
;
2122 master
->rt
= platform_info
->rt
;
2123 master
->dev
.of_node
= dev
->of_node
;
2125 if (platform_info
->num_chipselect
&& platform_info
->chipselects
) {
2126 for (i
= 0; i
< num_cs
; i
++)
2127 pl022
->chipselects
[i
] = platform_info
->chipselects
[i
];
2128 } else if (IS_ENABLED(CONFIG_OF
)) {
2129 for (i
= 0; i
< num_cs
; i
++) {
2130 int cs_gpio
= of_get_named_gpio(np
, "cs-gpios", i
);
2132 if (cs_gpio
== -EPROBE_DEFER
) {
2133 status
= -EPROBE_DEFER
;
2137 pl022
->chipselects
[i
] = cs_gpio
;
2139 if (gpio_is_valid(cs_gpio
)) {
2140 if (devm_gpio_request(dev
, cs_gpio
, "ssp-pl022"))
2142 "could not request %d gpio\n",
2144 else if (gpio_direction_output(cs_gpio
, 1))
2146 "could set gpio %d as output\n",
2153 * Supports mode 0-3, loopback, and active low CS. Transfers are
2154 * always MS bit first on the original pl022.
2156 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
| SPI_LOOP
;
2157 if (pl022
->vendor
->extended_cr
)
2158 master
->mode_bits
|= SPI_LSB_FIRST
;
2160 dev_dbg(&adev
->dev
, "BUSNO: %d\n", master
->bus_num
);
2162 status
= amba_request_regions(adev
, NULL
);
2164 goto err_no_ioregion
;
2166 pl022
->phybase
= adev
->res
.start
;
2167 pl022
->virtbase
= devm_ioremap(dev
, adev
->res
.start
,
2168 resource_size(&adev
->res
));
2169 if (pl022
->virtbase
== NULL
) {
2171 goto err_no_ioremap
;
2173 dev_info(&adev
->dev
, "mapped registers from %pa to %p\n",
2174 &adev
->res
.start
, pl022
->virtbase
);
2176 pl022
->clk
= devm_clk_get(&adev
->dev
, NULL
);
2177 if (IS_ERR(pl022
->clk
)) {
2178 status
= PTR_ERR(pl022
->clk
);
2179 dev_err(&adev
->dev
, "could not retrieve SSP/SPI bus clock\n");
2183 status
= clk_prepare_enable(pl022
->clk
);
2185 dev_err(&adev
->dev
, "could not enable SSP/SPI bus clock\n");
2189 /* Initialize transfer pump */
2190 tasklet_init(&pl022
->pump_transfers
, pump_transfers
,
2191 (unsigned long)pl022
);
2194 writew((readw(SSP_CR1(pl022
->virtbase
)) & (~SSP_CR1_MASK_SSE
)),
2195 SSP_CR1(pl022
->virtbase
));
2196 load_ssp_default_config(pl022
);
2198 status
= devm_request_irq(dev
, adev
->irq
[0], pl022_interrupt_handler
,
2201 dev_err(&adev
->dev
, "probe - cannot get IRQ (%d)\n", status
);
2205 /* Get DMA channels, try autoconfiguration first */
2206 status
= pl022_dma_autoprobe(pl022
);
2208 /* If that failed, use channels from platform_info */
2210 platform_info
->enable_dma
= 1;
2211 else if (platform_info
->enable_dma
) {
2212 status
= pl022_dma_probe(pl022
);
2214 platform_info
->enable_dma
= 0;
2217 /* Register with the SPI framework */
2218 amba_set_drvdata(adev
, pl022
);
2219 status
= devm_spi_register_master(&adev
->dev
, master
);
2222 "probe - problem registering spi master\n");
2223 goto err_spi_register
;
2225 dev_dbg(dev
, "probe succeeded\n");
2227 /* let runtime pm put suspend */
2228 if (platform_info
->autosuspend_delay
> 0) {
2229 dev_info(&adev
->dev
,
2230 "will use autosuspend for runtime pm, delay %dms\n",
2231 platform_info
->autosuspend_delay
);
2232 pm_runtime_set_autosuspend_delay(dev
,
2233 platform_info
->autosuspend_delay
);
2234 pm_runtime_use_autosuspend(dev
);
2236 pm_runtime_put(dev
);
2241 if (platform_info
->enable_dma
)
2242 pl022_dma_remove(pl022
);
2244 clk_disable_unprepare(pl022
->clk
);
2248 amba_release_regions(adev
);
2251 spi_master_put(master
);
2256 pl022_remove(struct amba_device
*adev
)
2258 struct pl022
*pl022
= amba_get_drvdata(adev
);
2264 * undo pm_runtime_put() in probe. I assume that we're not
2265 * accessing the primecell here.
2267 pm_runtime_get_noresume(&adev
->dev
);
2269 load_ssp_default_config(pl022
);
2270 if (pl022
->master_info
->enable_dma
)
2271 pl022_dma_remove(pl022
);
2273 clk_disable_unprepare(pl022
->clk
);
2274 amba_release_regions(adev
);
2275 tasklet_disable(&pl022
->pump_transfers
);
2279 #ifdef CONFIG_PM_SLEEP
2280 static int pl022_suspend(struct device
*dev
)
2282 struct pl022
*pl022
= dev_get_drvdata(dev
);
2285 ret
= spi_master_suspend(pl022
->master
);
2287 dev_warn(dev
, "cannot suspend master\n");
2291 ret
= pm_runtime_force_suspend(dev
);
2293 spi_master_resume(pl022
->master
);
2297 pinctrl_pm_select_sleep_state(dev
);
2299 dev_dbg(dev
, "suspended\n");
2303 static int pl022_resume(struct device
*dev
)
2305 struct pl022
*pl022
= dev_get_drvdata(dev
);
2308 ret
= pm_runtime_force_resume(dev
);
2310 dev_err(dev
, "problem resuming\n");
2312 /* Start the queue running */
2313 ret
= spi_master_resume(pl022
->master
);
2315 dev_err(dev
, "problem starting queue (%d)\n", ret
);
2317 dev_dbg(dev
, "resumed\n");
2324 static int pl022_runtime_suspend(struct device
*dev
)
2326 struct pl022
*pl022
= dev_get_drvdata(dev
);
2328 clk_disable_unprepare(pl022
->clk
);
2329 pinctrl_pm_select_idle_state(dev
);
2334 static int pl022_runtime_resume(struct device
*dev
)
2336 struct pl022
*pl022
= dev_get_drvdata(dev
);
2338 pinctrl_pm_select_default_state(dev
);
2339 clk_prepare_enable(pl022
->clk
);
2345 static const struct dev_pm_ops pl022_dev_pm_ops
= {
2346 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend
, pl022_resume
)
2347 SET_PM_RUNTIME_PM_OPS(pl022_runtime_suspend
, pl022_runtime_resume
, NULL
)
2350 static struct vendor_data vendor_arm
= {
2354 .extended_cr
= false,
2359 static struct vendor_data vendor_st
= {
2363 .extended_cr
= true,
2368 static struct vendor_data vendor_st_pl023
= {
2372 .extended_cr
= true,
2377 static struct amba_id pl022_ids
[] = {
2380 * ARM PL022 variant, this has a 16bit wide
2381 * and 8 locations deep TX/RX FIFO
2385 .data
= &vendor_arm
,
2389 * ST Micro derivative, this has 32bit wide
2390 * and 32 locations deep TX/RX FIFO
2398 * ST-Ericsson derivative "PL023" (this is not
2399 * an official ARM number), this is a PL022 SSP block
2400 * stripped to SPI mode only, it has 32bit wide
2401 * and 32 locations deep TX/RX FIFO but no extended
2406 .data
= &vendor_st_pl023
,
2411 MODULE_DEVICE_TABLE(amba
, pl022_ids
);
2413 static struct amba_driver pl022_driver
= {
2415 .name
= "ssp-pl022",
2416 .pm
= &pl022_dev_pm_ops
,
2418 .id_table
= pl022_ids
,
2419 .probe
= pl022_probe
,
2420 .remove
= pl022_remove
,
2423 static int __init
pl022_init(void)
2425 return amba_driver_register(&pl022_driver
);
2427 subsys_initcall(pl022_init
);
2429 static void __exit
pl022_exit(void)
2431 amba_driver_unregister(&pl022_driver
);
2433 module_exit(pl022_exit
);
2435 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2436 MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2437 MODULE_LICENSE("GPL");