2 * PXA2xx SPI private DMA support.
4 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/pxa2xx_ssp.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/pxa2xx_spi.h>
29 #include "spi-pxa2xx.h"
31 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
32 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
34 bool pxa2xx_spi_dma_is_possible(size_t len
)
36 /* Try to map dma buffer and do a dma transfer if successful, but
37 * only if the length is non-zero and less than MAX_DMA_LEN.
39 * Zero-length non-descriptor DMA is illegal on PXA2xx; force use
40 * of PIO instead. Care is needed above because the transfer may
41 * have have been passed with buffers that are already dma mapped.
42 * A zero-length transfer in PIO mode will not try to write/read
45 * REVISIT large transfers are exactly where we most want to be
46 * using DMA. If this happens much, split those transfers into
47 * multiple DMA segments rather than forcing PIO.
49 return len
> 0 && len
<= MAX_DMA_LEN
;
52 int pxa2xx_spi_map_dma_buffers(struct driver_data
*drv_data
)
54 struct spi_message
*msg
= drv_data
->cur_msg
;
55 struct device
*dev
= &msg
->spi
->dev
;
57 if (!drv_data
->cur_chip
->enable_dma
)
60 if (msg
->is_dma_mapped
)
61 return drv_data
->rx_dma
&& drv_data
->tx_dma
;
63 if (!IS_DMA_ALIGNED(drv_data
->rx
) || !IS_DMA_ALIGNED(drv_data
->tx
))
66 /* Modify setup if rx buffer is null */
67 if (drv_data
->rx
== NULL
) {
68 *drv_data
->null_dma_buf
= 0;
69 drv_data
->rx
= drv_data
->null_dma_buf
;
70 drv_data
->rx_map_len
= 4;
72 drv_data
->rx_map_len
= drv_data
->len
;
75 /* Modify setup if tx buffer is null */
76 if (drv_data
->tx
== NULL
) {
77 *drv_data
->null_dma_buf
= 0;
78 drv_data
->tx
= drv_data
->null_dma_buf
;
79 drv_data
->tx_map_len
= 4;
81 drv_data
->tx_map_len
= drv_data
->len
;
83 /* Stream map the tx buffer. Always do DMA_TO_DEVICE first
84 * so we flush the cache *before* invalidating it, in case
85 * the tx and rx buffers overlap.
87 drv_data
->tx_dma
= dma_map_single(dev
, drv_data
->tx
,
88 drv_data
->tx_map_len
, DMA_TO_DEVICE
);
89 if (dma_mapping_error(dev
, drv_data
->tx_dma
))
92 /* Stream map the rx buffer */
93 drv_data
->rx_dma
= dma_map_single(dev
, drv_data
->rx
,
94 drv_data
->rx_map_len
, DMA_FROM_DEVICE
);
95 if (dma_mapping_error(dev
, drv_data
->rx_dma
)) {
96 dma_unmap_single(dev
, drv_data
->tx_dma
,
97 drv_data
->tx_map_len
, DMA_TO_DEVICE
);
104 static void pxa2xx_spi_unmap_dma_buffers(struct driver_data
*drv_data
)
108 if (!drv_data
->dma_mapped
)
111 if (!drv_data
->cur_msg
->is_dma_mapped
) {
112 dev
= &drv_data
->cur_msg
->spi
->dev
;
113 dma_unmap_single(dev
, drv_data
->rx_dma
,
114 drv_data
->rx_map_len
, DMA_FROM_DEVICE
);
115 dma_unmap_single(dev
, drv_data
->tx_dma
,
116 drv_data
->tx_map_len
, DMA_TO_DEVICE
);
119 drv_data
->dma_mapped
= 0;
122 static int wait_ssp_rx_stall(void const __iomem
*ioaddr
)
124 unsigned long limit
= loops_per_jiffy
<< 1;
126 while ((read_SSSR(ioaddr
) & SSSR_BSY
) && --limit
)
132 static int wait_dma_channel_stop(int channel
)
134 unsigned long limit
= loops_per_jiffy
<< 1;
136 while (!(DCSR(channel
) & DCSR_STOPSTATE
) && --limit
)
142 static void pxa2xx_spi_dma_error_stop(struct driver_data
*drv_data
,
145 void __iomem
*reg
= drv_data
->ioaddr
;
148 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
149 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
150 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
151 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->dma_cr1
, reg
);
152 if (!pxa25x_ssp_comp(drv_data
))
154 pxa2xx_spi_flush(drv_data
);
155 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
157 pxa2xx_spi_unmap_dma_buffers(drv_data
);
159 dev_err(&drv_data
->pdev
->dev
, "%s\n", msg
);
161 drv_data
->cur_msg
->state
= ERROR_STATE
;
162 tasklet_schedule(&drv_data
->pump_transfers
);
165 static void pxa2xx_spi_dma_transfer_complete(struct driver_data
*drv_data
)
167 void __iomem
*reg
= drv_data
->ioaddr
;
168 struct spi_message
*msg
= drv_data
->cur_msg
;
170 /* Clear and disable interrupts on SSP and DMA channels*/
171 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->dma_cr1
, reg
);
172 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
173 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
174 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
176 if (wait_dma_channel_stop(drv_data
->rx_channel
) == 0)
177 dev_err(&drv_data
->pdev
->dev
,
178 "dma_handler: dma rx channel stop failed\n");
180 if (wait_ssp_rx_stall(drv_data
->ioaddr
) == 0)
181 dev_err(&drv_data
->pdev
->dev
,
182 "dma_transfer: ssp rx stall failed\n");
184 pxa2xx_spi_unmap_dma_buffers(drv_data
);
186 /* update the buffer pointer for the amount completed in dma */
187 drv_data
->rx
+= drv_data
->len
-
188 (DCMD(drv_data
->rx_channel
) & DCMD_LENGTH
);
190 /* read trailing data from fifo, it does not matter how many
191 * bytes are in the fifo just read until buffer is full
192 * or fifo is empty, which ever occurs first */
193 drv_data
->read(drv_data
);
195 /* return count of what was actually read */
196 msg
->actual_length
+= drv_data
->len
-
197 (drv_data
->rx_end
- drv_data
->rx
);
199 /* Transfer delays and chip select release are
200 * handled in pump_transfers or giveback
203 /* Move to next transfer */
204 msg
->state
= pxa2xx_spi_next_transfer(drv_data
);
206 /* Schedule transfer tasklet */
207 tasklet_schedule(&drv_data
->pump_transfers
);
210 void pxa2xx_spi_dma_handler(int channel
, void *data
)
212 struct driver_data
*drv_data
= data
;
213 u32 irq_status
= DCSR(channel
) & DMA_INT_MASK
;
215 if (irq_status
& DCSR_BUSERR
) {
217 if (channel
== drv_data
->tx_channel
)
218 pxa2xx_spi_dma_error_stop(drv_data
,
219 "dma_handler: bad bus address on tx channel");
221 pxa2xx_spi_dma_error_stop(drv_data
,
222 "dma_handler: bad bus address on rx channel");
226 /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
227 if ((channel
== drv_data
->tx_channel
)
228 && (irq_status
& DCSR_ENDINTR
)
229 && (drv_data
->ssp_type
== PXA25x_SSP
)) {
231 /* Wait for rx to stall */
232 if (wait_ssp_rx_stall(drv_data
->ioaddr
) == 0)
233 dev_err(&drv_data
->pdev
->dev
,
234 "dma_handler: ssp rx stall failed\n");
236 /* finish this transfer, start the next */
237 pxa2xx_spi_dma_transfer_complete(drv_data
);
241 irqreturn_t
pxa2xx_spi_dma_transfer(struct driver_data
*drv_data
)
244 void __iomem
*reg
= drv_data
->ioaddr
;
246 irq_status
= read_SSSR(reg
) & drv_data
->mask_sr
;
247 if (irq_status
& SSSR_ROR
) {
248 pxa2xx_spi_dma_error_stop(drv_data
,
249 "dma_transfer: fifo overrun");
253 /* Check for false positive timeout */
254 if ((irq_status
& SSSR_TINT
)
255 && (DCSR(drv_data
->tx_channel
) & DCSR_RUN
)) {
256 write_SSSR(SSSR_TINT
, reg
);
260 if (irq_status
& SSSR_TINT
|| drv_data
->rx
== drv_data
->rx_end
) {
262 /* Clear and disable timeout interrupt, do the rest in
263 * dma_transfer_complete */
264 if (!pxa25x_ssp_comp(drv_data
))
267 /* finish this transfer, start the next */
268 pxa2xx_spi_dma_transfer_complete(drv_data
);
273 /* Opps problem detected */
277 int pxa2xx_spi_dma_prepare(struct driver_data
*drv_data
, u32 dma_burst
)
281 switch (drv_data
->n_bytes
) {
283 dma_width
= DCMD_WIDTH1
;
286 dma_width
= DCMD_WIDTH2
;
289 dma_width
= DCMD_WIDTH4
;
293 /* Setup rx DMA Channel */
294 DCSR(drv_data
->rx_channel
) = RESET_DMA_CHANNEL
;
295 DSADR(drv_data
->rx_channel
) = drv_data
->ssdr_physical
;
296 DTADR(drv_data
->rx_channel
) = drv_data
->rx_dma
;
297 if (drv_data
->rx
== drv_data
->null_dma_buf
)
298 /* No target address increment */
299 DCMD(drv_data
->rx_channel
) = DCMD_FLOWSRC
304 DCMD(drv_data
->rx_channel
) = DCMD_INCTRGADDR
310 /* Setup tx DMA Channel */
311 DCSR(drv_data
->tx_channel
) = RESET_DMA_CHANNEL
;
312 DSADR(drv_data
->tx_channel
) = drv_data
->tx_dma
;
313 DTADR(drv_data
->tx_channel
) = drv_data
->ssdr_physical
;
314 if (drv_data
->tx
== drv_data
->null_dma_buf
)
315 /* No source address increment */
316 DCMD(drv_data
->tx_channel
) = DCMD_FLOWTRG
321 DCMD(drv_data
->tx_channel
) = DCMD_INCSRCADDR
327 /* Enable dma end irqs on SSP to detect end of transfer */
328 if (drv_data
->ssp_type
== PXA25x_SSP
)
329 DCMD(drv_data
->tx_channel
) |= DCMD_ENDIRQEN
;
334 void pxa2xx_spi_dma_start(struct driver_data
*drv_data
)
336 DCSR(drv_data
->rx_channel
) |= DCSR_RUN
;
337 DCSR(drv_data
->tx_channel
) |= DCSR_RUN
;
340 int pxa2xx_spi_dma_setup(struct driver_data
*drv_data
)
342 struct device
*dev
= &drv_data
->pdev
->dev
;
343 struct ssp_device
*ssp
= drv_data
->ssp
;
345 /* Get two DMA channels (rx and tx) */
346 drv_data
->rx_channel
= pxa_request_dma("pxa2xx_spi_ssp_rx",
348 pxa2xx_spi_dma_handler
,
350 if (drv_data
->rx_channel
< 0) {
351 dev_err(dev
, "problem (%d) requesting rx channel\n",
352 drv_data
->rx_channel
);
355 drv_data
->tx_channel
= pxa_request_dma("pxa2xx_spi_ssp_tx",
357 pxa2xx_spi_dma_handler
,
359 if (drv_data
->tx_channel
< 0) {
360 dev_err(dev
, "problem (%d) requesting tx channel\n",
361 drv_data
->tx_channel
);
362 pxa_free_dma(drv_data
->rx_channel
);
366 DRCMR(ssp
->drcmr_rx
) = DRCMR_MAPVLD
| drv_data
->rx_channel
;
367 DRCMR(ssp
->drcmr_tx
) = DRCMR_MAPVLD
| drv_data
->tx_channel
;
372 void pxa2xx_spi_dma_release(struct driver_data
*drv_data
)
374 struct ssp_device
*ssp
= drv_data
->ssp
;
376 DRCMR(ssp
->drcmr_rx
) = 0;
377 DRCMR(ssp
->drcmr_tx
) = 0;
379 if (drv_data
->tx_channel
!= 0)
380 pxa_free_dma(drv_data
->tx_channel
);
381 if (drv_data
->rx_channel
!= 0)
382 pxa_free_dma(drv_data
->rx_channel
);
385 void pxa2xx_spi_dma_resume(struct driver_data
*drv_data
)
387 if (drv_data
->rx_channel
!= -1)
388 DRCMR(drv_data
->ssp
->drcmr_rx
) =
389 DRCMR_MAPVLD
| drv_data
->rx_channel
;
390 if (drv_data
->tx_channel
!= -1)
391 DRCMR(drv_data
->ssp
->drcmr_tx
) =
392 DRCMR_MAPVLD
| drv_data
->tx_channel
;
395 int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data
*chip
,
396 struct spi_device
*spi
,
397 u8 bits_per_word
, u32
*burst_code
,
400 struct pxa2xx_spi_chip
*chip_info
=
401 (struct pxa2xx_spi_chip
*)spi
->controller_data
;
408 /* Set the threshold (in registers) to equal the same amount of data
409 * as represented by burst size (in bytes). The computation below
410 * is (burst_size rounded up to nearest 8 byte, word or long word)
411 * divided by (bytes/register); the tx threshold is the inverse of
412 * the rx, so that there will always be enough data in the rx fifo
413 * to satisfy a burst, and there will always be enough space in the
414 * tx fifo to accept a burst (a tx burst will overwrite the fifo if
415 * there is not enough space), there must always remain enough empty
416 * space in the rx fifo for any data loaded to the tx fifo.
417 * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
418 * will be 8, or half the fifo;
419 * The threshold can only be set to 2, 4 or 8, but not 16, because
420 * to burst 16 to the tx fifo, the fifo would have to be empty;
421 * however, the minimum fifo trigger level is 1, and the tx will
422 * request service when the fifo is at this level, with only 15 spaces.
425 /* find bytes/word */
426 if (bits_per_word
<= 8)
428 else if (bits_per_word
<= 16)
433 /* use struct pxa2xx_spi_chip->dma_burst_size if available */
435 req_burst_size
= chip_info
->dma_burst_size
;
437 switch (chip
->dma_burst_size
) {
439 /* if the default burst size is not set,
441 chip
->dma_burst_size
= DCMD_BURST8
;
453 if (req_burst_size
<= 8) {
454 *burst_code
= DCMD_BURST8
;
456 } else if (req_burst_size
<= 16) {
457 if (bytes_per_word
== 1) {
458 /* don't burst more than 1/2 the fifo */
459 *burst_code
= DCMD_BURST8
;
463 *burst_code
= DCMD_BURST16
;
467 if (bytes_per_word
== 1) {
468 /* don't burst more than 1/2 the fifo */
469 *burst_code
= DCMD_BURST8
;
472 } else if (bytes_per_word
== 2) {
473 /* don't burst more than 1/2 the fifo */
474 *burst_code
= DCMD_BURST16
;
478 *burst_code
= DCMD_BURST32
;
483 thresh_words
= burst_bytes
/ bytes_per_word
;
485 /* thresh_words will be between 2 and 8 */
486 *threshold
= (SSCR1_RxTresh(thresh_words
) & SSCR1_RFT
)
487 | (SSCR1_TxTresh(16-thresh_words
) & SSCR1_TFT
);
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