2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/ioport.h>
24 #include <linux/errno.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/spi/pxa2xx_spi.h>
29 #include <linux/spi/spi.h>
30 #include <linux/workqueue.h>
31 #include <linux/delay.h>
32 #include <linux/gpio.h>
33 #include <linux/slab.h>
34 #include <linux/clk.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/acpi.h>
40 #include <asm/delay.h>
42 #include "spi-pxa2xx.h"
44 MODULE_AUTHOR("Stephen Street");
45 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
46 MODULE_LICENSE("GPL");
47 MODULE_ALIAS("platform:pxa2xx-spi");
51 #define TIMOUT_DFLT 1000
54 * for testing SSCR1 changes that require SSP restart, basically
55 * everything except the service and interrupt enables, the pxa270 developer
56 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
57 * list, but the PXA255 dev man says all bits without really meaning the
58 * service and interrupt enables
60 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
61 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
62 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
63 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
64 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
67 #define LPSS_RX_THRESH_DFLT 64
68 #define LPSS_TX_LOTHRESH_DFLT 160
69 #define LPSS_TX_HITHRESH_DFLT 224
71 /* Offset from drv_data->lpss_base */
72 #define GENERAL_REG 0x08
73 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
75 #define SPI_CS_CONTROL 0x18
76 #define SPI_CS_CONTROL_SW_MODE BIT(0)
77 #define SPI_CS_CONTROL_CS_HIGH BIT(1)
79 static bool is_lpss_ssp(const struct driver_data
*drv_data
)
81 return drv_data
->ssp_type
== LPSS_SSP
;
85 * Read and write LPSS SSP private registers. Caller must first check that
86 * is_lpss_ssp() returns true before these can be called.
88 static u32
__lpss_ssp_read_priv(struct driver_data
*drv_data
, unsigned offset
)
90 WARN_ON(!drv_data
->lpss_base
);
91 return readl(drv_data
->lpss_base
+ offset
);
94 static void __lpss_ssp_write_priv(struct driver_data
*drv_data
,
95 unsigned offset
, u32 value
)
97 WARN_ON(!drv_data
->lpss_base
);
98 writel(value
, drv_data
->lpss_base
+ offset
);
102 * lpss_ssp_setup - perform LPSS SSP specific setup
103 * @drv_data: pointer to the driver private data
105 * Perform LPSS SSP specific setup. This function must be called first if
106 * one is going to use LPSS SSP private registers.
108 static void lpss_ssp_setup(struct driver_data
*drv_data
)
110 unsigned offset
= 0x400;
113 if (!is_lpss_ssp(drv_data
))
117 * Perform auto-detection of the LPSS SSP private registers. They
118 * can be either at 1k or 2k offset from the base address.
120 orig
= readl(drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
122 value
= orig
| SPI_CS_CONTROL_SW_MODE
;
123 writel(value
, drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
124 value
= readl(drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
125 if (value
!= (orig
| SPI_CS_CONTROL_SW_MODE
)) {
130 value
&= ~SPI_CS_CONTROL_SW_MODE
;
131 writel(value
, drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
132 value
= readl(drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
139 /* Now set the LPSS base */
140 drv_data
->lpss_base
= drv_data
->ioaddr
+ offset
;
142 /* Enable software chip select control */
143 value
= SPI_CS_CONTROL_SW_MODE
| SPI_CS_CONTROL_CS_HIGH
;
144 __lpss_ssp_write_priv(drv_data
, SPI_CS_CONTROL
, value
);
146 /* Enable multiblock DMA transfers */
147 if (drv_data
->master_info
->enable_dma
) {
148 __lpss_ssp_write_priv(drv_data
, SSP_REG
, 1);
150 value
= __lpss_ssp_read_priv(drv_data
, GENERAL_REG
);
151 value
|= GENERAL_REG_RXTO_HOLDOFF_DISABLE
;
152 __lpss_ssp_write_priv(drv_data
, GENERAL_REG
, value
);
156 static void lpss_ssp_cs_control(struct driver_data
*drv_data
, bool enable
)
160 if (!is_lpss_ssp(drv_data
))
163 value
= __lpss_ssp_read_priv(drv_data
, SPI_CS_CONTROL
);
165 value
&= ~SPI_CS_CONTROL_CS_HIGH
;
167 value
|= SPI_CS_CONTROL_CS_HIGH
;
168 __lpss_ssp_write_priv(drv_data
, SPI_CS_CONTROL
, value
);
171 static void cs_assert(struct driver_data
*drv_data
)
173 struct chip_data
*chip
= drv_data
->cur_chip
;
175 if (drv_data
->ssp_type
== CE4100_SSP
) {
176 write_SSSR(drv_data
->cur_chip
->frm
, drv_data
->ioaddr
);
180 if (chip
->cs_control
) {
181 chip
->cs_control(PXA2XX_CS_ASSERT
);
185 if (gpio_is_valid(chip
->gpio_cs
)) {
186 gpio_set_value(chip
->gpio_cs
, chip
->gpio_cs_inverted
);
190 lpss_ssp_cs_control(drv_data
, true);
193 static void cs_deassert(struct driver_data
*drv_data
)
195 struct chip_data
*chip
= drv_data
->cur_chip
;
197 if (drv_data
->ssp_type
== CE4100_SSP
)
200 if (chip
->cs_control
) {
201 chip
->cs_control(PXA2XX_CS_DEASSERT
);
205 if (gpio_is_valid(chip
->gpio_cs
)) {
206 gpio_set_value(chip
->gpio_cs
, !chip
->gpio_cs_inverted
);
210 lpss_ssp_cs_control(drv_data
, false);
213 int pxa2xx_spi_flush(struct driver_data
*drv_data
)
215 unsigned long limit
= loops_per_jiffy
<< 1;
217 void __iomem
*reg
= drv_data
->ioaddr
;
220 while (read_SSSR(reg
) & SSSR_RNE
) {
223 } while ((read_SSSR(reg
) & SSSR_BSY
) && --limit
);
224 write_SSSR_CS(drv_data
, SSSR_ROR
);
229 static int null_writer(struct driver_data
*drv_data
)
231 void __iomem
*reg
= drv_data
->ioaddr
;
232 u8 n_bytes
= drv_data
->n_bytes
;
234 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
235 || (drv_data
->tx
== drv_data
->tx_end
))
239 drv_data
->tx
+= n_bytes
;
244 static int null_reader(struct driver_data
*drv_data
)
246 void __iomem
*reg
= drv_data
->ioaddr
;
247 u8 n_bytes
= drv_data
->n_bytes
;
249 while ((read_SSSR(reg
) & SSSR_RNE
)
250 && (drv_data
->rx
< drv_data
->rx_end
)) {
252 drv_data
->rx
+= n_bytes
;
255 return drv_data
->rx
== drv_data
->rx_end
;
258 static int u8_writer(struct driver_data
*drv_data
)
260 void __iomem
*reg
= drv_data
->ioaddr
;
262 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
263 || (drv_data
->tx
== drv_data
->tx_end
))
266 write_SSDR(*(u8
*)(drv_data
->tx
), reg
);
272 static int u8_reader(struct driver_data
*drv_data
)
274 void __iomem
*reg
= drv_data
->ioaddr
;
276 while ((read_SSSR(reg
) & SSSR_RNE
)
277 && (drv_data
->rx
< drv_data
->rx_end
)) {
278 *(u8
*)(drv_data
->rx
) = read_SSDR(reg
);
282 return drv_data
->rx
== drv_data
->rx_end
;
285 static int u16_writer(struct driver_data
*drv_data
)
287 void __iomem
*reg
= drv_data
->ioaddr
;
289 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
290 || (drv_data
->tx
== drv_data
->tx_end
))
293 write_SSDR(*(u16
*)(drv_data
->tx
), reg
);
299 static int u16_reader(struct driver_data
*drv_data
)
301 void __iomem
*reg
= drv_data
->ioaddr
;
303 while ((read_SSSR(reg
) & SSSR_RNE
)
304 && (drv_data
->rx
< drv_data
->rx_end
)) {
305 *(u16
*)(drv_data
->rx
) = read_SSDR(reg
);
309 return drv_data
->rx
== drv_data
->rx_end
;
312 static int u32_writer(struct driver_data
*drv_data
)
314 void __iomem
*reg
= drv_data
->ioaddr
;
316 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
317 || (drv_data
->tx
== drv_data
->tx_end
))
320 write_SSDR(*(u32
*)(drv_data
->tx
), reg
);
326 static int u32_reader(struct driver_data
*drv_data
)
328 void __iomem
*reg
= drv_data
->ioaddr
;
330 while ((read_SSSR(reg
) & SSSR_RNE
)
331 && (drv_data
->rx
< drv_data
->rx_end
)) {
332 *(u32
*)(drv_data
->rx
) = read_SSDR(reg
);
336 return drv_data
->rx
== drv_data
->rx_end
;
339 void *pxa2xx_spi_next_transfer(struct driver_data
*drv_data
)
341 struct spi_message
*msg
= drv_data
->cur_msg
;
342 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
344 /* Move to next transfer */
345 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
346 drv_data
->cur_transfer
=
347 list_entry(trans
->transfer_list
.next
,
350 return RUNNING_STATE
;
355 /* caller already set message->status; dma and pio irqs are blocked */
356 static void giveback(struct driver_data
*drv_data
)
358 struct spi_transfer
* last_transfer
;
359 struct spi_message
*msg
;
361 msg
= drv_data
->cur_msg
;
362 drv_data
->cur_msg
= NULL
;
363 drv_data
->cur_transfer
= NULL
;
365 last_transfer
= list_last_entry(&msg
->transfers
, struct spi_transfer
,
368 /* Delay if requested before any change in chip select */
369 if (last_transfer
->delay_usecs
)
370 udelay(last_transfer
->delay_usecs
);
372 /* Drop chip select UNLESS cs_change is true or we are returning
373 * a message with an error, or next message is for another chip
375 if (!last_transfer
->cs_change
)
376 cs_deassert(drv_data
);
378 struct spi_message
*next_msg
;
380 /* Holding of cs was hinted, but we need to make sure
381 * the next message is for the same chip. Don't waste
382 * time with the following tests unless this was hinted.
384 * We cannot postpone this until pump_messages, because
385 * after calling msg->complete (below) the driver that
386 * sent the current message could be unloaded, which
387 * could invalidate the cs_control() callback...
390 /* get a pointer to the next message, if any */
391 next_msg
= spi_get_next_queued_message(drv_data
->master
);
393 /* see if the next and current messages point
396 if (next_msg
&& next_msg
->spi
!= msg
->spi
)
398 if (!next_msg
|| msg
->state
== ERROR_STATE
)
399 cs_deassert(drv_data
);
402 spi_finalize_current_message(drv_data
->master
);
403 drv_data
->cur_chip
= NULL
;
406 static void reset_sccr1(struct driver_data
*drv_data
)
408 void __iomem
*reg
= drv_data
->ioaddr
;
409 struct chip_data
*chip
= drv_data
->cur_chip
;
412 sccr1_reg
= read_SSCR1(reg
) & ~drv_data
->int_cr1
;
413 sccr1_reg
&= ~SSCR1_RFT
;
414 sccr1_reg
|= chip
->threshold
;
415 write_SSCR1(sccr1_reg
, reg
);
418 static void int_error_stop(struct driver_data
*drv_data
, const char* msg
)
420 void __iomem
*reg
= drv_data
->ioaddr
;
422 /* Stop and reset SSP */
423 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
424 reset_sccr1(drv_data
);
425 if (!pxa25x_ssp_comp(drv_data
))
427 pxa2xx_spi_flush(drv_data
);
428 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
430 dev_err(&drv_data
->pdev
->dev
, "%s\n", msg
);
432 drv_data
->cur_msg
->state
= ERROR_STATE
;
433 tasklet_schedule(&drv_data
->pump_transfers
);
436 static void int_transfer_complete(struct driver_data
*drv_data
)
438 void __iomem
*reg
= drv_data
->ioaddr
;
441 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
442 reset_sccr1(drv_data
);
443 if (!pxa25x_ssp_comp(drv_data
))
446 /* Update total byte transferred return count actual bytes read */
447 drv_data
->cur_msg
->actual_length
+= drv_data
->len
-
448 (drv_data
->rx_end
- drv_data
->rx
);
450 /* Transfer delays and chip select release are
451 * handled in pump_transfers or giveback
454 /* Move to next transfer */
455 drv_data
->cur_msg
->state
= pxa2xx_spi_next_transfer(drv_data
);
457 /* Schedule transfer tasklet */
458 tasklet_schedule(&drv_data
->pump_transfers
);
461 static irqreturn_t
interrupt_transfer(struct driver_data
*drv_data
)
463 void __iomem
*reg
= drv_data
->ioaddr
;
465 u32 irq_mask
= (read_SSCR1(reg
) & SSCR1_TIE
) ?
466 drv_data
->mask_sr
: drv_data
->mask_sr
& ~SSSR_TFS
;
468 u32 irq_status
= read_SSSR(reg
) & irq_mask
;
470 if (irq_status
& SSSR_ROR
) {
471 int_error_stop(drv_data
, "interrupt_transfer: fifo overrun");
475 if (irq_status
& SSSR_TINT
) {
476 write_SSSR(SSSR_TINT
, reg
);
477 if (drv_data
->read(drv_data
)) {
478 int_transfer_complete(drv_data
);
483 /* Drain rx fifo, Fill tx fifo and prevent overruns */
485 if (drv_data
->read(drv_data
)) {
486 int_transfer_complete(drv_data
);
489 } while (drv_data
->write(drv_data
));
491 if (drv_data
->read(drv_data
)) {
492 int_transfer_complete(drv_data
);
496 if (drv_data
->tx
== drv_data
->tx_end
) {
500 sccr1_reg
= read_SSCR1(reg
);
501 sccr1_reg
&= ~SSCR1_TIE
;
504 * PXA25x_SSP has no timeout, set up rx threshould for the
505 * remaining RX bytes.
507 if (pxa25x_ssp_comp(drv_data
)) {
509 sccr1_reg
&= ~SSCR1_RFT
;
511 bytes_left
= drv_data
->rx_end
- drv_data
->rx
;
512 switch (drv_data
->n_bytes
) {
519 if (bytes_left
> RX_THRESH_DFLT
)
520 bytes_left
= RX_THRESH_DFLT
;
522 sccr1_reg
|= SSCR1_RxTresh(bytes_left
);
524 write_SSCR1(sccr1_reg
, reg
);
527 /* We did something */
531 static irqreturn_t
ssp_int(int irq
, void *dev_id
)
533 struct driver_data
*drv_data
= dev_id
;
534 void __iomem
*reg
= drv_data
->ioaddr
;
536 u32 mask
= drv_data
->mask_sr
;
540 * The IRQ might be shared with other peripherals so we must first
541 * check that are we RPM suspended or not. If we are we assume that
542 * the IRQ was not for us (we shouldn't be RPM suspended when the
543 * interrupt is enabled).
545 if (pm_runtime_suspended(&drv_data
->pdev
->dev
))
549 * If the device is not yet in RPM suspended state and we get an
550 * interrupt that is meant for another device, check if status bits
551 * are all set to one. That means that the device is already
554 status
= read_SSSR(reg
);
558 sccr1_reg
= read_SSCR1(reg
);
560 /* Ignore possible writes if we don't need to write */
561 if (!(sccr1_reg
& SSCR1_TIE
))
564 if (!(status
& mask
))
567 if (!drv_data
->cur_msg
) {
569 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
570 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
571 if (!pxa25x_ssp_comp(drv_data
))
573 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
575 dev_err(&drv_data
->pdev
->dev
,
576 "bad message state in interrupt handler\n");
582 return drv_data
->transfer_handler(drv_data
);
585 static unsigned int ssp_get_clk_div(struct driver_data
*drv_data
, int rate
)
587 unsigned long ssp_clk
= drv_data
->max_clk_rate
;
588 const struct ssp_device
*ssp
= drv_data
->ssp
;
590 rate
= min_t(int, ssp_clk
, rate
);
592 if (ssp
->type
== PXA25x_SSP
|| ssp
->type
== CE4100_SSP
)
593 return ((ssp_clk
/ (2 * rate
) - 1) & 0xff) << 8;
595 return ((ssp_clk
/ rate
- 1) & 0xfff) << 8;
598 static void pump_transfers(unsigned long data
)
600 struct driver_data
*drv_data
= (struct driver_data
*)data
;
601 struct spi_message
*message
= NULL
;
602 struct spi_transfer
*transfer
= NULL
;
603 struct spi_transfer
*previous
= NULL
;
604 struct chip_data
*chip
= NULL
;
605 void __iomem
*reg
= drv_data
->ioaddr
;
611 u32 dma_thresh
= drv_data
->cur_chip
->dma_threshold
;
612 u32 dma_burst
= drv_data
->cur_chip
->dma_burst_size
;
614 /* Get current state information */
615 message
= drv_data
->cur_msg
;
616 transfer
= drv_data
->cur_transfer
;
617 chip
= drv_data
->cur_chip
;
619 /* Handle for abort */
620 if (message
->state
== ERROR_STATE
) {
621 message
->status
= -EIO
;
626 /* Handle end of message */
627 if (message
->state
== DONE_STATE
) {
633 /* Delay if requested at end of transfer before CS change */
634 if (message
->state
== RUNNING_STATE
) {
635 previous
= list_entry(transfer
->transfer_list
.prev
,
638 if (previous
->delay_usecs
)
639 udelay(previous
->delay_usecs
);
641 /* Drop chip select only if cs_change is requested */
642 if (previous
->cs_change
)
643 cs_deassert(drv_data
);
646 /* Check if we can DMA this transfer */
647 if (!pxa2xx_spi_dma_is_possible(transfer
->len
) && chip
->enable_dma
) {
649 /* reject already-mapped transfers; PIO won't always work */
650 if (message
->is_dma_mapped
651 || transfer
->rx_dma
|| transfer
->tx_dma
) {
652 dev_err(&drv_data
->pdev
->dev
,
653 "pump_transfers: mapped transfer length of "
654 "%u is greater than %d\n",
655 transfer
->len
, MAX_DMA_LEN
);
656 message
->status
= -EINVAL
;
661 /* warn ... we force this to PIO mode */
662 dev_warn_ratelimited(&message
->spi
->dev
,
663 "pump_transfers: DMA disabled for transfer length %ld "
665 (long)drv_data
->len
, MAX_DMA_LEN
);
668 /* Setup the transfer state based on the type of transfer */
669 if (pxa2xx_spi_flush(drv_data
) == 0) {
670 dev_err(&drv_data
->pdev
->dev
, "pump_transfers: flush failed\n");
671 message
->status
= -EIO
;
675 drv_data
->n_bytes
= chip
->n_bytes
;
676 drv_data
->tx
= (void *)transfer
->tx_buf
;
677 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
678 drv_data
->rx
= transfer
->rx_buf
;
679 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
680 drv_data
->rx_dma
= transfer
->rx_dma
;
681 drv_data
->tx_dma
= transfer
->tx_dma
;
682 drv_data
->len
= transfer
->len
;
683 drv_data
->write
= drv_data
->tx
? chip
->write
: null_writer
;
684 drv_data
->read
= drv_data
->rx
? chip
->read
: null_reader
;
686 /* Change speed and bit per word on a per transfer */
688 if (transfer
->speed_hz
|| transfer
->bits_per_word
) {
690 bits
= chip
->bits_per_word
;
691 speed
= chip
->speed_hz
;
693 if (transfer
->speed_hz
)
694 speed
= transfer
->speed_hz
;
696 if (transfer
->bits_per_word
)
697 bits
= transfer
->bits_per_word
;
699 clk_div
= ssp_get_clk_div(drv_data
, speed
);
702 drv_data
->n_bytes
= 1;
703 drv_data
->read
= drv_data
->read
!= null_reader
?
704 u8_reader
: null_reader
;
705 drv_data
->write
= drv_data
->write
!= null_writer
?
706 u8_writer
: null_writer
;
707 } else if (bits
<= 16) {
708 drv_data
->n_bytes
= 2;
709 drv_data
->read
= drv_data
->read
!= null_reader
?
710 u16_reader
: null_reader
;
711 drv_data
->write
= drv_data
->write
!= null_writer
?
712 u16_writer
: null_writer
;
713 } else if (bits
<= 32) {
714 drv_data
->n_bytes
= 4;
715 drv_data
->read
= drv_data
->read
!= null_reader
?
716 u32_reader
: null_reader
;
717 drv_data
->write
= drv_data
->write
!= null_writer
?
718 u32_writer
: null_writer
;
720 /* if bits/word is changed in dma mode, then must check the
721 * thresholds and burst also */
722 if (chip
->enable_dma
) {
723 if (pxa2xx_spi_set_dma_burst_and_threshold(chip
,
727 dev_warn_ratelimited(&message
->spi
->dev
,
728 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
733 | SSCR0_DataSize(bits
> 16 ? bits
- 16 : bits
)
735 | (bits
> 16 ? SSCR0_EDSS
: 0);
738 message
->state
= RUNNING_STATE
;
740 drv_data
->dma_mapped
= 0;
741 if (pxa2xx_spi_dma_is_possible(drv_data
->len
))
742 drv_data
->dma_mapped
= pxa2xx_spi_map_dma_buffers(drv_data
);
743 if (drv_data
->dma_mapped
) {
745 /* Ensure we have the correct interrupt handler */
746 drv_data
->transfer_handler
= pxa2xx_spi_dma_transfer
;
748 pxa2xx_spi_dma_prepare(drv_data
, dma_burst
);
750 /* Clear status and start DMA engine */
751 cr1
= chip
->cr1
| dma_thresh
| drv_data
->dma_cr1
;
752 write_SSSR(drv_data
->clear_sr
, reg
);
754 pxa2xx_spi_dma_start(drv_data
);
756 /* Ensure we have the correct interrupt handler */
757 drv_data
->transfer_handler
= interrupt_transfer
;
760 cr1
= chip
->cr1
| chip
->threshold
| drv_data
->int_cr1
;
761 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
764 if (is_lpss_ssp(drv_data
)) {
765 if ((read_SSIRF(reg
) & 0xff) != chip
->lpss_rx_threshold
)
766 write_SSIRF(chip
->lpss_rx_threshold
, reg
);
767 if ((read_SSITF(reg
) & 0xffff) != chip
->lpss_tx_threshold
)
768 write_SSITF(chip
->lpss_tx_threshold
, reg
);
771 /* see if we need to reload the config registers */
772 if ((read_SSCR0(reg
) != cr0
)
773 || (read_SSCR1(reg
) & SSCR1_CHANGE_MASK
) !=
774 (cr1
& SSCR1_CHANGE_MASK
)) {
776 /* stop the SSP, and update the other bits */
777 write_SSCR0(cr0
& ~SSCR0_SSE
, reg
);
778 if (!pxa25x_ssp_comp(drv_data
))
779 write_SSTO(chip
->timeout
, reg
);
780 /* first set CR1 without interrupt and service enables */
781 write_SSCR1(cr1
& SSCR1_CHANGE_MASK
, reg
);
782 /* restart the SSP */
783 write_SSCR0(cr0
, reg
);
786 if (!pxa25x_ssp_comp(drv_data
))
787 write_SSTO(chip
->timeout
, reg
);
792 /* after chip select, release the data by enabling service
793 * requests and interrupts, without changing any mode bits */
794 write_SSCR1(cr1
, reg
);
797 static int pxa2xx_spi_transfer_one_message(struct spi_master
*master
,
798 struct spi_message
*msg
)
800 struct driver_data
*drv_data
= spi_master_get_devdata(master
);
802 drv_data
->cur_msg
= msg
;
803 /* Initial message state*/
804 drv_data
->cur_msg
->state
= START_STATE
;
805 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
809 /* prepare to setup the SSP, in pump_transfers, using the per
810 * chip configuration */
811 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
813 /* Mark as busy and launch transfers */
814 tasklet_schedule(&drv_data
->pump_transfers
);
818 static int pxa2xx_spi_unprepare_transfer(struct spi_master
*master
)
820 struct driver_data
*drv_data
= spi_master_get_devdata(master
);
822 /* Disable the SSP now */
823 write_SSCR0(read_SSCR0(drv_data
->ioaddr
) & ~SSCR0_SSE
,
829 static int setup_cs(struct spi_device
*spi
, struct chip_data
*chip
,
830 struct pxa2xx_spi_chip
*chip_info
)
834 if (chip
== NULL
|| chip_info
== NULL
)
837 /* NOTE: setup() can be called multiple times, possibly with
838 * different chip_info, release previously requested GPIO
840 if (gpio_is_valid(chip
->gpio_cs
))
841 gpio_free(chip
->gpio_cs
);
843 /* If (*cs_control) is provided, ignore GPIO chip select */
844 if (chip_info
->cs_control
) {
845 chip
->cs_control
= chip_info
->cs_control
;
849 if (gpio_is_valid(chip_info
->gpio_cs
)) {
850 err
= gpio_request(chip_info
->gpio_cs
, "SPI_CS");
852 dev_err(&spi
->dev
, "failed to request chip select GPIO%d\n",
857 chip
->gpio_cs
= chip_info
->gpio_cs
;
858 chip
->gpio_cs_inverted
= spi
->mode
& SPI_CS_HIGH
;
860 err
= gpio_direction_output(chip
->gpio_cs
,
861 !chip
->gpio_cs_inverted
);
867 static int setup(struct spi_device
*spi
)
869 struct pxa2xx_spi_chip
*chip_info
= NULL
;
870 struct chip_data
*chip
;
871 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
872 unsigned int clk_div
;
873 uint tx_thres
, tx_hi_thres
, rx_thres
;
875 if (is_lpss_ssp(drv_data
)) {
876 tx_thres
= LPSS_TX_LOTHRESH_DFLT
;
877 tx_hi_thres
= LPSS_TX_HITHRESH_DFLT
;
878 rx_thres
= LPSS_RX_THRESH_DFLT
;
880 tx_thres
= TX_THRESH_DFLT
;
882 rx_thres
= RX_THRESH_DFLT
;
885 /* Only alloc on first setup */
886 chip
= spi_get_ctldata(spi
);
888 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
891 "failed setup: can't allocate chip data\n");
895 if (drv_data
->ssp_type
== CE4100_SSP
) {
896 if (spi
->chip_select
> 4) {
898 "failed setup: cs number must not be > 4.\n");
903 chip
->frm
= spi
->chip_select
;
906 chip
->enable_dma
= 0;
907 chip
->timeout
= TIMOUT_DFLT
;
910 /* protocol drivers may change the chip settings, so...
911 * if chip_info exists, use it */
912 chip_info
= spi
->controller_data
;
914 /* chip_info isn't always needed */
917 if (chip_info
->timeout
)
918 chip
->timeout
= chip_info
->timeout
;
919 if (chip_info
->tx_threshold
)
920 tx_thres
= chip_info
->tx_threshold
;
921 if (chip_info
->tx_hi_threshold
)
922 tx_hi_thres
= chip_info
->tx_hi_threshold
;
923 if (chip_info
->rx_threshold
)
924 rx_thres
= chip_info
->rx_threshold
;
925 chip
->enable_dma
= drv_data
->master_info
->enable_dma
;
926 chip
->dma_threshold
= 0;
927 if (chip_info
->enable_loopback
)
928 chip
->cr1
= SSCR1_LBM
;
929 } else if (ACPI_HANDLE(&spi
->dev
)) {
931 * Slave devices enumerated from ACPI namespace don't
932 * usually have chip_info but we still might want to use
935 chip
->enable_dma
= drv_data
->master_info
->enable_dma
;
938 chip
->threshold
= (SSCR1_RxTresh(rx_thres
) & SSCR1_RFT
) |
939 (SSCR1_TxTresh(tx_thres
) & SSCR1_TFT
);
941 chip
->lpss_rx_threshold
= SSIRF_RxThresh(rx_thres
);
942 chip
->lpss_tx_threshold
= SSITF_TxLoThresh(tx_thres
)
943 | SSITF_TxHiThresh(tx_hi_thres
);
945 /* set dma burst and threshold outside of chip_info path so that if
946 * chip_info goes away after setting chip->enable_dma, the
947 * burst and threshold can still respond to changes in bits_per_word */
948 if (chip
->enable_dma
) {
949 /* set up legal burst and threshold for dma */
950 if (pxa2xx_spi_set_dma_burst_and_threshold(chip
, spi
,
952 &chip
->dma_burst_size
,
953 &chip
->dma_threshold
)) {
955 "in setup: DMA burst size reduced to match bits_per_word\n");
959 clk_div
= ssp_get_clk_div(drv_data
, spi
->max_speed_hz
);
960 chip
->speed_hz
= spi
->max_speed_hz
;
964 | SSCR0_DataSize(spi
->bits_per_word
> 16 ?
965 spi
->bits_per_word
- 16 : spi
->bits_per_word
)
967 | (spi
->bits_per_word
> 16 ? SSCR0_EDSS
: 0);
968 chip
->cr1
&= ~(SSCR1_SPO
| SSCR1_SPH
);
969 chip
->cr1
|= (((spi
->mode
& SPI_CPHA
) != 0) ? SSCR1_SPH
: 0)
970 | (((spi
->mode
& SPI_CPOL
) != 0) ? SSCR1_SPO
: 0);
972 if (spi
->mode
& SPI_LOOP
)
973 chip
->cr1
|= SSCR1_LBM
;
975 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
976 if (!pxa25x_ssp_comp(drv_data
))
977 dev_dbg(&spi
->dev
, "%ld Hz actual, %s\n",
978 drv_data
->max_clk_rate
979 / (1 + ((chip
->cr0
& SSCR0_SCR(0xfff)) >> 8)),
980 chip
->enable_dma
? "DMA" : "PIO");
982 dev_dbg(&spi
->dev
, "%ld Hz actual, %s\n",
983 drv_data
->max_clk_rate
/ 2
984 / (1 + ((chip
->cr0
& SSCR0_SCR(0x0ff)) >> 8)),
985 chip
->enable_dma
? "DMA" : "PIO");
987 if (spi
->bits_per_word
<= 8) {
989 chip
->read
= u8_reader
;
990 chip
->write
= u8_writer
;
991 } else if (spi
->bits_per_word
<= 16) {
993 chip
->read
= u16_reader
;
994 chip
->write
= u16_writer
;
995 } else if (spi
->bits_per_word
<= 32) {
996 chip
->cr0
|= SSCR0_EDSS
;
998 chip
->read
= u32_reader
;
999 chip
->write
= u32_writer
;
1001 chip
->bits_per_word
= spi
->bits_per_word
;
1003 spi_set_ctldata(spi
, chip
);
1005 if (drv_data
->ssp_type
== CE4100_SSP
)
1008 return setup_cs(spi
, chip
, chip_info
);
1011 static void cleanup(struct spi_device
*spi
)
1013 struct chip_data
*chip
= spi_get_ctldata(spi
);
1014 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
1019 if (drv_data
->ssp_type
!= CE4100_SSP
&& gpio_is_valid(chip
->gpio_cs
))
1020 gpio_free(chip
->gpio_cs
);
1026 static struct pxa2xx_spi_master
*
1027 pxa2xx_spi_acpi_get_pdata(struct platform_device
*pdev
)
1029 struct pxa2xx_spi_master
*pdata
;
1030 struct acpi_device
*adev
;
1031 struct ssp_device
*ssp
;
1032 struct resource
*res
;
1035 if (!ACPI_HANDLE(&pdev
->dev
) ||
1036 acpi_bus_get_device(ACPI_HANDLE(&pdev
->dev
), &adev
))
1039 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1042 "failed to allocate memory for platform data\n");
1046 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1052 ssp
->phys_base
= res
->start
;
1053 ssp
->mmio_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1054 if (IS_ERR(ssp
->mmio_base
))
1057 ssp
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1058 ssp
->irq
= platform_get_irq(pdev
, 0);
1059 ssp
->type
= LPSS_SSP
;
1063 if (adev
->pnp
.unique_id
&& !kstrtoint(adev
->pnp
.unique_id
, 0, &devid
))
1064 ssp
->port_id
= devid
;
1066 pdata
->num_chipselect
= 1;
1067 pdata
->enable_dma
= true;
1068 pdata
->tx_chan_id
= -1;
1069 pdata
->rx_chan_id
= -1;
1074 static struct acpi_device_id pxa2xx_spi_acpi_match
[] = {
1082 MODULE_DEVICE_TABLE(acpi
, pxa2xx_spi_acpi_match
);
1084 static inline struct pxa2xx_spi_master
*
1085 pxa2xx_spi_acpi_get_pdata(struct platform_device
*pdev
)
1091 static int pxa2xx_spi_probe(struct platform_device
*pdev
)
1093 struct device
*dev
= &pdev
->dev
;
1094 struct pxa2xx_spi_master
*platform_info
;
1095 struct spi_master
*master
;
1096 struct driver_data
*drv_data
;
1097 struct ssp_device
*ssp
;
1100 platform_info
= dev_get_platdata(dev
);
1101 if (!platform_info
) {
1102 platform_info
= pxa2xx_spi_acpi_get_pdata(pdev
);
1103 if (!platform_info
) {
1104 dev_err(&pdev
->dev
, "missing platform data\n");
1109 ssp
= pxa_ssp_request(pdev
->id
, pdev
->name
);
1111 ssp
= &platform_info
->ssp
;
1113 if (!ssp
->mmio_base
) {
1114 dev_err(&pdev
->dev
, "failed to get ssp\n");
1118 /* Allocate master with space for drv_data and null dma buffer */
1119 master
= spi_alloc_master(dev
, sizeof(struct driver_data
) + 16);
1121 dev_err(&pdev
->dev
, "cannot alloc spi_master\n");
1125 drv_data
= spi_master_get_devdata(master
);
1126 drv_data
->master
= master
;
1127 drv_data
->master_info
= platform_info
;
1128 drv_data
->pdev
= pdev
;
1129 drv_data
->ssp
= ssp
;
1131 master
->dev
.parent
= &pdev
->dev
;
1132 master
->dev
.of_node
= pdev
->dev
.of_node
;
1133 /* the spi->mode bits understood by this driver: */
1134 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
| SPI_LOOP
;
1136 master
->bus_num
= ssp
->port_id
;
1137 master
->num_chipselect
= platform_info
->num_chipselect
;
1138 master
->dma_alignment
= DMA_ALIGNMENT
;
1139 master
->cleanup
= cleanup
;
1140 master
->setup
= setup
;
1141 master
->transfer_one_message
= pxa2xx_spi_transfer_one_message
;
1142 master
->unprepare_transfer_hardware
= pxa2xx_spi_unprepare_transfer
;
1143 master
->auto_runtime_pm
= true;
1145 drv_data
->ssp_type
= ssp
->type
;
1146 drv_data
->null_dma_buf
= (u32
*)PTR_ALIGN(&drv_data
[1], DMA_ALIGNMENT
);
1148 drv_data
->ioaddr
= ssp
->mmio_base
;
1149 drv_data
->ssdr_physical
= ssp
->phys_base
+ SSDR
;
1150 if (pxa25x_ssp_comp(drv_data
)) {
1151 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(4, 16);
1152 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
;
1153 drv_data
->dma_cr1
= 0;
1154 drv_data
->clear_sr
= SSSR_ROR
;
1155 drv_data
->mask_sr
= SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1157 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(4, 32);
1158 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
| SSCR1_TINTE
;
1159 drv_data
->dma_cr1
= DEFAULT_DMA_CR1
;
1160 drv_data
->clear_sr
= SSSR_ROR
| SSSR_TINT
;
1161 drv_data
->mask_sr
= SSSR_TINT
| SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1164 status
= request_irq(ssp
->irq
, ssp_int
, IRQF_SHARED
, dev_name(dev
),
1167 dev_err(&pdev
->dev
, "cannot get IRQ %d\n", ssp
->irq
);
1168 goto out_error_master_alloc
;
1171 /* Setup DMA if requested */
1172 drv_data
->tx_channel
= -1;
1173 drv_data
->rx_channel
= -1;
1174 if (platform_info
->enable_dma
) {
1175 status
= pxa2xx_spi_dma_setup(drv_data
);
1177 dev_dbg(dev
, "no DMA channels available, using PIO\n");
1178 platform_info
->enable_dma
= false;
1182 /* Enable SOC clock */
1183 clk_prepare_enable(ssp
->clk
);
1185 drv_data
->max_clk_rate
= clk_get_rate(ssp
->clk
);
1187 /* Load default SSP configuration */
1188 write_SSCR0(0, drv_data
->ioaddr
);
1189 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT
) |
1190 SSCR1_TxTresh(TX_THRESH_DFLT
),
1192 write_SSCR0(SSCR0_SCR(2)
1194 | SSCR0_DataSize(8),
1196 if (!pxa25x_ssp_comp(drv_data
))
1197 write_SSTO(0, drv_data
->ioaddr
);
1198 write_SSPSP(0, drv_data
->ioaddr
);
1200 lpss_ssp_setup(drv_data
);
1202 tasklet_init(&drv_data
->pump_transfers
, pump_transfers
,
1203 (unsigned long)drv_data
);
1205 /* Register with the SPI framework */
1206 platform_set_drvdata(pdev
, drv_data
);
1207 status
= devm_spi_register_master(&pdev
->dev
, master
);
1209 dev_err(&pdev
->dev
, "problem registering spi master\n");
1210 goto out_error_clock_enabled
;
1213 pm_runtime_set_autosuspend_delay(&pdev
->dev
, 50);
1214 pm_runtime_use_autosuspend(&pdev
->dev
);
1215 pm_runtime_set_active(&pdev
->dev
);
1216 pm_runtime_enable(&pdev
->dev
);
1220 out_error_clock_enabled
:
1221 clk_disable_unprepare(ssp
->clk
);
1222 pxa2xx_spi_dma_release(drv_data
);
1223 free_irq(ssp
->irq
, drv_data
);
1225 out_error_master_alloc
:
1226 spi_master_put(master
);
1231 static int pxa2xx_spi_remove(struct platform_device
*pdev
)
1233 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1234 struct ssp_device
*ssp
;
1238 ssp
= drv_data
->ssp
;
1240 pm_runtime_get_sync(&pdev
->dev
);
1242 /* Disable the SSP at the peripheral and SOC level */
1243 write_SSCR0(0, drv_data
->ioaddr
);
1244 clk_disable_unprepare(ssp
->clk
);
1247 if (drv_data
->master_info
->enable_dma
)
1248 pxa2xx_spi_dma_release(drv_data
);
1250 pm_runtime_put_noidle(&pdev
->dev
);
1251 pm_runtime_disable(&pdev
->dev
);
1254 free_irq(ssp
->irq
, drv_data
);
1262 static void pxa2xx_spi_shutdown(struct platform_device
*pdev
)
1266 if ((status
= pxa2xx_spi_remove(pdev
)) != 0)
1267 dev_err(&pdev
->dev
, "shutdown failed with %d\n", status
);
1270 #ifdef CONFIG_PM_SLEEP
1271 static int pxa2xx_spi_suspend(struct device
*dev
)
1273 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1274 struct ssp_device
*ssp
= drv_data
->ssp
;
1277 status
= spi_master_suspend(drv_data
->master
);
1280 write_SSCR0(0, drv_data
->ioaddr
);
1281 clk_disable_unprepare(ssp
->clk
);
1286 static int pxa2xx_spi_resume(struct device
*dev
)
1288 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1289 struct ssp_device
*ssp
= drv_data
->ssp
;
1292 pxa2xx_spi_dma_resume(drv_data
);
1294 /* Enable the SSP clock */
1295 clk_prepare_enable(ssp
->clk
);
1297 /* Restore LPSS private register bits */
1298 lpss_ssp_setup(drv_data
);
1300 /* Start the queue running */
1301 status
= spi_master_resume(drv_data
->master
);
1303 dev_err(dev
, "problem starting queue (%d)\n", status
);
1311 #ifdef CONFIG_PM_RUNTIME
1312 static int pxa2xx_spi_runtime_suspend(struct device
*dev
)
1314 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1316 clk_disable_unprepare(drv_data
->ssp
->clk
);
1320 static int pxa2xx_spi_runtime_resume(struct device
*dev
)
1322 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1324 clk_prepare_enable(drv_data
->ssp
->clk
);
1329 static const struct dev_pm_ops pxa2xx_spi_pm_ops
= {
1330 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend
, pxa2xx_spi_resume
)
1331 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend
,
1332 pxa2xx_spi_runtime_resume
, NULL
)
1335 static struct platform_driver driver
= {
1337 .name
= "pxa2xx-spi",
1338 .owner
= THIS_MODULE
,
1339 .pm
= &pxa2xx_spi_pm_ops
,
1340 .acpi_match_table
= ACPI_PTR(pxa2xx_spi_acpi_match
),
1342 .probe
= pxa2xx_spi_probe
,
1343 .remove
= pxa2xx_spi_remove
,
1344 .shutdown
= pxa2xx_spi_shutdown
,
1347 static int __init
pxa2xx_spi_init(void)
1349 return platform_driver_register(&driver
);
1351 subsys_initcall(pxa2xx_spi_init
);
1353 static void __exit
pxa2xx_spi_exit(void)
1355 platform_driver_unregister(&driver
);
1357 module_exit(pxa2xx_spi_exit
);