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Merge tag 'pci-v3.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[deliverable/linux.git] / drivers / spi / spi-pxa2xx.c
1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/ioport.h>
24 #include <linux/errno.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/spi/pxa2xx_spi.h>
29 #include <linux/spi/spi.h>
30 #include <linux/workqueue.h>
31 #include <linux/delay.h>
32 #include <linux/gpio.h>
33 #include <linux/slab.h>
34 #include <linux/clk.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/acpi.h>
37
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 #include <asm/delay.h>
41
42 #include "spi-pxa2xx.h"
43
44 MODULE_AUTHOR("Stephen Street");
45 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
46 MODULE_LICENSE("GPL");
47 MODULE_ALIAS("platform:pxa2xx-spi");
48
49 #define MAX_BUSES 3
50
51 #define TIMOUT_DFLT 1000
52
53 /*
54 * for testing SSCR1 changes that require SSP restart, basically
55 * everything except the service and interrupt enables, the pxa270 developer
56 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
57 * list, but the PXA255 dev man says all bits without really meaning the
58 * service and interrupt enables
59 */
60 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
61 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
62 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
63 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
64 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
66
67 #define LPSS_RX_THRESH_DFLT 64
68 #define LPSS_TX_LOTHRESH_DFLT 160
69 #define LPSS_TX_HITHRESH_DFLT 224
70
71 /* Offset from drv_data->lpss_base */
72 #define GENERAL_REG 0x08
73 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
74 #define SSP_REG 0x0c
75 #define SPI_CS_CONTROL 0x18
76 #define SPI_CS_CONTROL_SW_MODE BIT(0)
77 #define SPI_CS_CONTROL_CS_HIGH BIT(1)
78
79 static bool is_lpss_ssp(const struct driver_data *drv_data)
80 {
81 return drv_data->ssp_type == LPSS_SSP;
82 }
83
84 /*
85 * Read and write LPSS SSP private registers. Caller must first check that
86 * is_lpss_ssp() returns true before these can be called.
87 */
88 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
89 {
90 WARN_ON(!drv_data->lpss_base);
91 return readl(drv_data->lpss_base + offset);
92 }
93
94 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
95 unsigned offset, u32 value)
96 {
97 WARN_ON(!drv_data->lpss_base);
98 writel(value, drv_data->lpss_base + offset);
99 }
100
101 /*
102 * lpss_ssp_setup - perform LPSS SSP specific setup
103 * @drv_data: pointer to the driver private data
104 *
105 * Perform LPSS SSP specific setup. This function must be called first if
106 * one is going to use LPSS SSP private registers.
107 */
108 static void lpss_ssp_setup(struct driver_data *drv_data)
109 {
110 unsigned offset = 0x400;
111 u32 value, orig;
112
113 if (!is_lpss_ssp(drv_data))
114 return;
115
116 /*
117 * Perform auto-detection of the LPSS SSP private registers. They
118 * can be either at 1k or 2k offset from the base address.
119 */
120 orig = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
121
122 value = orig | SPI_CS_CONTROL_SW_MODE;
123 writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
124 value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
125 if (value != (orig | SPI_CS_CONTROL_SW_MODE)) {
126 offset = 0x800;
127 goto detection_done;
128 }
129
130 value &= ~SPI_CS_CONTROL_SW_MODE;
131 writel(value, drv_data->ioaddr + offset + SPI_CS_CONTROL);
132 value = readl(drv_data->ioaddr + offset + SPI_CS_CONTROL);
133 if (value != orig) {
134 offset = 0x800;
135 goto detection_done;
136 }
137
138 detection_done:
139 /* Now set the LPSS base */
140 drv_data->lpss_base = drv_data->ioaddr + offset;
141
142 /* Enable software chip select control */
143 value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
144 __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
145
146 /* Enable multiblock DMA transfers */
147 if (drv_data->master_info->enable_dma) {
148 __lpss_ssp_write_priv(drv_data, SSP_REG, 1);
149
150 value = __lpss_ssp_read_priv(drv_data, GENERAL_REG);
151 value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE;
152 __lpss_ssp_write_priv(drv_data, GENERAL_REG, value);
153 }
154 }
155
156 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
157 {
158 u32 value;
159
160 if (!is_lpss_ssp(drv_data))
161 return;
162
163 value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
164 if (enable)
165 value &= ~SPI_CS_CONTROL_CS_HIGH;
166 else
167 value |= SPI_CS_CONTROL_CS_HIGH;
168 __lpss_ssp_write_priv(drv_data, SPI_CS_CONTROL, value);
169 }
170
171 static void cs_assert(struct driver_data *drv_data)
172 {
173 struct chip_data *chip = drv_data->cur_chip;
174
175 if (drv_data->ssp_type == CE4100_SSP) {
176 write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
177 return;
178 }
179
180 if (chip->cs_control) {
181 chip->cs_control(PXA2XX_CS_ASSERT);
182 return;
183 }
184
185 if (gpio_is_valid(chip->gpio_cs)) {
186 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
187 return;
188 }
189
190 lpss_ssp_cs_control(drv_data, true);
191 }
192
193 static void cs_deassert(struct driver_data *drv_data)
194 {
195 struct chip_data *chip = drv_data->cur_chip;
196
197 if (drv_data->ssp_type == CE4100_SSP)
198 return;
199
200 if (chip->cs_control) {
201 chip->cs_control(PXA2XX_CS_DEASSERT);
202 return;
203 }
204
205 if (gpio_is_valid(chip->gpio_cs)) {
206 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
207 return;
208 }
209
210 lpss_ssp_cs_control(drv_data, false);
211 }
212
213 int pxa2xx_spi_flush(struct driver_data *drv_data)
214 {
215 unsigned long limit = loops_per_jiffy << 1;
216
217 void __iomem *reg = drv_data->ioaddr;
218
219 do {
220 while (read_SSSR(reg) & SSSR_RNE) {
221 read_SSDR(reg);
222 }
223 } while ((read_SSSR(reg) & SSSR_BSY) && --limit);
224 write_SSSR_CS(drv_data, SSSR_ROR);
225
226 return limit;
227 }
228
229 static int null_writer(struct driver_data *drv_data)
230 {
231 void __iomem *reg = drv_data->ioaddr;
232 u8 n_bytes = drv_data->n_bytes;
233
234 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
235 || (drv_data->tx == drv_data->tx_end))
236 return 0;
237
238 write_SSDR(0, reg);
239 drv_data->tx += n_bytes;
240
241 return 1;
242 }
243
244 static int null_reader(struct driver_data *drv_data)
245 {
246 void __iomem *reg = drv_data->ioaddr;
247 u8 n_bytes = drv_data->n_bytes;
248
249 while ((read_SSSR(reg) & SSSR_RNE)
250 && (drv_data->rx < drv_data->rx_end)) {
251 read_SSDR(reg);
252 drv_data->rx += n_bytes;
253 }
254
255 return drv_data->rx == drv_data->rx_end;
256 }
257
258 static int u8_writer(struct driver_data *drv_data)
259 {
260 void __iomem *reg = drv_data->ioaddr;
261
262 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
263 || (drv_data->tx == drv_data->tx_end))
264 return 0;
265
266 write_SSDR(*(u8 *)(drv_data->tx), reg);
267 ++drv_data->tx;
268
269 return 1;
270 }
271
272 static int u8_reader(struct driver_data *drv_data)
273 {
274 void __iomem *reg = drv_data->ioaddr;
275
276 while ((read_SSSR(reg) & SSSR_RNE)
277 && (drv_data->rx < drv_data->rx_end)) {
278 *(u8 *)(drv_data->rx) = read_SSDR(reg);
279 ++drv_data->rx;
280 }
281
282 return drv_data->rx == drv_data->rx_end;
283 }
284
285 static int u16_writer(struct driver_data *drv_data)
286 {
287 void __iomem *reg = drv_data->ioaddr;
288
289 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
290 || (drv_data->tx == drv_data->tx_end))
291 return 0;
292
293 write_SSDR(*(u16 *)(drv_data->tx), reg);
294 drv_data->tx += 2;
295
296 return 1;
297 }
298
299 static int u16_reader(struct driver_data *drv_data)
300 {
301 void __iomem *reg = drv_data->ioaddr;
302
303 while ((read_SSSR(reg) & SSSR_RNE)
304 && (drv_data->rx < drv_data->rx_end)) {
305 *(u16 *)(drv_data->rx) = read_SSDR(reg);
306 drv_data->rx += 2;
307 }
308
309 return drv_data->rx == drv_data->rx_end;
310 }
311
312 static int u32_writer(struct driver_data *drv_data)
313 {
314 void __iomem *reg = drv_data->ioaddr;
315
316 if (((read_SSSR(reg) & SSSR_TFL_MASK) == SSSR_TFL_MASK)
317 || (drv_data->tx == drv_data->tx_end))
318 return 0;
319
320 write_SSDR(*(u32 *)(drv_data->tx), reg);
321 drv_data->tx += 4;
322
323 return 1;
324 }
325
326 static int u32_reader(struct driver_data *drv_data)
327 {
328 void __iomem *reg = drv_data->ioaddr;
329
330 while ((read_SSSR(reg) & SSSR_RNE)
331 && (drv_data->rx < drv_data->rx_end)) {
332 *(u32 *)(drv_data->rx) = read_SSDR(reg);
333 drv_data->rx += 4;
334 }
335
336 return drv_data->rx == drv_data->rx_end;
337 }
338
339 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
340 {
341 struct spi_message *msg = drv_data->cur_msg;
342 struct spi_transfer *trans = drv_data->cur_transfer;
343
344 /* Move to next transfer */
345 if (trans->transfer_list.next != &msg->transfers) {
346 drv_data->cur_transfer =
347 list_entry(trans->transfer_list.next,
348 struct spi_transfer,
349 transfer_list);
350 return RUNNING_STATE;
351 } else
352 return DONE_STATE;
353 }
354
355 /* caller already set message->status; dma and pio irqs are blocked */
356 static void giveback(struct driver_data *drv_data)
357 {
358 struct spi_transfer* last_transfer;
359 struct spi_message *msg;
360
361 msg = drv_data->cur_msg;
362 drv_data->cur_msg = NULL;
363 drv_data->cur_transfer = NULL;
364
365 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
366 transfer_list);
367
368 /* Delay if requested before any change in chip select */
369 if (last_transfer->delay_usecs)
370 udelay(last_transfer->delay_usecs);
371
372 /* Drop chip select UNLESS cs_change is true or we are returning
373 * a message with an error, or next message is for another chip
374 */
375 if (!last_transfer->cs_change)
376 cs_deassert(drv_data);
377 else {
378 struct spi_message *next_msg;
379
380 /* Holding of cs was hinted, but we need to make sure
381 * the next message is for the same chip. Don't waste
382 * time with the following tests unless this was hinted.
383 *
384 * We cannot postpone this until pump_messages, because
385 * after calling msg->complete (below) the driver that
386 * sent the current message could be unloaded, which
387 * could invalidate the cs_control() callback...
388 */
389
390 /* get a pointer to the next message, if any */
391 next_msg = spi_get_next_queued_message(drv_data->master);
392
393 /* see if the next and current messages point
394 * to the same chip
395 */
396 if (next_msg && next_msg->spi != msg->spi)
397 next_msg = NULL;
398 if (!next_msg || msg->state == ERROR_STATE)
399 cs_deassert(drv_data);
400 }
401
402 spi_finalize_current_message(drv_data->master);
403 drv_data->cur_chip = NULL;
404 }
405
406 static void reset_sccr1(struct driver_data *drv_data)
407 {
408 void __iomem *reg = drv_data->ioaddr;
409 struct chip_data *chip = drv_data->cur_chip;
410 u32 sccr1_reg;
411
412 sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
413 sccr1_reg &= ~SSCR1_RFT;
414 sccr1_reg |= chip->threshold;
415 write_SSCR1(sccr1_reg, reg);
416 }
417
418 static void int_error_stop(struct driver_data *drv_data, const char* msg)
419 {
420 void __iomem *reg = drv_data->ioaddr;
421
422 /* Stop and reset SSP */
423 write_SSSR_CS(drv_data, drv_data->clear_sr);
424 reset_sccr1(drv_data);
425 if (!pxa25x_ssp_comp(drv_data))
426 write_SSTO(0, reg);
427 pxa2xx_spi_flush(drv_data);
428 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
429
430 dev_err(&drv_data->pdev->dev, "%s\n", msg);
431
432 drv_data->cur_msg->state = ERROR_STATE;
433 tasklet_schedule(&drv_data->pump_transfers);
434 }
435
436 static void int_transfer_complete(struct driver_data *drv_data)
437 {
438 void __iomem *reg = drv_data->ioaddr;
439
440 /* Stop SSP */
441 write_SSSR_CS(drv_data, drv_data->clear_sr);
442 reset_sccr1(drv_data);
443 if (!pxa25x_ssp_comp(drv_data))
444 write_SSTO(0, reg);
445
446 /* Update total byte transferred return count actual bytes read */
447 drv_data->cur_msg->actual_length += drv_data->len -
448 (drv_data->rx_end - drv_data->rx);
449
450 /* Transfer delays and chip select release are
451 * handled in pump_transfers or giveback
452 */
453
454 /* Move to next transfer */
455 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
456
457 /* Schedule transfer tasklet */
458 tasklet_schedule(&drv_data->pump_transfers);
459 }
460
461 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
462 {
463 void __iomem *reg = drv_data->ioaddr;
464
465 u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
466 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
467
468 u32 irq_status = read_SSSR(reg) & irq_mask;
469
470 if (irq_status & SSSR_ROR) {
471 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
472 return IRQ_HANDLED;
473 }
474
475 if (irq_status & SSSR_TINT) {
476 write_SSSR(SSSR_TINT, reg);
477 if (drv_data->read(drv_data)) {
478 int_transfer_complete(drv_data);
479 return IRQ_HANDLED;
480 }
481 }
482
483 /* Drain rx fifo, Fill tx fifo and prevent overruns */
484 do {
485 if (drv_data->read(drv_data)) {
486 int_transfer_complete(drv_data);
487 return IRQ_HANDLED;
488 }
489 } while (drv_data->write(drv_data));
490
491 if (drv_data->read(drv_data)) {
492 int_transfer_complete(drv_data);
493 return IRQ_HANDLED;
494 }
495
496 if (drv_data->tx == drv_data->tx_end) {
497 u32 bytes_left;
498 u32 sccr1_reg;
499
500 sccr1_reg = read_SSCR1(reg);
501 sccr1_reg &= ~SSCR1_TIE;
502
503 /*
504 * PXA25x_SSP has no timeout, set up rx threshould for the
505 * remaining RX bytes.
506 */
507 if (pxa25x_ssp_comp(drv_data)) {
508
509 sccr1_reg &= ~SSCR1_RFT;
510
511 bytes_left = drv_data->rx_end - drv_data->rx;
512 switch (drv_data->n_bytes) {
513 case 4:
514 bytes_left >>= 1;
515 case 2:
516 bytes_left >>= 1;
517 }
518
519 if (bytes_left > RX_THRESH_DFLT)
520 bytes_left = RX_THRESH_DFLT;
521
522 sccr1_reg |= SSCR1_RxTresh(bytes_left);
523 }
524 write_SSCR1(sccr1_reg, reg);
525 }
526
527 /* We did something */
528 return IRQ_HANDLED;
529 }
530
531 static irqreturn_t ssp_int(int irq, void *dev_id)
532 {
533 struct driver_data *drv_data = dev_id;
534 void __iomem *reg = drv_data->ioaddr;
535 u32 sccr1_reg;
536 u32 mask = drv_data->mask_sr;
537 u32 status;
538
539 /*
540 * The IRQ might be shared with other peripherals so we must first
541 * check that are we RPM suspended or not. If we are we assume that
542 * the IRQ was not for us (we shouldn't be RPM suspended when the
543 * interrupt is enabled).
544 */
545 if (pm_runtime_suspended(&drv_data->pdev->dev))
546 return IRQ_NONE;
547
548 /*
549 * If the device is not yet in RPM suspended state and we get an
550 * interrupt that is meant for another device, check if status bits
551 * are all set to one. That means that the device is already
552 * powered off.
553 */
554 status = read_SSSR(reg);
555 if (status == ~0)
556 return IRQ_NONE;
557
558 sccr1_reg = read_SSCR1(reg);
559
560 /* Ignore possible writes if we don't need to write */
561 if (!(sccr1_reg & SSCR1_TIE))
562 mask &= ~SSSR_TFS;
563
564 if (!(status & mask))
565 return IRQ_NONE;
566
567 if (!drv_data->cur_msg) {
568
569 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
570 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
571 if (!pxa25x_ssp_comp(drv_data))
572 write_SSTO(0, reg);
573 write_SSSR_CS(drv_data, drv_data->clear_sr);
574
575 dev_err(&drv_data->pdev->dev,
576 "bad message state in interrupt handler\n");
577
578 /* Never fail */
579 return IRQ_HANDLED;
580 }
581
582 return drv_data->transfer_handler(drv_data);
583 }
584
585 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
586 {
587 unsigned long ssp_clk = drv_data->max_clk_rate;
588 const struct ssp_device *ssp = drv_data->ssp;
589
590 rate = min_t(int, ssp_clk, rate);
591
592 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
593 return ((ssp_clk / (2 * rate) - 1) & 0xff) << 8;
594 else
595 return ((ssp_clk / rate - 1) & 0xfff) << 8;
596 }
597
598 static void pump_transfers(unsigned long data)
599 {
600 struct driver_data *drv_data = (struct driver_data *)data;
601 struct spi_message *message = NULL;
602 struct spi_transfer *transfer = NULL;
603 struct spi_transfer *previous = NULL;
604 struct chip_data *chip = NULL;
605 void __iomem *reg = drv_data->ioaddr;
606 u32 clk_div = 0;
607 u8 bits = 0;
608 u32 speed = 0;
609 u32 cr0;
610 u32 cr1;
611 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
612 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
613
614 /* Get current state information */
615 message = drv_data->cur_msg;
616 transfer = drv_data->cur_transfer;
617 chip = drv_data->cur_chip;
618
619 /* Handle for abort */
620 if (message->state == ERROR_STATE) {
621 message->status = -EIO;
622 giveback(drv_data);
623 return;
624 }
625
626 /* Handle end of message */
627 if (message->state == DONE_STATE) {
628 message->status = 0;
629 giveback(drv_data);
630 return;
631 }
632
633 /* Delay if requested at end of transfer before CS change */
634 if (message->state == RUNNING_STATE) {
635 previous = list_entry(transfer->transfer_list.prev,
636 struct spi_transfer,
637 transfer_list);
638 if (previous->delay_usecs)
639 udelay(previous->delay_usecs);
640
641 /* Drop chip select only if cs_change is requested */
642 if (previous->cs_change)
643 cs_deassert(drv_data);
644 }
645
646 /* Check if we can DMA this transfer */
647 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
648
649 /* reject already-mapped transfers; PIO won't always work */
650 if (message->is_dma_mapped
651 || transfer->rx_dma || transfer->tx_dma) {
652 dev_err(&drv_data->pdev->dev,
653 "pump_transfers: mapped transfer length of "
654 "%u is greater than %d\n",
655 transfer->len, MAX_DMA_LEN);
656 message->status = -EINVAL;
657 giveback(drv_data);
658 return;
659 }
660
661 /* warn ... we force this to PIO mode */
662 dev_warn_ratelimited(&message->spi->dev,
663 "pump_transfers: DMA disabled for transfer length %ld "
664 "greater than %d\n",
665 (long)drv_data->len, MAX_DMA_LEN);
666 }
667
668 /* Setup the transfer state based on the type of transfer */
669 if (pxa2xx_spi_flush(drv_data) == 0) {
670 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
671 message->status = -EIO;
672 giveback(drv_data);
673 return;
674 }
675 drv_data->n_bytes = chip->n_bytes;
676 drv_data->tx = (void *)transfer->tx_buf;
677 drv_data->tx_end = drv_data->tx + transfer->len;
678 drv_data->rx = transfer->rx_buf;
679 drv_data->rx_end = drv_data->rx + transfer->len;
680 drv_data->rx_dma = transfer->rx_dma;
681 drv_data->tx_dma = transfer->tx_dma;
682 drv_data->len = transfer->len;
683 drv_data->write = drv_data->tx ? chip->write : null_writer;
684 drv_data->read = drv_data->rx ? chip->read : null_reader;
685
686 /* Change speed and bit per word on a per transfer */
687 cr0 = chip->cr0;
688 if (transfer->speed_hz || transfer->bits_per_word) {
689
690 bits = chip->bits_per_word;
691 speed = chip->speed_hz;
692
693 if (transfer->speed_hz)
694 speed = transfer->speed_hz;
695
696 if (transfer->bits_per_word)
697 bits = transfer->bits_per_word;
698
699 clk_div = ssp_get_clk_div(drv_data, speed);
700
701 if (bits <= 8) {
702 drv_data->n_bytes = 1;
703 drv_data->read = drv_data->read != null_reader ?
704 u8_reader : null_reader;
705 drv_data->write = drv_data->write != null_writer ?
706 u8_writer : null_writer;
707 } else if (bits <= 16) {
708 drv_data->n_bytes = 2;
709 drv_data->read = drv_data->read != null_reader ?
710 u16_reader : null_reader;
711 drv_data->write = drv_data->write != null_writer ?
712 u16_writer : null_writer;
713 } else if (bits <= 32) {
714 drv_data->n_bytes = 4;
715 drv_data->read = drv_data->read != null_reader ?
716 u32_reader : null_reader;
717 drv_data->write = drv_data->write != null_writer ?
718 u32_writer : null_writer;
719 }
720 /* if bits/word is changed in dma mode, then must check the
721 * thresholds and burst also */
722 if (chip->enable_dma) {
723 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
724 message->spi,
725 bits, &dma_burst,
726 &dma_thresh))
727 dev_warn_ratelimited(&message->spi->dev,
728 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
729 }
730
731 cr0 = clk_div
732 | SSCR0_Motorola
733 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
734 | SSCR0_SSE
735 | (bits > 16 ? SSCR0_EDSS : 0);
736 }
737
738 message->state = RUNNING_STATE;
739
740 drv_data->dma_mapped = 0;
741 if (pxa2xx_spi_dma_is_possible(drv_data->len))
742 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
743 if (drv_data->dma_mapped) {
744
745 /* Ensure we have the correct interrupt handler */
746 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
747
748 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
749
750 /* Clear status and start DMA engine */
751 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
752 write_SSSR(drv_data->clear_sr, reg);
753
754 pxa2xx_spi_dma_start(drv_data);
755 } else {
756 /* Ensure we have the correct interrupt handler */
757 drv_data->transfer_handler = interrupt_transfer;
758
759 /* Clear status */
760 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
761 write_SSSR_CS(drv_data, drv_data->clear_sr);
762 }
763
764 if (is_lpss_ssp(drv_data)) {
765 if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
766 write_SSIRF(chip->lpss_rx_threshold, reg);
767 if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
768 write_SSITF(chip->lpss_tx_threshold, reg);
769 }
770
771 /* see if we need to reload the config registers */
772 if ((read_SSCR0(reg) != cr0)
773 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
774 (cr1 & SSCR1_CHANGE_MASK)) {
775
776 /* stop the SSP, and update the other bits */
777 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
778 if (!pxa25x_ssp_comp(drv_data))
779 write_SSTO(chip->timeout, reg);
780 /* first set CR1 without interrupt and service enables */
781 write_SSCR1(cr1 & SSCR1_CHANGE_MASK, reg);
782 /* restart the SSP */
783 write_SSCR0(cr0, reg);
784
785 } else {
786 if (!pxa25x_ssp_comp(drv_data))
787 write_SSTO(chip->timeout, reg);
788 }
789
790 cs_assert(drv_data);
791
792 /* after chip select, release the data by enabling service
793 * requests and interrupts, without changing any mode bits */
794 write_SSCR1(cr1, reg);
795 }
796
797 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
798 struct spi_message *msg)
799 {
800 struct driver_data *drv_data = spi_master_get_devdata(master);
801
802 drv_data->cur_msg = msg;
803 /* Initial message state*/
804 drv_data->cur_msg->state = START_STATE;
805 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
806 struct spi_transfer,
807 transfer_list);
808
809 /* prepare to setup the SSP, in pump_transfers, using the per
810 * chip configuration */
811 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
812
813 /* Mark as busy and launch transfers */
814 tasklet_schedule(&drv_data->pump_transfers);
815 return 0;
816 }
817
818 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
819 {
820 struct driver_data *drv_data = spi_master_get_devdata(master);
821
822 /* Disable the SSP now */
823 write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE,
824 drv_data->ioaddr);
825
826 return 0;
827 }
828
829 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
830 struct pxa2xx_spi_chip *chip_info)
831 {
832 int err = 0;
833
834 if (chip == NULL || chip_info == NULL)
835 return 0;
836
837 /* NOTE: setup() can be called multiple times, possibly with
838 * different chip_info, release previously requested GPIO
839 */
840 if (gpio_is_valid(chip->gpio_cs))
841 gpio_free(chip->gpio_cs);
842
843 /* If (*cs_control) is provided, ignore GPIO chip select */
844 if (chip_info->cs_control) {
845 chip->cs_control = chip_info->cs_control;
846 return 0;
847 }
848
849 if (gpio_is_valid(chip_info->gpio_cs)) {
850 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
851 if (err) {
852 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
853 chip_info->gpio_cs);
854 return err;
855 }
856
857 chip->gpio_cs = chip_info->gpio_cs;
858 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
859
860 err = gpio_direction_output(chip->gpio_cs,
861 !chip->gpio_cs_inverted);
862 }
863
864 return err;
865 }
866
867 static int setup(struct spi_device *spi)
868 {
869 struct pxa2xx_spi_chip *chip_info = NULL;
870 struct chip_data *chip;
871 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
872 unsigned int clk_div;
873 uint tx_thres, tx_hi_thres, rx_thres;
874
875 if (is_lpss_ssp(drv_data)) {
876 tx_thres = LPSS_TX_LOTHRESH_DFLT;
877 tx_hi_thres = LPSS_TX_HITHRESH_DFLT;
878 rx_thres = LPSS_RX_THRESH_DFLT;
879 } else {
880 tx_thres = TX_THRESH_DFLT;
881 tx_hi_thres = 0;
882 rx_thres = RX_THRESH_DFLT;
883 }
884
885 /* Only alloc on first setup */
886 chip = spi_get_ctldata(spi);
887 if (!chip) {
888 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
889 if (!chip) {
890 dev_err(&spi->dev,
891 "failed setup: can't allocate chip data\n");
892 return -ENOMEM;
893 }
894
895 if (drv_data->ssp_type == CE4100_SSP) {
896 if (spi->chip_select > 4) {
897 dev_err(&spi->dev,
898 "failed setup: cs number must not be > 4.\n");
899 kfree(chip);
900 return -EINVAL;
901 }
902
903 chip->frm = spi->chip_select;
904 } else
905 chip->gpio_cs = -1;
906 chip->enable_dma = 0;
907 chip->timeout = TIMOUT_DFLT;
908 }
909
910 /* protocol drivers may change the chip settings, so...
911 * if chip_info exists, use it */
912 chip_info = spi->controller_data;
913
914 /* chip_info isn't always needed */
915 chip->cr1 = 0;
916 if (chip_info) {
917 if (chip_info->timeout)
918 chip->timeout = chip_info->timeout;
919 if (chip_info->tx_threshold)
920 tx_thres = chip_info->tx_threshold;
921 if (chip_info->tx_hi_threshold)
922 tx_hi_thres = chip_info->tx_hi_threshold;
923 if (chip_info->rx_threshold)
924 rx_thres = chip_info->rx_threshold;
925 chip->enable_dma = drv_data->master_info->enable_dma;
926 chip->dma_threshold = 0;
927 if (chip_info->enable_loopback)
928 chip->cr1 = SSCR1_LBM;
929 } else if (ACPI_HANDLE(&spi->dev)) {
930 /*
931 * Slave devices enumerated from ACPI namespace don't
932 * usually have chip_info but we still might want to use
933 * DMA with them.
934 */
935 chip->enable_dma = drv_data->master_info->enable_dma;
936 }
937
938 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
939 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
940
941 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
942 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
943 | SSITF_TxHiThresh(tx_hi_thres);
944
945 /* set dma burst and threshold outside of chip_info path so that if
946 * chip_info goes away after setting chip->enable_dma, the
947 * burst and threshold can still respond to changes in bits_per_word */
948 if (chip->enable_dma) {
949 /* set up legal burst and threshold for dma */
950 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
951 spi->bits_per_word,
952 &chip->dma_burst_size,
953 &chip->dma_threshold)) {
954 dev_warn(&spi->dev,
955 "in setup: DMA burst size reduced to match bits_per_word\n");
956 }
957 }
958
959 clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz);
960 chip->speed_hz = spi->max_speed_hz;
961
962 chip->cr0 = clk_div
963 | SSCR0_Motorola
964 | SSCR0_DataSize(spi->bits_per_word > 16 ?
965 spi->bits_per_word - 16 : spi->bits_per_word)
966 | SSCR0_SSE
967 | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
968 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
969 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
970 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
971
972 if (spi->mode & SPI_LOOP)
973 chip->cr1 |= SSCR1_LBM;
974
975 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
976 if (!pxa25x_ssp_comp(drv_data))
977 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
978 drv_data->max_clk_rate
979 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
980 chip->enable_dma ? "DMA" : "PIO");
981 else
982 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
983 drv_data->max_clk_rate / 2
984 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
985 chip->enable_dma ? "DMA" : "PIO");
986
987 if (spi->bits_per_word <= 8) {
988 chip->n_bytes = 1;
989 chip->read = u8_reader;
990 chip->write = u8_writer;
991 } else if (spi->bits_per_word <= 16) {
992 chip->n_bytes = 2;
993 chip->read = u16_reader;
994 chip->write = u16_writer;
995 } else if (spi->bits_per_word <= 32) {
996 chip->cr0 |= SSCR0_EDSS;
997 chip->n_bytes = 4;
998 chip->read = u32_reader;
999 chip->write = u32_writer;
1000 }
1001 chip->bits_per_word = spi->bits_per_word;
1002
1003 spi_set_ctldata(spi, chip);
1004
1005 if (drv_data->ssp_type == CE4100_SSP)
1006 return 0;
1007
1008 return setup_cs(spi, chip, chip_info);
1009 }
1010
1011 static void cleanup(struct spi_device *spi)
1012 {
1013 struct chip_data *chip = spi_get_ctldata(spi);
1014 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1015
1016 if (!chip)
1017 return;
1018
1019 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1020 gpio_free(chip->gpio_cs);
1021
1022 kfree(chip);
1023 }
1024
1025 #ifdef CONFIG_ACPI
1026 static struct pxa2xx_spi_master *
1027 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1028 {
1029 struct pxa2xx_spi_master *pdata;
1030 struct acpi_device *adev;
1031 struct ssp_device *ssp;
1032 struct resource *res;
1033 int devid;
1034
1035 if (!ACPI_HANDLE(&pdev->dev) ||
1036 acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1037 return NULL;
1038
1039 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1040 if (!pdata) {
1041 dev_err(&pdev->dev,
1042 "failed to allocate memory for platform data\n");
1043 return NULL;
1044 }
1045
1046 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1047 if (!res)
1048 return NULL;
1049
1050 ssp = &pdata->ssp;
1051
1052 ssp->phys_base = res->start;
1053 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1054 if (IS_ERR(ssp->mmio_base))
1055 return NULL;
1056
1057 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1058 ssp->irq = platform_get_irq(pdev, 0);
1059 ssp->type = LPSS_SSP;
1060 ssp->pdev = pdev;
1061
1062 ssp->port_id = -1;
1063 if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
1064 ssp->port_id = devid;
1065
1066 pdata->num_chipselect = 1;
1067 pdata->enable_dma = true;
1068 pdata->tx_chan_id = -1;
1069 pdata->rx_chan_id = -1;
1070
1071 return pdata;
1072 }
1073
1074 static struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1075 { "INT33C0", 0 },
1076 { "INT33C1", 0 },
1077 { "INT3430", 0 },
1078 { "INT3431", 0 },
1079 { "80860F0E", 0 },
1080 { },
1081 };
1082 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1083 #else
1084 static inline struct pxa2xx_spi_master *
1085 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1086 {
1087 return NULL;
1088 }
1089 #endif
1090
1091 static int pxa2xx_spi_probe(struct platform_device *pdev)
1092 {
1093 struct device *dev = &pdev->dev;
1094 struct pxa2xx_spi_master *platform_info;
1095 struct spi_master *master;
1096 struct driver_data *drv_data;
1097 struct ssp_device *ssp;
1098 int status;
1099
1100 platform_info = dev_get_platdata(dev);
1101 if (!platform_info) {
1102 platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1103 if (!platform_info) {
1104 dev_err(&pdev->dev, "missing platform data\n");
1105 return -ENODEV;
1106 }
1107 }
1108
1109 ssp = pxa_ssp_request(pdev->id, pdev->name);
1110 if (!ssp)
1111 ssp = &platform_info->ssp;
1112
1113 if (!ssp->mmio_base) {
1114 dev_err(&pdev->dev, "failed to get ssp\n");
1115 return -ENODEV;
1116 }
1117
1118 /* Allocate master with space for drv_data and null dma buffer */
1119 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1120 if (!master) {
1121 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1122 pxa_ssp_free(ssp);
1123 return -ENOMEM;
1124 }
1125 drv_data = spi_master_get_devdata(master);
1126 drv_data->master = master;
1127 drv_data->master_info = platform_info;
1128 drv_data->pdev = pdev;
1129 drv_data->ssp = ssp;
1130
1131 master->dev.parent = &pdev->dev;
1132 master->dev.of_node = pdev->dev.of_node;
1133 /* the spi->mode bits understood by this driver: */
1134 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1135
1136 master->bus_num = ssp->port_id;
1137 master->num_chipselect = platform_info->num_chipselect;
1138 master->dma_alignment = DMA_ALIGNMENT;
1139 master->cleanup = cleanup;
1140 master->setup = setup;
1141 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1142 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1143 master->auto_runtime_pm = true;
1144
1145 drv_data->ssp_type = ssp->type;
1146 drv_data->null_dma_buf = (u32 *)PTR_ALIGN(&drv_data[1], DMA_ALIGNMENT);
1147
1148 drv_data->ioaddr = ssp->mmio_base;
1149 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1150 if (pxa25x_ssp_comp(drv_data)) {
1151 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1152 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1153 drv_data->dma_cr1 = 0;
1154 drv_data->clear_sr = SSSR_ROR;
1155 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1156 } else {
1157 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1158 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1159 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1160 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1161 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1162 }
1163
1164 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1165 drv_data);
1166 if (status < 0) {
1167 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1168 goto out_error_master_alloc;
1169 }
1170
1171 /* Setup DMA if requested */
1172 drv_data->tx_channel = -1;
1173 drv_data->rx_channel = -1;
1174 if (platform_info->enable_dma) {
1175 status = pxa2xx_spi_dma_setup(drv_data);
1176 if (status) {
1177 dev_dbg(dev, "no DMA channels available, using PIO\n");
1178 platform_info->enable_dma = false;
1179 }
1180 }
1181
1182 /* Enable SOC clock */
1183 clk_prepare_enable(ssp->clk);
1184
1185 drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1186
1187 /* Load default SSP configuration */
1188 write_SSCR0(0, drv_data->ioaddr);
1189 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
1190 SSCR1_TxTresh(TX_THRESH_DFLT),
1191 drv_data->ioaddr);
1192 write_SSCR0(SSCR0_SCR(2)
1193 | SSCR0_Motorola
1194 | SSCR0_DataSize(8),
1195 drv_data->ioaddr);
1196 if (!pxa25x_ssp_comp(drv_data))
1197 write_SSTO(0, drv_data->ioaddr);
1198 write_SSPSP(0, drv_data->ioaddr);
1199
1200 lpss_ssp_setup(drv_data);
1201
1202 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1203 (unsigned long)drv_data);
1204
1205 /* Register with the SPI framework */
1206 platform_set_drvdata(pdev, drv_data);
1207 status = devm_spi_register_master(&pdev->dev, master);
1208 if (status != 0) {
1209 dev_err(&pdev->dev, "problem registering spi master\n");
1210 goto out_error_clock_enabled;
1211 }
1212
1213 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1214 pm_runtime_use_autosuspend(&pdev->dev);
1215 pm_runtime_set_active(&pdev->dev);
1216 pm_runtime_enable(&pdev->dev);
1217
1218 return status;
1219
1220 out_error_clock_enabled:
1221 clk_disable_unprepare(ssp->clk);
1222 pxa2xx_spi_dma_release(drv_data);
1223 free_irq(ssp->irq, drv_data);
1224
1225 out_error_master_alloc:
1226 spi_master_put(master);
1227 pxa_ssp_free(ssp);
1228 return status;
1229 }
1230
1231 static int pxa2xx_spi_remove(struct platform_device *pdev)
1232 {
1233 struct driver_data *drv_data = platform_get_drvdata(pdev);
1234 struct ssp_device *ssp;
1235
1236 if (!drv_data)
1237 return 0;
1238 ssp = drv_data->ssp;
1239
1240 pm_runtime_get_sync(&pdev->dev);
1241
1242 /* Disable the SSP at the peripheral and SOC level */
1243 write_SSCR0(0, drv_data->ioaddr);
1244 clk_disable_unprepare(ssp->clk);
1245
1246 /* Release DMA */
1247 if (drv_data->master_info->enable_dma)
1248 pxa2xx_spi_dma_release(drv_data);
1249
1250 pm_runtime_put_noidle(&pdev->dev);
1251 pm_runtime_disable(&pdev->dev);
1252
1253 /* Release IRQ */
1254 free_irq(ssp->irq, drv_data);
1255
1256 /* Release SSP */
1257 pxa_ssp_free(ssp);
1258
1259 return 0;
1260 }
1261
1262 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1263 {
1264 int status = 0;
1265
1266 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1267 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1268 }
1269
1270 #ifdef CONFIG_PM_SLEEP
1271 static int pxa2xx_spi_suspend(struct device *dev)
1272 {
1273 struct driver_data *drv_data = dev_get_drvdata(dev);
1274 struct ssp_device *ssp = drv_data->ssp;
1275 int status = 0;
1276
1277 status = spi_master_suspend(drv_data->master);
1278 if (status != 0)
1279 return status;
1280 write_SSCR0(0, drv_data->ioaddr);
1281 clk_disable_unprepare(ssp->clk);
1282
1283 return 0;
1284 }
1285
1286 static int pxa2xx_spi_resume(struct device *dev)
1287 {
1288 struct driver_data *drv_data = dev_get_drvdata(dev);
1289 struct ssp_device *ssp = drv_data->ssp;
1290 int status = 0;
1291
1292 pxa2xx_spi_dma_resume(drv_data);
1293
1294 /* Enable the SSP clock */
1295 clk_prepare_enable(ssp->clk);
1296
1297 /* Restore LPSS private register bits */
1298 lpss_ssp_setup(drv_data);
1299
1300 /* Start the queue running */
1301 status = spi_master_resume(drv_data->master);
1302 if (status != 0) {
1303 dev_err(dev, "problem starting queue (%d)\n", status);
1304 return status;
1305 }
1306
1307 return 0;
1308 }
1309 #endif
1310
1311 #ifdef CONFIG_PM_RUNTIME
1312 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1313 {
1314 struct driver_data *drv_data = dev_get_drvdata(dev);
1315
1316 clk_disable_unprepare(drv_data->ssp->clk);
1317 return 0;
1318 }
1319
1320 static int pxa2xx_spi_runtime_resume(struct device *dev)
1321 {
1322 struct driver_data *drv_data = dev_get_drvdata(dev);
1323
1324 clk_prepare_enable(drv_data->ssp->clk);
1325 return 0;
1326 }
1327 #endif
1328
1329 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1330 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1331 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1332 pxa2xx_spi_runtime_resume, NULL)
1333 };
1334
1335 static struct platform_driver driver = {
1336 .driver = {
1337 .name = "pxa2xx-spi",
1338 .owner = THIS_MODULE,
1339 .pm = &pxa2xx_spi_pm_ops,
1340 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1341 },
1342 .probe = pxa2xx_spi_probe,
1343 .remove = pxa2xx_spi_remove,
1344 .shutdown = pxa2xx_spi_shutdown,
1345 };
1346
1347 static int __init pxa2xx_spi_init(void)
1348 {
1349 return platform_driver_register(&driver);
1350 }
1351 subsys_initcall(pxa2xx_spi_init);
1352
1353 static void __exit pxa2xx_spi_exit(void)
1354 {
1355 platform_driver_unregister(&driver);
1356 }
1357 module_exit(pxa2xx_spi_exit);
Linux kernel - Deliverables
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