2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/ioport.h>
24 #include <linux/errno.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/spi/pxa2xx_spi.h>
29 #include <linux/spi/spi.h>
30 #include <linux/delay.h>
31 #include <linux/gpio.h>
32 #include <linux/slab.h>
33 #include <linux/clk.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/acpi.h>
39 #include <asm/delay.h>
41 #include "spi-pxa2xx.h"
43 MODULE_AUTHOR("Stephen Street");
44 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
45 MODULE_LICENSE("GPL");
46 MODULE_ALIAS("platform:pxa2xx-spi");
50 #define TIMOUT_DFLT 1000
53 * for testing SSCR1 changes that require SSP restart, basically
54 * everything except the service and interrupt enables, the pxa270 developer
55 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
56 * list, but the PXA255 dev man says all bits without really meaning the
57 * service and interrupt enables
59 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
60 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
61 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
62 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
63 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
64 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
66 #define LPSS_RX_THRESH_DFLT 64
67 #define LPSS_TX_LOTHRESH_DFLT 160
68 #define LPSS_TX_HITHRESH_DFLT 224
70 /* Offset from drv_data->lpss_base */
71 #define GENERAL_REG 0x08
72 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
74 #define SPI_CS_CONTROL 0x18
75 #define SPI_CS_CONTROL_SW_MODE BIT(0)
76 #define SPI_CS_CONTROL_CS_HIGH BIT(1)
78 static bool is_lpss_ssp(const struct driver_data
*drv_data
)
80 return drv_data
->ssp_type
== LPSS_SSP
;
84 * Read and write LPSS SSP private registers. Caller must first check that
85 * is_lpss_ssp() returns true before these can be called.
87 static u32
__lpss_ssp_read_priv(struct driver_data
*drv_data
, unsigned offset
)
89 WARN_ON(!drv_data
->lpss_base
);
90 return readl(drv_data
->lpss_base
+ offset
);
93 static void __lpss_ssp_write_priv(struct driver_data
*drv_data
,
94 unsigned offset
, u32 value
)
96 WARN_ON(!drv_data
->lpss_base
);
97 writel(value
, drv_data
->lpss_base
+ offset
);
101 * lpss_ssp_setup - perform LPSS SSP specific setup
102 * @drv_data: pointer to the driver private data
104 * Perform LPSS SSP specific setup. This function must be called first if
105 * one is going to use LPSS SSP private registers.
107 static void lpss_ssp_setup(struct driver_data
*drv_data
)
109 unsigned offset
= 0x400;
112 if (!is_lpss_ssp(drv_data
))
116 * Perform auto-detection of the LPSS SSP private registers. They
117 * can be either at 1k or 2k offset from the base address.
119 orig
= readl(drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
121 value
= orig
| SPI_CS_CONTROL_SW_MODE
;
122 writel(value
, drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
123 value
= readl(drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
124 if (value
!= (orig
| SPI_CS_CONTROL_SW_MODE
)) {
129 value
&= ~SPI_CS_CONTROL_SW_MODE
;
130 writel(value
, drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
131 value
= readl(drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
138 /* Now set the LPSS base */
139 drv_data
->lpss_base
= drv_data
->ioaddr
+ offset
;
141 /* Enable software chip select control */
142 value
= SPI_CS_CONTROL_SW_MODE
| SPI_CS_CONTROL_CS_HIGH
;
143 __lpss_ssp_write_priv(drv_data
, SPI_CS_CONTROL
, value
);
145 /* Enable multiblock DMA transfers */
146 if (drv_data
->master_info
->enable_dma
) {
147 __lpss_ssp_write_priv(drv_data
, SSP_REG
, 1);
149 value
= __lpss_ssp_read_priv(drv_data
, GENERAL_REG
);
150 value
|= GENERAL_REG_RXTO_HOLDOFF_DISABLE
;
151 __lpss_ssp_write_priv(drv_data
, GENERAL_REG
, value
);
155 static void lpss_ssp_cs_control(struct driver_data
*drv_data
, bool enable
)
159 if (!is_lpss_ssp(drv_data
))
162 value
= __lpss_ssp_read_priv(drv_data
, SPI_CS_CONTROL
);
164 value
&= ~SPI_CS_CONTROL_CS_HIGH
;
166 value
|= SPI_CS_CONTROL_CS_HIGH
;
167 __lpss_ssp_write_priv(drv_data
, SPI_CS_CONTROL
, value
);
170 static void cs_assert(struct driver_data
*drv_data
)
172 struct chip_data
*chip
= drv_data
->cur_chip
;
174 if (drv_data
->ssp_type
== CE4100_SSP
) {
175 write_SSSR(drv_data
->cur_chip
->frm
, drv_data
->ioaddr
);
179 if (chip
->cs_control
) {
180 chip
->cs_control(PXA2XX_CS_ASSERT
);
184 if (gpio_is_valid(chip
->gpio_cs
)) {
185 gpio_set_value(chip
->gpio_cs
, chip
->gpio_cs_inverted
);
189 lpss_ssp_cs_control(drv_data
, true);
192 static void cs_deassert(struct driver_data
*drv_data
)
194 struct chip_data
*chip
= drv_data
->cur_chip
;
196 if (drv_data
->ssp_type
== CE4100_SSP
)
199 if (chip
->cs_control
) {
200 chip
->cs_control(PXA2XX_CS_DEASSERT
);
204 if (gpio_is_valid(chip
->gpio_cs
)) {
205 gpio_set_value(chip
->gpio_cs
, !chip
->gpio_cs_inverted
);
209 lpss_ssp_cs_control(drv_data
, false);
212 int pxa2xx_spi_flush(struct driver_data
*drv_data
)
214 unsigned long limit
= loops_per_jiffy
<< 1;
216 void __iomem
*reg
= drv_data
->ioaddr
;
219 while (read_SSSR(reg
) & SSSR_RNE
) {
222 } while ((read_SSSR(reg
) & SSSR_BSY
) && --limit
);
223 write_SSSR_CS(drv_data
, SSSR_ROR
);
228 static int null_writer(struct driver_data
*drv_data
)
230 void __iomem
*reg
= drv_data
->ioaddr
;
231 u8 n_bytes
= drv_data
->n_bytes
;
233 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
234 || (drv_data
->tx
== drv_data
->tx_end
))
238 drv_data
->tx
+= n_bytes
;
243 static int null_reader(struct driver_data
*drv_data
)
245 void __iomem
*reg
= drv_data
->ioaddr
;
246 u8 n_bytes
= drv_data
->n_bytes
;
248 while ((read_SSSR(reg
) & SSSR_RNE
)
249 && (drv_data
->rx
< drv_data
->rx_end
)) {
251 drv_data
->rx
+= n_bytes
;
254 return drv_data
->rx
== drv_data
->rx_end
;
257 static int u8_writer(struct driver_data
*drv_data
)
259 void __iomem
*reg
= drv_data
->ioaddr
;
261 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
262 || (drv_data
->tx
== drv_data
->tx_end
))
265 write_SSDR(*(u8
*)(drv_data
->tx
), reg
);
271 static int u8_reader(struct driver_data
*drv_data
)
273 void __iomem
*reg
= drv_data
->ioaddr
;
275 while ((read_SSSR(reg
) & SSSR_RNE
)
276 && (drv_data
->rx
< drv_data
->rx_end
)) {
277 *(u8
*)(drv_data
->rx
) = read_SSDR(reg
);
281 return drv_data
->rx
== drv_data
->rx_end
;
284 static int u16_writer(struct driver_data
*drv_data
)
286 void __iomem
*reg
= drv_data
->ioaddr
;
288 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
289 || (drv_data
->tx
== drv_data
->tx_end
))
292 write_SSDR(*(u16
*)(drv_data
->tx
), reg
);
298 static int u16_reader(struct driver_data
*drv_data
)
300 void __iomem
*reg
= drv_data
->ioaddr
;
302 while ((read_SSSR(reg
) & SSSR_RNE
)
303 && (drv_data
->rx
< drv_data
->rx_end
)) {
304 *(u16
*)(drv_data
->rx
) = read_SSDR(reg
);
308 return drv_data
->rx
== drv_data
->rx_end
;
311 static int u32_writer(struct driver_data
*drv_data
)
313 void __iomem
*reg
= drv_data
->ioaddr
;
315 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
316 || (drv_data
->tx
== drv_data
->tx_end
))
319 write_SSDR(*(u32
*)(drv_data
->tx
), reg
);
325 static int u32_reader(struct driver_data
*drv_data
)
327 void __iomem
*reg
= drv_data
->ioaddr
;
329 while ((read_SSSR(reg
) & SSSR_RNE
)
330 && (drv_data
->rx
< drv_data
->rx_end
)) {
331 *(u32
*)(drv_data
->rx
) = read_SSDR(reg
);
335 return drv_data
->rx
== drv_data
->rx_end
;
338 void *pxa2xx_spi_next_transfer(struct driver_data
*drv_data
)
340 struct spi_message
*msg
= drv_data
->cur_msg
;
341 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
343 /* Move to next transfer */
344 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
345 drv_data
->cur_transfer
=
346 list_entry(trans
->transfer_list
.next
,
349 return RUNNING_STATE
;
354 /* caller already set message->status; dma and pio irqs are blocked */
355 static void giveback(struct driver_data
*drv_data
)
357 struct spi_transfer
* last_transfer
;
358 struct spi_message
*msg
;
360 msg
= drv_data
->cur_msg
;
361 drv_data
->cur_msg
= NULL
;
362 drv_data
->cur_transfer
= NULL
;
364 last_transfer
= list_last_entry(&msg
->transfers
, struct spi_transfer
,
367 /* Delay if requested before any change in chip select */
368 if (last_transfer
->delay_usecs
)
369 udelay(last_transfer
->delay_usecs
);
371 /* Drop chip select UNLESS cs_change is true or we are returning
372 * a message with an error, or next message is for another chip
374 if (!last_transfer
->cs_change
)
375 cs_deassert(drv_data
);
377 struct spi_message
*next_msg
;
379 /* Holding of cs was hinted, but we need to make sure
380 * the next message is for the same chip. Don't waste
381 * time with the following tests unless this was hinted.
383 * We cannot postpone this until pump_messages, because
384 * after calling msg->complete (below) the driver that
385 * sent the current message could be unloaded, which
386 * could invalidate the cs_control() callback...
389 /* get a pointer to the next message, if any */
390 next_msg
= spi_get_next_queued_message(drv_data
->master
);
392 /* see if the next and current messages point
395 if (next_msg
&& next_msg
->spi
!= msg
->spi
)
397 if (!next_msg
|| msg
->state
== ERROR_STATE
)
398 cs_deassert(drv_data
);
401 spi_finalize_current_message(drv_data
->master
);
402 drv_data
->cur_chip
= NULL
;
405 static void reset_sccr1(struct driver_data
*drv_data
)
407 void __iomem
*reg
= drv_data
->ioaddr
;
408 struct chip_data
*chip
= drv_data
->cur_chip
;
411 sccr1_reg
= read_SSCR1(reg
) & ~drv_data
->int_cr1
;
412 sccr1_reg
&= ~SSCR1_RFT
;
413 sccr1_reg
|= chip
->threshold
;
414 write_SSCR1(sccr1_reg
, reg
);
417 static void int_error_stop(struct driver_data
*drv_data
, const char* msg
)
419 void __iomem
*reg
= drv_data
->ioaddr
;
421 /* Stop and reset SSP */
422 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
423 reset_sccr1(drv_data
);
424 if (!pxa25x_ssp_comp(drv_data
))
426 pxa2xx_spi_flush(drv_data
);
427 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
429 dev_err(&drv_data
->pdev
->dev
, "%s\n", msg
);
431 drv_data
->cur_msg
->state
= ERROR_STATE
;
432 tasklet_schedule(&drv_data
->pump_transfers
);
435 static void int_transfer_complete(struct driver_data
*drv_data
)
437 void __iomem
*reg
= drv_data
->ioaddr
;
440 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
441 reset_sccr1(drv_data
);
442 if (!pxa25x_ssp_comp(drv_data
))
445 /* Update total byte transferred return count actual bytes read */
446 drv_data
->cur_msg
->actual_length
+= drv_data
->len
-
447 (drv_data
->rx_end
- drv_data
->rx
);
449 /* Transfer delays and chip select release are
450 * handled in pump_transfers or giveback
453 /* Move to next transfer */
454 drv_data
->cur_msg
->state
= pxa2xx_spi_next_transfer(drv_data
);
456 /* Schedule transfer tasklet */
457 tasklet_schedule(&drv_data
->pump_transfers
);
460 static irqreturn_t
interrupt_transfer(struct driver_data
*drv_data
)
462 void __iomem
*reg
= drv_data
->ioaddr
;
464 u32 irq_mask
= (read_SSCR1(reg
) & SSCR1_TIE
) ?
465 drv_data
->mask_sr
: drv_data
->mask_sr
& ~SSSR_TFS
;
467 u32 irq_status
= read_SSSR(reg
) & irq_mask
;
469 if (irq_status
& SSSR_ROR
) {
470 int_error_stop(drv_data
, "interrupt_transfer: fifo overrun");
474 if (irq_status
& SSSR_TINT
) {
475 write_SSSR(SSSR_TINT
, reg
);
476 if (drv_data
->read(drv_data
)) {
477 int_transfer_complete(drv_data
);
482 /* Drain rx fifo, Fill tx fifo and prevent overruns */
484 if (drv_data
->read(drv_data
)) {
485 int_transfer_complete(drv_data
);
488 } while (drv_data
->write(drv_data
));
490 if (drv_data
->read(drv_data
)) {
491 int_transfer_complete(drv_data
);
495 if (drv_data
->tx
== drv_data
->tx_end
) {
499 sccr1_reg
= read_SSCR1(reg
);
500 sccr1_reg
&= ~SSCR1_TIE
;
503 * PXA25x_SSP has no timeout, set up rx threshould for the
504 * remaining RX bytes.
506 if (pxa25x_ssp_comp(drv_data
)) {
508 sccr1_reg
&= ~SSCR1_RFT
;
510 bytes_left
= drv_data
->rx_end
- drv_data
->rx
;
511 switch (drv_data
->n_bytes
) {
518 if (bytes_left
> RX_THRESH_DFLT
)
519 bytes_left
= RX_THRESH_DFLT
;
521 sccr1_reg
|= SSCR1_RxTresh(bytes_left
);
523 write_SSCR1(sccr1_reg
, reg
);
526 /* We did something */
530 static irqreturn_t
ssp_int(int irq
, void *dev_id
)
532 struct driver_data
*drv_data
= dev_id
;
533 void __iomem
*reg
= drv_data
->ioaddr
;
535 u32 mask
= drv_data
->mask_sr
;
539 * The IRQ might be shared with other peripherals so we must first
540 * check that are we RPM suspended or not. If we are we assume that
541 * the IRQ was not for us (we shouldn't be RPM suspended when the
542 * interrupt is enabled).
544 if (pm_runtime_suspended(&drv_data
->pdev
->dev
))
548 * If the device is not yet in RPM suspended state and we get an
549 * interrupt that is meant for another device, check if status bits
550 * are all set to one. That means that the device is already
553 status
= read_SSSR(reg
);
557 sccr1_reg
= read_SSCR1(reg
);
559 /* Ignore possible writes if we don't need to write */
560 if (!(sccr1_reg
& SSCR1_TIE
))
563 if (!(status
& mask
))
566 if (!drv_data
->cur_msg
) {
568 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
569 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
570 if (!pxa25x_ssp_comp(drv_data
))
572 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
574 dev_err(&drv_data
->pdev
->dev
,
575 "bad message state in interrupt handler\n");
581 return drv_data
->transfer_handler(drv_data
);
584 static unsigned int ssp_get_clk_div(struct driver_data
*drv_data
, int rate
)
586 unsigned long ssp_clk
= drv_data
->max_clk_rate
;
587 const struct ssp_device
*ssp
= drv_data
->ssp
;
589 rate
= min_t(int, ssp_clk
, rate
);
591 if (ssp
->type
== PXA25x_SSP
|| ssp
->type
== CE4100_SSP
)
592 return ((ssp_clk
/ (2 * rate
) - 1) & 0xff) << 8;
594 return ((ssp_clk
/ rate
- 1) & 0xfff) << 8;
597 static void pump_transfers(unsigned long data
)
599 struct driver_data
*drv_data
= (struct driver_data
*)data
;
600 struct spi_message
*message
= NULL
;
601 struct spi_transfer
*transfer
= NULL
;
602 struct spi_transfer
*previous
= NULL
;
603 struct chip_data
*chip
= NULL
;
604 void __iomem
*reg
= drv_data
->ioaddr
;
610 u32 dma_thresh
= drv_data
->cur_chip
->dma_threshold
;
611 u32 dma_burst
= drv_data
->cur_chip
->dma_burst_size
;
613 /* Get current state information */
614 message
= drv_data
->cur_msg
;
615 transfer
= drv_data
->cur_transfer
;
616 chip
= drv_data
->cur_chip
;
618 /* Handle for abort */
619 if (message
->state
== ERROR_STATE
) {
620 message
->status
= -EIO
;
625 /* Handle end of message */
626 if (message
->state
== DONE_STATE
) {
632 /* Delay if requested at end of transfer before CS change */
633 if (message
->state
== RUNNING_STATE
) {
634 previous
= list_entry(transfer
->transfer_list
.prev
,
637 if (previous
->delay_usecs
)
638 udelay(previous
->delay_usecs
);
640 /* Drop chip select only if cs_change is requested */
641 if (previous
->cs_change
)
642 cs_deassert(drv_data
);
645 /* Check if we can DMA this transfer */
646 if (!pxa2xx_spi_dma_is_possible(transfer
->len
) && chip
->enable_dma
) {
648 /* reject already-mapped transfers; PIO won't always work */
649 if (message
->is_dma_mapped
650 || transfer
->rx_dma
|| transfer
->tx_dma
) {
651 dev_err(&drv_data
->pdev
->dev
,
652 "pump_transfers: mapped transfer length of "
653 "%u is greater than %d\n",
654 transfer
->len
, MAX_DMA_LEN
);
655 message
->status
= -EINVAL
;
660 /* warn ... we force this to PIO mode */
661 dev_warn_ratelimited(&message
->spi
->dev
,
662 "pump_transfers: DMA disabled for transfer length %ld "
664 (long)drv_data
->len
, MAX_DMA_LEN
);
667 /* Setup the transfer state based on the type of transfer */
668 if (pxa2xx_spi_flush(drv_data
) == 0) {
669 dev_err(&drv_data
->pdev
->dev
, "pump_transfers: flush failed\n");
670 message
->status
= -EIO
;
674 drv_data
->n_bytes
= chip
->n_bytes
;
675 drv_data
->tx
= (void *)transfer
->tx_buf
;
676 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
677 drv_data
->rx
= transfer
->rx_buf
;
678 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
679 drv_data
->rx_dma
= transfer
->rx_dma
;
680 drv_data
->tx_dma
= transfer
->tx_dma
;
681 drv_data
->len
= transfer
->len
;
682 drv_data
->write
= drv_data
->tx
? chip
->write
: null_writer
;
683 drv_data
->read
= drv_data
->rx
? chip
->read
: null_reader
;
685 /* Change speed and bit per word on a per transfer */
687 if (transfer
->speed_hz
|| transfer
->bits_per_word
) {
689 bits
= chip
->bits_per_word
;
690 speed
= chip
->speed_hz
;
692 if (transfer
->speed_hz
)
693 speed
= transfer
->speed_hz
;
695 if (transfer
->bits_per_word
)
696 bits
= transfer
->bits_per_word
;
698 clk_div
= ssp_get_clk_div(drv_data
, speed
);
701 drv_data
->n_bytes
= 1;
702 drv_data
->read
= drv_data
->read
!= null_reader
?
703 u8_reader
: null_reader
;
704 drv_data
->write
= drv_data
->write
!= null_writer
?
705 u8_writer
: null_writer
;
706 } else if (bits
<= 16) {
707 drv_data
->n_bytes
= 2;
708 drv_data
->read
= drv_data
->read
!= null_reader
?
709 u16_reader
: null_reader
;
710 drv_data
->write
= drv_data
->write
!= null_writer
?
711 u16_writer
: null_writer
;
712 } else if (bits
<= 32) {
713 drv_data
->n_bytes
= 4;
714 drv_data
->read
= drv_data
->read
!= null_reader
?
715 u32_reader
: null_reader
;
716 drv_data
->write
= drv_data
->write
!= null_writer
?
717 u32_writer
: null_writer
;
719 /* if bits/word is changed in dma mode, then must check the
720 * thresholds and burst also */
721 if (chip
->enable_dma
) {
722 if (pxa2xx_spi_set_dma_burst_and_threshold(chip
,
726 dev_warn_ratelimited(&message
->spi
->dev
,
727 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
732 | SSCR0_DataSize(bits
> 16 ? bits
- 16 : bits
)
734 | (bits
> 16 ? SSCR0_EDSS
: 0);
737 message
->state
= RUNNING_STATE
;
739 drv_data
->dma_mapped
= 0;
740 if (pxa2xx_spi_dma_is_possible(drv_data
->len
))
741 drv_data
->dma_mapped
= pxa2xx_spi_map_dma_buffers(drv_data
);
742 if (drv_data
->dma_mapped
) {
744 /* Ensure we have the correct interrupt handler */
745 drv_data
->transfer_handler
= pxa2xx_spi_dma_transfer
;
747 pxa2xx_spi_dma_prepare(drv_data
, dma_burst
);
749 /* Clear status and start DMA engine */
750 cr1
= chip
->cr1
| dma_thresh
| drv_data
->dma_cr1
;
751 write_SSSR(drv_data
->clear_sr
, reg
);
753 pxa2xx_spi_dma_start(drv_data
);
755 /* Ensure we have the correct interrupt handler */
756 drv_data
->transfer_handler
= interrupt_transfer
;
759 cr1
= chip
->cr1
| chip
->threshold
| drv_data
->int_cr1
;
760 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
763 if (is_lpss_ssp(drv_data
)) {
764 if ((read_SSIRF(reg
) & 0xff) != chip
->lpss_rx_threshold
)
765 write_SSIRF(chip
->lpss_rx_threshold
, reg
);
766 if ((read_SSITF(reg
) & 0xffff) != chip
->lpss_tx_threshold
)
767 write_SSITF(chip
->lpss_tx_threshold
, reg
);
770 /* see if we need to reload the config registers */
771 if ((read_SSCR0(reg
) != cr0
)
772 || (read_SSCR1(reg
) & SSCR1_CHANGE_MASK
) !=
773 (cr1
& SSCR1_CHANGE_MASK
)) {
775 /* stop the SSP, and update the other bits */
776 write_SSCR0(cr0
& ~SSCR0_SSE
, reg
);
777 if (!pxa25x_ssp_comp(drv_data
))
778 write_SSTO(chip
->timeout
, reg
);
779 /* first set CR1 without interrupt and service enables */
780 write_SSCR1(cr1
& SSCR1_CHANGE_MASK
, reg
);
781 /* restart the SSP */
782 write_SSCR0(cr0
, reg
);
785 if (!pxa25x_ssp_comp(drv_data
))
786 write_SSTO(chip
->timeout
, reg
);
791 /* after chip select, release the data by enabling service
792 * requests and interrupts, without changing any mode bits */
793 write_SSCR1(cr1
, reg
);
796 static int pxa2xx_spi_transfer_one_message(struct spi_master
*master
,
797 struct spi_message
*msg
)
799 struct driver_data
*drv_data
= spi_master_get_devdata(master
);
801 drv_data
->cur_msg
= msg
;
802 /* Initial message state*/
803 drv_data
->cur_msg
->state
= START_STATE
;
804 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
808 /* prepare to setup the SSP, in pump_transfers, using the per
809 * chip configuration */
810 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
812 /* Mark as busy and launch transfers */
813 tasklet_schedule(&drv_data
->pump_transfers
);
817 static int pxa2xx_spi_unprepare_transfer(struct spi_master
*master
)
819 struct driver_data
*drv_data
= spi_master_get_devdata(master
);
821 /* Disable the SSP now */
822 write_SSCR0(read_SSCR0(drv_data
->ioaddr
) & ~SSCR0_SSE
,
828 static int setup_cs(struct spi_device
*spi
, struct chip_data
*chip
,
829 struct pxa2xx_spi_chip
*chip_info
)
833 if (chip
== NULL
|| chip_info
== NULL
)
836 /* NOTE: setup() can be called multiple times, possibly with
837 * different chip_info, release previously requested GPIO
839 if (gpio_is_valid(chip
->gpio_cs
))
840 gpio_free(chip
->gpio_cs
);
842 /* If (*cs_control) is provided, ignore GPIO chip select */
843 if (chip_info
->cs_control
) {
844 chip
->cs_control
= chip_info
->cs_control
;
848 if (gpio_is_valid(chip_info
->gpio_cs
)) {
849 err
= gpio_request(chip_info
->gpio_cs
, "SPI_CS");
851 dev_err(&spi
->dev
, "failed to request chip select GPIO%d\n",
856 chip
->gpio_cs
= chip_info
->gpio_cs
;
857 chip
->gpio_cs_inverted
= spi
->mode
& SPI_CS_HIGH
;
859 err
= gpio_direction_output(chip
->gpio_cs
,
860 !chip
->gpio_cs_inverted
);
866 static int setup(struct spi_device
*spi
)
868 struct pxa2xx_spi_chip
*chip_info
= NULL
;
869 struct chip_data
*chip
;
870 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
871 unsigned int clk_div
;
872 uint tx_thres
, tx_hi_thres
, rx_thres
;
874 if (is_lpss_ssp(drv_data
)) {
875 tx_thres
= LPSS_TX_LOTHRESH_DFLT
;
876 tx_hi_thres
= LPSS_TX_HITHRESH_DFLT
;
877 rx_thres
= LPSS_RX_THRESH_DFLT
;
879 tx_thres
= TX_THRESH_DFLT
;
881 rx_thres
= RX_THRESH_DFLT
;
884 /* Only alloc on first setup */
885 chip
= spi_get_ctldata(spi
);
887 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
891 if (drv_data
->ssp_type
== CE4100_SSP
) {
892 if (spi
->chip_select
> 4) {
894 "failed setup: cs number must not be > 4.\n");
899 chip
->frm
= spi
->chip_select
;
902 chip
->enable_dma
= 0;
903 chip
->timeout
= TIMOUT_DFLT
;
906 /* protocol drivers may change the chip settings, so...
907 * if chip_info exists, use it */
908 chip_info
= spi
->controller_data
;
910 /* chip_info isn't always needed */
913 if (chip_info
->timeout
)
914 chip
->timeout
= chip_info
->timeout
;
915 if (chip_info
->tx_threshold
)
916 tx_thres
= chip_info
->tx_threshold
;
917 if (chip_info
->tx_hi_threshold
)
918 tx_hi_thres
= chip_info
->tx_hi_threshold
;
919 if (chip_info
->rx_threshold
)
920 rx_thres
= chip_info
->rx_threshold
;
921 chip
->enable_dma
= drv_data
->master_info
->enable_dma
;
922 chip
->dma_threshold
= 0;
923 if (chip_info
->enable_loopback
)
924 chip
->cr1
= SSCR1_LBM
;
925 } else if (ACPI_HANDLE(&spi
->dev
)) {
927 * Slave devices enumerated from ACPI namespace don't
928 * usually have chip_info but we still might want to use
931 chip
->enable_dma
= drv_data
->master_info
->enable_dma
;
934 chip
->threshold
= (SSCR1_RxTresh(rx_thres
) & SSCR1_RFT
) |
935 (SSCR1_TxTresh(tx_thres
) & SSCR1_TFT
);
937 chip
->lpss_rx_threshold
= SSIRF_RxThresh(rx_thres
);
938 chip
->lpss_tx_threshold
= SSITF_TxLoThresh(tx_thres
)
939 | SSITF_TxHiThresh(tx_hi_thres
);
941 /* set dma burst and threshold outside of chip_info path so that if
942 * chip_info goes away after setting chip->enable_dma, the
943 * burst and threshold can still respond to changes in bits_per_word */
944 if (chip
->enable_dma
) {
945 /* set up legal burst and threshold for dma */
946 if (pxa2xx_spi_set_dma_burst_and_threshold(chip
, spi
,
948 &chip
->dma_burst_size
,
949 &chip
->dma_threshold
)) {
951 "in setup: DMA burst size reduced to match bits_per_word\n");
955 clk_div
= ssp_get_clk_div(drv_data
, spi
->max_speed_hz
);
956 chip
->speed_hz
= spi
->max_speed_hz
;
960 | SSCR0_DataSize(spi
->bits_per_word
> 16 ?
961 spi
->bits_per_word
- 16 : spi
->bits_per_word
)
963 | (spi
->bits_per_word
> 16 ? SSCR0_EDSS
: 0);
964 chip
->cr1
&= ~(SSCR1_SPO
| SSCR1_SPH
);
965 chip
->cr1
|= (((spi
->mode
& SPI_CPHA
) != 0) ? SSCR1_SPH
: 0)
966 | (((spi
->mode
& SPI_CPOL
) != 0) ? SSCR1_SPO
: 0);
968 if (spi
->mode
& SPI_LOOP
)
969 chip
->cr1
|= SSCR1_LBM
;
971 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
972 if (!pxa25x_ssp_comp(drv_data
))
973 dev_dbg(&spi
->dev
, "%ld Hz actual, %s\n",
974 drv_data
->max_clk_rate
975 / (1 + ((chip
->cr0
& SSCR0_SCR(0xfff)) >> 8)),
976 chip
->enable_dma
? "DMA" : "PIO");
978 dev_dbg(&spi
->dev
, "%ld Hz actual, %s\n",
979 drv_data
->max_clk_rate
/ 2
980 / (1 + ((chip
->cr0
& SSCR0_SCR(0x0ff)) >> 8)),
981 chip
->enable_dma
? "DMA" : "PIO");
983 if (spi
->bits_per_word
<= 8) {
985 chip
->read
= u8_reader
;
986 chip
->write
= u8_writer
;
987 } else if (spi
->bits_per_word
<= 16) {
989 chip
->read
= u16_reader
;
990 chip
->write
= u16_writer
;
991 } else if (spi
->bits_per_word
<= 32) {
992 chip
->cr0
|= SSCR0_EDSS
;
994 chip
->read
= u32_reader
;
995 chip
->write
= u32_writer
;
997 chip
->bits_per_word
= spi
->bits_per_word
;
999 spi_set_ctldata(spi
, chip
);
1001 if (drv_data
->ssp_type
== CE4100_SSP
)
1004 return setup_cs(spi
, chip
, chip_info
);
1007 static void cleanup(struct spi_device
*spi
)
1009 struct chip_data
*chip
= spi_get_ctldata(spi
);
1010 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
1015 if (drv_data
->ssp_type
!= CE4100_SSP
&& gpio_is_valid(chip
->gpio_cs
))
1016 gpio_free(chip
->gpio_cs
);
1022 static struct pxa2xx_spi_master
*
1023 pxa2xx_spi_acpi_get_pdata(struct platform_device
*pdev
)
1025 struct pxa2xx_spi_master
*pdata
;
1026 struct acpi_device
*adev
;
1027 struct ssp_device
*ssp
;
1028 struct resource
*res
;
1031 if (!ACPI_HANDLE(&pdev
->dev
) ||
1032 acpi_bus_get_device(ACPI_HANDLE(&pdev
->dev
), &adev
))
1035 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
1039 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1045 ssp
->phys_base
= res
->start
;
1046 ssp
->mmio_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1047 if (IS_ERR(ssp
->mmio_base
))
1050 ssp
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1051 ssp
->irq
= platform_get_irq(pdev
, 0);
1052 ssp
->type
= LPSS_SSP
;
1056 if (adev
->pnp
.unique_id
&& !kstrtoint(adev
->pnp
.unique_id
, 0, &devid
))
1057 ssp
->port_id
= devid
;
1059 pdata
->num_chipselect
= 1;
1060 pdata
->enable_dma
= true;
1061 pdata
->tx_chan_id
= -1;
1062 pdata
->rx_chan_id
= -1;
1067 static struct acpi_device_id pxa2xx_spi_acpi_match
[] = {
1075 MODULE_DEVICE_TABLE(acpi
, pxa2xx_spi_acpi_match
);
1077 static inline struct pxa2xx_spi_master
*
1078 pxa2xx_spi_acpi_get_pdata(struct platform_device
*pdev
)
1084 static int pxa2xx_spi_probe(struct platform_device
*pdev
)
1086 struct device
*dev
= &pdev
->dev
;
1087 struct pxa2xx_spi_master
*platform_info
;
1088 struct spi_master
*master
;
1089 struct driver_data
*drv_data
;
1090 struct ssp_device
*ssp
;
1093 platform_info
= dev_get_platdata(dev
);
1094 if (!platform_info
) {
1095 platform_info
= pxa2xx_spi_acpi_get_pdata(pdev
);
1096 if (!platform_info
) {
1097 dev_err(&pdev
->dev
, "missing platform data\n");
1102 ssp
= pxa_ssp_request(pdev
->id
, pdev
->name
);
1104 ssp
= &platform_info
->ssp
;
1106 if (!ssp
->mmio_base
) {
1107 dev_err(&pdev
->dev
, "failed to get ssp\n");
1111 /* Allocate master with space for drv_data and null dma buffer */
1112 master
= spi_alloc_master(dev
, sizeof(struct driver_data
) + 16);
1114 dev_err(&pdev
->dev
, "cannot alloc spi_master\n");
1118 drv_data
= spi_master_get_devdata(master
);
1119 drv_data
->master
= master
;
1120 drv_data
->master_info
= platform_info
;
1121 drv_data
->pdev
= pdev
;
1122 drv_data
->ssp
= ssp
;
1124 master
->dev
.parent
= &pdev
->dev
;
1125 master
->dev
.of_node
= pdev
->dev
.of_node
;
1126 /* the spi->mode bits understood by this driver: */
1127 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
| SPI_LOOP
;
1129 master
->bus_num
= ssp
->port_id
;
1130 master
->num_chipselect
= platform_info
->num_chipselect
;
1131 master
->dma_alignment
= DMA_ALIGNMENT
;
1132 master
->cleanup
= cleanup
;
1133 master
->setup
= setup
;
1134 master
->transfer_one_message
= pxa2xx_spi_transfer_one_message
;
1135 master
->unprepare_transfer_hardware
= pxa2xx_spi_unprepare_transfer
;
1136 master
->auto_runtime_pm
= true;
1138 drv_data
->ssp_type
= ssp
->type
;
1139 drv_data
->null_dma_buf
= (u32
*)PTR_ALIGN(&drv_data
[1], DMA_ALIGNMENT
);
1141 drv_data
->ioaddr
= ssp
->mmio_base
;
1142 drv_data
->ssdr_physical
= ssp
->phys_base
+ SSDR
;
1143 if (pxa25x_ssp_comp(drv_data
)) {
1144 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(4, 16);
1145 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
;
1146 drv_data
->dma_cr1
= 0;
1147 drv_data
->clear_sr
= SSSR_ROR
;
1148 drv_data
->mask_sr
= SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1150 master
->bits_per_word_mask
= SPI_BPW_RANGE_MASK(4, 32);
1151 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
| SSCR1_TINTE
;
1152 drv_data
->dma_cr1
= DEFAULT_DMA_CR1
;
1153 drv_data
->clear_sr
= SSSR_ROR
| SSSR_TINT
;
1154 drv_data
->mask_sr
= SSSR_TINT
| SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1157 status
= request_irq(ssp
->irq
, ssp_int
, IRQF_SHARED
, dev_name(dev
),
1160 dev_err(&pdev
->dev
, "cannot get IRQ %d\n", ssp
->irq
);
1161 goto out_error_master_alloc
;
1164 /* Setup DMA if requested */
1165 drv_data
->tx_channel
= -1;
1166 drv_data
->rx_channel
= -1;
1167 if (platform_info
->enable_dma
) {
1168 status
= pxa2xx_spi_dma_setup(drv_data
);
1170 dev_dbg(dev
, "no DMA channels available, using PIO\n");
1171 platform_info
->enable_dma
= false;
1175 /* Enable SOC clock */
1176 clk_prepare_enable(ssp
->clk
);
1178 drv_data
->max_clk_rate
= clk_get_rate(ssp
->clk
);
1180 /* Load default SSP configuration */
1181 write_SSCR0(0, drv_data
->ioaddr
);
1182 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT
) |
1183 SSCR1_TxTresh(TX_THRESH_DFLT
),
1185 write_SSCR0(SSCR0_SCR(2)
1187 | SSCR0_DataSize(8),
1189 if (!pxa25x_ssp_comp(drv_data
))
1190 write_SSTO(0, drv_data
->ioaddr
);
1191 write_SSPSP(0, drv_data
->ioaddr
);
1193 lpss_ssp_setup(drv_data
);
1195 tasklet_init(&drv_data
->pump_transfers
, pump_transfers
,
1196 (unsigned long)drv_data
);
1198 pm_runtime_set_autosuspend_delay(&pdev
->dev
, 50);
1199 pm_runtime_use_autosuspend(&pdev
->dev
);
1200 pm_runtime_set_active(&pdev
->dev
);
1201 pm_runtime_enable(&pdev
->dev
);
1203 /* Register with the SPI framework */
1204 platform_set_drvdata(pdev
, drv_data
);
1205 status
= devm_spi_register_master(&pdev
->dev
, master
);
1207 dev_err(&pdev
->dev
, "problem registering spi master\n");
1208 goto out_error_clock_enabled
;
1213 out_error_clock_enabled
:
1214 clk_disable_unprepare(ssp
->clk
);
1215 pxa2xx_spi_dma_release(drv_data
);
1216 free_irq(ssp
->irq
, drv_data
);
1218 out_error_master_alloc
:
1219 spi_master_put(master
);
1224 static int pxa2xx_spi_remove(struct platform_device
*pdev
)
1226 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1227 struct ssp_device
*ssp
;
1231 ssp
= drv_data
->ssp
;
1233 pm_runtime_get_sync(&pdev
->dev
);
1235 /* Disable the SSP at the peripheral and SOC level */
1236 write_SSCR0(0, drv_data
->ioaddr
);
1237 clk_disable_unprepare(ssp
->clk
);
1240 if (drv_data
->master_info
->enable_dma
)
1241 pxa2xx_spi_dma_release(drv_data
);
1243 pm_runtime_put_noidle(&pdev
->dev
);
1244 pm_runtime_disable(&pdev
->dev
);
1247 free_irq(ssp
->irq
, drv_data
);
1255 static void pxa2xx_spi_shutdown(struct platform_device
*pdev
)
1259 if ((status
= pxa2xx_spi_remove(pdev
)) != 0)
1260 dev_err(&pdev
->dev
, "shutdown failed with %d\n", status
);
1263 #ifdef CONFIG_PM_SLEEP
1264 static int pxa2xx_spi_suspend(struct device
*dev
)
1266 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1267 struct ssp_device
*ssp
= drv_data
->ssp
;
1270 status
= spi_master_suspend(drv_data
->master
);
1273 write_SSCR0(0, drv_data
->ioaddr
);
1274 clk_disable_unprepare(ssp
->clk
);
1279 static int pxa2xx_spi_resume(struct device
*dev
)
1281 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1282 struct ssp_device
*ssp
= drv_data
->ssp
;
1285 pxa2xx_spi_dma_resume(drv_data
);
1287 /* Enable the SSP clock */
1288 clk_prepare_enable(ssp
->clk
);
1290 /* Restore LPSS private register bits */
1291 lpss_ssp_setup(drv_data
);
1293 /* Start the queue running */
1294 status
= spi_master_resume(drv_data
->master
);
1296 dev_err(dev
, "problem starting queue (%d)\n", status
);
1304 #ifdef CONFIG_PM_RUNTIME
1305 static int pxa2xx_spi_runtime_suspend(struct device
*dev
)
1307 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1309 clk_disable_unprepare(drv_data
->ssp
->clk
);
1313 static int pxa2xx_spi_runtime_resume(struct device
*dev
)
1315 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1317 clk_prepare_enable(drv_data
->ssp
->clk
);
1322 static const struct dev_pm_ops pxa2xx_spi_pm_ops
= {
1323 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend
, pxa2xx_spi_resume
)
1324 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend
,
1325 pxa2xx_spi_runtime_resume
, NULL
)
1328 static struct platform_driver driver
= {
1330 .name
= "pxa2xx-spi",
1331 .owner
= THIS_MODULE
,
1332 .pm
= &pxa2xx_spi_pm_ops
,
1333 .acpi_match_table
= ACPI_PTR(pxa2xx_spi_acpi_match
),
1335 .probe
= pxa2xx_spi_probe
,
1336 .remove
= pxa2xx_spi_remove
,
1337 .shutdown
= pxa2xx_spi_shutdown
,
1340 static int __init
pxa2xx_spi_init(void)
1342 return platform_driver_register(&driver
);
1344 subsys_initcall(pxa2xx_spi_init
);
1346 static void __exit
pxa2xx_spi_exit(void)
1348 platform_driver_unregister(&driver
);
1350 module_exit(pxa2xx_spi_exit
);