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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rkuo/linux...
[deliverable/linux.git] / drivers / spi / spi-pxa2xx.c
1 /*
2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/device.h>
19 #include <linux/ioport.h>
20 #include <linux/errno.h>
21 #include <linux/err.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/spi/pxa2xx_spi.h>
27 #include <linux/spi/spi.h>
28 #include <linux/delay.h>
29 #include <linux/gpio.h>
30 #include <linux/slab.h>
31 #include <linux/clk.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/acpi.h>
34
35 #include "spi-pxa2xx.h"
36
37 MODULE_AUTHOR("Stephen Street");
38 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
39 MODULE_LICENSE("GPL");
40 MODULE_ALIAS("platform:pxa2xx-spi");
41
42 #define TIMOUT_DFLT 1000
43
44 /*
45 * for testing SSCR1 changes that require SSP restart, basically
46 * everything except the service and interrupt enables, the pxa270 developer
47 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
48 * list, but the PXA255 dev man says all bits without really meaning the
49 * service and interrupt enables
50 */
51 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
52 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
53 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
54 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
55 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
56 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
57
58 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
59 | QUARK_X1000_SSCR1_EFWR \
60 | QUARK_X1000_SSCR1_RFT \
61 | QUARK_X1000_SSCR1_TFT \
62 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
63
64 #define GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
65 #define SPI_CS_CONTROL_SW_MODE BIT(0)
66 #define SPI_CS_CONTROL_CS_HIGH BIT(1)
67
68 struct lpss_config {
69 /* LPSS offset from drv_data->ioaddr */
70 unsigned offset;
71 /* Register offsets from drv_data->lpss_base or -1 */
72 int reg_general;
73 int reg_ssp;
74 int reg_cs_ctrl;
75 /* FIFO thresholds */
76 u32 rx_threshold;
77 u32 tx_threshold_lo;
78 u32 tx_threshold_hi;
79 };
80
81 /* Keep these sorted with enum pxa_ssp_type */
82 static const struct lpss_config lpss_platforms[] = {
83 { /* LPSS_LPT_SSP */
84 .offset = 0x800,
85 .reg_general = 0x08,
86 .reg_ssp = 0x0c,
87 .reg_cs_ctrl = 0x18,
88 .rx_threshold = 64,
89 .tx_threshold_lo = 160,
90 .tx_threshold_hi = 224,
91 },
92 { /* LPSS_BYT_SSP */
93 .offset = 0x400,
94 .reg_general = 0x08,
95 .reg_ssp = 0x0c,
96 .reg_cs_ctrl = 0x18,
97 .rx_threshold = 64,
98 .tx_threshold_lo = 160,
99 .tx_threshold_hi = 224,
100 },
101 { /* LPSS_SPT_SSP */
102 .offset = 0x200,
103 .reg_general = -1,
104 .reg_ssp = 0x20,
105 .reg_cs_ctrl = 0x24,
106 .rx_threshold = 1,
107 .tx_threshold_lo = 32,
108 .tx_threshold_hi = 56,
109 },
110 };
111
112 static inline const struct lpss_config
113 *lpss_get_config(const struct driver_data *drv_data)
114 {
115 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
116 }
117
118 static bool is_lpss_ssp(const struct driver_data *drv_data)
119 {
120 switch (drv_data->ssp_type) {
121 case LPSS_LPT_SSP:
122 case LPSS_BYT_SSP:
123 case LPSS_SPT_SSP:
124 return true;
125 default:
126 return false;
127 }
128 }
129
130 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
131 {
132 return drv_data->ssp_type == QUARK_X1000_SSP;
133 }
134
135 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
136 {
137 switch (drv_data->ssp_type) {
138 case QUARK_X1000_SSP:
139 return QUARK_X1000_SSCR1_CHANGE_MASK;
140 default:
141 return SSCR1_CHANGE_MASK;
142 }
143 }
144
145 static u32
146 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
147 {
148 switch (drv_data->ssp_type) {
149 case QUARK_X1000_SSP:
150 return RX_THRESH_QUARK_X1000_DFLT;
151 default:
152 return RX_THRESH_DFLT;
153 }
154 }
155
156 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
157 {
158 u32 mask;
159
160 switch (drv_data->ssp_type) {
161 case QUARK_X1000_SSP:
162 mask = QUARK_X1000_SSSR_TFL_MASK;
163 break;
164 default:
165 mask = SSSR_TFL_MASK;
166 break;
167 }
168
169 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
170 }
171
172 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
173 u32 *sccr1_reg)
174 {
175 u32 mask;
176
177 switch (drv_data->ssp_type) {
178 case QUARK_X1000_SSP:
179 mask = QUARK_X1000_SSCR1_RFT;
180 break;
181 default:
182 mask = SSCR1_RFT;
183 break;
184 }
185 *sccr1_reg &= ~mask;
186 }
187
188 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
189 u32 *sccr1_reg, u32 threshold)
190 {
191 switch (drv_data->ssp_type) {
192 case QUARK_X1000_SSP:
193 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
194 break;
195 default:
196 *sccr1_reg |= SSCR1_RxTresh(threshold);
197 break;
198 }
199 }
200
201 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
202 u32 clk_div, u8 bits)
203 {
204 switch (drv_data->ssp_type) {
205 case QUARK_X1000_SSP:
206 return clk_div
207 | QUARK_X1000_SSCR0_Motorola
208 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
209 | SSCR0_SSE;
210 default:
211 return clk_div
212 | SSCR0_Motorola
213 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
214 | SSCR0_SSE
215 | (bits > 16 ? SSCR0_EDSS : 0);
216 }
217 }
218
219 /*
220 * Read and write LPSS SSP private registers. Caller must first check that
221 * is_lpss_ssp() returns true before these can be called.
222 */
223 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
224 {
225 WARN_ON(!drv_data->lpss_base);
226 return readl(drv_data->lpss_base + offset);
227 }
228
229 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
230 unsigned offset, u32 value)
231 {
232 WARN_ON(!drv_data->lpss_base);
233 writel(value, drv_data->lpss_base + offset);
234 }
235
236 /*
237 * lpss_ssp_setup - perform LPSS SSP specific setup
238 * @drv_data: pointer to the driver private data
239 *
240 * Perform LPSS SSP specific setup. This function must be called first if
241 * one is going to use LPSS SSP private registers.
242 */
243 static void lpss_ssp_setup(struct driver_data *drv_data)
244 {
245 const struct lpss_config *config;
246 u32 value;
247
248 config = lpss_get_config(drv_data);
249 drv_data->lpss_base = drv_data->ioaddr + config->offset;
250
251 /* Enable software chip select control */
252 value = SPI_CS_CONTROL_SW_MODE | SPI_CS_CONTROL_CS_HIGH;
253 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
254
255 /* Enable multiblock DMA transfers */
256 if (drv_data->master_info->enable_dma) {
257 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
258
259 if (config->reg_general >= 0) {
260 value = __lpss_ssp_read_priv(drv_data,
261 config->reg_general);
262 value |= GENERAL_REG_RXTO_HOLDOFF_DISABLE;
263 __lpss_ssp_write_priv(drv_data,
264 config->reg_general, value);
265 }
266 }
267 }
268
269 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
270 {
271 const struct lpss_config *config;
272 u32 value;
273
274 config = lpss_get_config(drv_data);
275
276 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
277 if (enable)
278 value &= ~SPI_CS_CONTROL_CS_HIGH;
279 else
280 value |= SPI_CS_CONTROL_CS_HIGH;
281 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
282 }
283
284 static void cs_assert(struct driver_data *drv_data)
285 {
286 struct chip_data *chip = drv_data->cur_chip;
287
288 if (drv_data->ssp_type == CE4100_SSP) {
289 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
290 return;
291 }
292
293 if (chip->cs_control) {
294 chip->cs_control(PXA2XX_CS_ASSERT);
295 return;
296 }
297
298 if (gpio_is_valid(chip->gpio_cs)) {
299 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
300 return;
301 }
302
303 if (is_lpss_ssp(drv_data))
304 lpss_ssp_cs_control(drv_data, true);
305 }
306
307 static void cs_deassert(struct driver_data *drv_data)
308 {
309 struct chip_data *chip = drv_data->cur_chip;
310
311 if (drv_data->ssp_type == CE4100_SSP)
312 return;
313
314 if (chip->cs_control) {
315 chip->cs_control(PXA2XX_CS_DEASSERT);
316 return;
317 }
318
319 if (gpio_is_valid(chip->gpio_cs)) {
320 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
321 return;
322 }
323
324 if (is_lpss_ssp(drv_data))
325 lpss_ssp_cs_control(drv_data, false);
326 }
327
328 int pxa2xx_spi_flush(struct driver_data *drv_data)
329 {
330 unsigned long limit = loops_per_jiffy << 1;
331
332 do {
333 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
334 pxa2xx_spi_read(drv_data, SSDR);
335 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
336 write_SSSR_CS(drv_data, SSSR_ROR);
337
338 return limit;
339 }
340
341 static int null_writer(struct driver_data *drv_data)
342 {
343 u8 n_bytes = drv_data->n_bytes;
344
345 if (pxa2xx_spi_txfifo_full(drv_data)
346 || (drv_data->tx == drv_data->tx_end))
347 return 0;
348
349 pxa2xx_spi_write(drv_data, SSDR, 0);
350 drv_data->tx += n_bytes;
351
352 return 1;
353 }
354
355 static int null_reader(struct driver_data *drv_data)
356 {
357 u8 n_bytes = drv_data->n_bytes;
358
359 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
360 && (drv_data->rx < drv_data->rx_end)) {
361 pxa2xx_spi_read(drv_data, SSDR);
362 drv_data->rx += n_bytes;
363 }
364
365 return drv_data->rx == drv_data->rx_end;
366 }
367
368 static int u8_writer(struct driver_data *drv_data)
369 {
370 if (pxa2xx_spi_txfifo_full(drv_data)
371 || (drv_data->tx == drv_data->tx_end))
372 return 0;
373
374 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
375 ++drv_data->tx;
376
377 return 1;
378 }
379
380 static int u8_reader(struct driver_data *drv_data)
381 {
382 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
383 && (drv_data->rx < drv_data->rx_end)) {
384 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
385 ++drv_data->rx;
386 }
387
388 return drv_data->rx == drv_data->rx_end;
389 }
390
391 static int u16_writer(struct driver_data *drv_data)
392 {
393 if (pxa2xx_spi_txfifo_full(drv_data)
394 || (drv_data->tx == drv_data->tx_end))
395 return 0;
396
397 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
398 drv_data->tx += 2;
399
400 return 1;
401 }
402
403 static int u16_reader(struct driver_data *drv_data)
404 {
405 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
406 && (drv_data->rx < drv_data->rx_end)) {
407 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
408 drv_data->rx += 2;
409 }
410
411 return drv_data->rx == drv_data->rx_end;
412 }
413
414 static int u32_writer(struct driver_data *drv_data)
415 {
416 if (pxa2xx_spi_txfifo_full(drv_data)
417 || (drv_data->tx == drv_data->tx_end))
418 return 0;
419
420 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
421 drv_data->tx += 4;
422
423 return 1;
424 }
425
426 static int u32_reader(struct driver_data *drv_data)
427 {
428 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
429 && (drv_data->rx < drv_data->rx_end)) {
430 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
431 drv_data->rx += 4;
432 }
433
434 return drv_data->rx == drv_data->rx_end;
435 }
436
437 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
438 {
439 struct spi_message *msg = drv_data->cur_msg;
440 struct spi_transfer *trans = drv_data->cur_transfer;
441
442 /* Move to next transfer */
443 if (trans->transfer_list.next != &msg->transfers) {
444 drv_data->cur_transfer =
445 list_entry(trans->transfer_list.next,
446 struct spi_transfer,
447 transfer_list);
448 return RUNNING_STATE;
449 } else
450 return DONE_STATE;
451 }
452
453 /* caller already set message->status; dma and pio irqs are blocked */
454 static void giveback(struct driver_data *drv_data)
455 {
456 struct spi_transfer* last_transfer;
457 struct spi_message *msg;
458
459 msg = drv_data->cur_msg;
460 drv_data->cur_msg = NULL;
461 drv_data->cur_transfer = NULL;
462
463 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
464 transfer_list);
465
466 /* Delay if requested before any change in chip select */
467 if (last_transfer->delay_usecs)
468 udelay(last_transfer->delay_usecs);
469
470 /* Drop chip select UNLESS cs_change is true or we are returning
471 * a message with an error, or next message is for another chip
472 */
473 if (!last_transfer->cs_change)
474 cs_deassert(drv_data);
475 else {
476 struct spi_message *next_msg;
477
478 /* Holding of cs was hinted, but we need to make sure
479 * the next message is for the same chip. Don't waste
480 * time with the following tests unless this was hinted.
481 *
482 * We cannot postpone this until pump_messages, because
483 * after calling msg->complete (below) the driver that
484 * sent the current message could be unloaded, which
485 * could invalidate the cs_control() callback...
486 */
487
488 /* get a pointer to the next message, if any */
489 next_msg = spi_get_next_queued_message(drv_data->master);
490
491 /* see if the next and current messages point
492 * to the same chip
493 */
494 if (next_msg && next_msg->spi != msg->spi)
495 next_msg = NULL;
496 if (!next_msg || msg->state == ERROR_STATE)
497 cs_deassert(drv_data);
498 }
499
500 drv_data->cur_chip = NULL;
501 spi_finalize_current_message(drv_data->master);
502 }
503
504 static void reset_sccr1(struct driver_data *drv_data)
505 {
506 struct chip_data *chip = drv_data->cur_chip;
507 u32 sccr1_reg;
508
509 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
510 sccr1_reg &= ~SSCR1_RFT;
511 sccr1_reg |= chip->threshold;
512 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
513 }
514
515 static void int_error_stop(struct driver_data *drv_data, const char* msg)
516 {
517 /* Stop and reset SSP */
518 write_SSSR_CS(drv_data, drv_data->clear_sr);
519 reset_sccr1(drv_data);
520 if (!pxa25x_ssp_comp(drv_data))
521 pxa2xx_spi_write(drv_data, SSTO, 0);
522 pxa2xx_spi_flush(drv_data);
523 pxa2xx_spi_write(drv_data, SSCR0,
524 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
525
526 dev_err(&drv_data->pdev->dev, "%s\n", msg);
527
528 drv_data->cur_msg->state = ERROR_STATE;
529 tasklet_schedule(&drv_data->pump_transfers);
530 }
531
532 static void int_transfer_complete(struct driver_data *drv_data)
533 {
534 /* Stop SSP */
535 write_SSSR_CS(drv_data, drv_data->clear_sr);
536 reset_sccr1(drv_data);
537 if (!pxa25x_ssp_comp(drv_data))
538 pxa2xx_spi_write(drv_data, SSTO, 0);
539
540 /* Update total byte transferred return count actual bytes read */
541 drv_data->cur_msg->actual_length += drv_data->len -
542 (drv_data->rx_end - drv_data->rx);
543
544 /* Transfer delays and chip select release are
545 * handled in pump_transfers or giveback
546 */
547
548 /* Move to next transfer */
549 drv_data->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
550
551 /* Schedule transfer tasklet */
552 tasklet_schedule(&drv_data->pump_transfers);
553 }
554
555 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
556 {
557 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
558 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
559
560 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
561
562 if (irq_status & SSSR_ROR) {
563 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
564 return IRQ_HANDLED;
565 }
566
567 if (irq_status & SSSR_TINT) {
568 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
569 if (drv_data->read(drv_data)) {
570 int_transfer_complete(drv_data);
571 return IRQ_HANDLED;
572 }
573 }
574
575 /* Drain rx fifo, Fill tx fifo and prevent overruns */
576 do {
577 if (drv_data->read(drv_data)) {
578 int_transfer_complete(drv_data);
579 return IRQ_HANDLED;
580 }
581 } while (drv_data->write(drv_data));
582
583 if (drv_data->read(drv_data)) {
584 int_transfer_complete(drv_data);
585 return IRQ_HANDLED;
586 }
587
588 if (drv_data->tx == drv_data->tx_end) {
589 u32 bytes_left;
590 u32 sccr1_reg;
591
592 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
593 sccr1_reg &= ~SSCR1_TIE;
594
595 /*
596 * PXA25x_SSP has no timeout, set up rx threshould for the
597 * remaining RX bytes.
598 */
599 if (pxa25x_ssp_comp(drv_data)) {
600 u32 rx_thre;
601
602 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
603
604 bytes_left = drv_data->rx_end - drv_data->rx;
605 switch (drv_data->n_bytes) {
606 case 4:
607 bytes_left >>= 1;
608 case 2:
609 bytes_left >>= 1;
610 }
611
612 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
613 if (rx_thre > bytes_left)
614 rx_thre = bytes_left;
615
616 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
617 }
618 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
619 }
620
621 /* We did something */
622 return IRQ_HANDLED;
623 }
624
625 static irqreturn_t ssp_int(int irq, void *dev_id)
626 {
627 struct driver_data *drv_data = dev_id;
628 u32 sccr1_reg;
629 u32 mask = drv_data->mask_sr;
630 u32 status;
631
632 /*
633 * The IRQ might be shared with other peripherals so we must first
634 * check that are we RPM suspended or not. If we are we assume that
635 * the IRQ was not for us (we shouldn't be RPM suspended when the
636 * interrupt is enabled).
637 */
638 if (pm_runtime_suspended(&drv_data->pdev->dev))
639 return IRQ_NONE;
640
641 /*
642 * If the device is not yet in RPM suspended state and we get an
643 * interrupt that is meant for another device, check if status bits
644 * are all set to one. That means that the device is already
645 * powered off.
646 */
647 status = pxa2xx_spi_read(drv_data, SSSR);
648 if (status == ~0)
649 return IRQ_NONE;
650
651 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
652
653 /* Ignore possible writes if we don't need to write */
654 if (!(sccr1_reg & SSCR1_TIE))
655 mask &= ~SSSR_TFS;
656
657 if (!(status & mask))
658 return IRQ_NONE;
659
660 if (!drv_data->cur_msg) {
661
662 pxa2xx_spi_write(drv_data, SSCR0,
663 pxa2xx_spi_read(drv_data, SSCR0)
664 & ~SSCR0_SSE);
665 pxa2xx_spi_write(drv_data, SSCR1,
666 pxa2xx_spi_read(drv_data, SSCR1)
667 & ~drv_data->int_cr1);
668 if (!pxa25x_ssp_comp(drv_data))
669 pxa2xx_spi_write(drv_data, SSTO, 0);
670 write_SSSR_CS(drv_data, drv_data->clear_sr);
671
672 dev_err(&drv_data->pdev->dev,
673 "bad message state in interrupt handler\n");
674
675 /* Never fail */
676 return IRQ_HANDLED;
677 }
678
679 return drv_data->transfer_handler(drv_data);
680 }
681
682 /*
683 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
684 * input frequency by fractions of 2^24. It also has a divider by 5.
685 *
686 * There are formulas to get baud rate value for given input frequency and
687 * divider parameters, such as DDS_CLK_RATE and SCR:
688 *
689 * Fsys = 200MHz
690 *
691 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
692 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
693 *
694 * DDS_CLK_RATE either 2^n or 2^n / 5.
695 * SCR is in range 0 .. 255
696 *
697 * Divisor = 5^i * 2^j * 2 * k
698 * i = [0, 1] i = 1 iff j = 0 or j > 3
699 * j = [0, 23] j = 0 iff i = 1
700 * k = [1, 256]
701 * Special case: j = 0, i = 1: Divisor = 2 / 5
702 *
703 * Accordingly to the specification the recommended values for DDS_CLK_RATE
704 * are:
705 * Case 1: 2^n, n = [0, 23]
706 * Case 2: 2^24 * 2 / 5 (0x666666)
707 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
708 *
709 * In all cases the lowest possible value is better.
710 *
711 * The function calculates parameters for all cases and chooses the one closest
712 * to the asked baud rate.
713 */
714 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
715 {
716 unsigned long xtal = 200000000;
717 unsigned long fref = xtal / 2; /* mandatory division by 2,
718 see (2) */
719 /* case 3 */
720 unsigned long fref1 = fref / 2; /* case 1 */
721 unsigned long fref2 = fref * 2 / 5; /* case 2 */
722 unsigned long scale;
723 unsigned long q, q1, q2;
724 long r, r1, r2;
725 u32 mul;
726
727 /* Case 1 */
728
729 /* Set initial value for DDS_CLK_RATE */
730 mul = (1 << 24) >> 1;
731
732 /* Calculate initial quot */
733 q1 = DIV_ROUND_CLOSEST(fref1, rate);
734
735 /* Scale q1 if it's too big */
736 if (q1 > 256) {
737 /* Scale q1 to range [1, 512] */
738 scale = fls_long(q1 - 1);
739 if (scale > 9) {
740 q1 >>= scale - 9;
741 mul >>= scale - 9;
742 }
743
744 /* Round the result if we have a remainder */
745 q1 += q1 & 1;
746 }
747
748 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
749 scale = __ffs(q1);
750 q1 >>= scale;
751 mul >>= scale;
752
753 /* Get the remainder */
754 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
755
756 /* Case 2 */
757
758 q2 = DIV_ROUND_CLOSEST(fref2, rate);
759 r2 = abs(fref2 / q2 - rate);
760
761 /*
762 * Choose the best between two: less remainder we have the better. We
763 * can't go case 2 if q2 is greater than 256 since SCR register can
764 * hold only values 0 .. 255.
765 */
766 if (r2 >= r1 || q2 > 256) {
767 /* case 1 is better */
768 r = r1;
769 q = q1;
770 } else {
771 /* case 2 is better */
772 r = r2;
773 q = q2;
774 mul = (1 << 24) * 2 / 5;
775 }
776
777 /* Check case 3 only If the divisor is big enough */
778 if (fref / rate >= 80) {
779 u64 fssp;
780 u32 m;
781
782 /* Calculate initial quot */
783 q1 = DIV_ROUND_CLOSEST(fref, rate);
784 m = (1 << 24) / q1;
785
786 /* Get the remainder */
787 fssp = (u64)fref * m;
788 do_div(fssp, 1 << 24);
789 r1 = abs(fssp - rate);
790
791 /* Choose this one if it suits better */
792 if (r1 < r) {
793 /* case 3 is better */
794 q = 1;
795 mul = m;
796 }
797 }
798
799 *dds = mul;
800 return q - 1;
801 }
802
803 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
804 {
805 unsigned long ssp_clk = drv_data->max_clk_rate;
806 const struct ssp_device *ssp = drv_data->ssp;
807
808 rate = min_t(int, ssp_clk, rate);
809
810 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
811 return (ssp_clk / (2 * rate) - 1) & 0xff;
812 else
813 return (ssp_clk / rate - 1) & 0xfff;
814 }
815
816 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
817 struct chip_data *chip, int rate)
818 {
819 unsigned int clk_div;
820
821 switch (drv_data->ssp_type) {
822 case QUARK_X1000_SSP:
823 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
824 break;
825 default:
826 clk_div = ssp_get_clk_div(drv_data, rate);
827 break;
828 }
829 return clk_div << 8;
830 }
831
832 static void pump_transfers(unsigned long data)
833 {
834 struct driver_data *drv_data = (struct driver_data *)data;
835 struct spi_message *message = NULL;
836 struct spi_transfer *transfer = NULL;
837 struct spi_transfer *previous = NULL;
838 struct chip_data *chip = NULL;
839 u32 clk_div = 0;
840 u8 bits = 0;
841 u32 speed = 0;
842 u32 cr0;
843 u32 cr1;
844 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
845 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
846 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
847
848 /* Get current state information */
849 message = drv_data->cur_msg;
850 transfer = drv_data->cur_transfer;
851 chip = drv_data->cur_chip;
852
853 /* Handle for abort */
854 if (message->state == ERROR_STATE) {
855 message->status = -EIO;
856 giveback(drv_data);
857 return;
858 }
859
860 /* Handle end of message */
861 if (message->state == DONE_STATE) {
862 message->status = 0;
863 giveback(drv_data);
864 return;
865 }
866
867 /* Delay if requested at end of transfer before CS change */
868 if (message->state == RUNNING_STATE) {
869 previous = list_entry(transfer->transfer_list.prev,
870 struct spi_transfer,
871 transfer_list);
872 if (previous->delay_usecs)
873 udelay(previous->delay_usecs);
874
875 /* Drop chip select only if cs_change is requested */
876 if (previous->cs_change)
877 cs_deassert(drv_data);
878 }
879
880 /* Check if we can DMA this transfer */
881 if (!pxa2xx_spi_dma_is_possible(transfer->len) && chip->enable_dma) {
882
883 /* reject already-mapped transfers; PIO won't always work */
884 if (message->is_dma_mapped
885 || transfer->rx_dma || transfer->tx_dma) {
886 dev_err(&drv_data->pdev->dev,
887 "pump_transfers: mapped transfer length of "
888 "%u is greater than %d\n",
889 transfer->len, MAX_DMA_LEN);
890 message->status = -EINVAL;
891 giveback(drv_data);
892 return;
893 }
894
895 /* warn ... we force this to PIO mode */
896 dev_warn_ratelimited(&message->spi->dev,
897 "pump_transfers: DMA disabled for transfer length %ld "
898 "greater than %d\n",
899 (long)drv_data->len, MAX_DMA_LEN);
900 }
901
902 /* Setup the transfer state based on the type of transfer */
903 if (pxa2xx_spi_flush(drv_data) == 0) {
904 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
905 message->status = -EIO;
906 giveback(drv_data);
907 return;
908 }
909 drv_data->n_bytes = chip->n_bytes;
910 drv_data->tx = (void *)transfer->tx_buf;
911 drv_data->tx_end = drv_data->tx + transfer->len;
912 drv_data->rx = transfer->rx_buf;
913 drv_data->rx_end = drv_data->rx + transfer->len;
914 drv_data->rx_dma = transfer->rx_dma;
915 drv_data->tx_dma = transfer->tx_dma;
916 drv_data->len = transfer->len;
917 drv_data->write = drv_data->tx ? chip->write : null_writer;
918 drv_data->read = drv_data->rx ? chip->read : null_reader;
919
920 /* Change speed and bit per word on a per transfer */
921 cr0 = chip->cr0;
922 if (transfer->speed_hz || transfer->bits_per_word) {
923
924 bits = chip->bits_per_word;
925 speed = chip->speed_hz;
926
927 if (transfer->speed_hz)
928 speed = transfer->speed_hz;
929
930 if (transfer->bits_per_word)
931 bits = transfer->bits_per_word;
932
933 clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, speed);
934
935 if (bits <= 8) {
936 drv_data->n_bytes = 1;
937 drv_data->read = drv_data->read != null_reader ?
938 u8_reader : null_reader;
939 drv_data->write = drv_data->write != null_writer ?
940 u8_writer : null_writer;
941 } else if (bits <= 16) {
942 drv_data->n_bytes = 2;
943 drv_data->read = drv_data->read != null_reader ?
944 u16_reader : null_reader;
945 drv_data->write = drv_data->write != null_writer ?
946 u16_writer : null_writer;
947 } else if (bits <= 32) {
948 drv_data->n_bytes = 4;
949 drv_data->read = drv_data->read != null_reader ?
950 u32_reader : null_reader;
951 drv_data->write = drv_data->write != null_writer ?
952 u32_writer : null_writer;
953 }
954 /* if bits/word is changed in dma mode, then must check the
955 * thresholds and burst also */
956 if (chip->enable_dma) {
957 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
958 message->spi,
959 bits, &dma_burst,
960 &dma_thresh))
961 dev_warn_ratelimited(&message->spi->dev,
962 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
963 }
964
965 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
966 }
967
968 message->state = RUNNING_STATE;
969
970 drv_data->dma_mapped = 0;
971 if (pxa2xx_spi_dma_is_possible(drv_data->len))
972 drv_data->dma_mapped = pxa2xx_spi_map_dma_buffers(drv_data);
973 if (drv_data->dma_mapped) {
974
975 /* Ensure we have the correct interrupt handler */
976 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
977
978 pxa2xx_spi_dma_prepare(drv_data, dma_burst);
979
980 /* Clear status and start DMA engine */
981 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
982 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
983
984 pxa2xx_spi_dma_start(drv_data);
985 } else {
986 /* Ensure we have the correct interrupt handler */
987 drv_data->transfer_handler = interrupt_transfer;
988
989 /* Clear status */
990 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
991 write_SSSR_CS(drv_data, drv_data->clear_sr);
992 }
993
994 if (is_lpss_ssp(drv_data)) {
995 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
996 != chip->lpss_rx_threshold)
997 pxa2xx_spi_write(drv_data, SSIRF,
998 chip->lpss_rx_threshold);
999 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1000 != chip->lpss_tx_threshold)
1001 pxa2xx_spi_write(drv_data, SSITF,
1002 chip->lpss_tx_threshold);
1003 }
1004
1005 if (is_quark_x1000_ssp(drv_data) &&
1006 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1007 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1008
1009 /* see if we need to reload the config registers */
1010 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1011 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1012 != (cr1 & change_mask)) {
1013 /* stop the SSP, and update the other bits */
1014 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1015 if (!pxa25x_ssp_comp(drv_data))
1016 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1017 /* first set CR1 without interrupt and service enables */
1018 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1019 /* restart the SSP */
1020 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1021
1022 } else {
1023 if (!pxa25x_ssp_comp(drv_data))
1024 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1025 }
1026
1027 cs_assert(drv_data);
1028
1029 /* after chip select, release the data by enabling service
1030 * requests and interrupts, without changing any mode bits */
1031 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1032 }
1033
1034 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1035 struct spi_message *msg)
1036 {
1037 struct driver_data *drv_data = spi_master_get_devdata(master);
1038
1039 drv_data->cur_msg = msg;
1040 /* Initial message state*/
1041 drv_data->cur_msg->state = START_STATE;
1042 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1043 struct spi_transfer,
1044 transfer_list);
1045
1046 /* prepare to setup the SSP, in pump_transfers, using the per
1047 * chip configuration */
1048 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1049
1050 /* Mark as busy and launch transfers */
1051 tasklet_schedule(&drv_data->pump_transfers);
1052 return 0;
1053 }
1054
1055 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1056 {
1057 struct driver_data *drv_data = spi_master_get_devdata(master);
1058
1059 /* Disable the SSP now */
1060 pxa2xx_spi_write(drv_data, SSCR0,
1061 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1062
1063 return 0;
1064 }
1065
1066 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1067 struct pxa2xx_spi_chip *chip_info)
1068 {
1069 int err = 0;
1070
1071 if (chip == NULL || chip_info == NULL)
1072 return 0;
1073
1074 /* NOTE: setup() can be called multiple times, possibly with
1075 * different chip_info, release previously requested GPIO
1076 */
1077 if (gpio_is_valid(chip->gpio_cs))
1078 gpio_free(chip->gpio_cs);
1079
1080 /* If (*cs_control) is provided, ignore GPIO chip select */
1081 if (chip_info->cs_control) {
1082 chip->cs_control = chip_info->cs_control;
1083 return 0;
1084 }
1085
1086 if (gpio_is_valid(chip_info->gpio_cs)) {
1087 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1088 if (err) {
1089 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1090 chip_info->gpio_cs);
1091 return err;
1092 }
1093
1094 chip->gpio_cs = chip_info->gpio_cs;
1095 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1096
1097 err = gpio_direction_output(chip->gpio_cs,
1098 !chip->gpio_cs_inverted);
1099 }
1100
1101 return err;
1102 }
1103
1104 static int setup(struct spi_device *spi)
1105 {
1106 struct pxa2xx_spi_chip *chip_info = NULL;
1107 struct chip_data *chip;
1108 const struct lpss_config *config;
1109 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1110 unsigned int clk_div;
1111 uint tx_thres, tx_hi_thres, rx_thres;
1112
1113 switch (drv_data->ssp_type) {
1114 case QUARK_X1000_SSP:
1115 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1116 tx_hi_thres = 0;
1117 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1118 break;
1119 case LPSS_LPT_SSP:
1120 case LPSS_BYT_SSP:
1121 case LPSS_SPT_SSP:
1122 config = lpss_get_config(drv_data);
1123 tx_thres = config->tx_threshold_lo;
1124 tx_hi_thres = config->tx_threshold_hi;
1125 rx_thres = config->rx_threshold;
1126 break;
1127 default:
1128 tx_thres = TX_THRESH_DFLT;
1129 tx_hi_thres = 0;
1130 rx_thres = RX_THRESH_DFLT;
1131 break;
1132 }
1133
1134 /* Only alloc on first setup */
1135 chip = spi_get_ctldata(spi);
1136 if (!chip) {
1137 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1138 if (!chip)
1139 return -ENOMEM;
1140
1141 if (drv_data->ssp_type == CE4100_SSP) {
1142 if (spi->chip_select > 4) {
1143 dev_err(&spi->dev,
1144 "failed setup: cs number must not be > 4.\n");
1145 kfree(chip);
1146 return -EINVAL;
1147 }
1148
1149 chip->frm = spi->chip_select;
1150 } else
1151 chip->gpio_cs = -1;
1152 chip->enable_dma = 0;
1153 chip->timeout = TIMOUT_DFLT;
1154 }
1155
1156 /* protocol drivers may change the chip settings, so...
1157 * if chip_info exists, use it */
1158 chip_info = spi->controller_data;
1159
1160 /* chip_info isn't always needed */
1161 chip->cr1 = 0;
1162 if (chip_info) {
1163 if (chip_info->timeout)
1164 chip->timeout = chip_info->timeout;
1165 if (chip_info->tx_threshold)
1166 tx_thres = chip_info->tx_threshold;
1167 if (chip_info->tx_hi_threshold)
1168 tx_hi_thres = chip_info->tx_hi_threshold;
1169 if (chip_info->rx_threshold)
1170 rx_thres = chip_info->rx_threshold;
1171 chip->enable_dma = drv_data->master_info->enable_dma;
1172 chip->dma_threshold = 0;
1173 if (chip_info->enable_loopback)
1174 chip->cr1 = SSCR1_LBM;
1175 } else if (ACPI_HANDLE(&spi->dev)) {
1176 /*
1177 * Slave devices enumerated from ACPI namespace don't
1178 * usually have chip_info but we still might want to use
1179 * DMA with them.
1180 */
1181 chip->enable_dma = drv_data->master_info->enable_dma;
1182 }
1183
1184 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1185 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1186 | SSITF_TxHiThresh(tx_hi_thres);
1187
1188 /* set dma burst and threshold outside of chip_info path so that if
1189 * chip_info goes away after setting chip->enable_dma, the
1190 * burst and threshold can still respond to changes in bits_per_word */
1191 if (chip->enable_dma) {
1192 /* set up legal burst and threshold for dma */
1193 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1194 spi->bits_per_word,
1195 &chip->dma_burst_size,
1196 &chip->dma_threshold)) {
1197 dev_warn(&spi->dev,
1198 "in setup: DMA burst size reduced to match bits_per_word\n");
1199 }
1200 }
1201
1202 clk_div = pxa2xx_ssp_get_clk_div(drv_data, chip, spi->max_speed_hz);
1203 chip->speed_hz = spi->max_speed_hz;
1204
1205 chip->cr0 = pxa2xx_configure_sscr0(drv_data, clk_div,
1206 spi->bits_per_word);
1207 switch (drv_data->ssp_type) {
1208 case QUARK_X1000_SSP:
1209 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1210 & QUARK_X1000_SSCR1_RFT)
1211 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1212 & QUARK_X1000_SSCR1_TFT);
1213 break;
1214 default:
1215 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1216 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1217 break;
1218 }
1219
1220 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1221 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1222 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1223
1224 if (spi->mode & SPI_LOOP)
1225 chip->cr1 |= SSCR1_LBM;
1226
1227 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1228 if (!pxa25x_ssp_comp(drv_data))
1229 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1230 drv_data->max_clk_rate
1231 / (1 + ((chip->cr0 & SSCR0_SCR(0xfff)) >> 8)),
1232 chip->enable_dma ? "DMA" : "PIO");
1233 else
1234 dev_dbg(&spi->dev, "%ld Hz actual, %s\n",
1235 drv_data->max_clk_rate / 2
1236 / (1 + ((chip->cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1237 chip->enable_dma ? "DMA" : "PIO");
1238
1239 if (spi->bits_per_word <= 8) {
1240 chip->n_bytes = 1;
1241 chip->read = u8_reader;
1242 chip->write = u8_writer;
1243 } else if (spi->bits_per_word <= 16) {
1244 chip->n_bytes = 2;
1245 chip->read = u16_reader;
1246 chip->write = u16_writer;
1247 } else if (spi->bits_per_word <= 32) {
1248 if (!is_quark_x1000_ssp(drv_data))
1249 chip->cr0 |= SSCR0_EDSS;
1250 chip->n_bytes = 4;
1251 chip->read = u32_reader;
1252 chip->write = u32_writer;
1253 }
1254 chip->bits_per_word = spi->bits_per_word;
1255
1256 spi_set_ctldata(spi, chip);
1257
1258 if (drv_data->ssp_type == CE4100_SSP)
1259 return 0;
1260
1261 return setup_cs(spi, chip, chip_info);
1262 }
1263
1264 static void cleanup(struct spi_device *spi)
1265 {
1266 struct chip_data *chip = spi_get_ctldata(spi);
1267 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1268
1269 if (!chip)
1270 return;
1271
1272 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1273 gpio_free(chip->gpio_cs);
1274
1275 kfree(chip);
1276 }
1277
1278 #ifdef CONFIG_ACPI
1279
1280 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1281 { "INT33C0", LPSS_LPT_SSP },
1282 { "INT33C1", LPSS_LPT_SSP },
1283 { "INT3430", LPSS_LPT_SSP },
1284 { "INT3431", LPSS_LPT_SSP },
1285 { "80860F0E", LPSS_BYT_SSP },
1286 { "8086228E", LPSS_BYT_SSP },
1287 { },
1288 };
1289 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1290
1291 /*
1292 * PCI IDs of compound devices that integrate both host controller and private
1293 * integrated DMA engine. Please note these are not used in module
1294 * autoloading and probing in this module but matching the LPSS SSP type.
1295 */
1296 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1297 /* SPT-LP */
1298 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1299 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1300 /* SPT-H */
1301 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1302 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1303 { },
1304 };
1305
1306 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1307 {
1308 struct device *dev = param;
1309
1310 if (dev != chan->device->dev->parent)
1311 return false;
1312
1313 return true;
1314 }
1315
1316 static struct pxa2xx_spi_master *
1317 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1318 {
1319 struct pxa2xx_spi_master *pdata;
1320 struct acpi_device *adev;
1321 struct ssp_device *ssp;
1322 struct resource *res;
1323 const struct acpi_device_id *adev_id = NULL;
1324 const struct pci_device_id *pcidev_id = NULL;
1325 int devid, type;
1326
1327 if (!ACPI_HANDLE(&pdev->dev) ||
1328 acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
1329 return NULL;
1330
1331 if (dev_is_pci(pdev->dev.parent))
1332 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1333 to_pci_dev(pdev->dev.parent));
1334 else
1335 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1336 &pdev->dev);
1337
1338 if (adev_id)
1339 type = (int)adev_id->driver_data;
1340 else if (pcidev_id)
1341 type = (int)pcidev_id->driver_data;
1342 else
1343 return NULL;
1344
1345 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1346 if (!pdata)
1347 return NULL;
1348
1349 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1350 if (!res)
1351 return NULL;
1352
1353 ssp = &pdata->ssp;
1354
1355 ssp->phys_base = res->start;
1356 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1357 if (IS_ERR(ssp->mmio_base))
1358 return NULL;
1359
1360 if (pcidev_id) {
1361 pdata->tx_param = pdev->dev.parent;
1362 pdata->rx_param = pdev->dev.parent;
1363 pdata->dma_filter = pxa2xx_spi_idma_filter;
1364 }
1365
1366 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1367 ssp->irq = platform_get_irq(pdev, 0);
1368 ssp->type = type;
1369 ssp->pdev = pdev;
1370
1371 ssp->port_id = -1;
1372 if (adev->pnp.unique_id && !kstrtoint(adev->pnp.unique_id, 0, &devid))
1373 ssp->port_id = devid;
1374
1375 pdata->num_chipselect = 1;
1376 pdata->enable_dma = true;
1377
1378 return pdata;
1379 }
1380
1381 #else
1382 static inline struct pxa2xx_spi_master *
1383 pxa2xx_spi_acpi_get_pdata(struct platform_device *pdev)
1384 {
1385 return NULL;
1386 }
1387 #endif
1388
1389 static int pxa2xx_spi_probe(struct platform_device *pdev)
1390 {
1391 struct device *dev = &pdev->dev;
1392 struct pxa2xx_spi_master *platform_info;
1393 struct spi_master *master;
1394 struct driver_data *drv_data;
1395 struct ssp_device *ssp;
1396 int status;
1397 u32 tmp;
1398
1399 platform_info = dev_get_platdata(dev);
1400 if (!platform_info) {
1401 platform_info = pxa2xx_spi_acpi_get_pdata(pdev);
1402 if (!platform_info) {
1403 dev_err(&pdev->dev, "missing platform data\n");
1404 return -ENODEV;
1405 }
1406 }
1407
1408 ssp = pxa_ssp_request(pdev->id, pdev->name);
1409 if (!ssp)
1410 ssp = &platform_info->ssp;
1411
1412 if (!ssp->mmio_base) {
1413 dev_err(&pdev->dev, "failed to get ssp\n");
1414 return -ENODEV;
1415 }
1416
1417 master = spi_alloc_master(dev, sizeof(struct driver_data));
1418 if (!master) {
1419 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1420 pxa_ssp_free(ssp);
1421 return -ENOMEM;
1422 }
1423 drv_data = spi_master_get_devdata(master);
1424 drv_data->master = master;
1425 drv_data->master_info = platform_info;
1426 drv_data->pdev = pdev;
1427 drv_data->ssp = ssp;
1428
1429 master->dev.parent = &pdev->dev;
1430 master->dev.of_node = pdev->dev.of_node;
1431 /* the spi->mode bits understood by this driver: */
1432 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1433
1434 master->bus_num = ssp->port_id;
1435 master->num_chipselect = platform_info->num_chipselect;
1436 master->dma_alignment = DMA_ALIGNMENT;
1437 master->cleanup = cleanup;
1438 master->setup = setup;
1439 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1440 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1441 master->auto_runtime_pm = true;
1442
1443 drv_data->ssp_type = ssp->type;
1444
1445 drv_data->ioaddr = ssp->mmio_base;
1446 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1447 if (pxa25x_ssp_comp(drv_data)) {
1448 switch (drv_data->ssp_type) {
1449 case QUARK_X1000_SSP:
1450 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1451 break;
1452 default:
1453 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1454 break;
1455 }
1456
1457 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1458 drv_data->dma_cr1 = 0;
1459 drv_data->clear_sr = SSSR_ROR;
1460 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1461 } else {
1462 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1463 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1464 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1465 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1466 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1467 }
1468
1469 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1470 drv_data);
1471 if (status < 0) {
1472 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1473 goto out_error_master_alloc;
1474 }
1475
1476 /* Setup DMA if requested */
1477 if (platform_info->enable_dma) {
1478 status = pxa2xx_spi_dma_setup(drv_data);
1479 if (status) {
1480 dev_dbg(dev, "no DMA channels available, using PIO\n");
1481 platform_info->enable_dma = false;
1482 }
1483 }
1484
1485 /* Enable SOC clock */
1486 clk_prepare_enable(ssp->clk);
1487
1488 drv_data->max_clk_rate = clk_get_rate(ssp->clk);
1489
1490 /* Load default SSP configuration */
1491 pxa2xx_spi_write(drv_data, SSCR0, 0);
1492 switch (drv_data->ssp_type) {
1493 case QUARK_X1000_SSP:
1494 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1495 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1496 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1497
1498 /* using the Motorola SPI protocol and use 8 bit frame */
1499 pxa2xx_spi_write(drv_data, SSCR0,
1500 QUARK_X1000_SSCR0_Motorola
1501 | QUARK_X1000_SSCR0_DataSize(8));
1502 break;
1503 default:
1504 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1505 SSCR1_TxTresh(TX_THRESH_DFLT);
1506 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1507 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1508 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1509 break;
1510 }
1511
1512 if (!pxa25x_ssp_comp(drv_data))
1513 pxa2xx_spi_write(drv_data, SSTO, 0);
1514
1515 if (!is_quark_x1000_ssp(drv_data))
1516 pxa2xx_spi_write(drv_data, SSPSP, 0);
1517
1518 if (is_lpss_ssp(drv_data))
1519 lpss_ssp_setup(drv_data);
1520
1521 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1522 (unsigned long)drv_data);
1523
1524 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1525 pm_runtime_use_autosuspend(&pdev->dev);
1526 pm_runtime_set_active(&pdev->dev);
1527 pm_runtime_enable(&pdev->dev);
1528
1529 /* Register with the SPI framework */
1530 platform_set_drvdata(pdev, drv_data);
1531 status = devm_spi_register_master(&pdev->dev, master);
1532 if (status != 0) {
1533 dev_err(&pdev->dev, "problem registering spi master\n");
1534 goto out_error_clock_enabled;
1535 }
1536
1537 return status;
1538
1539 out_error_clock_enabled:
1540 clk_disable_unprepare(ssp->clk);
1541 pxa2xx_spi_dma_release(drv_data);
1542 free_irq(ssp->irq, drv_data);
1543
1544 out_error_master_alloc:
1545 spi_master_put(master);
1546 pxa_ssp_free(ssp);
1547 return status;
1548 }
1549
1550 static int pxa2xx_spi_remove(struct platform_device *pdev)
1551 {
1552 struct driver_data *drv_data = platform_get_drvdata(pdev);
1553 struct ssp_device *ssp;
1554
1555 if (!drv_data)
1556 return 0;
1557 ssp = drv_data->ssp;
1558
1559 pm_runtime_get_sync(&pdev->dev);
1560
1561 /* Disable the SSP at the peripheral and SOC level */
1562 pxa2xx_spi_write(drv_data, SSCR0, 0);
1563 clk_disable_unprepare(ssp->clk);
1564
1565 /* Release DMA */
1566 if (drv_data->master_info->enable_dma)
1567 pxa2xx_spi_dma_release(drv_data);
1568
1569 pm_runtime_put_noidle(&pdev->dev);
1570 pm_runtime_disable(&pdev->dev);
1571
1572 /* Release IRQ */
1573 free_irq(ssp->irq, drv_data);
1574
1575 /* Release SSP */
1576 pxa_ssp_free(ssp);
1577
1578 return 0;
1579 }
1580
1581 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1582 {
1583 int status = 0;
1584
1585 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1586 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1587 }
1588
1589 #ifdef CONFIG_PM_SLEEP
1590 static int pxa2xx_spi_suspend(struct device *dev)
1591 {
1592 struct driver_data *drv_data = dev_get_drvdata(dev);
1593 struct ssp_device *ssp = drv_data->ssp;
1594 int status = 0;
1595
1596 status = spi_master_suspend(drv_data->master);
1597 if (status != 0)
1598 return status;
1599 pxa2xx_spi_write(drv_data, SSCR0, 0);
1600
1601 if (!pm_runtime_suspended(dev))
1602 clk_disable_unprepare(ssp->clk);
1603
1604 return 0;
1605 }
1606
1607 static int pxa2xx_spi_resume(struct device *dev)
1608 {
1609 struct driver_data *drv_data = dev_get_drvdata(dev);
1610 struct ssp_device *ssp = drv_data->ssp;
1611 int status = 0;
1612
1613 pxa2xx_spi_dma_resume(drv_data);
1614
1615 /* Enable the SSP clock */
1616 if (!pm_runtime_suspended(dev))
1617 clk_prepare_enable(ssp->clk);
1618
1619 /* Restore LPSS private register bits */
1620 if (is_lpss_ssp(drv_data))
1621 lpss_ssp_setup(drv_data);
1622
1623 /* Start the queue running */
1624 status = spi_master_resume(drv_data->master);
1625 if (status != 0) {
1626 dev_err(dev, "problem starting queue (%d)\n", status);
1627 return status;
1628 }
1629
1630 return 0;
1631 }
1632 #endif
1633
1634 #ifdef CONFIG_PM
1635 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1636 {
1637 struct driver_data *drv_data = dev_get_drvdata(dev);
1638
1639 clk_disable_unprepare(drv_data->ssp->clk);
1640 return 0;
1641 }
1642
1643 static int pxa2xx_spi_runtime_resume(struct device *dev)
1644 {
1645 struct driver_data *drv_data = dev_get_drvdata(dev);
1646
1647 clk_prepare_enable(drv_data->ssp->clk);
1648 return 0;
1649 }
1650 #endif
1651
1652 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1653 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1654 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1655 pxa2xx_spi_runtime_resume, NULL)
1656 };
1657
1658 static struct platform_driver driver = {
1659 .driver = {
1660 .name = "pxa2xx-spi",
1661 .pm = &pxa2xx_spi_pm_ops,
1662 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1663 },
1664 .probe = pxa2xx_spi_probe,
1665 .remove = pxa2xx_spi_remove,
1666 .shutdown = pxa2xx_spi_shutdown,
1667 };
1668
1669 static int __init pxa2xx_spi_init(void)
1670 {
1671 return platform_driver_register(&driver);
1672 }
1673 subsys_initcall(pxa2xx_spi_init);
1674
1675 static void __exit pxa2xx_spi_exit(void)
1676 {
1677 platform_driver_unregister(&driver);
1678 }
1679 module_exit(pxa2xx_spi_exit);
Linux kernel - Deliverables
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