2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/ioport.h>
24 #include <linux/errno.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/spi/pxa2xx_spi.h>
29 #include <linux/spi/spi.h>
30 #include <linux/workqueue.h>
31 #include <linux/delay.h>
32 #include <linux/gpio.h>
33 #include <linux/slab.h>
34 #include <linux/clk.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/acpi.h>
40 #include <asm/delay.h>
42 #include "spi-pxa2xx.h"
44 MODULE_AUTHOR("Stephen Street");
45 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
46 MODULE_LICENSE("GPL");
47 MODULE_ALIAS("platform:pxa2xx-spi");
51 #define TIMOUT_DFLT 1000
54 * for testing SSCR1 changes that require SSP restart, basically
55 * everything except the service and interrupt enables, the pxa270 developer
56 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
57 * list, but the PXA255 dev man says all bits without really meaning the
58 * service and interrupt enables
60 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
61 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
62 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
63 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
64 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
65 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
67 #define LPSS_RX_THRESH_DFLT 64
68 #define LPSS_TX_LOTHRESH_DFLT 160
69 #define LPSS_TX_HITHRESH_DFLT 224
71 /* Offset from drv_data->lpss_base */
73 #define SPI_CS_CONTROL 0x18
74 #define SPI_CS_CONTROL_SW_MODE BIT(0)
75 #define SPI_CS_CONTROL_CS_HIGH BIT(1)
77 static bool is_lpss_ssp(const struct driver_data
*drv_data
)
79 return drv_data
->ssp_type
== LPSS_SSP
;
83 * Read and write LPSS SSP private registers. Caller must first check that
84 * is_lpss_ssp() returns true before these can be called.
86 static u32
__lpss_ssp_read_priv(struct driver_data
*drv_data
, unsigned offset
)
88 WARN_ON(!drv_data
->lpss_base
);
89 return readl(drv_data
->lpss_base
+ offset
);
92 static void __lpss_ssp_write_priv(struct driver_data
*drv_data
,
93 unsigned offset
, u32 value
)
95 WARN_ON(!drv_data
->lpss_base
);
96 writel(value
, drv_data
->lpss_base
+ offset
);
100 * lpss_ssp_setup - perform LPSS SSP specific setup
101 * @drv_data: pointer to the driver private data
103 * Perform LPSS SSP specific setup. This function must be called first if
104 * one is going to use LPSS SSP private registers.
106 static void lpss_ssp_setup(struct driver_data
*drv_data
)
108 unsigned offset
= 0x400;
111 if (!is_lpss_ssp(drv_data
))
115 * Perform auto-detection of the LPSS SSP private registers. They
116 * can be either at 1k or 2k offset from the base address.
118 orig
= readl(drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
120 value
= orig
| SPI_CS_CONTROL_SW_MODE
;
121 writel(value
, drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
122 value
= readl(drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
123 if (value
!= (orig
| SPI_CS_CONTROL_SW_MODE
)) {
128 value
&= ~SPI_CS_CONTROL_SW_MODE
;
129 writel(value
, drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
130 value
= readl(drv_data
->ioaddr
+ offset
+ SPI_CS_CONTROL
);
137 /* Now set the LPSS base */
138 drv_data
->lpss_base
= drv_data
->ioaddr
+ offset
;
140 /* Enable software chip select control */
141 value
= SPI_CS_CONTROL_SW_MODE
| SPI_CS_CONTROL_CS_HIGH
;
142 __lpss_ssp_write_priv(drv_data
, SPI_CS_CONTROL
, value
);
144 /* Enable multiblock DMA transfers */
145 if (drv_data
->master_info
->enable_dma
)
146 __lpss_ssp_write_priv(drv_data
, SSP_REG
, 1);
149 static void lpss_ssp_cs_control(struct driver_data
*drv_data
, bool enable
)
153 if (!is_lpss_ssp(drv_data
))
156 value
= __lpss_ssp_read_priv(drv_data
, SPI_CS_CONTROL
);
158 value
&= ~SPI_CS_CONTROL_CS_HIGH
;
160 value
|= SPI_CS_CONTROL_CS_HIGH
;
161 __lpss_ssp_write_priv(drv_data
, SPI_CS_CONTROL
, value
);
164 static void cs_assert(struct driver_data
*drv_data
)
166 struct chip_data
*chip
= drv_data
->cur_chip
;
168 if (drv_data
->ssp_type
== CE4100_SSP
) {
169 write_SSSR(drv_data
->cur_chip
->frm
, drv_data
->ioaddr
);
173 if (chip
->cs_control
) {
174 chip
->cs_control(PXA2XX_CS_ASSERT
);
178 if (gpio_is_valid(chip
->gpio_cs
)) {
179 gpio_set_value(chip
->gpio_cs
, chip
->gpio_cs_inverted
);
183 lpss_ssp_cs_control(drv_data
, true);
186 static void cs_deassert(struct driver_data
*drv_data
)
188 struct chip_data
*chip
= drv_data
->cur_chip
;
190 if (drv_data
->ssp_type
== CE4100_SSP
)
193 if (chip
->cs_control
) {
194 chip
->cs_control(PXA2XX_CS_DEASSERT
);
198 if (gpio_is_valid(chip
->gpio_cs
)) {
199 gpio_set_value(chip
->gpio_cs
, !chip
->gpio_cs_inverted
);
203 lpss_ssp_cs_control(drv_data
, false);
206 int pxa2xx_spi_flush(struct driver_data
*drv_data
)
208 unsigned long limit
= loops_per_jiffy
<< 1;
210 void __iomem
*reg
= drv_data
->ioaddr
;
213 while (read_SSSR(reg
) & SSSR_RNE
) {
216 } while ((read_SSSR(reg
) & SSSR_BSY
) && --limit
);
217 write_SSSR_CS(drv_data
, SSSR_ROR
);
222 static int null_writer(struct driver_data
*drv_data
)
224 void __iomem
*reg
= drv_data
->ioaddr
;
225 u8 n_bytes
= drv_data
->n_bytes
;
227 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
228 || (drv_data
->tx
== drv_data
->tx_end
))
232 drv_data
->tx
+= n_bytes
;
237 static int null_reader(struct driver_data
*drv_data
)
239 void __iomem
*reg
= drv_data
->ioaddr
;
240 u8 n_bytes
= drv_data
->n_bytes
;
242 while ((read_SSSR(reg
) & SSSR_RNE
)
243 && (drv_data
->rx
< drv_data
->rx_end
)) {
245 drv_data
->rx
+= n_bytes
;
248 return drv_data
->rx
== drv_data
->rx_end
;
251 static int u8_writer(struct driver_data
*drv_data
)
253 void __iomem
*reg
= drv_data
->ioaddr
;
255 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
256 || (drv_data
->tx
== drv_data
->tx_end
))
259 write_SSDR(*(u8
*)(drv_data
->tx
), reg
);
265 static int u8_reader(struct driver_data
*drv_data
)
267 void __iomem
*reg
= drv_data
->ioaddr
;
269 while ((read_SSSR(reg
) & SSSR_RNE
)
270 && (drv_data
->rx
< drv_data
->rx_end
)) {
271 *(u8
*)(drv_data
->rx
) = read_SSDR(reg
);
275 return drv_data
->rx
== drv_data
->rx_end
;
278 static int u16_writer(struct driver_data
*drv_data
)
280 void __iomem
*reg
= drv_data
->ioaddr
;
282 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
283 || (drv_data
->tx
== drv_data
->tx_end
))
286 write_SSDR(*(u16
*)(drv_data
->tx
), reg
);
292 static int u16_reader(struct driver_data
*drv_data
)
294 void __iomem
*reg
= drv_data
->ioaddr
;
296 while ((read_SSSR(reg
) & SSSR_RNE
)
297 && (drv_data
->rx
< drv_data
->rx_end
)) {
298 *(u16
*)(drv_data
->rx
) = read_SSDR(reg
);
302 return drv_data
->rx
== drv_data
->rx_end
;
305 static int u32_writer(struct driver_data
*drv_data
)
307 void __iomem
*reg
= drv_data
->ioaddr
;
309 if (((read_SSSR(reg
) & SSSR_TFL_MASK
) == SSSR_TFL_MASK
)
310 || (drv_data
->tx
== drv_data
->tx_end
))
313 write_SSDR(*(u32
*)(drv_data
->tx
), reg
);
319 static int u32_reader(struct driver_data
*drv_data
)
321 void __iomem
*reg
= drv_data
->ioaddr
;
323 while ((read_SSSR(reg
) & SSSR_RNE
)
324 && (drv_data
->rx
< drv_data
->rx_end
)) {
325 *(u32
*)(drv_data
->rx
) = read_SSDR(reg
);
329 return drv_data
->rx
== drv_data
->rx_end
;
332 void *pxa2xx_spi_next_transfer(struct driver_data
*drv_data
)
334 struct spi_message
*msg
= drv_data
->cur_msg
;
335 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
337 /* Move to next transfer */
338 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
339 drv_data
->cur_transfer
=
340 list_entry(trans
->transfer_list
.next
,
343 return RUNNING_STATE
;
348 /* caller already set message->status; dma and pio irqs are blocked */
349 static void giveback(struct driver_data
*drv_data
)
351 struct spi_transfer
* last_transfer
;
352 struct spi_message
*msg
;
354 msg
= drv_data
->cur_msg
;
355 drv_data
->cur_msg
= NULL
;
356 drv_data
->cur_transfer
= NULL
;
358 last_transfer
= list_entry(msg
->transfers
.prev
,
362 /* Delay if requested before any change in chip select */
363 if (last_transfer
->delay_usecs
)
364 udelay(last_transfer
->delay_usecs
);
366 /* Drop chip select UNLESS cs_change is true or we are returning
367 * a message with an error, or next message is for another chip
369 if (!last_transfer
->cs_change
)
370 cs_deassert(drv_data
);
372 struct spi_message
*next_msg
;
374 /* Holding of cs was hinted, but we need to make sure
375 * the next message is for the same chip. Don't waste
376 * time with the following tests unless this was hinted.
378 * We cannot postpone this until pump_messages, because
379 * after calling msg->complete (below) the driver that
380 * sent the current message could be unloaded, which
381 * could invalidate the cs_control() callback...
384 /* get a pointer to the next message, if any */
385 next_msg
= spi_get_next_queued_message(drv_data
->master
);
387 /* see if the next and current messages point
390 if (next_msg
&& next_msg
->spi
!= msg
->spi
)
392 if (!next_msg
|| msg
->state
== ERROR_STATE
)
393 cs_deassert(drv_data
);
396 spi_finalize_current_message(drv_data
->master
);
397 drv_data
->cur_chip
= NULL
;
400 static void reset_sccr1(struct driver_data
*drv_data
)
402 void __iomem
*reg
= drv_data
->ioaddr
;
403 struct chip_data
*chip
= drv_data
->cur_chip
;
406 sccr1_reg
= read_SSCR1(reg
) & ~drv_data
->int_cr1
;
407 sccr1_reg
&= ~SSCR1_RFT
;
408 sccr1_reg
|= chip
->threshold
;
409 write_SSCR1(sccr1_reg
, reg
);
412 static void int_error_stop(struct driver_data
*drv_data
, const char* msg
)
414 void __iomem
*reg
= drv_data
->ioaddr
;
416 /* Stop and reset SSP */
417 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
418 reset_sccr1(drv_data
);
419 if (!pxa25x_ssp_comp(drv_data
))
421 pxa2xx_spi_flush(drv_data
);
422 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
424 dev_err(&drv_data
->pdev
->dev
, "%s\n", msg
);
426 drv_data
->cur_msg
->state
= ERROR_STATE
;
427 tasklet_schedule(&drv_data
->pump_transfers
);
430 static void int_transfer_complete(struct driver_data
*drv_data
)
432 void __iomem
*reg
= drv_data
->ioaddr
;
435 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
436 reset_sccr1(drv_data
);
437 if (!pxa25x_ssp_comp(drv_data
))
440 /* Update total byte transferred return count actual bytes read */
441 drv_data
->cur_msg
->actual_length
+= drv_data
->len
-
442 (drv_data
->rx_end
- drv_data
->rx
);
444 /* Transfer delays and chip select release are
445 * handled in pump_transfers or giveback
448 /* Move to next transfer */
449 drv_data
->cur_msg
->state
= pxa2xx_spi_next_transfer(drv_data
);
451 /* Schedule transfer tasklet */
452 tasklet_schedule(&drv_data
->pump_transfers
);
455 static irqreturn_t
interrupt_transfer(struct driver_data
*drv_data
)
457 void __iomem
*reg
= drv_data
->ioaddr
;
459 u32 irq_mask
= (read_SSCR1(reg
) & SSCR1_TIE
) ?
460 drv_data
->mask_sr
: drv_data
->mask_sr
& ~SSSR_TFS
;
462 u32 irq_status
= read_SSSR(reg
) & irq_mask
;
464 if (irq_status
& SSSR_ROR
) {
465 int_error_stop(drv_data
, "interrupt_transfer: fifo overrun");
469 if (irq_status
& SSSR_TINT
) {
470 write_SSSR(SSSR_TINT
, reg
);
471 if (drv_data
->read(drv_data
)) {
472 int_transfer_complete(drv_data
);
477 /* Drain rx fifo, Fill tx fifo and prevent overruns */
479 if (drv_data
->read(drv_data
)) {
480 int_transfer_complete(drv_data
);
483 } while (drv_data
->write(drv_data
));
485 if (drv_data
->read(drv_data
)) {
486 int_transfer_complete(drv_data
);
490 if (drv_data
->tx
== drv_data
->tx_end
) {
494 sccr1_reg
= read_SSCR1(reg
);
495 sccr1_reg
&= ~SSCR1_TIE
;
498 * PXA25x_SSP has no timeout, set up rx threshould for the
499 * remaining RX bytes.
501 if (pxa25x_ssp_comp(drv_data
)) {
503 sccr1_reg
&= ~SSCR1_RFT
;
505 bytes_left
= drv_data
->rx_end
- drv_data
->rx
;
506 switch (drv_data
->n_bytes
) {
513 if (bytes_left
> RX_THRESH_DFLT
)
514 bytes_left
= RX_THRESH_DFLT
;
516 sccr1_reg
|= SSCR1_RxTresh(bytes_left
);
518 write_SSCR1(sccr1_reg
, reg
);
521 /* We did something */
525 static irqreturn_t
ssp_int(int irq
, void *dev_id
)
527 struct driver_data
*drv_data
= dev_id
;
528 void __iomem
*reg
= drv_data
->ioaddr
;
530 u32 mask
= drv_data
->mask_sr
;
534 * The IRQ might be shared with other peripherals so we must first
535 * check that are we RPM suspended or not. If we are we assume that
536 * the IRQ was not for us (we shouldn't be RPM suspended when the
537 * interrupt is enabled).
539 if (pm_runtime_suspended(&drv_data
->pdev
->dev
))
542 sccr1_reg
= read_SSCR1(reg
);
543 status
= read_SSSR(reg
);
545 /* Ignore possible writes if we don't need to write */
546 if (!(sccr1_reg
& SSCR1_TIE
))
549 if (!(status
& mask
))
552 if (!drv_data
->cur_msg
) {
554 write_SSCR0(read_SSCR0(reg
) & ~SSCR0_SSE
, reg
);
555 write_SSCR1(read_SSCR1(reg
) & ~drv_data
->int_cr1
, reg
);
556 if (!pxa25x_ssp_comp(drv_data
))
558 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
560 dev_err(&drv_data
->pdev
->dev
, "bad message state "
561 "in interrupt handler\n");
567 return drv_data
->transfer_handler(drv_data
);
570 static unsigned int ssp_get_clk_div(struct driver_data
*drv_data
, int rate
)
572 unsigned long ssp_clk
= drv_data
->max_clk_rate
;
573 const struct ssp_device
*ssp
= drv_data
->ssp
;
575 rate
= min_t(int, ssp_clk
, rate
);
577 if (ssp
->type
== PXA25x_SSP
|| ssp
->type
== CE4100_SSP
)
578 return ((ssp_clk
/ (2 * rate
) - 1) & 0xff) << 8;
580 return ((ssp_clk
/ rate
- 1) & 0xfff) << 8;
583 static void pump_transfers(unsigned long data
)
585 struct driver_data
*drv_data
= (struct driver_data
*)data
;
586 struct spi_message
*message
= NULL
;
587 struct spi_transfer
*transfer
= NULL
;
588 struct spi_transfer
*previous
= NULL
;
589 struct chip_data
*chip
= NULL
;
590 void __iomem
*reg
= drv_data
->ioaddr
;
596 u32 dma_thresh
= drv_data
->cur_chip
->dma_threshold
;
597 u32 dma_burst
= drv_data
->cur_chip
->dma_burst_size
;
599 /* Get current state information */
600 message
= drv_data
->cur_msg
;
601 transfer
= drv_data
->cur_transfer
;
602 chip
= drv_data
->cur_chip
;
604 /* Handle for abort */
605 if (message
->state
== ERROR_STATE
) {
606 message
->status
= -EIO
;
611 /* Handle end of message */
612 if (message
->state
== DONE_STATE
) {
618 /* Delay if requested at end of transfer before CS change */
619 if (message
->state
== RUNNING_STATE
) {
620 previous
= list_entry(transfer
->transfer_list
.prev
,
623 if (previous
->delay_usecs
)
624 udelay(previous
->delay_usecs
);
626 /* Drop chip select only if cs_change is requested */
627 if (previous
->cs_change
)
628 cs_deassert(drv_data
);
631 /* Check if we can DMA this transfer */
632 if (!pxa2xx_spi_dma_is_possible(transfer
->len
) && chip
->enable_dma
) {
634 /* reject already-mapped transfers; PIO won't always work */
635 if (message
->is_dma_mapped
636 || transfer
->rx_dma
|| transfer
->tx_dma
) {
637 dev_err(&drv_data
->pdev
->dev
,
638 "pump_transfers: mapped transfer length "
639 "of %u is greater than %d\n",
640 transfer
->len
, MAX_DMA_LEN
);
641 message
->status
= -EINVAL
;
646 /* warn ... we force this to PIO mode */
647 if (printk_ratelimit())
648 dev_warn(&message
->spi
->dev
, "pump_transfers: "
649 "DMA disabled for transfer length %ld "
651 (long)drv_data
->len
, MAX_DMA_LEN
);
654 /* Setup the transfer state based on the type of transfer */
655 if (pxa2xx_spi_flush(drv_data
) == 0) {
656 dev_err(&drv_data
->pdev
->dev
, "pump_transfers: flush failed\n");
657 message
->status
= -EIO
;
661 drv_data
->n_bytes
= chip
->n_bytes
;
662 drv_data
->tx
= (void *)transfer
->tx_buf
;
663 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
664 drv_data
->rx
= transfer
->rx_buf
;
665 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
666 drv_data
->rx_dma
= transfer
->rx_dma
;
667 drv_data
->tx_dma
= transfer
->tx_dma
;
668 drv_data
->len
= transfer
->len
;
669 drv_data
->write
= drv_data
->tx
? chip
->write
: null_writer
;
670 drv_data
->read
= drv_data
->rx
? chip
->read
: null_reader
;
672 /* Change speed and bit per word on a per transfer */
674 if (transfer
->speed_hz
|| transfer
->bits_per_word
) {
676 bits
= chip
->bits_per_word
;
677 speed
= chip
->speed_hz
;
679 if (transfer
->speed_hz
)
680 speed
= transfer
->speed_hz
;
682 if (transfer
->bits_per_word
)
683 bits
= transfer
->bits_per_word
;
685 clk_div
= ssp_get_clk_div(drv_data
, speed
);
688 drv_data
->n_bytes
= 1;
689 drv_data
->read
= drv_data
->read
!= null_reader
?
690 u8_reader
: null_reader
;
691 drv_data
->write
= drv_data
->write
!= null_writer
?
692 u8_writer
: null_writer
;
693 } else if (bits
<= 16) {
694 drv_data
->n_bytes
= 2;
695 drv_data
->read
= drv_data
->read
!= null_reader
?
696 u16_reader
: null_reader
;
697 drv_data
->write
= drv_data
->write
!= null_writer
?
698 u16_writer
: null_writer
;
699 } else if (bits
<= 32) {
700 drv_data
->n_bytes
= 4;
701 drv_data
->read
= drv_data
->read
!= null_reader
?
702 u32_reader
: null_reader
;
703 drv_data
->write
= drv_data
->write
!= null_writer
?
704 u32_writer
: null_writer
;
706 /* if bits/word is changed in dma mode, then must check the
707 * thresholds and burst also */
708 if (chip
->enable_dma
) {
709 if (pxa2xx_spi_set_dma_burst_and_threshold(chip
,
713 if (printk_ratelimit())
714 dev_warn(&message
->spi
->dev
,
716 "DMA burst size reduced to "
717 "match bits_per_word\n");
722 | SSCR0_DataSize(bits
> 16 ? bits
- 16 : bits
)
724 | (bits
> 16 ? SSCR0_EDSS
: 0);
727 message
->state
= RUNNING_STATE
;
729 drv_data
->dma_mapped
= 0;
730 if (pxa2xx_spi_dma_is_possible(drv_data
->len
))
731 drv_data
->dma_mapped
= pxa2xx_spi_map_dma_buffers(drv_data
);
732 if (drv_data
->dma_mapped
) {
734 /* Ensure we have the correct interrupt handler */
735 drv_data
->transfer_handler
= pxa2xx_spi_dma_transfer
;
737 pxa2xx_spi_dma_prepare(drv_data
, dma_burst
);
739 /* Clear status and start DMA engine */
740 cr1
= chip
->cr1
| dma_thresh
| drv_data
->dma_cr1
;
741 write_SSSR(drv_data
->clear_sr
, reg
);
743 pxa2xx_spi_dma_start(drv_data
);
745 /* Ensure we have the correct interrupt handler */
746 drv_data
->transfer_handler
= interrupt_transfer
;
749 cr1
= chip
->cr1
| chip
->threshold
| drv_data
->int_cr1
;
750 write_SSSR_CS(drv_data
, drv_data
->clear_sr
);
753 if (is_lpss_ssp(drv_data
)) {
754 if ((read_SSIRF(reg
) & 0xff) != chip
->lpss_rx_threshold
)
755 write_SSIRF(chip
->lpss_rx_threshold
, reg
);
756 if ((read_SSITF(reg
) & 0xffff) != chip
->lpss_tx_threshold
)
757 write_SSITF(chip
->lpss_tx_threshold
, reg
);
760 /* see if we need to reload the config registers */
761 if ((read_SSCR0(reg
) != cr0
)
762 || (read_SSCR1(reg
) & SSCR1_CHANGE_MASK
) !=
763 (cr1
& SSCR1_CHANGE_MASK
)) {
765 /* stop the SSP, and update the other bits */
766 write_SSCR0(cr0
& ~SSCR0_SSE
, reg
);
767 if (!pxa25x_ssp_comp(drv_data
))
768 write_SSTO(chip
->timeout
, reg
);
769 /* first set CR1 without interrupt and service enables */
770 write_SSCR1(cr1
& SSCR1_CHANGE_MASK
, reg
);
771 /* restart the SSP */
772 write_SSCR0(cr0
, reg
);
775 if (!pxa25x_ssp_comp(drv_data
))
776 write_SSTO(chip
->timeout
, reg
);
781 /* after chip select, release the data by enabling service
782 * requests and interrupts, without changing any mode bits */
783 write_SSCR1(cr1
, reg
);
786 static int pxa2xx_spi_transfer_one_message(struct spi_master
*master
,
787 struct spi_message
*msg
)
789 struct driver_data
*drv_data
= spi_master_get_devdata(master
);
791 drv_data
->cur_msg
= msg
;
792 /* Initial message state*/
793 drv_data
->cur_msg
->state
= START_STATE
;
794 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
798 /* prepare to setup the SSP, in pump_transfers, using the per
799 * chip configuration */
800 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
802 /* Mark as busy and launch transfers */
803 tasklet_schedule(&drv_data
->pump_transfers
);
807 static int pxa2xx_spi_prepare_transfer(struct spi_master
*master
)
809 struct driver_data
*drv_data
= spi_master_get_devdata(master
);
811 pm_runtime_get_sync(&drv_data
->pdev
->dev
);
815 static int pxa2xx_spi_unprepare_transfer(struct spi_master
*master
)
817 struct driver_data
*drv_data
= spi_master_get_devdata(master
);
819 /* Disable the SSP now */
820 write_SSCR0(read_SSCR0(drv_data
->ioaddr
) & ~SSCR0_SSE
,
823 pm_runtime_mark_last_busy(&drv_data
->pdev
->dev
);
824 pm_runtime_put_autosuspend(&drv_data
->pdev
->dev
);
828 static int setup_cs(struct spi_device
*spi
, struct chip_data
*chip
,
829 struct pxa2xx_spi_chip
*chip_info
)
833 if (chip
== NULL
|| chip_info
== NULL
)
836 /* NOTE: setup() can be called multiple times, possibly with
837 * different chip_info, release previously requested GPIO
839 if (gpio_is_valid(chip
->gpio_cs
))
840 gpio_free(chip
->gpio_cs
);
842 /* If (*cs_control) is provided, ignore GPIO chip select */
843 if (chip_info
->cs_control
) {
844 chip
->cs_control
= chip_info
->cs_control
;
848 if (gpio_is_valid(chip_info
->gpio_cs
)) {
849 err
= gpio_request(chip_info
->gpio_cs
, "SPI_CS");
851 dev_err(&spi
->dev
, "failed to request chip select "
852 "GPIO%d\n", chip_info
->gpio_cs
);
856 chip
->gpio_cs
= chip_info
->gpio_cs
;
857 chip
->gpio_cs_inverted
= spi
->mode
& SPI_CS_HIGH
;
859 err
= gpio_direction_output(chip
->gpio_cs
,
860 !chip
->gpio_cs_inverted
);
866 static int setup(struct spi_device
*spi
)
868 struct pxa2xx_spi_chip
*chip_info
= NULL
;
869 struct chip_data
*chip
;
870 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
871 unsigned int clk_div
;
872 uint tx_thres
, tx_hi_thres
, rx_thres
;
874 if (is_lpss_ssp(drv_data
)) {
875 tx_thres
= LPSS_TX_LOTHRESH_DFLT
;
876 tx_hi_thres
= LPSS_TX_HITHRESH_DFLT
;
877 rx_thres
= LPSS_RX_THRESH_DFLT
;
879 tx_thres
= TX_THRESH_DFLT
;
881 rx_thres
= RX_THRESH_DFLT
;
884 if (!pxa25x_ssp_comp(drv_data
)
885 && (spi
->bits_per_word
< 4 || spi
->bits_per_word
> 32)) {
886 dev_err(&spi
->dev
, "failed setup: ssp_type=%d, bits/wrd=%d "
887 "b/w not 4-32 for type non-PXA25x_SSP\n",
888 drv_data
->ssp_type
, spi
->bits_per_word
);
890 } else if (pxa25x_ssp_comp(drv_data
)
891 && (spi
->bits_per_word
< 4
892 || spi
->bits_per_word
> 16)) {
893 dev_err(&spi
->dev
, "failed setup: ssp_type=%d, bits/wrd=%d "
894 "b/w not 4-16 for type PXA25x_SSP\n",
895 drv_data
->ssp_type
, spi
->bits_per_word
);
899 /* Only alloc on first setup */
900 chip
= spi_get_ctldata(spi
);
902 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
905 "failed setup: can't allocate chip data\n");
909 if (drv_data
->ssp_type
== CE4100_SSP
) {
910 if (spi
->chip_select
> 4) {
911 dev_err(&spi
->dev
, "failed setup: "
912 "cs number must not be > 4.\n");
917 chip
->frm
= spi
->chip_select
;
920 chip
->enable_dma
= 0;
921 chip
->timeout
= TIMOUT_DFLT
;
924 /* protocol drivers may change the chip settings, so...
925 * if chip_info exists, use it */
926 chip_info
= spi
->controller_data
;
928 /* chip_info isn't always needed */
931 if (chip_info
->timeout
)
932 chip
->timeout
= chip_info
->timeout
;
933 if (chip_info
->tx_threshold
)
934 tx_thres
= chip_info
->tx_threshold
;
935 if (chip_info
->tx_hi_threshold
)
936 tx_hi_thres
= chip_info
->tx_hi_threshold
;
937 if (chip_info
->rx_threshold
)
938 rx_thres
= chip_info
->rx_threshold
;
939 chip
->enable_dma
= drv_data
->master_info
->enable_dma
;
940 chip
->dma_threshold
= 0;
941 if (chip_info
->enable_loopback
)
942 chip
->cr1
= SSCR1_LBM
;
943 } else if (ACPI_HANDLE(&spi
->dev
)) {
945 * Slave devices enumerated from ACPI namespace don't
946 * usually have chip_info but we still might want to use
949 chip
->enable_dma
= drv_data
->master_info
->enable_dma
;
952 chip
->threshold
= (SSCR1_RxTresh(rx_thres
) & SSCR1_RFT
) |
953 (SSCR1_TxTresh(tx_thres
) & SSCR1_TFT
);
955 chip
->lpss_rx_threshold
= SSIRF_RxThresh(rx_thres
);
956 chip
->lpss_tx_threshold
= SSITF_TxLoThresh(tx_thres
)
957 | SSITF_TxHiThresh(tx_hi_thres
);
959 /* set dma burst and threshold outside of chip_info path so that if
960 * chip_info goes away after setting chip->enable_dma, the
961 * burst and threshold can still respond to changes in bits_per_word */
962 if (chip
->enable_dma
) {
963 /* set up legal burst and threshold for dma */
964 if (pxa2xx_spi_set_dma_burst_and_threshold(chip
, spi
,
966 &chip
->dma_burst_size
,
967 &chip
->dma_threshold
)) {
968 dev_warn(&spi
->dev
, "in setup: DMA burst size reduced "
969 "to match bits_per_word\n");
973 clk_div
= ssp_get_clk_div(drv_data
, spi
->max_speed_hz
);
974 chip
->speed_hz
= spi
->max_speed_hz
;
978 | SSCR0_DataSize(spi
->bits_per_word
> 16 ?
979 spi
->bits_per_word
- 16 : spi
->bits_per_word
)
981 | (spi
->bits_per_word
> 16 ? SSCR0_EDSS
: 0);
982 chip
->cr1
&= ~(SSCR1_SPO
| SSCR1_SPH
);
983 chip
->cr1
|= (((spi
->mode
& SPI_CPHA
) != 0) ? SSCR1_SPH
: 0)
984 | (((spi
->mode
& SPI_CPOL
) != 0) ? SSCR1_SPO
: 0);
986 if (spi
->mode
& SPI_LOOP
)
987 chip
->cr1
|= SSCR1_LBM
;
989 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
990 if (!pxa25x_ssp_comp(drv_data
))
991 dev_dbg(&spi
->dev
, "%ld Hz actual, %s\n",
992 drv_data
->max_clk_rate
993 / (1 + ((chip
->cr0
& SSCR0_SCR(0xfff)) >> 8)),
994 chip
->enable_dma
? "DMA" : "PIO");
996 dev_dbg(&spi
->dev
, "%ld Hz actual, %s\n",
997 drv_data
->max_clk_rate
/ 2
998 / (1 + ((chip
->cr0
& SSCR0_SCR(0x0ff)) >> 8)),
999 chip
->enable_dma
? "DMA" : "PIO");
1001 if (spi
->bits_per_word
<= 8) {
1003 chip
->read
= u8_reader
;
1004 chip
->write
= u8_writer
;
1005 } else if (spi
->bits_per_word
<= 16) {
1007 chip
->read
= u16_reader
;
1008 chip
->write
= u16_writer
;
1009 } else if (spi
->bits_per_word
<= 32) {
1010 chip
->cr0
|= SSCR0_EDSS
;
1012 chip
->read
= u32_reader
;
1013 chip
->write
= u32_writer
;
1015 dev_err(&spi
->dev
, "invalid wordsize\n");
1018 chip
->bits_per_word
= spi
->bits_per_word
;
1020 spi_set_ctldata(spi
, chip
);
1022 if (drv_data
->ssp_type
== CE4100_SSP
)
1025 return setup_cs(spi
, chip
, chip_info
);
1028 static void cleanup(struct spi_device
*spi
)
1030 struct chip_data
*chip
= spi_get_ctldata(spi
);
1031 struct driver_data
*drv_data
= spi_master_get_devdata(spi
->master
);
1036 if (drv_data
->ssp_type
!= CE4100_SSP
&& gpio_is_valid(chip
->gpio_cs
))
1037 gpio_free(chip
->gpio_cs
);
1043 static int pxa2xx_spi_acpi_add_dma(struct acpi_resource
*res
, void *data
)
1045 struct pxa2xx_spi_master
*pdata
= data
;
1047 if (res
->type
== ACPI_RESOURCE_TYPE_FIXED_DMA
) {
1048 const struct acpi_resource_fixed_dma
*dma
;
1050 dma
= &res
->data
.fixed_dma
;
1051 if (pdata
->tx_slave_id
< 0) {
1052 pdata
->tx_slave_id
= dma
->request_lines
;
1053 pdata
->tx_chan_id
= dma
->channels
;
1054 } else if (pdata
->rx_slave_id
< 0) {
1055 pdata
->rx_slave_id
= dma
->request_lines
;
1056 pdata
->rx_chan_id
= dma
->channels
;
1060 /* Tell the ACPI core to skip this resource */
1064 static struct pxa2xx_spi_master
*
1065 pxa2xx_spi_acpi_get_pdata(struct platform_device
*pdev
)
1067 struct pxa2xx_spi_master
*pdata
;
1068 struct list_head resource_list
;
1069 struct acpi_device
*adev
;
1070 struct ssp_device
*ssp
;
1071 struct resource
*res
;
1074 if (!ACPI_HANDLE(&pdev
->dev
) ||
1075 acpi_bus_get_device(ACPI_HANDLE(&pdev
->dev
), &adev
))
1078 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*ssp
), GFP_KERNEL
);
1081 "failed to allocate memory for platform data\n");
1085 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1091 ssp
->phys_base
= res
->start
;
1092 ssp
->mmio_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1093 if (IS_ERR(ssp
->mmio_base
))
1094 return PTR_ERR(ssp
->mmio_base
);
1096 ssp
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
1097 ssp
->irq
= platform_get_irq(pdev
, 0);
1098 ssp
->type
= LPSS_SSP
;
1102 if (adev
->pnp
.unique_id
&& !kstrtoint(adev
->pnp
.unique_id
, 0, &devid
))
1103 ssp
->port_id
= devid
;
1105 pdata
->num_chipselect
= 1;
1106 pdata
->rx_slave_id
= -1;
1107 pdata
->tx_slave_id
= -1;
1109 INIT_LIST_HEAD(&resource_list
);
1110 acpi_dev_get_resources(adev
, &resource_list
, pxa2xx_spi_acpi_add_dma
,
1112 acpi_dev_free_resource_list(&resource_list
);
1114 pdata
->enable_dma
= pdata
->rx_slave_id
>= 0 && pdata
->tx_slave_id
>= 0;
1119 static struct acpi_device_id pxa2xx_spi_acpi_match
[] = {
1124 MODULE_DEVICE_TABLE(acpi
, pxa2xx_spi_acpi_match
);
1126 static inline struct pxa2xx_spi_master
*
1127 pxa2xx_spi_acpi_get_pdata(struct platform_device
*pdev
)
1133 static int pxa2xx_spi_probe(struct platform_device
*pdev
)
1135 struct device
*dev
= &pdev
->dev
;
1136 struct pxa2xx_spi_master
*platform_info
;
1137 struct spi_master
*master
;
1138 struct driver_data
*drv_data
;
1139 struct ssp_device
*ssp
;
1142 platform_info
= dev_get_platdata(dev
);
1143 if (!platform_info
) {
1144 platform_info
= pxa2xx_spi_acpi_get_pdata(pdev
);
1145 if (!platform_info
) {
1146 dev_err(&pdev
->dev
, "missing platform data\n");
1151 ssp
= pxa_ssp_request(pdev
->id
, pdev
->name
);
1153 ssp
= &platform_info
->ssp
;
1155 if (!ssp
->mmio_base
) {
1156 dev_err(&pdev
->dev
, "failed to get ssp\n");
1160 /* Allocate master with space for drv_data and null dma buffer */
1161 master
= spi_alloc_master(dev
, sizeof(struct driver_data
) + 16);
1163 dev_err(&pdev
->dev
, "cannot alloc spi_master\n");
1167 drv_data
= spi_master_get_devdata(master
);
1168 drv_data
->master
= master
;
1169 drv_data
->master_info
= platform_info
;
1170 drv_data
->pdev
= pdev
;
1171 drv_data
->ssp
= ssp
;
1173 master
->dev
.parent
= &pdev
->dev
;
1174 master
->dev
.of_node
= pdev
->dev
.of_node
;
1175 /* the spi->mode bits understood by this driver: */
1176 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
| SPI_LOOP
;
1178 master
->bus_num
= ssp
->port_id
;
1179 master
->num_chipselect
= platform_info
->num_chipselect
;
1180 master
->dma_alignment
= DMA_ALIGNMENT
;
1181 master
->cleanup
= cleanup
;
1182 master
->setup
= setup
;
1183 master
->transfer_one_message
= pxa2xx_spi_transfer_one_message
;
1184 master
->prepare_transfer_hardware
= pxa2xx_spi_prepare_transfer
;
1185 master
->unprepare_transfer_hardware
= pxa2xx_spi_unprepare_transfer
;
1187 drv_data
->ssp_type
= ssp
->type
;
1188 drv_data
->null_dma_buf
= (u32
*)PTR_ALIGN(&drv_data
[1], DMA_ALIGNMENT
);
1190 drv_data
->ioaddr
= ssp
->mmio_base
;
1191 drv_data
->ssdr_physical
= ssp
->phys_base
+ SSDR
;
1192 if (pxa25x_ssp_comp(drv_data
)) {
1193 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
;
1194 drv_data
->dma_cr1
= 0;
1195 drv_data
->clear_sr
= SSSR_ROR
;
1196 drv_data
->mask_sr
= SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1198 drv_data
->int_cr1
= SSCR1_TIE
| SSCR1_RIE
| SSCR1_TINTE
;
1199 drv_data
->dma_cr1
= DEFAULT_DMA_CR1
;
1200 drv_data
->clear_sr
= SSSR_ROR
| SSSR_TINT
;
1201 drv_data
->mask_sr
= SSSR_TINT
| SSSR_RFS
| SSSR_TFS
| SSSR_ROR
;
1204 status
= request_irq(ssp
->irq
, ssp_int
, IRQF_SHARED
, dev_name(dev
),
1207 dev_err(&pdev
->dev
, "cannot get IRQ %d\n", ssp
->irq
);
1208 goto out_error_master_alloc
;
1211 /* Setup DMA if requested */
1212 drv_data
->tx_channel
= -1;
1213 drv_data
->rx_channel
= -1;
1214 if (platform_info
->enable_dma
) {
1215 status
= pxa2xx_spi_dma_setup(drv_data
);
1217 dev_warn(dev
, "failed to setup DMA, using PIO\n");
1218 platform_info
->enable_dma
= false;
1222 /* Enable SOC clock */
1223 clk_prepare_enable(ssp
->clk
);
1225 drv_data
->max_clk_rate
= clk_get_rate(ssp
->clk
);
1227 /* Load default SSP configuration */
1228 write_SSCR0(0, drv_data
->ioaddr
);
1229 write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT
) |
1230 SSCR1_TxTresh(TX_THRESH_DFLT
),
1232 write_SSCR0(SSCR0_SCR(2)
1234 | SSCR0_DataSize(8),
1236 if (!pxa25x_ssp_comp(drv_data
))
1237 write_SSTO(0, drv_data
->ioaddr
);
1238 write_SSPSP(0, drv_data
->ioaddr
);
1240 lpss_ssp_setup(drv_data
);
1242 tasklet_init(&drv_data
->pump_transfers
, pump_transfers
,
1243 (unsigned long)drv_data
);
1245 /* Register with the SPI framework */
1246 platform_set_drvdata(pdev
, drv_data
);
1247 status
= spi_register_master(master
);
1249 dev_err(&pdev
->dev
, "problem registering spi master\n");
1250 goto out_error_clock_enabled
;
1253 pm_runtime_set_autosuspend_delay(&pdev
->dev
, 50);
1254 pm_runtime_use_autosuspend(&pdev
->dev
);
1255 pm_runtime_set_active(&pdev
->dev
);
1256 pm_runtime_enable(&pdev
->dev
);
1260 out_error_clock_enabled
:
1261 clk_disable_unprepare(ssp
->clk
);
1262 pxa2xx_spi_dma_release(drv_data
);
1263 free_irq(ssp
->irq
, drv_data
);
1265 out_error_master_alloc
:
1266 spi_master_put(master
);
1271 static int pxa2xx_spi_remove(struct platform_device
*pdev
)
1273 struct driver_data
*drv_data
= platform_get_drvdata(pdev
);
1274 struct ssp_device
*ssp
;
1278 ssp
= drv_data
->ssp
;
1280 pm_runtime_get_sync(&pdev
->dev
);
1282 /* Disable the SSP at the peripheral and SOC level */
1283 write_SSCR0(0, drv_data
->ioaddr
);
1284 clk_disable_unprepare(ssp
->clk
);
1287 if (drv_data
->master_info
->enable_dma
)
1288 pxa2xx_spi_dma_release(drv_data
);
1290 pm_runtime_put_noidle(&pdev
->dev
);
1291 pm_runtime_disable(&pdev
->dev
);
1294 free_irq(ssp
->irq
, drv_data
);
1299 /* Disconnect from the SPI framework */
1300 spi_unregister_master(drv_data
->master
);
1302 /* Prevent double remove */
1303 platform_set_drvdata(pdev
, NULL
);
1308 static void pxa2xx_spi_shutdown(struct platform_device
*pdev
)
1312 if ((status
= pxa2xx_spi_remove(pdev
)) != 0)
1313 dev_err(&pdev
->dev
, "shutdown failed with %d\n", status
);
1317 static int pxa2xx_spi_suspend(struct device
*dev
)
1319 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1320 struct ssp_device
*ssp
= drv_data
->ssp
;
1323 status
= spi_master_suspend(drv_data
->master
);
1326 write_SSCR0(0, drv_data
->ioaddr
);
1327 clk_disable_unprepare(ssp
->clk
);
1332 static int pxa2xx_spi_resume(struct device
*dev
)
1334 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1335 struct ssp_device
*ssp
= drv_data
->ssp
;
1338 pxa2xx_spi_dma_resume(drv_data
);
1340 /* Enable the SSP clock */
1341 clk_prepare_enable(ssp
->clk
);
1343 /* Start the queue running */
1344 status
= spi_master_resume(drv_data
->master
);
1346 dev_err(dev
, "problem starting queue (%d)\n", status
);
1354 #ifdef CONFIG_PM_RUNTIME
1355 static int pxa2xx_spi_runtime_suspend(struct device
*dev
)
1357 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1359 clk_disable_unprepare(drv_data
->ssp
->clk
);
1363 static int pxa2xx_spi_runtime_resume(struct device
*dev
)
1365 struct driver_data
*drv_data
= dev_get_drvdata(dev
);
1367 clk_prepare_enable(drv_data
->ssp
->clk
);
1372 static const struct dev_pm_ops pxa2xx_spi_pm_ops
= {
1373 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend
, pxa2xx_spi_resume
)
1374 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend
,
1375 pxa2xx_spi_runtime_resume
, NULL
)
1378 static struct platform_driver driver
= {
1380 .name
= "pxa2xx-spi",
1381 .owner
= THIS_MODULE
,
1382 .pm
= &pxa2xx_spi_pm_ops
,
1383 .acpi_match_table
= ACPI_PTR(pxa2xx_spi_acpi_match
),
1385 .probe
= pxa2xx_spi_probe
,
1386 .remove
= pxa2xx_spi_remove
,
1387 .shutdown
= pxa2xx_spi_shutdown
,
1390 static int __init
pxa2xx_spi_init(void)
1392 return platform_driver_register(&driver
);
1394 subsys_initcall(pxa2xx_spi_init
);
1396 static void __exit
pxa2xx_spi_exit(void)
1398 platform_driver_unregister(&driver
);
1400 module_exit(pxa2xx_spi_exit
);