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[deliverable/linux.git] / drivers / spi / spi-rockchip.c
1 /*
2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3 * Author: Addy Ke <addy.ke@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 */
15
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
24 #include <linux/spi/spi.h>
25 #include <linux/scatterlist.h>
26 #include <linux/of.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/io.h>
29 #include <linux/dmaengine.h>
30
31 #define DRIVER_NAME "rockchip-spi"
32
33 /* SPI register offsets */
34 #define ROCKCHIP_SPI_CTRLR0 0x0000
35 #define ROCKCHIP_SPI_CTRLR1 0x0004
36 #define ROCKCHIP_SPI_SSIENR 0x0008
37 #define ROCKCHIP_SPI_SER 0x000c
38 #define ROCKCHIP_SPI_BAUDR 0x0010
39 #define ROCKCHIP_SPI_TXFTLR 0x0014
40 #define ROCKCHIP_SPI_RXFTLR 0x0018
41 #define ROCKCHIP_SPI_TXFLR 0x001c
42 #define ROCKCHIP_SPI_RXFLR 0x0020
43 #define ROCKCHIP_SPI_SR 0x0024
44 #define ROCKCHIP_SPI_IPR 0x0028
45 #define ROCKCHIP_SPI_IMR 0x002c
46 #define ROCKCHIP_SPI_ISR 0x0030
47 #define ROCKCHIP_SPI_RISR 0x0034
48 #define ROCKCHIP_SPI_ICR 0x0038
49 #define ROCKCHIP_SPI_DMACR 0x003c
50 #define ROCKCHIP_SPI_DMATDLR 0x0040
51 #define ROCKCHIP_SPI_DMARDLR 0x0044
52 #define ROCKCHIP_SPI_TXDR 0x0400
53 #define ROCKCHIP_SPI_RXDR 0x0800
54
55 /* Bit fields in CTRLR0 */
56 #define CR0_DFS_OFFSET 0
57
58 #define CR0_CFS_OFFSET 2
59
60 #define CR0_SCPH_OFFSET 6
61
62 #define CR0_SCPOL_OFFSET 7
63
64 #define CR0_CSM_OFFSET 8
65 #define CR0_CSM_KEEP 0x0
66 /* ss_n be high for half sclk_out cycles */
67 #define CR0_CSM_HALF 0X1
68 /* ss_n be high for one sclk_out cycle */
69 #define CR0_CSM_ONE 0x2
70
71 /* ss_n to sclk_out delay */
72 #define CR0_SSD_OFFSET 10
73 /*
74 * The period between ss_n active and
75 * sclk_out active is half sclk_out cycles
76 */
77 #define CR0_SSD_HALF 0x0
78 /*
79 * The period between ss_n active and
80 * sclk_out active is one sclk_out cycle
81 */
82 #define CR0_SSD_ONE 0x1
83
84 #define CR0_EM_OFFSET 11
85 #define CR0_EM_LITTLE 0x0
86 #define CR0_EM_BIG 0x1
87
88 #define CR0_FBM_OFFSET 12
89 #define CR0_FBM_MSB 0x0
90 #define CR0_FBM_LSB 0x1
91
92 #define CR0_BHT_OFFSET 13
93 #define CR0_BHT_16BIT 0x0
94 #define CR0_BHT_8BIT 0x1
95
96 #define CR0_RSD_OFFSET 14
97
98 #define CR0_FRF_OFFSET 16
99 #define CR0_FRF_SPI 0x0
100 #define CR0_FRF_SSP 0x1
101 #define CR0_FRF_MICROWIRE 0x2
102
103 #define CR0_XFM_OFFSET 18
104 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
105 #define CR0_XFM_TR 0x0
106 #define CR0_XFM_TO 0x1
107 #define CR0_XFM_RO 0x2
108
109 #define CR0_OPM_OFFSET 20
110 #define CR0_OPM_MASTER 0x0
111 #define CR0_OPM_SLAVE 0x1
112
113 #define CR0_MTM_OFFSET 0x21
114
115 /* Bit fields in SER, 2bit */
116 #define SER_MASK 0x3
117
118 /* Bit fields in SR, 5bit */
119 #define SR_MASK 0x1f
120 #define SR_BUSY (1 << 0)
121 #define SR_TF_FULL (1 << 1)
122 #define SR_TF_EMPTY (1 << 2)
123 #define SR_RF_EMPTY (1 << 3)
124 #define SR_RF_FULL (1 << 4)
125
126 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */
127 #define INT_MASK 0x1f
128 #define INT_TF_EMPTY (1 << 0)
129 #define INT_TF_OVERFLOW (1 << 1)
130 #define INT_RF_UNDERFLOW (1 << 2)
131 #define INT_RF_OVERFLOW (1 << 3)
132 #define INT_RF_FULL (1 << 4)
133
134 /* Bit fields in ICR, 4bit */
135 #define ICR_MASK 0x0f
136 #define ICR_ALL (1 << 0)
137 #define ICR_RF_UNDERFLOW (1 << 1)
138 #define ICR_RF_OVERFLOW (1 << 2)
139 #define ICR_TF_OVERFLOW (1 << 3)
140
141 /* Bit fields in DMACR */
142 #define RF_DMA_EN (1 << 0)
143 #define TF_DMA_EN (1 << 1)
144
145 #define RXBUSY (1 << 0)
146 #define TXBUSY (1 << 1)
147
148 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
149 #define MAX_SCLK_OUT 50000000
150
151 enum rockchip_ssi_type {
152 SSI_MOTO_SPI = 0,
153 SSI_TI_SSP,
154 SSI_NS_MICROWIRE,
155 };
156
157 struct rockchip_spi_dma_data {
158 struct dma_chan *ch;
159 enum dma_transfer_direction direction;
160 dma_addr_t addr;
161 };
162
163 struct rockchip_spi {
164 struct device *dev;
165 struct spi_master *master;
166
167 struct clk *spiclk;
168 struct clk *apb_pclk;
169
170 void __iomem *regs;
171 /*depth of the FIFO buffer */
172 u32 fifo_len;
173 /* max bus freq supported */
174 u32 max_freq;
175 /* supported slave numbers */
176 enum rockchip_ssi_type type;
177
178 u16 mode;
179 u8 tmode;
180 u8 bpw;
181 u8 n_bytes;
182 unsigned len;
183 u32 speed;
184
185 const void *tx;
186 const void *tx_end;
187 void *rx;
188 void *rx_end;
189
190 u32 state;
191 /* protect state */
192 spinlock_t lock;
193
194 struct completion xfer_completion;
195
196 u32 use_dma;
197 struct sg_table tx_sg;
198 struct sg_table rx_sg;
199 struct rockchip_spi_dma_data dma_rx;
200 struct rockchip_spi_dma_data dma_tx;
201 };
202
203 static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
204 {
205 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
206 }
207
208 static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
209 {
210 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
211 }
212
213 static inline void flush_fifo(struct rockchip_spi *rs)
214 {
215 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
216 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
217 }
218
219 static inline void wait_for_idle(struct rockchip_spi *rs)
220 {
221 unsigned long timeout = jiffies + msecs_to_jiffies(5);
222
223 do {
224 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
225 return;
226 } while (!time_after(jiffies, timeout));
227
228 dev_warn(rs->dev, "spi controller is in busy state!\n");
229 }
230
231 static u32 get_fifo_len(struct rockchip_spi *rs)
232 {
233 u32 fifo;
234
235 for (fifo = 2; fifo < 32; fifo++) {
236 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
237 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
238 break;
239 }
240
241 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
242
243 return (fifo == 31) ? 0 : fifo;
244 }
245
246 static inline u32 tx_max(struct rockchip_spi *rs)
247 {
248 u32 tx_left, tx_room;
249
250 tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
251 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
252
253 return min(tx_left, tx_room);
254 }
255
256 static inline u32 rx_max(struct rockchip_spi *rs)
257 {
258 u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
259 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
260
261 return min(rx_left, rx_room);
262 }
263
264 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
265 {
266 u32 ser;
267 struct rockchip_spi *rs = spi_master_get_devdata(spi->master);
268
269 ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK;
270
271 /*
272 * drivers/spi/spi.c:
273 * static void spi_set_cs(struct spi_device *spi, bool enable)
274 * {
275 * if (spi->mode & SPI_CS_HIGH)
276 * enable = !enable;
277 *
278 * if (spi->cs_gpio >= 0)
279 * gpio_set_value(spi->cs_gpio, !enable);
280 * else if (spi->master->set_cs)
281 * spi->master->set_cs(spi, !enable);
282 * }
283 *
284 * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
285 */
286 if (!enable)
287 ser |= 1 << spi->chip_select;
288 else
289 ser &= ~(1 << spi->chip_select);
290
291 writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER);
292 }
293
294 static int rockchip_spi_prepare_message(struct spi_master *master,
295 struct spi_message *msg)
296 {
297 struct rockchip_spi *rs = spi_master_get_devdata(master);
298 struct spi_device *spi = msg->spi;
299
300 rs->mode = spi->mode;
301
302 return 0;
303 }
304
305 static int rockchip_spi_unprepare_message(struct spi_master *master,
306 struct spi_message *msg)
307 {
308 unsigned long flags;
309 struct rockchip_spi *rs = spi_master_get_devdata(master);
310
311 spin_lock_irqsave(&rs->lock, flags);
312
313 /*
314 * For DMA mode, we need terminate DMA channel and flush
315 * fifo for the next transfer if DMA thansfer timeout.
316 * unprepare_message() was called by core if transfer complete
317 * or timeout. Maybe it is reasonable for error handling here.
318 */
319 if (rs->use_dma) {
320 if (rs->state & RXBUSY) {
321 dmaengine_terminate_all(rs->dma_rx.ch);
322 flush_fifo(rs);
323 }
324
325 if (rs->state & TXBUSY)
326 dmaengine_terminate_all(rs->dma_tx.ch);
327 }
328
329 spin_unlock_irqrestore(&rs->lock, flags);
330
331 return 0;
332 }
333
334 static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
335 {
336 u32 max = tx_max(rs);
337 u32 txw = 0;
338
339 while (max--) {
340 if (rs->n_bytes == 1)
341 txw = *(u8 *)(rs->tx);
342 else
343 txw = *(u16 *)(rs->tx);
344
345 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
346 rs->tx += rs->n_bytes;
347 }
348 }
349
350 static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
351 {
352 u32 max = rx_max(rs);
353 u32 rxw;
354
355 while (max--) {
356 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
357 if (rs->n_bytes == 1)
358 *(u8 *)(rs->rx) = (u8)rxw;
359 else
360 *(u16 *)(rs->rx) = (u16)rxw;
361 rs->rx += rs->n_bytes;
362 }
363 }
364
365 static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
366 {
367 int remain = 0;
368
369 do {
370 if (rs->tx) {
371 remain = rs->tx_end - rs->tx;
372 rockchip_spi_pio_writer(rs);
373 }
374
375 if (rs->rx) {
376 remain = rs->rx_end - rs->rx;
377 rockchip_spi_pio_reader(rs);
378 }
379
380 cpu_relax();
381 } while (remain);
382
383 /* If tx, wait until the FIFO data completely. */
384 if (rs->tx)
385 wait_for_idle(rs);
386
387 return 0;
388 }
389
390 static void rockchip_spi_dma_rxcb(void *data)
391 {
392 unsigned long flags;
393 struct rockchip_spi *rs = data;
394
395 spin_lock_irqsave(&rs->lock, flags);
396
397 rs->state &= ~RXBUSY;
398 if (!(rs->state & TXBUSY))
399 spi_finalize_current_transfer(rs->master);
400
401 spin_unlock_irqrestore(&rs->lock, flags);
402 }
403
404 static void rockchip_spi_dma_txcb(void *data)
405 {
406 unsigned long flags;
407 struct rockchip_spi *rs = data;
408
409 /* Wait until the FIFO data completely. */
410 wait_for_idle(rs);
411
412 spin_lock_irqsave(&rs->lock, flags);
413
414 rs->state &= ~TXBUSY;
415 if (!(rs->state & RXBUSY))
416 spi_finalize_current_transfer(rs->master);
417
418 spin_unlock_irqrestore(&rs->lock, flags);
419 }
420
421 static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
422 {
423 unsigned long flags;
424 struct dma_slave_config rxconf, txconf;
425 struct dma_async_tx_descriptor *rxdesc, *txdesc;
426
427 spin_lock_irqsave(&rs->lock, flags);
428 rs->state &= ~RXBUSY;
429 rs->state &= ~TXBUSY;
430 spin_unlock_irqrestore(&rs->lock, flags);
431
432 if (rs->rx) {
433 rxconf.direction = rs->dma_rx.direction;
434 rxconf.src_addr = rs->dma_rx.addr;
435 rxconf.src_addr_width = rs->n_bytes;
436 rxconf.src_maxburst = rs->n_bytes;
437 dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
438
439 rxdesc = dmaengine_prep_slave_sg(
440 rs->dma_rx.ch,
441 rs->rx_sg.sgl, rs->rx_sg.nents,
442 rs->dma_rx.direction, DMA_PREP_INTERRUPT);
443
444 rxdesc->callback = rockchip_spi_dma_rxcb;
445 rxdesc->callback_param = rs;
446 }
447
448 if (rs->tx) {
449 txconf.direction = rs->dma_tx.direction;
450 txconf.dst_addr = rs->dma_tx.addr;
451 txconf.dst_addr_width = rs->n_bytes;
452 txconf.dst_maxburst = rs->n_bytes;
453 dmaengine_slave_config(rs->dma_tx.ch, &txconf);
454
455 txdesc = dmaengine_prep_slave_sg(
456 rs->dma_tx.ch,
457 rs->tx_sg.sgl, rs->tx_sg.nents,
458 rs->dma_tx.direction, DMA_PREP_INTERRUPT);
459
460 txdesc->callback = rockchip_spi_dma_txcb;
461 txdesc->callback_param = rs;
462 }
463
464 /* rx must be started before tx due to spi instinct */
465 if (rs->rx) {
466 spin_lock_irqsave(&rs->lock, flags);
467 rs->state |= RXBUSY;
468 spin_unlock_irqrestore(&rs->lock, flags);
469 dmaengine_submit(rxdesc);
470 dma_async_issue_pending(rs->dma_rx.ch);
471 }
472
473 if (rs->tx) {
474 spin_lock_irqsave(&rs->lock, flags);
475 rs->state |= TXBUSY;
476 spin_unlock_irqrestore(&rs->lock, flags);
477 dmaengine_submit(txdesc);
478 dma_async_issue_pending(rs->dma_tx.ch);
479 }
480 }
481
482 static void rockchip_spi_config(struct rockchip_spi *rs)
483 {
484 u32 div = 0;
485 u32 dmacr = 0;
486
487 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
488 | (CR0_SSD_ONE << CR0_SSD_OFFSET);
489
490 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
491 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
492 cr0 |= (rs->tmode << CR0_XFM_OFFSET);
493 cr0 |= (rs->type << CR0_FRF_OFFSET);
494
495 if (rs->use_dma) {
496 if (rs->tx)
497 dmacr |= TF_DMA_EN;
498 if (rs->rx)
499 dmacr |= RF_DMA_EN;
500 }
501
502 if (WARN_ON(rs->speed > MAX_SCLK_OUT))
503 rs->speed = MAX_SCLK_OUT;
504
505 /* the minimum divsor is 2 */
506 if (rs->max_freq < 2 * rs->speed) {
507 clk_set_rate(rs->spiclk, 2 * rs->speed);
508 rs->max_freq = clk_get_rate(rs->spiclk);
509 }
510
511 /* div doesn't support odd number */
512 div = max_t(u32, rs->max_freq / rs->speed, 1);
513 div = (div + 1) & 0xfffe;
514
515 spi_enable_chip(rs, 0);
516
517 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
518
519 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
520 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
521 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
522
523 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
524 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
525 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
526
527 spi_set_clk(rs, div);
528
529 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
530
531 spi_enable_chip(rs, 1);
532 }
533
534 static int rockchip_spi_transfer_one(
535 struct spi_master *master,
536 struct spi_device *spi,
537 struct spi_transfer *xfer)
538 {
539 int ret = 0;
540 struct rockchip_spi *rs = spi_master_get_devdata(master);
541
542 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) &&
543 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
544
545 if (!xfer->tx_buf && !xfer->rx_buf) {
546 dev_err(rs->dev, "No buffer for transfer\n");
547 return -EINVAL;
548 }
549
550 rs->speed = xfer->speed_hz;
551 rs->bpw = xfer->bits_per_word;
552 rs->n_bytes = rs->bpw >> 3;
553
554 rs->tx = xfer->tx_buf;
555 rs->tx_end = rs->tx + xfer->len;
556 rs->rx = xfer->rx_buf;
557 rs->rx_end = rs->rx + xfer->len;
558 rs->len = xfer->len;
559
560 rs->tx_sg = xfer->tx_sg;
561 rs->rx_sg = xfer->rx_sg;
562
563 if (rs->tx && rs->rx)
564 rs->tmode = CR0_XFM_TR;
565 else if (rs->tx)
566 rs->tmode = CR0_XFM_TO;
567 else if (rs->rx)
568 rs->tmode = CR0_XFM_RO;
569
570 /* we need prepare dma before spi was enabled */
571 if (master->can_dma && master->can_dma(master, spi, xfer)) {
572 rs->use_dma = 1;
573 rockchip_spi_prepare_dma(rs);
574 } else {
575 rs->use_dma = 0;
576 }
577
578 rockchip_spi_config(rs);
579
580 if (!rs->use_dma)
581 ret = rockchip_spi_pio_transfer(rs);
582
583 return ret;
584 }
585
586 static bool rockchip_spi_can_dma(struct spi_master *master,
587 struct spi_device *spi,
588 struct spi_transfer *xfer)
589 {
590 struct rockchip_spi *rs = spi_master_get_devdata(master);
591
592 return (xfer->len > rs->fifo_len);
593 }
594
595 static int rockchip_spi_probe(struct platform_device *pdev)
596 {
597 int ret = 0;
598 struct rockchip_spi *rs;
599 struct spi_master *master;
600 struct resource *mem;
601
602 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
603 if (!master)
604 return -ENOMEM;
605
606 platform_set_drvdata(pdev, master);
607
608 rs = spi_master_get_devdata(master);
609 memset(rs, 0, sizeof(struct rockchip_spi));
610
611 /* Get basic io resource and map it */
612 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
613 rs->regs = devm_ioremap_resource(&pdev->dev, mem);
614 if (IS_ERR(rs->regs)) {
615 ret = PTR_ERR(rs->regs);
616 goto err_ioremap_resource;
617 }
618
619 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
620 if (IS_ERR(rs->apb_pclk)) {
621 dev_err(&pdev->dev, "Failed to get apb_pclk\n");
622 ret = PTR_ERR(rs->apb_pclk);
623 goto err_ioremap_resource;
624 }
625
626 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
627 if (IS_ERR(rs->spiclk)) {
628 dev_err(&pdev->dev, "Failed to get spi_pclk\n");
629 ret = PTR_ERR(rs->spiclk);
630 goto err_ioremap_resource;
631 }
632
633 ret = clk_prepare_enable(rs->apb_pclk);
634 if (ret) {
635 dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
636 goto err_ioremap_resource;
637 }
638
639 ret = clk_prepare_enable(rs->spiclk);
640 if (ret) {
641 dev_err(&pdev->dev, "Failed to enable spi_clk\n");
642 goto err_spiclk_enable;
643 }
644
645 spi_enable_chip(rs, 0);
646
647 rs->type = SSI_MOTO_SPI;
648 rs->master = master;
649 rs->dev = &pdev->dev;
650 rs->max_freq = clk_get_rate(rs->spiclk);
651
652 rs->fifo_len = get_fifo_len(rs);
653 if (!rs->fifo_len) {
654 dev_err(&pdev->dev, "Failed to get fifo length\n");
655 ret = -EINVAL;
656 goto err_get_fifo_len;
657 }
658
659 spin_lock_init(&rs->lock);
660
661 pm_runtime_set_active(&pdev->dev);
662 pm_runtime_enable(&pdev->dev);
663
664 master->auto_runtime_pm = true;
665 master->bus_num = pdev->id;
666 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
667 master->num_chipselect = 2;
668 master->dev.of_node = pdev->dev.of_node;
669 master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
670
671 master->set_cs = rockchip_spi_set_cs;
672 master->prepare_message = rockchip_spi_prepare_message;
673 master->unprepare_message = rockchip_spi_unprepare_message;
674 master->transfer_one = rockchip_spi_transfer_one;
675
676 rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx");
677 if (!rs->dma_tx.ch)
678 dev_warn(rs->dev, "Failed to request TX DMA channel\n");
679
680 rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx");
681 if (!rs->dma_rx.ch) {
682 if (rs->dma_tx.ch) {
683 dma_release_channel(rs->dma_tx.ch);
684 rs->dma_tx.ch = NULL;
685 }
686 dev_warn(rs->dev, "Failed to request RX DMA channel\n");
687 }
688
689 if (rs->dma_tx.ch && rs->dma_rx.ch) {
690 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
691 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
692 rs->dma_tx.direction = DMA_MEM_TO_DEV;
693 rs->dma_rx.direction = DMA_DEV_TO_MEM;
694
695 master->can_dma = rockchip_spi_can_dma;
696 master->dma_tx = rs->dma_tx.ch;
697 master->dma_rx = rs->dma_rx.ch;
698 }
699
700 ret = devm_spi_register_master(&pdev->dev, master);
701 if (ret) {
702 dev_err(&pdev->dev, "Failed to register master\n");
703 goto err_register_master;
704 }
705
706 return 0;
707
708 err_register_master:
709 if (rs->dma_tx.ch)
710 dma_release_channel(rs->dma_tx.ch);
711 if (rs->dma_rx.ch)
712 dma_release_channel(rs->dma_rx.ch);
713 err_get_fifo_len:
714 clk_disable_unprepare(rs->spiclk);
715 err_spiclk_enable:
716 clk_disable_unprepare(rs->apb_pclk);
717 err_ioremap_resource:
718 spi_master_put(master);
719
720 return ret;
721 }
722
723 static int rockchip_spi_remove(struct platform_device *pdev)
724 {
725 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
726 struct rockchip_spi *rs = spi_master_get_devdata(master);
727
728 pm_runtime_disable(&pdev->dev);
729
730 clk_disable_unprepare(rs->spiclk);
731 clk_disable_unprepare(rs->apb_pclk);
732
733 if (rs->dma_tx.ch)
734 dma_release_channel(rs->dma_tx.ch);
735 if (rs->dma_rx.ch)
736 dma_release_channel(rs->dma_rx.ch);
737
738 spi_master_put(master);
739
740 return 0;
741 }
742
743 #ifdef CONFIG_PM_SLEEP
744 static int rockchip_spi_suspend(struct device *dev)
745 {
746 int ret = 0;
747 struct spi_master *master = dev_get_drvdata(dev);
748 struct rockchip_spi *rs = spi_master_get_devdata(master);
749
750 ret = spi_master_suspend(rs->master);
751 if (ret)
752 return ret;
753
754 if (!pm_runtime_suspended(dev)) {
755 clk_disable_unprepare(rs->spiclk);
756 clk_disable_unprepare(rs->apb_pclk);
757 }
758
759 return ret;
760 }
761
762 static int rockchip_spi_resume(struct device *dev)
763 {
764 int ret = 0;
765 struct spi_master *master = dev_get_drvdata(dev);
766 struct rockchip_spi *rs = spi_master_get_devdata(master);
767
768 if (!pm_runtime_suspended(dev)) {
769 ret = clk_prepare_enable(rs->apb_pclk);
770 if (ret < 0)
771 return ret;
772
773 ret = clk_prepare_enable(rs->spiclk);
774 if (ret < 0) {
775 clk_disable_unprepare(rs->apb_pclk);
776 return ret;
777 }
778 }
779
780 ret = spi_master_resume(rs->master);
781 if (ret < 0) {
782 clk_disable_unprepare(rs->spiclk);
783 clk_disable_unprepare(rs->apb_pclk);
784 }
785
786 return ret;
787 }
788 #endif /* CONFIG_PM_SLEEP */
789
790 #ifdef CONFIG_PM_RUNTIME
791 static int rockchip_spi_runtime_suspend(struct device *dev)
792 {
793 struct spi_master *master = dev_get_drvdata(dev);
794 struct rockchip_spi *rs = spi_master_get_devdata(master);
795
796 clk_disable_unprepare(rs->spiclk);
797 clk_disable_unprepare(rs->apb_pclk);
798
799 return 0;
800 }
801
802 static int rockchip_spi_runtime_resume(struct device *dev)
803 {
804 int ret;
805 struct spi_master *master = dev_get_drvdata(dev);
806 struct rockchip_spi *rs = spi_master_get_devdata(master);
807
808 ret = clk_prepare_enable(rs->apb_pclk);
809 if (ret)
810 return ret;
811
812 ret = clk_prepare_enable(rs->spiclk);
813 if (ret)
814 clk_disable_unprepare(rs->apb_pclk);
815
816 return ret;
817 }
818 #endif /* CONFIG_PM_RUNTIME */
819
820 static const struct dev_pm_ops rockchip_spi_pm = {
821 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
822 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
823 rockchip_spi_runtime_resume, NULL)
824 };
825
826 static const struct of_device_id rockchip_spi_dt_match[] = {
827 { .compatible = "rockchip,rk3066-spi", },
828 { .compatible = "rockchip,rk3188-spi", },
829 { .compatible = "rockchip,rk3288-spi", },
830 { },
831 };
832 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
833
834 static struct platform_driver rockchip_spi_driver = {
835 .driver = {
836 .name = DRIVER_NAME,
837 .owner = THIS_MODULE,
838 .pm = &rockchip_spi_pm,
839 .of_match_table = of_match_ptr(rockchip_spi_dt_match),
840 },
841 .probe = rockchip_spi_probe,
842 .remove = rockchip_spi_remove,
843 };
844
845 module_platform_driver(rockchip_spi_driver);
846
847 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
848 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
849 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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