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0a7a2d618f0f7860f8875375ae58b515b0a4ff44
[deliverable/linux.git] / drivers / spi / spi-rspi.c
1 /*
2 * SH RSPI driver
3 *
4 * Copyright (C) 2012, 2013 Renesas Solutions Corp.
5 * Copyright (C) 2014 Glider bvba
6 *
7 * Based on spi-sh.c:
8 * Copyright (C) 2011 Renesas Solutions Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 *
23 */
24
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/platform_device.h>
31 #include <linux/io.h>
32 #include <linux/clk.h>
33 #include <linux/dmaengine.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/of_device.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/sh_dma.h>
38 #include <linux/spi/spi.h>
39 #include <linux/spi/rspi.h>
40
41 #define RSPI_SPCR 0x00 /* Control Register */
42 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */
43 #define RSPI_SPPCR 0x02 /* Pin Control Register */
44 #define RSPI_SPSR 0x03 /* Status Register */
45 #define RSPI_SPDR 0x04 /* Data Register */
46 #define RSPI_SPSCR 0x08 /* Sequence Control Register */
47 #define RSPI_SPSSR 0x09 /* Sequence Status Register */
48 #define RSPI_SPBR 0x0a /* Bit Rate Register */
49 #define RSPI_SPDCR 0x0b /* Data Control Register */
50 #define RSPI_SPCKD 0x0c /* Clock Delay Register */
51 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */
52 #define RSPI_SPND 0x0e /* Next-Access Delay Register */
53 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */
54 #define RSPI_SPCMD0 0x10 /* Command Register 0 */
55 #define RSPI_SPCMD1 0x12 /* Command Register 1 */
56 #define RSPI_SPCMD2 0x14 /* Command Register 2 */
57 #define RSPI_SPCMD3 0x16 /* Command Register 3 */
58 #define RSPI_SPCMD4 0x18 /* Command Register 4 */
59 #define RSPI_SPCMD5 0x1a /* Command Register 5 */
60 #define RSPI_SPCMD6 0x1c /* Command Register 6 */
61 #define RSPI_SPCMD7 0x1e /* Command Register 7 */
62 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2)
63 #define RSPI_NUM_SPCMD 8
64 #define RSPI_RZ_NUM_SPCMD 4
65 #define QSPI_NUM_SPCMD 4
66
67 /* RSPI on RZ only */
68 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */
69 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */
70
71 /* QSPI only */
72 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */
73 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */
74 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */
75 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */
76 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */
77 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */
78 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4)
79
80 /* SPCR - Control Register */
81 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */
82 #define SPCR_SPE 0x40 /* Function Enable */
83 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */
84 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */
85 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */
86 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */
87 /* RSPI on SH only */
88 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */
89 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */
90 /* QSPI on R-Car M2 only */
91 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */
92 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */
93
94 /* SSLP - Slave Select Polarity Register */
95 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */
96 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */
97
98 /* SPPCR - Pin Control Register */
99 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */
100 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */
101 #define SPPCR_SPOM 0x04
102 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */
103 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */
104
105 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */
106 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */
107
108 /* SPSR - Status Register */
109 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */
110 #define SPSR_TEND 0x40 /* Transmit End */
111 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */
112 #define SPSR_PERF 0x08 /* Parity Error Flag */
113 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */
114 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */
115 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */
116
117 /* SPSCR - Sequence Control Register */
118 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */
119
120 /* SPSSR - Sequence Status Register */
121 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */
122 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */
123
124 /* SPDCR - Data Control Register */
125 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */
126 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */
127 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */
128 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0)
129 #define SPDCR_SPLWORD SPDCR_SPLW1
130 #define SPDCR_SPLBYTE SPDCR_SPLW0
131 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */
132 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */
133 #define SPDCR_SLSEL1 0x08
134 #define SPDCR_SLSEL0 0x04
135 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */
136 #define SPDCR_SPFC1 0x02
137 #define SPDCR_SPFC0 0x01
138 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */
139
140 /* SPCKD - Clock Delay Register */
141 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */
142
143 /* SSLND - Slave Select Negation Delay Register */
144 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */
145
146 /* SPND - Next-Access Delay Register */
147 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */
148
149 /* SPCR2 - Control Register 2 */
150 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */
151 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */
152 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */
153 #define SPCR2_SPPE 0x01 /* Parity Enable */
154
155 /* SPCMDn - Command Registers */
156 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */
157 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */
158 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */
159 #define SPCMD_LSBF 0x1000 /* LSB First */
160 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */
161 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK)
162 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */
163 #define SPCMD_SPB_16BIT 0x0100
164 #define SPCMD_SPB_20BIT 0x0000
165 #define SPCMD_SPB_24BIT 0x0100
166 #define SPCMD_SPB_32BIT 0x0200
167 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */
168 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */
169 #define SPCMD_SPIMOD1 0x0040
170 #define SPCMD_SPIMOD0 0x0020
171 #define SPCMD_SPIMOD_SINGLE 0
172 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0
173 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1
174 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */
175 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */
176 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */
177 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */
178 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */
179
180 /* SPBFCR - Buffer Control Register */
181 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */
182 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */
183 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */
184 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */
185
186 struct rspi_data {
187 void __iomem *addr;
188 u32 max_speed_hz;
189 struct spi_master *master;
190 wait_queue_head_t wait;
191 struct clk *clk;
192 u16 spcmd;
193 u8 spsr;
194 u8 sppcr;
195 int rx_irq, tx_irq;
196 const struct spi_ops *ops;
197
198 /* for dmaengine */
199 struct dma_chan *chan_tx;
200 struct dma_chan *chan_rx;
201
202 unsigned dma_callbacked:1;
203 unsigned byte_access:1;
204 };
205
206 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset)
207 {
208 iowrite8(data, rspi->addr + offset);
209 }
210
211 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset)
212 {
213 iowrite16(data, rspi->addr + offset);
214 }
215
216 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset)
217 {
218 iowrite32(data, rspi->addr + offset);
219 }
220
221 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset)
222 {
223 return ioread8(rspi->addr + offset);
224 }
225
226 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset)
227 {
228 return ioread16(rspi->addr + offset);
229 }
230
231 static void rspi_write_data(const struct rspi_data *rspi, u16 data)
232 {
233 if (rspi->byte_access)
234 rspi_write8(rspi, data, RSPI_SPDR);
235 else /* 16 bit */
236 rspi_write16(rspi, data, RSPI_SPDR);
237 }
238
239 static u16 rspi_read_data(const struct rspi_data *rspi)
240 {
241 if (rspi->byte_access)
242 return rspi_read8(rspi, RSPI_SPDR);
243 else /* 16 bit */
244 return rspi_read16(rspi, RSPI_SPDR);
245 }
246
247 /* optional functions */
248 struct spi_ops {
249 int (*set_config_register)(struct rspi_data *rspi, int access_size);
250 int (*transfer_one)(struct spi_master *master, struct spi_device *spi,
251 struct spi_transfer *xfer);
252 u16 mode_bits;
253 u16 flags;
254 };
255
256 /*
257 * functions for RSPI on legacy SH
258 */
259 static int rspi_set_config_register(struct rspi_data *rspi, int access_size)
260 {
261 int spbr;
262
263 /* Sets output mode, MOSI signal, and (optionally) loopback */
264 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
265
266 /* Sets transfer bit rate */
267 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
268 2 * rspi->max_speed_hz) - 1;
269 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
270
271 /* Disable dummy transmission, set 16-bit word access, 1 frame */
272 rspi_write8(rspi, 0, RSPI_SPDCR);
273 rspi->byte_access = 0;
274
275 /* Sets RSPCK, SSL, next-access delay value */
276 rspi_write8(rspi, 0x00, RSPI_SPCKD);
277 rspi_write8(rspi, 0x00, RSPI_SSLND);
278 rspi_write8(rspi, 0x00, RSPI_SPND);
279
280 /* Sets parity, interrupt mask */
281 rspi_write8(rspi, 0x00, RSPI_SPCR2);
282
283 /* Sets SPCMD */
284 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
285 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
286
287 /* Sets RSPI mode */
288 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
289
290 return 0;
291 }
292
293 /*
294 * functions for RSPI on RZ
295 */
296 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size)
297 {
298 int spbr;
299
300 /* Sets output mode, MOSI signal, and (optionally) loopback */
301 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
302
303 /* Sets transfer bit rate */
304 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk),
305 2 * rspi->max_speed_hz) - 1;
306 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
307
308 /* Disable dummy transmission, set byte access */
309 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR);
310 rspi->byte_access = 1;
311
312 /* Sets RSPCK, SSL, next-access delay value */
313 rspi_write8(rspi, 0x00, RSPI_SPCKD);
314 rspi_write8(rspi, 0x00, RSPI_SSLND);
315 rspi_write8(rspi, 0x00, RSPI_SPND);
316
317 /* Sets SPCMD */
318 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size);
319 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
320
321 /* Sets RSPI mode */
322 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR);
323
324 return 0;
325 }
326
327 /*
328 * functions for QSPI
329 */
330 static int qspi_set_config_register(struct rspi_data *rspi, int access_size)
331 {
332 int spbr;
333
334 /* Sets output mode, MOSI signal, and (optionally) loopback */
335 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR);
336
337 /* Sets transfer bit rate */
338 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz);
339 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR);
340
341 /* Disable dummy transmission, set byte access */
342 rspi_write8(rspi, 0, RSPI_SPDCR);
343 rspi->byte_access = 1;
344
345 /* Sets RSPCK, SSL, next-access delay value */
346 rspi_write8(rspi, 0x00, RSPI_SPCKD);
347 rspi_write8(rspi, 0x00, RSPI_SSLND);
348 rspi_write8(rspi, 0x00, RSPI_SPND);
349
350 /* Data Length Setting */
351 if (access_size == 8)
352 rspi->spcmd |= SPCMD_SPB_8BIT;
353 else if (access_size == 16)
354 rspi->spcmd |= SPCMD_SPB_16BIT;
355 else
356 rspi->spcmd |= SPCMD_SPB_32BIT;
357
358 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN;
359
360 /* Resets transfer data length */
361 rspi_write32(rspi, 0, QSPI_SPBMUL0);
362
363 /* Resets transmit and receive buffer */
364 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
365 /* Sets buffer to allow normal operation */
366 rspi_write8(rspi, 0x00, QSPI_SPBFCR);
367
368 /* Sets SPCMD */
369 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
370
371 /* Enables SPI function in master mode */
372 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR);
373
374 return 0;
375 }
376
377 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n)
378
379 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable)
380 {
381 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR);
382 }
383
384 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable)
385 {
386 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR);
387 }
388
389 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask,
390 u8 enable_bit)
391 {
392 int ret;
393
394 rspi->spsr = rspi_read8(rspi, RSPI_SPSR);
395 if (rspi->spsr & wait_mask)
396 return 0;
397
398 rspi_enable_irq(rspi, enable_bit);
399 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ);
400 if (ret == 0 && !(rspi->spsr & wait_mask))
401 return -ETIMEDOUT;
402
403 return 0;
404 }
405
406 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi)
407 {
408 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE);
409 }
410
411 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi)
412 {
413 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE);
414 }
415
416 static int rspi_data_out(struct rspi_data *rspi, u8 data)
417 {
418 int error = rspi_wait_for_tx_empty(rspi);
419 if (error < 0) {
420 dev_err(&rspi->master->dev, "transmit timeout\n");
421 return error;
422 }
423 rspi_write_data(rspi, data);
424 return 0;
425 }
426
427 static int rspi_data_in(struct rspi_data *rspi)
428 {
429 int error;
430 u8 data;
431
432 error = rspi_wait_for_rx_full(rspi);
433 if (error < 0) {
434 dev_err(&rspi->master->dev, "receive timeout\n");
435 return error;
436 }
437 data = rspi_read_data(rspi);
438 return data;
439 }
440
441 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx,
442 unsigned int n)
443 {
444 while (n-- > 0) {
445 if (tx) {
446 int ret = rspi_data_out(rspi, *tx++);
447 if (ret < 0)
448 return ret;
449 }
450 if (rx) {
451 int ret = rspi_data_in(rspi);
452 if (ret < 0)
453 return ret;
454 *rx++ = ret;
455 }
456 }
457
458 return 0;
459 }
460
461 static void rspi_dma_complete(void *arg)
462 {
463 struct rspi_data *rspi = arg;
464
465 rspi->dma_callbacked = 1;
466 wake_up_interruptible(&rspi->wait);
467 }
468
469 static int rspi_dma_map_sg(struct scatterlist *sg, const void *buf,
470 unsigned len, struct dma_chan *chan,
471 enum dma_transfer_direction dir)
472 {
473 sg_init_table(sg, 1);
474 sg_set_buf(sg, buf, len);
475 sg_dma_len(sg) = len;
476 return dma_map_sg(chan->device->dev, sg, 1, dir);
477 }
478
479 static void rspi_dma_unmap_sg(struct scatterlist *sg, struct dma_chan *chan,
480 enum dma_transfer_direction dir)
481 {
482 dma_unmap_sg(chan->device->dev, sg, 1, dir);
483 }
484
485 static int rspi_send_dma(struct rspi_data *rspi, struct spi_transfer *t)
486 {
487 struct scatterlist sg;
488 const void *buf = t->tx_buf;
489 struct dma_async_tx_descriptor *desc;
490 unsigned int len = t->len;
491 int ret = 0;
492
493 if (!rspi_dma_map_sg(&sg, buf, len, rspi->chan_tx, DMA_TO_DEVICE))
494 return -EFAULT;
495
496 desc = dmaengine_prep_slave_sg(rspi->chan_tx, &sg, 1, DMA_TO_DEVICE,
497 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
498 if (!desc) {
499 ret = -EIO;
500 goto end;
501 }
502
503 /*
504 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
505 * called. So, this driver disables the IRQ while DMA transfer.
506 */
507 disable_irq(rspi->tx_irq);
508
509 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_TXMD, RSPI_SPCR);
510 rspi_enable_irq(rspi, SPCR_SPTIE);
511 rspi->dma_callbacked = 0;
512
513 desc->callback = rspi_dma_complete;
514 desc->callback_param = rspi;
515 dmaengine_submit(desc);
516 dma_async_issue_pending(rspi->chan_tx);
517
518 ret = wait_event_interruptible_timeout(rspi->wait,
519 rspi->dma_callbacked, HZ);
520 if (ret > 0 && rspi->dma_callbacked)
521 ret = 0;
522 else if (!ret)
523 ret = -ETIMEDOUT;
524 rspi_disable_irq(rspi, SPCR_SPTIE);
525
526 enable_irq(rspi->tx_irq);
527
528 end:
529 rspi_dma_unmap_sg(&sg, rspi->chan_tx, DMA_TO_DEVICE);
530 return ret;
531 }
532
533 static void rspi_receive_init(const struct rspi_data *rspi)
534 {
535 u8 spsr;
536
537 spsr = rspi_read8(rspi, RSPI_SPSR);
538 if (spsr & SPSR_SPRF)
539 rspi_read_data(rspi); /* dummy read */
540 if (spsr & SPSR_OVRF)
541 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF,
542 RSPI_SPSR);
543 }
544
545 static void rspi_rz_receive_init(const struct rspi_data *rspi)
546 {
547 rspi_receive_init(rspi);
548 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR);
549 rspi_write8(rspi, 0, RSPI_SPBFCR);
550 }
551
552 static void qspi_receive_init(const struct rspi_data *rspi)
553 {
554 u8 spsr;
555
556 spsr = rspi_read8(rspi, RSPI_SPSR);
557 if (spsr & SPSR_SPRF)
558 rspi_read_data(rspi); /* dummy read */
559 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR);
560 rspi_write8(rspi, 0, QSPI_SPBFCR);
561 }
562
563 static int rspi_send_receive_dma(struct rspi_data *rspi, struct spi_transfer *t)
564 {
565 struct scatterlist sg_rx, sg_tx;
566 const void *tx_buf = t->tx_buf;
567 void *rx_buf = t->rx_buf;
568 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
569 unsigned int len = t->len;
570 int ret = 0;
571
572 /* prepare transmit transfer */
573 if (!rspi_dma_map_sg(&sg_tx, tx_buf, len, rspi->chan_tx,
574 DMA_TO_DEVICE))
575 return -EFAULT;
576
577 desc_tx = dmaengine_prep_slave_sg(rspi->chan_tx, &sg_tx, 1,
578 DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
579 if (!desc_tx) {
580 ret = -EIO;
581 goto end_tx_mapped;
582 }
583
584 /* prepare receive transfer */
585 if (!rspi_dma_map_sg(&sg_rx, rx_buf, len, rspi->chan_rx,
586 DMA_FROM_DEVICE)) {
587 ret = -EFAULT;
588 goto end_tx_mapped;
589
590 }
591 desc_rx = dmaengine_prep_slave_sg(rspi->chan_rx, &sg_rx, 1,
592 DMA_FROM_DEVICE,
593 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
594 if (!desc_rx) {
595 ret = -EIO;
596 goto end;
597 }
598
599 rspi_receive_init(rspi);
600
601 /*
602 * DMAC needs SPTIE, but if SPTIE is set, this IRQ routine will be
603 * called. So, this driver disables the IRQ while DMA transfer.
604 */
605 disable_irq(rspi->tx_irq);
606 if (rspi->rx_irq != rspi->tx_irq)
607 disable_irq(rspi->rx_irq);
608
609 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_TXMD, RSPI_SPCR);
610 rspi_enable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
611 rspi->dma_callbacked = 0;
612
613 desc_rx->callback = rspi_dma_complete;
614 desc_rx->callback_param = rspi;
615 dmaengine_submit(desc_rx);
616 dma_async_issue_pending(rspi->chan_rx);
617
618 desc_tx->callback = NULL; /* No callback */
619 dmaengine_submit(desc_tx);
620 dma_async_issue_pending(rspi->chan_tx);
621
622 ret = wait_event_interruptible_timeout(rspi->wait,
623 rspi->dma_callbacked, HZ);
624 if (ret > 0 && rspi->dma_callbacked)
625 ret = 0;
626 else if (!ret)
627 ret = -ETIMEDOUT;
628 rspi_disable_irq(rspi, SPCR_SPTIE | SPCR_SPRIE);
629
630 enable_irq(rspi->tx_irq);
631 if (rspi->rx_irq != rspi->tx_irq)
632 enable_irq(rspi->rx_irq);
633
634 end:
635 rspi_dma_unmap_sg(&sg_rx, rspi->chan_rx, DMA_FROM_DEVICE);
636 end_tx_mapped:
637 rspi_dma_unmap_sg(&sg_tx, rspi->chan_tx, DMA_TO_DEVICE);
638 return ret;
639 }
640
641 static int rspi_is_dma(const struct rspi_data *rspi, struct spi_transfer *t)
642 {
643 /* If the module receives data by DMAC, it also needs TX DMAC */
644 if (t->rx_buf)
645 return rspi->chan_tx && rspi->chan_rx;
646
647 if (rspi->chan_tx)
648 return 1;
649
650 return 0;
651 }
652
653 static int rspi_transfer_out_in(struct rspi_data *rspi,
654 struct spi_transfer *xfer)
655 {
656 u8 spcr;
657 int ret;
658
659 spcr = rspi_read8(rspi, RSPI_SPCR);
660 if (xfer->rx_buf) {
661 rspi_receive_init(rspi);
662 spcr &= ~SPCR_TXMD;
663 } else {
664 spcr |= SPCR_TXMD;
665 }
666 rspi_write8(rspi, spcr, RSPI_SPCR);
667
668 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
669 if (ret < 0)
670 return ret;
671
672 /* Wait for the last transmission */
673 rspi_wait_for_tx_empty(rspi);
674
675 return 0;
676 }
677
678 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi,
679 struct spi_transfer *xfer)
680 {
681 struct rspi_data *rspi = spi_master_get_devdata(master);
682
683 if (!rspi_is_dma(rspi, xfer))
684 return rspi_transfer_out_in(rspi, xfer);
685
686 if (xfer->rx_buf)
687 return rspi_send_receive_dma(rspi, xfer);
688 else
689 return rspi_send_dma(rspi, xfer);
690 }
691
692 static int rspi_rz_transfer_out_in(struct rspi_data *rspi,
693 struct spi_transfer *xfer)
694 {
695 int ret;
696
697 rspi_rz_receive_init(rspi);
698
699 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
700 if (ret < 0)
701 return ret;
702
703 /* Wait for the last transmission */
704 rspi_wait_for_tx_empty(rspi);
705
706 return 0;
707 }
708
709 static int rspi_rz_transfer_one(struct spi_master *master,
710 struct spi_device *spi,
711 struct spi_transfer *xfer)
712 {
713 struct rspi_data *rspi = spi_master_get_devdata(master);
714
715 return rspi_rz_transfer_out_in(rspi, xfer);
716 }
717
718 static int qspi_transfer_out_in(struct rspi_data *rspi,
719 struct spi_transfer *xfer)
720 {
721 int ret;
722
723 qspi_receive_init(rspi);
724
725 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len);
726 if (ret < 0)
727 return ret;
728
729 /* Wait for the last transmission */
730 rspi_wait_for_tx_empty(rspi);
731
732 return 0;
733 }
734
735 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer)
736 {
737 int ret;
738
739 ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len);
740 if (ret < 0)
741 return ret;
742
743 /* Wait for the last transmission */
744 rspi_wait_for_tx_empty(rspi);
745
746 return 0;
747 }
748
749 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer)
750 {
751 return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len);
752 }
753
754 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi,
755 struct spi_transfer *xfer)
756 {
757 struct rspi_data *rspi = spi_master_get_devdata(master);
758
759 if (spi->mode & SPI_LOOP) {
760 return qspi_transfer_out_in(rspi, xfer);
761 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) {
762 /* Quad or Dual SPI Write */
763 return qspi_transfer_out(rspi, xfer);
764 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) {
765 /* Quad or Dual SPI Read */
766 return qspi_transfer_in(rspi, xfer);
767 } else {
768 /* Single SPI Transfer */
769 return qspi_transfer_out_in(rspi, xfer);
770 }
771 }
772
773 static int rspi_setup(struct spi_device *spi)
774 {
775 struct rspi_data *rspi = spi_master_get_devdata(spi->master);
776
777 rspi->max_speed_hz = spi->max_speed_hz;
778
779 rspi->spcmd = SPCMD_SSLKP;
780 if (spi->mode & SPI_CPOL)
781 rspi->spcmd |= SPCMD_CPOL;
782 if (spi->mode & SPI_CPHA)
783 rspi->spcmd |= SPCMD_CPHA;
784
785 /* CMOS output mode and MOSI signal from previous transfer */
786 rspi->sppcr = 0;
787 if (spi->mode & SPI_LOOP)
788 rspi->sppcr |= SPPCR_SPLP;
789
790 set_config_register(rspi, 8);
791
792 return 0;
793 }
794
795 static u16 qspi_transfer_mode(const struct spi_transfer *xfer)
796 {
797 if (xfer->tx_buf)
798 switch (xfer->tx_nbits) {
799 case SPI_NBITS_QUAD:
800 return SPCMD_SPIMOD_QUAD;
801 case SPI_NBITS_DUAL:
802 return SPCMD_SPIMOD_DUAL;
803 default:
804 return 0;
805 }
806 if (xfer->rx_buf)
807 switch (xfer->rx_nbits) {
808 case SPI_NBITS_QUAD:
809 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW;
810 case SPI_NBITS_DUAL:
811 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW;
812 default:
813 return 0;
814 }
815
816 return 0;
817 }
818
819 static int qspi_setup_sequencer(struct rspi_data *rspi,
820 const struct spi_message *msg)
821 {
822 const struct spi_transfer *xfer;
823 unsigned int i = 0, len = 0;
824 u16 current_mode = 0xffff, mode;
825
826 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
827 mode = qspi_transfer_mode(xfer);
828 if (mode == current_mode) {
829 len += xfer->len;
830 continue;
831 }
832
833 /* Transfer mode change */
834 if (i) {
835 /* Set transfer data length of previous transfer */
836 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
837 }
838
839 if (i >= QSPI_NUM_SPCMD) {
840 dev_err(&msg->spi->dev,
841 "Too many different transfer modes");
842 return -EINVAL;
843 }
844
845 /* Program transfer mode for this transfer */
846 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i));
847 current_mode = mode;
848 len = xfer->len;
849 i++;
850 }
851 if (i) {
852 /* Set final transfer data length and sequence length */
853 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1));
854 rspi_write8(rspi, i - 1, RSPI_SPSCR);
855 }
856
857 return 0;
858 }
859
860 static int rspi_prepare_message(struct spi_master *master,
861 struct spi_message *msg)
862 {
863 struct rspi_data *rspi = spi_master_get_devdata(master);
864 int ret;
865
866 if (msg->spi->mode &
867 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) {
868 /* Setup sequencer for messages with multiple transfer modes */
869 ret = qspi_setup_sequencer(rspi, msg);
870 if (ret < 0)
871 return ret;
872 }
873
874 /* Enable SPI function in master mode */
875 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR);
876 return 0;
877 }
878
879 static int rspi_unprepare_message(struct spi_master *master,
880 struct spi_message *msg)
881 {
882 struct rspi_data *rspi = spi_master_get_devdata(master);
883
884 /* Disable SPI function */
885 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR);
886
887 /* Reset sequencer for Single SPI Transfers */
888 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0);
889 rspi_write8(rspi, 0, RSPI_SPSCR);
890 return 0;
891 }
892
893 static irqreturn_t rspi_irq_mux(int irq, void *_sr)
894 {
895 struct rspi_data *rspi = _sr;
896 u8 spsr;
897 irqreturn_t ret = IRQ_NONE;
898 u8 disable_irq = 0;
899
900 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
901 if (spsr & SPSR_SPRF)
902 disable_irq |= SPCR_SPRIE;
903 if (spsr & SPSR_SPTEF)
904 disable_irq |= SPCR_SPTIE;
905
906 if (disable_irq) {
907 ret = IRQ_HANDLED;
908 rspi_disable_irq(rspi, disable_irq);
909 wake_up(&rspi->wait);
910 }
911
912 return ret;
913 }
914
915 static irqreturn_t rspi_irq_rx(int irq, void *_sr)
916 {
917 struct rspi_data *rspi = _sr;
918 u8 spsr;
919
920 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
921 if (spsr & SPSR_SPRF) {
922 rspi_disable_irq(rspi, SPCR_SPRIE);
923 wake_up(&rspi->wait);
924 return IRQ_HANDLED;
925 }
926
927 return 0;
928 }
929
930 static irqreturn_t rspi_irq_tx(int irq, void *_sr)
931 {
932 struct rspi_data *rspi = _sr;
933 u8 spsr;
934
935 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR);
936 if (spsr & SPSR_SPTEF) {
937 rspi_disable_irq(rspi, SPCR_SPTIE);
938 wake_up(&rspi->wait);
939 return IRQ_HANDLED;
940 }
941
942 return 0;
943 }
944
945 static struct dma_chan *rspi_request_dma_chan(struct device *dev,
946 enum dma_transfer_direction dir,
947 unsigned int id,
948 dma_addr_t port_addr)
949 {
950 dma_cap_mask_t mask;
951 struct dma_chan *chan;
952 struct dma_slave_config cfg;
953 int ret;
954
955 dma_cap_zero(mask);
956 dma_cap_set(DMA_SLAVE, mask);
957
958 chan = dma_request_channel(mask, shdma_chan_filter,
959 (void *)(unsigned long)id);
960 if (!chan) {
961 dev_warn(dev, "dma_request_channel failed\n");
962 return NULL;
963 }
964
965 memset(&cfg, 0, sizeof(cfg));
966 cfg.slave_id = id;
967 cfg.direction = dir;
968 if (dir == DMA_MEM_TO_DEV)
969 cfg.dst_addr = port_addr;
970 else
971 cfg.src_addr = port_addr;
972
973 ret = dmaengine_slave_config(chan, &cfg);
974 if (ret) {
975 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
976 dma_release_channel(chan);
977 return NULL;
978 }
979
980 return chan;
981 }
982
983 static int rspi_request_dma(struct rspi_data *rspi,
984 struct platform_device *pdev)
985 {
986 const struct rspi_plat_data *rspi_pd = dev_get_platdata(&pdev->dev);
987 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
988
989 if (!res || !rspi_pd)
990 return 0; /* The driver assumes no error. */
991
992 /* If the module receives data by DMAC, it also needs TX DMAC */
993 if (rspi_pd->dma_rx_id && rspi_pd->dma_tx_id) {
994 rspi->chan_rx = rspi_request_dma_chan(&pdev->dev,
995 DMA_DEV_TO_MEM,
996 rspi_pd->dma_rx_id,
997 res->start + RSPI_SPDR);
998 if (!rspi->chan_rx)
999 return -ENODEV;
1000
1001 dev_info(&pdev->dev, "Use DMA when rx.\n");
1002 }
1003 if (rspi_pd->dma_tx_id) {
1004 rspi->chan_tx = rspi_request_dma_chan(&pdev->dev,
1005 DMA_MEM_TO_DEV,
1006 rspi_pd->dma_tx_id,
1007 res->start + RSPI_SPDR);
1008 if (!rspi->chan_tx)
1009 return -ENODEV;
1010
1011 dev_info(&pdev->dev, "Use DMA when tx\n");
1012 }
1013
1014 return 0;
1015 }
1016
1017 static void rspi_release_dma(struct rspi_data *rspi)
1018 {
1019 if (rspi->chan_tx)
1020 dma_release_channel(rspi->chan_tx);
1021 if (rspi->chan_rx)
1022 dma_release_channel(rspi->chan_rx);
1023 }
1024
1025 static int rspi_remove(struct platform_device *pdev)
1026 {
1027 struct rspi_data *rspi = platform_get_drvdata(pdev);
1028
1029 rspi_release_dma(rspi);
1030 pm_runtime_disable(&pdev->dev);
1031
1032 return 0;
1033 }
1034
1035 static const struct spi_ops rspi_ops = {
1036 .set_config_register = rspi_set_config_register,
1037 .transfer_one = rspi_transfer_one,
1038 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1039 .flags = SPI_MASTER_MUST_TX,
1040 };
1041
1042 static const struct spi_ops rspi_rz_ops = {
1043 .set_config_register = rspi_rz_set_config_register,
1044 .transfer_one = rspi_rz_transfer_one,
1045 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP,
1046 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1047 };
1048
1049 static const struct spi_ops qspi_ops = {
1050 .set_config_register = qspi_set_config_register,
1051 .transfer_one = qspi_transfer_one,
1052 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP |
1053 SPI_TX_DUAL | SPI_TX_QUAD |
1054 SPI_RX_DUAL | SPI_RX_QUAD,
1055 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX,
1056 };
1057
1058 #ifdef CONFIG_OF
1059 static const struct of_device_id rspi_of_match[] = {
1060 /* RSPI on legacy SH */
1061 { .compatible = "renesas,rspi", .data = &rspi_ops },
1062 /* RSPI on RZ/A1H */
1063 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops },
1064 /* QSPI on R-Car Gen2 */
1065 { .compatible = "renesas,qspi", .data = &qspi_ops },
1066 { /* sentinel */ }
1067 };
1068
1069 MODULE_DEVICE_TABLE(of, rspi_of_match);
1070
1071 static int rspi_parse_dt(struct device *dev, struct spi_master *master)
1072 {
1073 u32 num_cs;
1074 int error;
1075
1076 /* Parse DT properties */
1077 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs);
1078 if (error) {
1079 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error);
1080 return error;
1081 }
1082
1083 master->num_chipselect = num_cs;
1084 return 0;
1085 }
1086 #else
1087 #define rspi_of_match NULL
1088 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master)
1089 {
1090 return -EINVAL;
1091 }
1092 #endif /* CONFIG_OF */
1093
1094 static int rspi_request_irq(struct device *dev, unsigned int irq,
1095 irq_handler_t handler, const char *suffix,
1096 void *dev_id)
1097 {
1098 const char *base = dev_name(dev);
1099 size_t len = strlen(base) + strlen(suffix) + 2;
1100 char *name = devm_kzalloc(dev, len, GFP_KERNEL);
1101 if (!name)
1102 return -ENOMEM;
1103 snprintf(name, len, "%s:%s", base, suffix);
1104 return devm_request_irq(dev, irq, handler, 0, name, dev_id);
1105 }
1106
1107 static int rspi_probe(struct platform_device *pdev)
1108 {
1109 struct resource *res;
1110 struct spi_master *master;
1111 struct rspi_data *rspi;
1112 int ret;
1113 const struct of_device_id *of_id;
1114 const struct rspi_plat_data *rspi_pd;
1115 const struct spi_ops *ops;
1116
1117 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data));
1118 if (master == NULL) {
1119 dev_err(&pdev->dev, "spi_alloc_master error.\n");
1120 return -ENOMEM;
1121 }
1122
1123 of_id = of_match_device(rspi_of_match, &pdev->dev);
1124 if (of_id) {
1125 ops = of_id->data;
1126 ret = rspi_parse_dt(&pdev->dev, master);
1127 if (ret)
1128 goto error1;
1129 } else {
1130 ops = (struct spi_ops *)pdev->id_entry->driver_data;
1131 rspi_pd = dev_get_platdata(&pdev->dev);
1132 if (rspi_pd && rspi_pd->num_chipselect)
1133 master->num_chipselect = rspi_pd->num_chipselect;
1134 else
1135 master->num_chipselect = 2; /* default */
1136 };
1137
1138 /* ops parameter check */
1139 if (!ops->set_config_register) {
1140 dev_err(&pdev->dev, "there is no set_config_register\n");
1141 ret = -ENODEV;
1142 goto error1;
1143 }
1144
1145 rspi = spi_master_get_devdata(master);
1146 platform_set_drvdata(pdev, rspi);
1147 rspi->ops = ops;
1148 rspi->master = master;
1149
1150 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1151 rspi->addr = devm_ioremap_resource(&pdev->dev, res);
1152 if (IS_ERR(rspi->addr)) {
1153 ret = PTR_ERR(rspi->addr);
1154 goto error1;
1155 }
1156
1157 rspi->clk = devm_clk_get(&pdev->dev, NULL);
1158 if (IS_ERR(rspi->clk)) {
1159 dev_err(&pdev->dev, "cannot get clock\n");
1160 ret = PTR_ERR(rspi->clk);
1161 goto error1;
1162 }
1163
1164 pm_runtime_enable(&pdev->dev);
1165
1166 init_waitqueue_head(&rspi->wait);
1167
1168 master->bus_num = pdev->id;
1169 master->setup = rspi_setup;
1170 master->auto_runtime_pm = true;
1171 master->transfer_one = ops->transfer_one;
1172 master->prepare_message = rspi_prepare_message;
1173 master->unprepare_message = rspi_unprepare_message;
1174 master->mode_bits = ops->mode_bits;
1175 master->flags = ops->flags;
1176 master->dev.of_node = pdev->dev.of_node;
1177
1178 ret = platform_get_irq_byname(pdev, "rx");
1179 if (ret < 0) {
1180 ret = platform_get_irq_byname(pdev, "mux");
1181 if (ret < 0)
1182 ret = platform_get_irq(pdev, 0);
1183 if (ret >= 0)
1184 rspi->rx_irq = rspi->tx_irq = ret;
1185 } else {
1186 rspi->rx_irq = ret;
1187 ret = platform_get_irq_byname(pdev, "tx");
1188 if (ret >= 0)
1189 rspi->tx_irq = ret;
1190 }
1191 if (ret < 0) {
1192 dev_err(&pdev->dev, "platform_get_irq error\n");
1193 goto error2;
1194 }
1195
1196 if (rspi->rx_irq == rspi->tx_irq) {
1197 /* Single multiplexed interrupt */
1198 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux,
1199 "mux", rspi);
1200 } else {
1201 /* Multi-interrupt mode, only SPRI and SPTI are used */
1202 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx,
1203 "rx", rspi);
1204 if (!ret)
1205 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq,
1206 rspi_irq_tx, "tx", rspi);
1207 }
1208 if (ret < 0) {
1209 dev_err(&pdev->dev, "request_irq error\n");
1210 goto error2;
1211 }
1212
1213 ret = rspi_request_dma(rspi, pdev);
1214 if (ret < 0)
1215 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1216
1217 ret = devm_spi_register_master(&pdev->dev, master);
1218 if (ret < 0) {
1219 dev_err(&pdev->dev, "spi_register_master error.\n");
1220 goto error3;
1221 }
1222
1223 dev_info(&pdev->dev, "probed\n");
1224
1225 return 0;
1226
1227 error3:
1228 rspi_release_dma(rspi);
1229 error2:
1230 pm_runtime_disable(&pdev->dev);
1231 error1:
1232 spi_master_put(master);
1233
1234 return ret;
1235 }
1236
1237 static struct platform_device_id spi_driver_ids[] = {
1238 { "rspi", (kernel_ulong_t)&rspi_ops },
1239 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops },
1240 { "qspi", (kernel_ulong_t)&qspi_ops },
1241 {},
1242 };
1243
1244 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1245
1246 static struct platform_driver rspi_driver = {
1247 .probe = rspi_probe,
1248 .remove = rspi_remove,
1249 .id_table = spi_driver_ids,
1250 .driver = {
1251 .name = "renesas_spi",
1252 .owner = THIS_MODULE,
1253 .of_match_table = of_match_ptr(rspi_of_match),
1254 },
1255 };
1256 module_platform_driver(rspi_driver);
1257
1258 MODULE_DESCRIPTION("Renesas RSPI bus driver");
1259 MODULE_LICENSE("GPL v2");
1260 MODULE_AUTHOR("Yoshihiro Shimoda");
1261 MODULE_ALIAS("platform:rspi");
Linux kernel - Deliverables
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